1 /* SPDX-License-Identifier: GPL-2.0-only 2 * 3 * Copyright © 2018-2020 Intel Corporation 4 */ 5 6 #ifndef __KMB_DRV_H__ 7 #define __KMB_DRV_H__ 8 9 #include <drm/drm_device.h> 10 11 #include "kmb_plane.h" 12 #include "kmb_regs.h" 13 14 #define KMB_MAX_WIDTH 1920 /*Max width in pixels */ 15 #define KMB_MAX_HEIGHT 1080 /*Max height in pixels */ 16 #define KMB_MIN_WIDTH 1920 /*Max width in pixels */ 17 #define KMB_MIN_HEIGHT 1080 /*Max height in pixels */ 18 19 #define DRIVER_MAJOR 1 20 #define DRIVER_MINOR 1 21 22 /* Platform definitions */ 23 #define KMB_CRTC_MIN_VFP 4 24 #define KMB_CRTC_MAX_WIDTH 1920 /* max width in pixels */ 25 #define KMB_CRTC_MAX_HEIGHT 1080 /* max height in pixels */ 26 #define KMB_CRTC_MIN_WIDTH 1920 27 #define KMB_CRTC_MIN_HEIGHT 1080 28 #define KMB_FB_MAX_WIDTH 1920 29 #define KMB_FB_MAX_HEIGHT 1080 30 #define KMB_FB_MIN_WIDTH 1 31 #define KMB_FB_MIN_HEIGHT 1 32 #define KMB_MIN_VREFRESH 59 /*vertical refresh in Hz */ 33 #define KMB_MAX_VREFRESH 60 /*vertical refresh in Hz */ 34 #define KMB_LCD_DEFAULT_CLK 200000000 35 #define KMB_SYS_CLK_MHZ 500 36 37 #define ICAM_MMIO 0x3b100000 38 #define ICAM_LCD_OFFSET 0x1080 39 #define ICAM_MMIO_SIZE 0x2000 40 41 struct kmb_dsi; 42 43 struct kmb_clock { 44 struct clk *clk_lcd; 45 struct clk *clk_pll0; 46 }; 47 48 struct kmb_drm_private { 49 struct drm_device drm; 50 struct kmb_dsi *kmb_dsi; 51 void __iomem *lcd_mmio; 52 struct kmb_clock kmb_clk; 53 struct drm_crtc crtc; 54 struct kmb_plane *plane; 55 struct drm_atomic_state *state; 56 spinlock_t irq_lock; 57 int irq_lcd; 58 int sys_clk_mhz; 59 struct disp_cfg init_disp_cfg[KMB_MAX_PLANES]; 60 struct layer_status plane_status[KMB_MAX_PLANES]; 61 int kmb_under_flow; 62 int kmb_flush_done; 63 int layer_no; 64 }; 65 66 static inline struct kmb_drm_private *to_kmb(const struct drm_device *dev) 67 { 68 return container_of(dev, struct kmb_drm_private, drm); 69 } 70 71 static inline struct kmb_drm_private *crtc_to_kmb_priv(const struct drm_crtc *x) 72 { 73 return container_of(x, struct kmb_drm_private, crtc); 74 } 75 76 static inline void kmb_write_lcd(struct kmb_drm_private *dev_p, 77 unsigned int reg, u32 value) 78 { 79 writel(value, (dev_p->lcd_mmio + reg)); 80 } 81 82 static inline u32 kmb_read_lcd(struct kmb_drm_private *dev_p, unsigned int reg) 83 { 84 return readl(dev_p->lcd_mmio + reg); 85 } 86 87 static inline void kmb_set_bitmask_lcd(struct kmb_drm_private *dev_p, 88 unsigned int reg, u32 mask) 89 { 90 u32 reg_val = kmb_read_lcd(dev_p, reg); 91 92 kmb_write_lcd(dev_p, reg, (reg_val | mask)); 93 } 94 95 static inline void kmb_clr_bitmask_lcd(struct kmb_drm_private *dev_p, 96 unsigned int reg, u32 mask) 97 { 98 u32 reg_val = kmb_read_lcd(dev_p, reg); 99 100 kmb_write_lcd(dev_p, reg, (reg_val & (~mask))); 101 } 102 103 int kmb_setup_crtc(struct drm_device *dev); 104 void kmb_set_scanout(struct kmb_drm_private *lcd); 105 #endif /* __KMB_DRV_H__ */ 106