1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright © 2018-2020 Intel Corporation 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/module.h> 8 #include <linux/of_graph.h> 9 #include <linux/of_platform.h> 10 #include <linux/of_reserved_mem.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/regmap.h> 15 16 #include <drm/drm_atomic_helper.h> 17 #include <drm/drm_drv.h> 18 #include <drm/drm_fb_helper.h> 19 #include <drm/drm_gem_cma_helper.h> 20 #include <drm/drm_gem_framebuffer_helper.h> 21 #include <drm/drm_probe_helper.h> 22 #include <drm/drm_vblank.h> 23 24 #include "kmb_drv.h" 25 #include "kmb_dsi.h" 26 #include "kmb_regs.h" 27 28 static int kmb_display_clk_enable(struct kmb_drm_private *kmb) 29 { 30 int ret = 0; 31 32 ret = clk_prepare_enable(kmb->kmb_clk.clk_lcd); 33 if (ret) { 34 drm_err(&kmb->drm, "Failed to enable LCD clock: %d\n", ret); 35 return ret; 36 } 37 DRM_INFO("SUCCESS : enabled LCD clocks\n"); 38 return 0; 39 } 40 41 static int kmb_initialize_clocks(struct kmb_drm_private *kmb, struct device *dev) 42 { 43 int ret = 0; 44 struct regmap *msscam; 45 46 kmb->kmb_clk.clk_lcd = devm_clk_get(dev, "clk_lcd"); 47 if (IS_ERR(kmb->kmb_clk.clk_lcd)) { 48 drm_err(&kmb->drm, "clk_get() failed clk_lcd\n"); 49 return PTR_ERR(kmb->kmb_clk.clk_lcd); 50 } 51 52 kmb->kmb_clk.clk_pll0 = devm_clk_get(dev, "clk_pll0"); 53 if (IS_ERR(kmb->kmb_clk.clk_pll0)) { 54 drm_err(&kmb->drm, "clk_get() failed clk_pll0 "); 55 return PTR_ERR(kmb->kmb_clk.clk_pll0); 56 } 57 kmb->sys_clk_mhz = clk_get_rate(kmb->kmb_clk.clk_pll0) / 1000000; 58 drm_info(&kmb->drm, "system clk = %d Mhz", kmb->sys_clk_mhz); 59 60 ret = kmb_dsi_clk_init(kmb->kmb_dsi); 61 62 /* Set LCD clock to 200 Mhz */ 63 clk_set_rate(kmb->kmb_clk.clk_lcd, KMB_LCD_DEFAULT_CLK); 64 if (clk_get_rate(kmb->kmb_clk.clk_lcd) != KMB_LCD_DEFAULT_CLK) { 65 drm_err(&kmb->drm, "failed to set to clk_lcd to %d\n", 66 KMB_LCD_DEFAULT_CLK); 67 return -1; 68 } 69 drm_dbg(&kmb->drm, "clk_lcd = %ld\n", clk_get_rate(kmb->kmb_clk.clk_lcd)); 70 71 ret = kmb_display_clk_enable(kmb); 72 if (ret) 73 return ret; 74 75 msscam = syscon_regmap_lookup_by_compatible("intel,keembay-msscam"); 76 if (IS_ERR(msscam)) { 77 drm_err(&kmb->drm, "failed to get msscam syscon"); 78 return -1; 79 } 80 81 /* Enable MSS_CAM_CLK_CTRL for MIPI TX and LCD */ 82 regmap_update_bits(msscam, MSS_CAM_CLK_CTRL, 0x1fff, 0x1fff); 83 regmap_update_bits(msscam, MSS_CAM_RSTN_CTRL, 0xffffffff, 0xffffffff); 84 return 0; 85 } 86 87 static void kmb_display_clk_disable(struct kmb_drm_private *kmb) 88 { 89 clk_disable_unprepare(kmb->kmb_clk.clk_lcd); 90 } 91 92 static void __iomem *kmb_map_mmio(struct drm_device *drm, 93 struct platform_device *pdev, 94 char *name) 95 { 96 struct resource *res; 97 void __iomem *mem; 98 99 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); 100 if (!res) { 101 drm_err(drm, "failed to get resource for %s", name); 102 return ERR_PTR(-ENOMEM); 103 } 104 mem = devm_ioremap_resource(drm->dev, res); 105 if (IS_ERR(mem)) 106 drm_err(drm, "failed to ioremap %s registers", name); 107 return mem; 108 } 109 110 static int kmb_hw_init(struct drm_device *drm, unsigned long flags) 111 { 112 struct kmb_drm_private *kmb = to_kmb(drm); 113 struct platform_device *pdev = to_platform_device(drm->dev); 114 int irq_lcd; 115 int ret = 0; 116 117 /* Map LCD MMIO registers */ 118 kmb->lcd_mmio = kmb_map_mmio(drm, pdev, "lcd"); 119 if (IS_ERR(kmb->lcd_mmio)) { 120 drm_err(&kmb->drm, "failed to map LCD registers\n"); 121 return -ENOMEM; 122 } 123 124 /* Map MIPI MMIO registers */ 125 ret = kmb_dsi_map_mmio(kmb->kmb_dsi); 126 if (ret) 127 return ret; 128 129 /* Enable display clocks */ 130 kmb_initialize_clocks(kmb, &pdev->dev); 131 132 /* Register irqs here - section 17.3 in databook 133 * lists LCD at 79 and 82 for MIPI under MSS CPU - 134 * firmware has redirected 79 to A53 IRQ 33 135 */ 136 137 /* Allocate LCD interrupt resources */ 138 irq_lcd = platform_get_irq(pdev, 0); 139 if (irq_lcd < 0) { 140 ret = irq_lcd; 141 drm_err(&kmb->drm, "irq_lcd not found"); 142 goto setup_fail; 143 } 144 145 /* Get the optional framebuffer memory resource */ 146 ret = of_reserved_mem_device_init(drm->dev); 147 if (ret && ret != -ENODEV) 148 return ret; 149 150 spin_lock_init(&kmb->irq_lock); 151 152 kmb->irq_lcd = irq_lcd; 153 154 return 0; 155 156 setup_fail: 157 of_reserved_mem_device_release(drm->dev); 158 159 return ret; 160 } 161 162 static const struct drm_mode_config_funcs kmb_mode_config_funcs = { 163 .fb_create = drm_gem_fb_create, 164 .atomic_check = drm_atomic_helper_check, 165 .atomic_commit = drm_atomic_helper_commit, 166 }; 167 168 static int kmb_setup_mode_config(struct drm_device *drm) 169 { 170 int ret; 171 struct kmb_drm_private *kmb = to_kmb(drm); 172 173 ret = drmm_mode_config_init(drm); 174 if (ret) 175 return ret; 176 drm->mode_config.min_width = KMB_FB_MIN_WIDTH; 177 drm->mode_config.min_height = KMB_FB_MIN_HEIGHT; 178 drm->mode_config.max_width = KMB_FB_MAX_WIDTH; 179 drm->mode_config.max_height = KMB_FB_MAX_HEIGHT; 180 drm->mode_config.preferred_depth = 24; 181 drm->mode_config.funcs = &kmb_mode_config_funcs; 182 183 ret = kmb_setup_crtc(drm); 184 if (ret < 0) { 185 drm_err(drm, "failed to create crtc\n"); 186 return ret; 187 } 188 ret = kmb_dsi_encoder_init(drm, kmb->kmb_dsi); 189 /* Set the CRTC's port so that the encoder component can find it */ 190 kmb->crtc.port = of_graph_get_port_by_id(drm->dev->of_node, 0); 191 ret = drm_vblank_init(drm, drm->mode_config.num_crtc); 192 if (ret < 0) { 193 drm_err(drm, "failed to initialize vblank\n"); 194 pm_runtime_disable(drm->dev); 195 return ret; 196 } 197 198 drm_mode_config_reset(drm); 199 return 0; 200 } 201 202 static irqreturn_t handle_lcd_irq(struct drm_device *dev) 203 { 204 unsigned long status, val, val1; 205 int plane_id, dma0_state, dma1_state; 206 struct kmb_drm_private *kmb = to_kmb(dev); 207 u32 ctrl = 0; 208 209 status = kmb_read_lcd(kmb, LCD_INT_STATUS); 210 211 spin_lock(&kmb->irq_lock); 212 if (status & LCD_INT_EOF) { 213 kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_EOF); 214 215 /* When disabling/enabling LCD layers, the change takes effect 216 * immediately and does not wait for EOF (end of frame). 217 * When kmb_plane_atomic_disable is called, mark the plane as 218 * disabled but actually disable the plane when EOF irq is 219 * being handled. 220 */ 221 for (plane_id = LAYER_0; 222 plane_id < KMB_MAX_PLANES; plane_id++) { 223 if (kmb->plane_status[plane_id].disable) { 224 kmb_clr_bitmask_lcd(kmb, 225 LCD_LAYERn_DMA_CFG 226 (plane_id), 227 LCD_DMA_LAYER_ENABLE); 228 229 kmb_clr_bitmask_lcd(kmb, LCD_CONTROL, 230 kmb->plane_status[plane_id].ctrl); 231 232 ctrl = kmb_read_lcd(kmb, LCD_CONTROL); 233 if (!(ctrl & (LCD_CTRL_VL1_ENABLE | 234 LCD_CTRL_VL2_ENABLE | 235 LCD_CTRL_GL1_ENABLE | 236 LCD_CTRL_GL2_ENABLE))) { 237 /* If no LCD layers are using DMA, 238 * then disable DMA pipelined AXI read 239 * transactions. 240 */ 241 kmb_clr_bitmask_lcd(kmb, LCD_CONTROL, 242 LCD_CTRL_PIPELINE_DMA); 243 } 244 245 kmb->plane_status[plane_id].disable = false; 246 } 247 } 248 if (kmb->kmb_under_flow) { 249 /* DMA Recovery after underflow */ 250 dma0_state = (kmb->layer_no == 0) ? 251 LCD_VIDEO0_DMA0_STATE : LCD_VIDEO1_DMA0_STATE; 252 dma1_state = (kmb->layer_no == 0) ? 253 LCD_VIDEO0_DMA1_STATE : LCD_VIDEO1_DMA1_STATE; 254 255 do { 256 kmb_write_lcd(kmb, LCD_FIFO_FLUSH, 1); 257 val = kmb_read_lcd(kmb, dma0_state) 258 & LCD_DMA_STATE_ACTIVE; 259 val1 = kmb_read_lcd(kmb, dma1_state) 260 & LCD_DMA_STATE_ACTIVE; 261 } while ((val || val1)); 262 /* disable dma */ 263 kmb_clr_bitmask_lcd(kmb, 264 LCD_LAYERn_DMA_CFG(kmb->layer_no), 265 LCD_DMA_LAYER_ENABLE); 266 kmb_write_lcd(kmb, LCD_FIFO_FLUSH, 1); 267 kmb->kmb_flush_done = 1; 268 kmb->kmb_under_flow = 0; 269 } 270 } 271 272 if (status & LCD_INT_LINE_CMP) { 273 /* clear line compare interrupt */ 274 kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_LINE_CMP); 275 } 276 277 if (status & LCD_INT_VERT_COMP) { 278 /* Read VSTATUS */ 279 val = kmb_read_lcd(kmb, LCD_VSTATUS); 280 val = (val & LCD_VSTATUS_VERTICAL_STATUS_MASK); 281 switch (val) { 282 case LCD_VSTATUS_COMPARE_VSYNC: 283 /* Clear vertical compare interrupt */ 284 kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_VERT_COMP); 285 if (kmb->kmb_flush_done) { 286 kmb_set_bitmask_lcd(kmb, 287 LCD_LAYERn_DMA_CFG 288 (kmb->layer_no), 289 LCD_DMA_LAYER_ENABLE); 290 kmb->kmb_flush_done = 0; 291 } 292 drm_crtc_handle_vblank(&kmb->crtc); 293 break; 294 case LCD_VSTATUS_COMPARE_BACKPORCH: 295 case LCD_VSTATUS_COMPARE_ACTIVE: 296 case LCD_VSTATUS_COMPARE_FRONT_PORCH: 297 kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_VERT_COMP); 298 break; 299 } 300 } 301 if (status & LCD_INT_DMA_ERR) { 302 val = 303 (status & LCD_INT_DMA_ERR & 304 kmb_read_lcd(kmb, LCD_INT_ENABLE)); 305 /* LAYER0 - VL0 */ 306 if (val & (LAYER0_DMA_FIFO_UNDERFLOW | 307 LAYER0_DMA_CB_FIFO_UNDERFLOW | 308 LAYER0_DMA_CR_FIFO_UNDERFLOW)) { 309 kmb->kmb_under_flow++; 310 drm_info(&kmb->drm, 311 "!LAYER0:VL0 DMA UNDERFLOW val = 0x%lx,under_flow=%d", 312 val, kmb->kmb_under_flow); 313 /* disable underflow interrupt */ 314 kmb_clr_bitmask_lcd(kmb, LCD_INT_ENABLE, 315 LAYER0_DMA_FIFO_UNDERFLOW | 316 LAYER0_DMA_CB_FIFO_UNDERFLOW | 317 LAYER0_DMA_CR_FIFO_UNDERFLOW); 318 kmb_set_bitmask_lcd(kmb, LCD_INT_CLEAR, 319 LAYER0_DMA_CB_FIFO_UNDERFLOW | 320 LAYER0_DMA_FIFO_UNDERFLOW | 321 LAYER0_DMA_CR_FIFO_UNDERFLOW); 322 /* disable auto restart mode */ 323 kmb_clr_bitmask_lcd(kmb, LCD_LAYERn_DMA_CFG(0), 324 LCD_DMA_LAYER_CONT_PING_PONG_UPDATE); 325 326 kmb->layer_no = 0; 327 } 328 329 if (val & LAYER0_DMA_FIFO_OVERFLOW) 330 drm_dbg(&kmb->drm, 331 "LAYER0:VL0 DMA OVERFLOW val = 0x%lx", val); 332 if (val & LAYER0_DMA_CB_FIFO_OVERFLOW) 333 drm_dbg(&kmb->drm, 334 "LAYER0:VL0 DMA CB OVERFLOW val = 0x%lx", val); 335 if (val & LAYER0_DMA_CR_FIFO_OVERFLOW) 336 drm_dbg(&kmb->drm, 337 "LAYER0:VL0 DMA CR OVERFLOW val = 0x%lx", val); 338 339 /* LAYER1 - VL1 */ 340 if (val & (LAYER1_DMA_FIFO_UNDERFLOW | 341 LAYER1_DMA_CB_FIFO_UNDERFLOW | 342 LAYER1_DMA_CR_FIFO_UNDERFLOW)) { 343 kmb->kmb_under_flow++; 344 drm_info(&kmb->drm, 345 "!LAYER1:VL1 DMA UNDERFLOW val = 0x%lx, under_flow=%d", 346 val, kmb->kmb_under_flow); 347 /* disable underflow interrupt */ 348 kmb_clr_bitmask_lcd(kmb, LCD_INT_ENABLE, 349 LAYER1_DMA_FIFO_UNDERFLOW | 350 LAYER1_DMA_CB_FIFO_UNDERFLOW | 351 LAYER1_DMA_CR_FIFO_UNDERFLOW); 352 kmb_set_bitmask_lcd(kmb, LCD_INT_CLEAR, 353 LAYER1_DMA_CB_FIFO_UNDERFLOW | 354 LAYER1_DMA_FIFO_UNDERFLOW | 355 LAYER1_DMA_CR_FIFO_UNDERFLOW); 356 /* disable auto restart mode */ 357 kmb_clr_bitmask_lcd(kmb, LCD_LAYERn_DMA_CFG(1), 358 LCD_DMA_LAYER_CONT_PING_PONG_UPDATE); 359 kmb->layer_no = 1; 360 } 361 362 /* LAYER1 - VL1 */ 363 if (val & LAYER1_DMA_FIFO_OVERFLOW) 364 drm_dbg(&kmb->drm, 365 "LAYER1:VL1 DMA OVERFLOW val = 0x%lx", val); 366 if (val & LAYER1_DMA_CB_FIFO_OVERFLOW) 367 drm_dbg(&kmb->drm, 368 "LAYER1:VL1 DMA CB OVERFLOW val = 0x%lx", val); 369 if (val & LAYER1_DMA_CR_FIFO_OVERFLOW) 370 drm_dbg(&kmb->drm, 371 "LAYER1:VL1 DMA CR OVERFLOW val = 0x%lx", val); 372 373 /* LAYER2 - GL0 */ 374 if (val & LAYER2_DMA_FIFO_UNDERFLOW) 375 drm_dbg(&kmb->drm, 376 "LAYER2:GL0 DMA UNDERFLOW val = 0x%lx", val); 377 if (val & LAYER2_DMA_FIFO_OVERFLOW) 378 drm_dbg(&kmb->drm, 379 "LAYER2:GL0 DMA OVERFLOW val = 0x%lx", val); 380 381 /* LAYER3 - GL1 */ 382 if (val & LAYER3_DMA_FIFO_UNDERFLOW) 383 drm_dbg(&kmb->drm, 384 "LAYER3:GL1 DMA UNDERFLOW val = 0x%lx", val); 385 if (val & LAYER3_DMA_FIFO_OVERFLOW) 386 drm_dbg(&kmb->drm, 387 "LAYER3:GL1 DMA OVERFLOW val = 0x%lx", val); 388 } 389 390 spin_unlock(&kmb->irq_lock); 391 392 if (status & LCD_INT_LAYER) { 393 /* Clear layer interrupts */ 394 kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_LAYER); 395 } 396 397 /* Clear all interrupts */ 398 kmb_set_bitmask_lcd(kmb, LCD_INT_CLEAR, 1); 399 return IRQ_HANDLED; 400 } 401 402 /* IRQ handler */ 403 static irqreturn_t kmb_isr(int irq, void *arg) 404 { 405 struct drm_device *dev = (struct drm_device *)arg; 406 407 handle_lcd_irq(dev); 408 return IRQ_HANDLED; 409 } 410 411 static void kmb_irq_reset(struct drm_device *drm) 412 { 413 kmb_write_lcd(to_kmb(drm), LCD_INT_CLEAR, 0xFFFF); 414 kmb_write_lcd(to_kmb(drm), LCD_INT_ENABLE, 0); 415 } 416 417 static int kmb_irq_install(struct drm_device *drm, unsigned int irq) 418 { 419 if (irq == IRQ_NOTCONNECTED) 420 return -ENOTCONN; 421 422 kmb_irq_reset(drm); 423 424 return request_irq(irq, kmb_isr, 0, drm->driver->name, drm); 425 } 426 427 static void kmb_irq_uninstall(struct drm_device *drm) 428 { 429 struct kmb_drm_private *kmb = to_kmb(drm); 430 431 kmb_irq_reset(drm); 432 free_irq(kmb->irq_lcd, drm); 433 } 434 435 DEFINE_DRM_GEM_CMA_FOPS(fops); 436 437 static const struct drm_driver kmb_driver = { 438 .driver_features = DRIVER_GEM | 439 DRIVER_MODESET | DRIVER_ATOMIC, 440 /* GEM Operations */ 441 .fops = &fops, 442 DRM_GEM_CMA_DRIVER_OPS_VMAP, 443 .name = "kmb-drm", 444 .desc = "KEEMBAY DISPLAY DRIVER", 445 .date = DRIVER_DATE, 446 .major = DRIVER_MAJOR, 447 .minor = DRIVER_MINOR, 448 }; 449 450 static int kmb_remove(struct platform_device *pdev) 451 { 452 struct device *dev = &pdev->dev; 453 struct drm_device *drm = dev_get_drvdata(dev); 454 struct kmb_drm_private *kmb = to_kmb(drm); 455 456 drm_dev_unregister(drm); 457 drm_kms_helper_poll_fini(drm); 458 of_node_put(kmb->crtc.port); 459 kmb->crtc.port = NULL; 460 pm_runtime_get_sync(drm->dev); 461 kmb_irq_uninstall(drm); 462 pm_runtime_put_sync(drm->dev); 463 pm_runtime_disable(drm->dev); 464 465 of_reserved_mem_device_release(drm->dev); 466 467 /* Release clks */ 468 kmb_display_clk_disable(kmb); 469 470 dev_set_drvdata(dev, NULL); 471 472 /* Unregister DSI host */ 473 kmb_dsi_host_unregister(kmb->kmb_dsi); 474 drm_atomic_helper_shutdown(drm); 475 return 0; 476 } 477 478 static int kmb_probe(struct platform_device *pdev) 479 { 480 struct device *dev = get_device(&pdev->dev); 481 struct kmb_drm_private *kmb; 482 int ret = 0; 483 struct device_node *dsi_in; 484 struct device_node *dsi_node; 485 struct platform_device *dsi_pdev; 486 487 /* The bridge (ADV 7535) will return -EPROBE_DEFER until it 488 * has a mipi_dsi_host to register its device to. So, we 489 * first register the DSI host during probe time, and then return 490 * -EPROBE_DEFER until the bridge is loaded. Probe will be called again 491 * and then the rest of the driver initialization can proceed 492 * afterwards and the bridge can be successfully attached. 493 */ 494 dsi_in = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0); 495 if (!dsi_in) { 496 DRM_ERROR("Failed to get dsi_in node info from DT"); 497 return -EINVAL; 498 } 499 dsi_node = of_graph_get_remote_port_parent(dsi_in); 500 if (!dsi_node) { 501 of_node_put(dsi_in); 502 DRM_ERROR("Failed to get dsi node from DT\n"); 503 return -EINVAL; 504 } 505 506 dsi_pdev = of_find_device_by_node(dsi_node); 507 if (!dsi_pdev) { 508 of_node_put(dsi_in); 509 of_node_put(dsi_node); 510 DRM_ERROR("Failed to get dsi platform device\n"); 511 return -EINVAL; 512 } 513 514 of_node_put(dsi_in); 515 of_node_put(dsi_node); 516 ret = kmb_dsi_host_bridge_init(get_device(&dsi_pdev->dev)); 517 518 if (ret == -EPROBE_DEFER) { 519 return -EPROBE_DEFER; 520 } else if (ret) { 521 DRM_ERROR("probe failed to initialize DSI host bridge\n"); 522 return ret; 523 } 524 525 /* Create DRM device */ 526 kmb = devm_drm_dev_alloc(dev, &kmb_driver, 527 struct kmb_drm_private, drm); 528 if (IS_ERR(kmb)) 529 return PTR_ERR(kmb); 530 531 dev_set_drvdata(dev, &kmb->drm); 532 533 /* Initialize MIPI DSI */ 534 kmb->kmb_dsi = kmb_dsi_init(dsi_pdev); 535 if (IS_ERR(kmb->kmb_dsi)) { 536 drm_err(&kmb->drm, "failed to initialize DSI\n"); 537 ret = PTR_ERR(kmb->kmb_dsi); 538 goto err_free1; 539 } 540 541 kmb->kmb_dsi->dev = &dsi_pdev->dev; 542 kmb->kmb_dsi->pdev = dsi_pdev; 543 ret = kmb_hw_init(&kmb->drm, 0); 544 if (ret) 545 goto err_free1; 546 547 ret = kmb_setup_mode_config(&kmb->drm); 548 if (ret) 549 goto err_free; 550 551 ret = kmb_irq_install(&kmb->drm, kmb->irq_lcd); 552 if (ret < 0) { 553 drm_err(&kmb->drm, "failed to install IRQ handler\n"); 554 goto err_irq; 555 } 556 557 drm_kms_helper_poll_init(&kmb->drm); 558 559 /* Register graphics device with the kernel */ 560 ret = drm_dev_register(&kmb->drm, 0); 561 if (ret) 562 goto err_register; 563 564 drm_fbdev_generic_setup(&kmb->drm, 0); 565 566 return 0; 567 568 err_register: 569 drm_kms_helper_poll_fini(&kmb->drm); 570 err_irq: 571 pm_runtime_disable(kmb->drm.dev); 572 err_free: 573 drm_crtc_cleanup(&kmb->crtc); 574 drm_mode_config_cleanup(&kmb->drm); 575 err_free1: 576 dev_set_drvdata(dev, NULL); 577 kmb_dsi_host_unregister(kmb->kmb_dsi); 578 579 return ret; 580 } 581 582 static const struct of_device_id kmb_of_match[] = { 583 {.compatible = "intel,keembay-display"}, 584 {}, 585 }; 586 587 MODULE_DEVICE_TABLE(of, kmb_of_match); 588 589 static int __maybe_unused kmb_pm_suspend(struct device *dev) 590 { 591 struct drm_device *drm = dev_get_drvdata(dev); 592 struct kmb_drm_private *kmb = to_kmb(drm); 593 594 drm_kms_helper_poll_disable(drm); 595 596 kmb->state = drm_atomic_helper_suspend(drm); 597 if (IS_ERR(kmb->state)) { 598 drm_kms_helper_poll_enable(drm); 599 return PTR_ERR(kmb->state); 600 } 601 602 return 0; 603 } 604 605 static int __maybe_unused kmb_pm_resume(struct device *dev) 606 { 607 struct drm_device *drm = dev_get_drvdata(dev); 608 struct kmb_drm_private *kmb = drm ? to_kmb(drm) : NULL; 609 610 if (!kmb) 611 return 0; 612 613 drm_atomic_helper_resume(drm, kmb->state); 614 drm_kms_helper_poll_enable(drm); 615 616 return 0; 617 } 618 619 static SIMPLE_DEV_PM_OPS(kmb_pm_ops, kmb_pm_suspend, kmb_pm_resume); 620 621 static struct platform_driver kmb_platform_driver = { 622 .probe = kmb_probe, 623 .remove = kmb_remove, 624 .driver = { 625 .name = "kmb-drm", 626 .pm = &kmb_pm_ops, 627 .of_match_table = kmb_of_match, 628 }, 629 }; 630 631 module_platform_driver(kmb_platform_driver); 632 633 MODULE_AUTHOR("Intel Corporation"); 634 MODULE_DESCRIPTION("Keembay Display driver"); 635 MODULE_LICENSE("GPL v2"); 636