1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright © 2018-2020 Intel Corporation 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/module.h> 8 #include <linux/of_graph.h> 9 #include <linux/of_platform.h> 10 #include <linux/of_reserved_mem.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/regmap.h> 15 16 #include <drm/drm_atomic_helper.h> 17 #include <drm/drm_drv.h> 18 #include <drm/drm_gem_cma_helper.h> 19 #include <drm/drm_gem_framebuffer_helper.h> 20 #include <drm/drm_irq.h> 21 #include <drm/drm_probe_helper.h> 22 #include <drm/drm_vblank.h> 23 24 #include "kmb_drv.h" 25 #include "kmb_dsi.h" 26 #include "kmb_regs.h" 27 28 static int kmb_display_clk_enable(struct kmb_drm_private *kmb) 29 { 30 int ret = 0; 31 32 ret = clk_prepare_enable(kmb->kmb_clk.clk_lcd); 33 if (ret) { 34 drm_err(&kmb->drm, "Failed to enable LCD clock: %d\n", ret); 35 return ret; 36 } 37 DRM_INFO("SUCCESS : enabled LCD clocks\n"); 38 return 0; 39 } 40 41 static int kmb_initialize_clocks(struct kmb_drm_private *kmb, struct device *dev) 42 { 43 int ret = 0; 44 struct regmap *msscam; 45 46 kmb->kmb_clk.clk_lcd = devm_clk_get(dev, "clk_lcd"); 47 if (IS_ERR(kmb->kmb_clk.clk_lcd)) { 48 drm_err(&kmb->drm, "clk_get() failed clk_lcd\n"); 49 return PTR_ERR(kmb->kmb_clk.clk_lcd); 50 } 51 52 kmb->kmb_clk.clk_pll0 = devm_clk_get(dev, "clk_pll0"); 53 if (IS_ERR(kmb->kmb_clk.clk_pll0)) { 54 drm_err(&kmb->drm, "clk_get() failed clk_pll0 "); 55 return PTR_ERR(kmb->kmb_clk.clk_pll0); 56 } 57 kmb->sys_clk_mhz = clk_get_rate(kmb->kmb_clk.clk_pll0) / 1000000; 58 drm_info(&kmb->drm, "system clk = %d Mhz", kmb->sys_clk_mhz); 59 60 ret = kmb_dsi_clk_init(kmb->kmb_dsi); 61 62 /* Set LCD clock to 200 Mhz */ 63 clk_set_rate(kmb->kmb_clk.clk_lcd, KMB_LCD_DEFAULT_CLK); 64 if (clk_get_rate(kmb->kmb_clk.clk_lcd) != KMB_LCD_DEFAULT_CLK) { 65 drm_err(&kmb->drm, "failed to set to clk_lcd to %d\n", 66 KMB_LCD_DEFAULT_CLK); 67 return -1; 68 } 69 drm_dbg(&kmb->drm, "clk_lcd = %ld\n", clk_get_rate(kmb->kmb_clk.clk_lcd)); 70 71 ret = kmb_display_clk_enable(kmb); 72 if (ret) 73 return ret; 74 75 msscam = syscon_regmap_lookup_by_compatible("intel,keembay-msscam"); 76 if (IS_ERR(msscam)) { 77 drm_err(&kmb->drm, "failed to get msscam syscon"); 78 return -1; 79 } 80 81 /* Enable MSS_CAM_CLK_CTRL for MIPI TX and LCD */ 82 regmap_update_bits(msscam, MSS_CAM_CLK_CTRL, 0x1fff, 0x1fff); 83 regmap_update_bits(msscam, MSS_CAM_RSTN_CTRL, 0xffffffff, 0xffffffff); 84 return 0; 85 } 86 87 static void kmb_display_clk_disable(struct kmb_drm_private *kmb) 88 { 89 clk_disable_unprepare(kmb->kmb_clk.clk_lcd); 90 } 91 92 static void __iomem *kmb_map_mmio(struct drm_device *drm, 93 struct platform_device *pdev, 94 char *name) 95 { 96 struct resource *res; 97 void __iomem *mem; 98 99 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); 100 if (!res) { 101 drm_err(drm, "failed to get resource for %s", name); 102 return ERR_PTR(-ENOMEM); 103 } 104 mem = devm_ioremap_resource(drm->dev, res); 105 if (IS_ERR(mem)) 106 drm_err(drm, "failed to ioremap %s registers", name); 107 return mem; 108 } 109 110 static int kmb_hw_init(struct drm_device *drm, unsigned long flags) 111 { 112 struct kmb_drm_private *kmb = to_kmb(drm); 113 struct platform_device *pdev = to_platform_device(drm->dev); 114 int irq_lcd; 115 int ret = 0; 116 117 /* Map LCD MMIO registers */ 118 kmb->lcd_mmio = kmb_map_mmio(drm, pdev, "lcd"); 119 if (IS_ERR(kmb->lcd_mmio)) { 120 drm_err(&kmb->drm, "failed to map LCD registers\n"); 121 return -ENOMEM; 122 } 123 124 /* Map MIPI MMIO registers */ 125 ret = kmb_dsi_map_mmio(kmb->kmb_dsi); 126 if (ret) 127 return ret; 128 129 /* Enable display clocks */ 130 kmb_initialize_clocks(kmb, &pdev->dev); 131 132 /* Register irqs here - section 17.3 in databook 133 * lists LCD at 79 and 82 for MIPI under MSS CPU - 134 * firmware has redirected 79 to A53 IRQ 33 135 */ 136 137 /* Allocate LCD interrupt resources */ 138 irq_lcd = platform_get_irq(pdev, 0); 139 if (irq_lcd < 0) { 140 ret = irq_lcd; 141 drm_err(&kmb->drm, "irq_lcd not found"); 142 goto setup_fail; 143 } 144 145 /* Get the optional framebuffer memory resource */ 146 ret = of_reserved_mem_device_init(drm->dev); 147 if (ret && ret != -ENODEV) 148 return ret; 149 150 spin_lock_init(&kmb->irq_lock); 151 152 kmb->irq_lcd = irq_lcd; 153 154 return 0; 155 156 setup_fail: 157 of_reserved_mem_device_release(drm->dev); 158 159 return ret; 160 } 161 162 static const struct drm_mode_config_funcs kmb_mode_config_funcs = { 163 .fb_create = drm_gem_fb_create, 164 .atomic_check = drm_atomic_helper_check, 165 .atomic_commit = drm_atomic_helper_commit, 166 }; 167 168 static int kmb_setup_mode_config(struct drm_device *drm) 169 { 170 int ret; 171 struct kmb_drm_private *kmb = to_kmb(drm); 172 173 ret = drmm_mode_config_init(drm); 174 if (ret) 175 return ret; 176 drm->mode_config.min_width = KMB_MIN_WIDTH; 177 drm->mode_config.min_height = KMB_MIN_HEIGHT; 178 drm->mode_config.max_width = KMB_MAX_WIDTH; 179 drm->mode_config.max_height = KMB_MAX_HEIGHT; 180 drm->mode_config.funcs = &kmb_mode_config_funcs; 181 182 ret = kmb_setup_crtc(drm); 183 if (ret < 0) { 184 drm_err(drm, "failed to create crtc\n"); 185 return ret; 186 } 187 ret = kmb_dsi_encoder_init(drm, kmb->kmb_dsi); 188 /* Set the CRTC's port so that the encoder component can find it */ 189 kmb->crtc.port = of_graph_get_port_by_id(drm->dev->of_node, 0); 190 ret = drm_vblank_init(drm, drm->mode_config.num_crtc); 191 if (ret < 0) { 192 drm_err(drm, "failed to initialize vblank\n"); 193 pm_runtime_disable(drm->dev); 194 return ret; 195 } 196 197 drm_mode_config_reset(drm); 198 return 0; 199 } 200 201 static irqreturn_t handle_lcd_irq(struct drm_device *dev) 202 { 203 unsigned long status, val, val1; 204 int plane_id, dma0_state, dma1_state; 205 struct kmb_drm_private *kmb = to_kmb(dev); 206 207 status = kmb_read_lcd(kmb, LCD_INT_STATUS); 208 209 spin_lock(&kmb->irq_lock); 210 if (status & LCD_INT_EOF) { 211 kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_EOF); 212 213 /* When disabling/enabling LCD layers, the change takes effect 214 * immediately and does not wait for EOF (end of frame). 215 * When kmb_plane_atomic_disable is called, mark the plane as 216 * disabled but actually disable the plane when EOF irq is 217 * being handled. 218 */ 219 for (plane_id = LAYER_0; 220 plane_id < KMB_MAX_PLANES; plane_id++) { 221 if (kmb->plane_status[plane_id].disable) { 222 kmb_clr_bitmask_lcd(kmb, 223 LCD_LAYERn_DMA_CFG 224 (plane_id), 225 LCD_DMA_LAYER_ENABLE); 226 227 kmb_clr_bitmask_lcd(kmb, LCD_CONTROL, 228 kmb->plane_status[plane_id].ctrl); 229 230 kmb->plane_status[plane_id].disable = false; 231 } 232 } 233 if (kmb->kmb_under_flow) { 234 /* DMA Recovery after underflow */ 235 dma0_state = (kmb->layer_no == 0) ? 236 LCD_VIDEO0_DMA0_STATE : LCD_VIDEO1_DMA0_STATE; 237 dma1_state = (kmb->layer_no == 0) ? 238 LCD_VIDEO0_DMA1_STATE : LCD_VIDEO1_DMA1_STATE; 239 240 do { 241 kmb_write_lcd(kmb, LCD_FIFO_FLUSH, 1); 242 val = kmb_read_lcd(kmb, dma0_state) 243 & LCD_DMA_STATE_ACTIVE; 244 val1 = kmb_read_lcd(kmb, dma1_state) 245 & LCD_DMA_STATE_ACTIVE; 246 } while ((val || val1)); 247 /* disable dma */ 248 kmb_clr_bitmask_lcd(kmb, 249 LCD_LAYERn_DMA_CFG(kmb->layer_no), 250 LCD_DMA_LAYER_ENABLE); 251 kmb_write_lcd(kmb, LCD_FIFO_FLUSH, 1); 252 kmb->kmb_flush_done = 1; 253 kmb->kmb_under_flow = 0; 254 } 255 } 256 257 if (status & LCD_INT_LINE_CMP) { 258 /* clear line compare interrupt */ 259 kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_LINE_CMP); 260 } 261 262 if (status & LCD_INT_VERT_COMP) { 263 /* Read VSTATUS */ 264 val = kmb_read_lcd(kmb, LCD_VSTATUS); 265 val = (val & LCD_VSTATUS_VERTICAL_STATUS_MASK); 266 switch (val) { 267 case LCD_VSTATUS_COMPARE_VSYNC: 268 /* Clear vertical compare interrupt */ 269 kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_VERT_COMP); 270 if (kmb->kmb_flush_done) { 271 kmb_set_bitmask_lcd(kmb, 272 LCD_LAYERn_DMA_CFG 273 (kmb->layer_no), 274 LCD_DMA_LAYER_ENABLE); 275 kmb->kmb_flush_done = 0; 276 } 277 drm_crtc_handle_vblank(&kmb->crtc); 278 break; 279 case LCD_VSTATUS_COMPARE_BACKPORCH: 280 case LCD_VSTATUS_COMPARE_ACTIVE: 281 case LCD_VSTATUS_COMPARE_FRONT_PORCH: 282 kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_VERT_COMP); 283 break; 284 } 285 } 286 if (status & LCD_INT_DMA_ERR) { 287 val = 288 (status & LCD_INT_DMA_ERR & 289 kmb_read_lcd(kmb, LCD_INT_ENABLE)); 290 /* LAYER0 - VL0 */ 291 if (val & (LAYER0_DMA_FIFO_UNDERFLOW | 292 LAYER0_DMA_CB_FIFO_UNDERFLOW | 293 LAYER0_DMA_CR_FIFO_UNDERFLOW)) { 294 kmb->kmb_under_flow++; 295 drm_info(&kmb->drm, 296 "!LAYER0:VL0 DMA UNDERFLOW val = 0x%lx,under_flow=%d", 297 val, kmb->kmb_under_flow); 298 /* disable underflow interrupt */ 299 kmb_clr_bitmask_lcd(kmb, LCD_INT_ENABLE, 300 LAYER0_DMA_FIFO_UNDERFLOW | 301 LAYER0_DMA_CB_FIFO_UNDERFLOW | 302 LAYER0_DMA_CR_FIFO_UNDERFLOW); 303 kmb_set_bitmask_lcd(kmb, LCD_INT_CLEAR, 304 LAYER0_DMA_CB_FIFO_UNDERFLOW | 305 LAYER0_DMA_FIFO_UNDERFLOW | 306 LAYER0_DMA_CR_FIFO_UNDERFLOW); 307 /* disable auto restart mode */ 308 kmb_clr_bitmask_lcd(kmb, LCD_LAYERn_DMA_CFG(0), 309 LCD_DMA_LAYER_CONT_PING_PONG_UPDATE); 310 311 kmb->layer_no = 0; 312 } 313 314 if (val & LAYER0_DMA_FIFO_OVERFLOW) 315 drm_dbg(&kmb->drm, 316 "LAYER0:VL0 DMA OVERFLOW val = 0x%lx", val); 317 if (val & LAYER0_DMA_CB_FIFO_OVERFLOW) 318 drm_dbg(&kmb->drm, 319 "LAYER0:VL0 DMA CB OVERFLOW val = 0x%lx", val); 320 if (val & LAYER0_DMA_CR_FIFO_OVERFLOW) 321 drm_dbg(&kmb->drm, 322 "LAYER0:VL0 DMA CR OVERFLOW val = 0x%lx", val); 323 324 /* LAYER1 - VL1 */ 325 if (val & (LAYER1_DMA_FIFO_UNDERFLOW | 326 LAYER1_DMA_CB_FIFO_UNDERFLOW | 327 LAYER1_DMA_CR_FIFO_UNDERFLOW)) { 328 kmb->kmb_under_flow++; 329 drm_info(&kmb->drm, 330 "!LAYER1:VL1 DMA UNDERFLOW val = 0x%lx, under_flow=%d", 331 val, kmb->kmb_under_flow); 332 /* disable underflow interrupt */ 333 kmb_clr_bitmask_lcd(kmb, LCD_INT_ENABLE, 334 LAYER1_DMA_FIFO_UNDERFLOW | 335 LAYER1_DMA_CB_FIFO_UNDERFLOW | 336 LAYER1_DMA_CR_FIFO_UNDERFLOW); 337 kmb_set_bitmask_lcd(kmb, LCD_INT_CLEAR, 338 LAYER1_DMA_CB_FIFO_UNDERFLOW | 339 LAYER1_DMA_FIFO_UNDERFLOW | 340 LAYER1_DMA_CR_FIFO_UNDERFLOW); 341 /* disable auto restart mode */ 342 kmb_clr_bitmask_lcd(kmb, LCD_LAYERn_DMA_CFG(1), 343 LCD_DMA_LAYER_CONT_PING_PONG_UPDATE); 344 kmb->layer_no = 1; 345 } 346 347 /* LAYER1 - VL1 */ 348 if (val & LAYER1_DMA_FIFO_OVERFLOW) 349 drm_dbg(&kmb->drm, 350 "LAYER1:VL1 DMA OVERFLOW val = 0x%lx", val); 351 if (val & LAYER1_DMA_CB_FIFO_OVERFLOW) 352 drm_dbg(&kmb->drm, 353 "LAYER1:VL1 DMA CB OVERFLOW val = 0x%lx", val); 354 if (val & LAYER1_DMA_CR_FIFO_OVERFLOW) 355 drm_dbg(&kmb->drm, 356 "LAYER1:VL1 DMA CR OVERFLOW val = 0x%lx", val); 357 358 /* LAYER2 - GL0 */ 359 if (val & LAYER2_DMA_FIFO_UNDERFLOW) 360 drm_dbg(&kmb->drm, 361 "LAYER2:GL0 DMA UNDERFLOW val = 0x%lx", val); 362 if (val & LAYER2_DMA_FIFO_OVERFLOW) 363 drm_dbg(&kmb->drm, 364 "LAYER2:GL0 DMA OVERFLOW val = 0x%lx", val); 365 366 /* LAYER3 - GL1 */ 367 if (val & LAYER3_DMA_FIFO_UNDERFLOW) 368 drm_dbg(&kmb->drm, 369 "LAYER3:GL1 DMA UNDERFLOW val = 0x%lx", val); 370 if (val & LAYER3_DMA_FIFO_UNDERFLOW) 371 drm_dbg(&kmb->drm, 372 "LAYER3:GL1 DMA OVERFLOW val = 0x%lx", val); 373 } 374 375 spin_unlock(&kmb->irq_lock); 376 377 if (status & LCD_INT_LAYER) { 378 /* Clear layer interrupts */ 379 kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_LAYER); 380 } 381 382 /* Clear all interrupts */ 383 kmb_set_bitmask_lcd(kmb, LCD_INT_CLEAR, 1); 384 return IRQ_HANDLED; 385 } 386 387 /* IRQ handler */ 388 static irqreturn_t kmb_isr(int irq, void *arg) 389 { 390 struct drm_device *dev = (struct drm_device *)arg; 391 392 handle_lcd_irq(dev); 393 return IRQ_HANDLED; 394 } 395 396 static void kmb_irq_reset(struct drm_device *drm) 397 { 398 kmb_write_lcd(to_kmb(drm), LCD_INT_CLEAR, 0xFFFF); 399 kmb_write_lcd(to_kmb(drm), LCD_INT_ENABLE, 0); 400 } 401 402 DEFINE_DRM_GEM_CMA_FOPS(fops); 403 404 static const struct drm_driver kmb_driver = { 405 .driver_features = DRIVER_GEM | 406 DRIVER_MODESET | DRIVER_ATOMIC, 407 .irq_handler = kmb_isr, 408 .irq_preinstall = kmb_irq_reset, 409 .irq_uninstall = kmb_irq_reset, 410 /* GEM Operations */ 411 .fops = &fops, 412 DRM_GEM_CMA_DRIVER_OPS_VMAP, 413 .name = "kmb-drm", 414 .desc = "KEEMBAY DISPLAY DRIVER ", 415 .date = "20201008", 416 .major = 1, 417 .minor = 0, 418 }; 419 420 static int kmb_remove(struct platform_device *pdev) 421 { 422 struct device *dev = &pdev->dev; 423 struct drm_device *drm = dev_get_drvdata(dev); 424 struct kmb_drm_private *kmb = to_kmb(drm); 425 426 drm_dev_unregister(drm); 427 drm_kms_helper_poll_fini(drm); 428 of_node_put(kmb->crtc.port); 429 kmb->crtc.port = NULL; 430 pm_runtime_get_sync(drm->dev); 431 drm_irq_uninstall(drm); 432 pm_runtime_put_sync(drm->dev); 433 pm_runtime_disable(drm->dev); 434 435 of_reserved_mem_device_release(drm->dev); 436 437 /* Release clks */ 438 kmb_display_clk_disable(kmb); 439 440 dev_set_drvdata(dev, NULL); 441 442 /* Unregister DSI host */ 443 kmb_dsi_host_unregister(kmb->kmb_dsi); 444 drm_atomic_helper_shutdown(drm); 445 return 0; 446 } 447 448 static int kmb_probe(struct platform_device *pdev) 449 { 450 struct device *dev = get_device(&pdev->dev); 451 struct kmb_drm_private *kmb; 452 int ret = 0; 453 struct device_node *dsi_in; 454 struct device_node *dsi_node; 455 struct platform_device *dsi_pdev; 456 457 /* The bridge (ADV 7535) will return -EPROBE_DEFER until it 458 * has a mipi_dsi_host to register its device to. So, we 459 * first register the DSI host during probe time, and then return 460 * -EPROBE_DEFER until the bridge is loaded. Probe will be called again 461 * and then the rest of the driver initialization can proceed 462 * afterwards and the bridge can be successfully attached. 463 */ 464 dsi_in = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0); 465 if (!dsi_in) { 466 DRM_ERROR("Failed to get dsi_in node info from DT"); 467 return -EINVAL; 468 } 469 dsi_node = of_graph_get_remote_port_parent(dsi_in); 470 if (!dsi_node) { 471 of_node_put(dsi_in); 472 DRM_ERROR("Failed to get dsi node from DT\n"); 473 return -EINVAL; 474 } 475 476 dsi_pdev = of_find_device_by_node(dsi_node); 477 if (!dsi_pdev) { 478 of_node_put(dsi_in); 479 of_node_put(dsi_node); 480 DRM_ERROR("Failed to get dsi platform device\n"); 481 return -EINVAL; 482 } 483 484 of_node_put(dsi_in); 485 of_node_put(dsi_node); 486 ret = kmb_dsi_host_bridge_init(get_device(&dsi_pdev->dev)); 487 488 if (ret == -EPROBE_DEFER) { 489 return -EPROBE_DEFER; 490 } else if (ret) { 491 DRM_ERROR("probe failed to initialize DSI host bridge\n"); 492 return ret; 493 } 494 495 /* Create DRM device */ 496 kmb = devm_drm_dev_alloc(dev, &kmb_driver, 497 struct kmb_drm_private, drm); 498 if (IS_ERR(kmb)) 499 return PTR_ERR(kmb); 500 501 dev_set_drvdata(dev, &kmb->drm); 502 503 /* Initialize MIPI DSI */ 504 kmb->kmb_dsi = kmb_dsi_init(dsi_pdev); 505 if (IS_ERR(kmb->kmb_dsi)) { 506 drm_err(&kmb->drm, "failed to initialize DSI\n"); 507 ret = PTR_ERR(kmb->kmb_dsi); 508 goto err_free1; 509 } 510 511 kmb->kmb_dsi->dev = &dsi_pdev->dev; 512 kmb->kmb_dsi->pdev = dsi_pdev; 513 ret = kmb_hw_init(&kmb->drm, 0); 514 if (ret) 515 goto err_free1; 516 517 ret = kmb_setup_mode_config(&kmb->drm); 518 if (ret) 519 goto err_free; 520 521 ret = drm_irq_install(&kmb->drm, kmb->irq_lcd); 522 if (ret < 0) { 523 drm_err(&kmb->drm, "failed to install IRQ handler\n"); 524 goto err_irq; 525 } 526 527 drm_kms_helper_poll_init(&kmb->drm); 528 529 /* Register graphics device with the kernel */ 530 ret = drm_dev_register(&kmb->drm, 0); 531 if (ret) 532 goto err_register; 533 534 return 0; 535 536 err_register: 537 drm_kms_helper_poll_fini(&kmb->drm); 538 err_irq: 539 pm_runtime_disable(kmb->drm.dev); 540 err_free: 541 drm_crtc_cleanup(&kmb->crtc); 542 drm_mode_config_cleanup(&kmb->drm); 543 err_free1: 544 dev_set_drvdata(dev, NULL); 545 kmb_dsi_host_unregister(kmb->kmb_dsi); 546 547 return ret; 548 } 549 550 static const struct of_device_id kmb_of_match[] = { 551 {.compatible = "intel,keembay-display"}, 552 {}, 553 }; 554 555 MODULE_DEVICE_TABLE(of, kmb_of_match); 556 557 static int __maybe_unused kmb_pm_suspend(struct device *dev) 558 { 559 struct drm_device *drm = dev_get_drvdata(dev); 560 struct kmb_drm_private *kmb = to_kmb(drm); 561 562 drm_kms_helper_poll_disable(drm); 563 564 kmb->state = drm_atomic_helper_suspend(drm); 565 if (IS_ERR(kmb->state)) { 566 drm_kms_helper_poll_enable(drm); 567 return PTR_ERR(kmb->state); 568 } 569 570 return 0; 571 } 572 573 static int __maybe_unused kmb_pm_resume(struct device *dev) 574 { 575 struct drm_device *drm = dev_get_drvdata(dev); 576 struct kmb_drm_private *kmb = drm ? to_kmb(drm) : NULL; 577 578 if (!kmb) 579 return 0; 580 581 drm_atomic_helper_resume(drm, kmb->state); 582 drm_kms_helper_poll_enable(drm); 583 584 return 0; 585 } 586 587 static SIMPLE_DEV_PM_OPS(kmb_pm_ops, kmb_pm_suspend, kmb_pm_resume); 588 589 static struct platform_driver kmb_platform_driver = { 590 .probe = kmb_probe, 591 .remove = kmb_remove, 592 .driver = { 593 .name = "kmb-drm", 594 .pm = &kmb_pm_ops, 595 .of_match_table = kmb_of_match, 596 }, 597 }; 598 599 module_platform_driver(kmb_platform_driver); 600 601 MODULE_AUTHOR("Intel Corporation"); 602 MODULE_DESCRIPTION("Keembay Display driver"); 603 MODULE_LICENSE("GPL v2"); 604