1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright © 2018-2020 Intel Corporation 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/module.h> 8 #include <linux/of_graph.h> 9 #include <linux/of_platform.h> 10 #include <linux/of_reserved_mem.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/regmap.h> 15 16 #include <drm/drm_atomic_helper.h> 17 #include <drm/drm_drv.h> 18 #include <drm/drm_gem_cma_helper.h> 19 #include <drm/drm_gem_framebuffer_helper.h> 20 #include <drm/drm_irq.h> 21 #include <drm/drm_probe_helper.h> 22 #include <drm/drm_vblank.h> 23 24 #include "kmb_drv.h" 25 #include "kmb_dsi.h" 26 #include "kmb_regs.h" 27 28 static int kmb_display_clk_enable(struct kmb_drm_private *kmb) 29 { 30 int ret = 0; 31 32 ret = clk_prepare_enable(kmb->kmb_clk.clk_lcd); 33 if (ret) { 34 drm_err(&kmb->drm, "Failed to enable LCD clock: %d\n", ret); 35 return ret; 36 } 37 DRM_INFO("SUCCESS : enabled LCD clocks\n"); 38 return 0; 39 } 40 41 static int kmb_initialize_clocks(struct kmb_drm_private *kmb, struct device *dev) 42 { 43 int ret = 0; 44 struct regmap *msscam; 45 46 kmb->kmb_clk.clk_lcd = devm_clk_get(dev, "clk_lcd"); 47 if (IS_ERR(kmb->kmb_clk.clk_lcd)) { 48 drm_err(&kmb->drm, "clk_get() failed clk_lcd\n"); 49 return PTR_ERR(kmb->kmb_clk.clk_lcd); 50 } 51 52 kmb->kmb_clk.clk_pll0 = devm_clk_get(dev, "clk_pll0"); 53 if (IS_ERR(kmb->kmb_clk.clk_pll0)) { 54 drm_err(&kmb->drm, "clk_get() failed clk_pll0 "); 55 return PTR_ERR(kmb->kmb_clk.clk_pll0); 56 } 57 kmb->sys_clk_mhz = clk_get_rate(kmb->kmb_clk.clk_pll0) / 1000000; 58 drm_info(&kmb->drm, "system clk = %d Mhz", kmb->sys_clk_mhz); 59 60 ret = kmb_dsi_clk_init(kmb->kmb_dsi); 61 62 /* Set LCD clock to 200 Mhz */ 63 clk_set_rate(kmb->kmb_clk.clk_lcd, KMB_LCD_DEFAULT_CLK); 64 if (clk_get_rate(kmb->kmb_clk.clk_lcd) != KMB_LCD_DEFAULT_CLK) { 65 drm_err(&kmb->drm, "failed to set to clk_lcd to %d\n", 66 KMB_LCD_DEFAULT_CLK); 67 return -1; 68 } 69 drm_dbg(&kmb->drm, "clk_lcd = %ld\n", clk_get_rate(kmb->kmb_clk.clk_lcd)); 70 71 ret = kmb_display_clk_enable(kmb); 72 if (ret) 73 return ret; 74 75 msscam = syscon_regmap_lookup_by_compatible("intel,keembay-msscam"); 76 if (IS_ERR(msscam)) { 77 drm_err(&kmb->drm, "failed to get msscam syscon"); 78 return -1; 79 } 80 81 /* Enable MSS_CAM_CLK_CTRL for MIPI TX and LCD */ 82 regmap_update_bits(msscam, MSS_CAM_CLK_CTRL, 0x1fff, 0x1fff); 83 regmap_update_bits(msscam, MSS_CAM_RSTN_CTRL, 0xffffffff, 0xffffffff); 84 return 0; 85 } 86 87 static void kmb_display_clk_disable(struct kmb_drm_private *kmb) 88 { 89 clk_disable_unprepare(kmb->kmb_clk.clk_lcd); 90 } 91 92 static void __iomem *kmb_map_mmio(struct drm_device *drm, 93 struct platform_device *pdev, 94 char *name) 95 { 96 struct resource *res; 97 void __iomem *mem; 98 99 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); 100 if (!res) { 101 drm_err(drm, "failed to get resource for %s", name); 102 return ERR_PTR(-ENOMEM); 103 } 104 mem = devm_ioremap_resource(drm->dev, res); 105 if (IS_ERR(mem)) 106 drm_err(drm, "failed to ioremap %s registers", name); 107 return mem; 108 } 109 110 static int kmb_hw_init(struct drm_device *drm, unsigned long flags) 111 { 112 struct kmb_drm_private *kmb = to_kmb(drm); 113 struct platform_device *pdev = to_platform_device(drm->dev); 114 int irq_lcd; 115 int ret = 0; 116 117 /* Map LCD MMIO registers */ 118 kmb->lcd_mmio = kmb_map_mmio(drm, pdev, "lcd"); 119 if (IS_ERR(kmb->lcd_mmio)) { 120 drm_err(&kmb->drm, "failed to map LCD registers\n"); 121 return -ENOMEM; 122 } 123 124 /* Map MIPI MMIO registers */ 125 ret = kmb_dsi_map_mmio(kmb->kmb_dsi); 126 if (ret) 127 return ret; 128 129 /* Enable display clocks */ 130 kmb_initialize_clocks(kmb, &pdev->dev); 131 132 /* Register irqs here - section 17.3 in databook 133 * lists LCD at 79 and 82 for MIPI under MSS CPU - 134 * firmware has redirected 79 to A53 IRQ 33 135 */ 136 137 /* Allocate LCD interrupt resources */ 138 irq_lcd = platform_get_irq(pdev, 0); 139 if (irq_lcd < 0) { 140 ret = irq_lcd; 141 drm_err(&kmb->drm, "irq_lcd not found"); 142 goto setup_fail; 143 } 144 145 /* Get the optional framebuffer memory resource */ 146 ret = of_reserved_mem_device_init(drm->dev); 147 if (ret && ret != -ENODEV) 148 return ret; 149 150 spin_lock_init(&kmb->irq_lock); 151 152 kmb->irq_lcd = irq_lcd; 153 154 return 0; 155 156 setup_fail: 157 of_reserved_mem_device_release(drm->dev); 158 159 return ret; 160 } 161 162 static const struct drm_mode_config_funcs kmb_mode_config_funcs = { 163 .fb_create = drm_gem_fb_create, 164 .atomic_check = drm_atomic_helper_check, 165 .atomic_commit = drm_atomic_helper_commit, 166 }; 167 168 static int kmb_setup_mode_config(struct drm_device *drm) 169 { 170 int ret; 171 struct kmb_drm_private *kmb = to_kmb(drm); 172 173 ret = drmm_mode_config_init(drm); 174 if (ret) 175 return ret; 176 drm->mode_config.min_width = KMB_MIN_WIDTH; 177 drm->mode_config.min_height = KMB_MIN_HEIGHT; 178 drm->mode_config.max_width = KMB_MAX_WIDTH; 179 drm->mode_config.max_height = KMB_MAX_HEIGHT; 180 drm->mode_config.funcs = &kmb_mode_config_funcs; 181 182 ret = kmb_setup_crtc(drm); 183 if (ret < 0) { 184 drm_err(drm, "failed to create crtc\n"); 185 return ret; 186 } 187 ret = kmb_dsi_encoder_init(drm, kmb->kmb_dsi); 188 /* Set the CRTC's port so that the encoder component can find it */ 189 kmb->crtc.port = of_graph_get_port_by_id(drm->dev->of_node, 0); 190 ret = drm_vblank_init(drm, drm->mode_config.num_crtc); 191 if (ret < 0) { 192 drm_err(drm, "failed to initialize vblank\n"); 193 pm_runtime_disable(drm->dev); 194 return ret; 195 } 196 197 drm_mode_config_reset(drm); 198 return 0; 199 } 200 201 static irqreturn_t handle_lcd_irq(struct drm_device *dev) 202 { 203 unsigned long status, val, val1; 204 int plane_id, dma0_state, dma1_state; 205 struct kmb_drm_private *kmb = to_kmb(dev); 206 u32 ctrl = 0; 207 208 status = kmb_read_lcd(kmb, LCD_INT_STATUS); 209 210 spin_lock(&kmb->irq_lock); 211 if (status & LCD_INT_EOF) { 212 kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_EOF); 213 214 /* When disabling/enabling LCD layers, the change takes effect 215 * immediately and does not wait for EOF (end of frame). 216 * When kmb_plane_atomic_disable is called, mark the plane as 217 * disabled but actually disable the plane when EOF irq is 218 * being handled. 219 */ 220 for (plane_id = LAYER_0; 221 plane_id < KMB_MAX_PLANES; plane_id++) { 222 if (kmb->plane_status[plane_id].disable) { 223 kmb_clr_bitmask_lcd(kmb, 224 LCD_LAYERn_DMA_CFG 225 (plane_id), 226 LCD_DMA_LAYER_ENABLE); 227 228 kmb_clr_bitmask_lcd(kmb, LCD_CONTROL, 229 kmb->plane_status[plane_id].ctrl); 230 231 ctrl = kmb_read_lcd(kmb, LCD_CONTROL); 232 if (!(ctrl & (LCD_CTRL_VL1_ENABLE | 233 LCD_CTRL_VL2_ENABLE | 234 LCD_CTRL_GL1_ENABLE | 235 LCD_CTRL_GL2_ENABLE))) { 236 /* If no LCD layers are using DMA, 237 * then disable DMA pipelined AXI read 238 * transactions. 239 */ 240 kmb_clr_bitmask_lcd(kmb, LCD_CONTROL, 241 LCD_CTRL_PIPELINE_DMA); 242 } 243 244 kmb->plane_status[plane_id].disable = false; 245 } 246 } 247 if (kmb->kmb_under_flow) { 248 /* DMA Recovery after underflow */ 249 dma0_state = (kmb->layer_no == 0) ? 250 LCD_VIDEO0_DMA0_STATE : LCD_VIDEO1_DMA0_STATE; 251 dma1_state = (kmb->layer_no == 0) ? 252 LCD_VIDEO0_DMA1_STATE : LCD_VIDEO1_DMA1_STATE; 253 254 do { 255 kmb_write_lcd(kmb, LCD_FIFO_FLUSH, 1); 256 val = kmb_read_lcd(kmb, dma0_state) 257 & LCD_DMA_STATE_ACTIVE; 258 val1 = kmb_read_lcd(kmb, dma1_state) 259 & LCD_DMA_STATE_ACTIVE; 260 } while ((val || val1)); 261 /* disable dma */ 262 kmb_clr_bitmask_lcd(kmb, 263 LCD_LAYERn_DMA_CFG(kmb->layer_no), 264 LCD_DMA_LAYER_ENABLE); 265 kmb_write_lcd(kmb, LCD_FIFO_FLUSH, 1); 266 kmb->kmb_flush_done = 1; 267 kmb->kmb_under_flow = 0; 268 } 269 } 270 271 if (status & LCD_INT_LINE_CMP) { 272 /* clear line compare interrupt */ 273 kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_LINE_CMP); 274 } 275 276 if (status & LCD_INT_VERT_COMP) { 277 /* Read VSTATUS */ 278 val = kmb_read_lcd(kmb, LCD_VSTATUS); 279 val = (val & LCD_VSTATUS_VERTICAL_STATUS_MASK); 280 switch (val) { 281 case LCD_VSTATUS_COMPARE_VSYNC: 282 /* Clear vertical compare interrupt */ 283 kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_VERT_COMP); 284 if (kmb->kmb_flush_done) { 285 kmb_set_bitmask_lcd(kmb, 286 LCD_LAYERn_DMA_CFG 287 (kmb->layer_no), 288 LCD_DMA_LAYER_ENABLE); 289 kmb->kmb_flush_done = 0; 290 } 291 drm_crtc_handle_vblank(&kmb->crtc); 292 break; 293 case LCD_VSTATUS_COMPARE_BACKPORCH: 294 case LCD_VSTATUS_COMPARE_ACTIVE: 295 case LCD_VSTATUS_COMPARE_FRONT_PORCH: 296 kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_VERT_COMP); 297 break; 298 } 299 } 300 if (status & LCD_INT_DMA_ERR) { 301 val = 302 (status & LCD_INT_DMA_ERR & 303 kmb_read_lcd(kmb, LCD_INT_ENABLE)); 304 /* LAYER0 - VL0 */ 305 if (val & (LAYER0_DMA_FIFO_UNDERFLOW | 306 LAYER0_DMA_CB_FIFO_UNDERFLOW | 307 LAYER0_DMA_CR_FIFO_UNDERFLOW)) { 308 kmb->kmb_under_flow++; 309 drm_info(&kmb->drm, 310 "!LAYER0:VL0 DMA UNDERFLOW val = 0x%lx,under_flow=%d", 311 val, kmb->kmb_under_flow); 312 /* disable underflow interrupt */ 313 kmb_clr_bitmask_lcd(kmb, LCD_INT_ENABLE, 314 LAYER0_DMA_FIFO_UNDERFLOW | 315 LAYER0_DMA_CB_FIFO_UNDERFLOW | 316 LAYER0_DMA_CR_FIFO_UNDERFLOW); 317 kmb_set_bitmask_lcd(kmb, LCD_INT_CLEAR, 318 LAYER0_DMA_CB_FIFO_UNDERFLOW | 319 LAYER0_DMA_FIFO_UNDERFLOW | 320 LAYER0_DMA_CR_FIFO_UNDERFLOW); 321 /* disable auto restart mode */ 322 kmb_clr_bitmask_lcd(kmb, LCD_LAYERn_DMA_CFG(0), 323 LCD_DMA_LAYER_CONT_PING_PONG_UPDATE); 324 325 kmb->layer_no = 0; 326 } 327 328 if (val & LAYER0_DMA_FIFO_OVERFLOW) 329 drm_dbg(&kmb->drm, 330 "LAYER0:VL0 DMA OVERFLOW val = 0x%lx", val); 331 if (val & LAYER0_DMA_CB_FIFO_OVERFLOW) 332 drm_dbg(&kmb->drm, 333 "LAYER0:VL0 DMA CB OVERFLOW val = 0x%lx", val); 334 if (val & LAYER0_DMA_CR_FIFO_OVERFLOW) 335 drm_dbg(&kmb->drm, 336 "LAYER0:VL0 DMA CR OVERFLOW val = 0x%lx", val); 337 338 /* LAYER1 - VL1 */ 339 if (val & (LAYER1_DMA_FIFO_UNDERFLOW | 340 LAYER1_DMA_CB_FIFO_UNDERFLOW | 341 LAYER1_DMA_CR_FIFO_UNDERFLOW)) { 342 kmb->kmb_under_flow++; 343 drm_info(&kmb->drm, 344 "!LAYER1:VL1 DMA UNDERFLOW val = 0x%lx, under_flow=%d", 345 val, kmb->kmb_under_flow); 346 /* disable underflow interrupt */ 347 kmb_clr_bitmask_lcd(kmb, LCD_INT_ENABLE, 348 LAYER1_DMA_FIFO_UNDERFLOW | 349 LAYER1_DMA_CB_FIFO_UNDERFLOW | 350 LAYER1_DMA_CR_FIFO_UNDERFLOW); 351 kmb_set_bitmask_lcd(kmb, LCD_INT_CLEAR, 352 LAYER1_DMA_CB_FIFO_UNDERFLOW | 353 LAYER1_DMA_FIFO_UNDERFLOW | 354 LAYER1_DMA_CR_FIFO_UNDERFLOW); 355 /* disable auto restart mode */ 356 kmb_clr_bitmask_lcd(kmb, LCD_LAYERn_DMA_CFG(1), 357 LCD_DMA_LAYER_CONT_PING_PONG_UPDATE); 358 kmb->layer_no = 1; 359 } 360 361 /* LAYER1 - VL1 */ 362 if (val & LAYER1_DMA_FIFO_OVERFLOW) 363 drm_dbg(&kmb->drm, 364 "LAYER1:VL1 DMA OVERFLOW val = 0x%lx", val); 365 if (val & LAYER1_DMA_CB_FIFO_OVERFLOW) 366 drm_dbg(&kmb->drm, 367 "LAYER1:VL1 DMA CB OVERFLOW val = 0x%lx", val); 368 if (val & LAYER1_DMA_CR_FIFO_OVERFLOW) 369 drm_dbg(&kmb->drm, 370 "LAYER1:VL1 DMA CR OVERFLOW val = 0x%lx", val); 371 372 /* LAYER2 - GL0 */ 373 if (val & LAYER2_DMA_FIFO_UNDERFLOW) 374 drm_dbg(&kmb->drm, 375 "LAYER2:GL0 DMA UNDERFLOW val = 0x%lx", val); 376 if (val & LAYER2_DMA_FIFO_OVERFLOW) 377 drm_dbg(&kmb->drm, 378 "LAYER2:GL0 DMA OVERFLOW val = 0x%lx", val); 379 380 /* LAYER3 - GL1 */ 381 if (val & LAYER3_DMA_FIFO_UNDERFLOW) 382 drm_dbg(&kmb->drm, 383 "LAYER3:GL1 DMA UNDERFLOW val = 0x%lx", val); 384 if (val & LAYER3_DMA_FIFO_UNDERFLOW) 385 drm_dbg(&kmb->drm, 386 "LAYER3:GL1 DMA OVERFLOW val = 0x%lx", val); 387 } 388 389 spin_unlock(&kmb->irq_lock); 390 391 if (status & LCD_INT_LAYER) { 392 /* Clear layer interrupts */ 393 kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_LAYER); 394 } 395 396 /* Clear all interrupts */ 397 kmb_set_bitmask_lcd(kmb, LCD_INT_CLEAR, 1); 398 return IRQ_HANDLED; 399 } 400 401 /* IRQ handler */ 402 static irqreturn_t kmb_isr(int irq, void *arg) 403 { 404 struct drm_device *dev = (struct drm_device *)arg; 405 406 handle_lcd_irq(dev); 407 return IRQ_HANDLED; 408 } 409 410 static void kmb_irq_reset(struct drm_device *drm) 411 { 412 kmb_write_lcd(to_kmb(drm), LCD_INT_CLEAR, 0xFFFF); 413 kmb_write_lcd(to_kmb(drm), LCD_INT_ENABLE, 0); 414 } 415 416 DEFINE_DRM_GEM_CMA_FOPS(fops); 417 418 static const struct drm_driver kmb_driver = { 419 .driver_features = DRIVER_GEM | 420 DRIVER_MODESET | DRIVER_ATOMIC, 421 .irq_handler = kmb_isr, 422 .irq_preinstall = kmb_irq_reset, 423 .irq_uninstall = kmb_irq_reset, 424 /* GEM Operations */ 425 .fops = &fops, 426 DRM_GEM_CMA_DRIVER_OPS_VMAP, 427 .name = "kmb-drm", 428 .desc = "KEEMBAY DISPLAY DRIVER ", 429 .date = "20201008", 430 .major = 1, 431 .minor = 0, 432 }; 433 434 static int kmb_remove(struct platform_device *pdev) 435 { 436 struct device *dev = &pdev->dev; 437 struct drm_device *drm = dev_get_drvdata(dev); 438 struct kmb_drm_private *kmb = to_kmb(drm); 439 440 drm_dev_unregister(drm); 441 drm_kms_helper_poll_fini(drm); 442 of_node_put(kmb->crtc.port); 443 kmb->crtc.port = NULL; 444 pm_runtime_get_sync(drm->dev); 445 drm_irq_uninstall(drm); 446 pm_runtime_put_sync(drm->dev); 447 pm_runtime_disable(drm->dev); 448 449 of_reserved_mem_device_release(drm->dev); 450 451 /* Release clks */ 452 kmb_display_clk_disable(kmb); 453 454 dev_set_drvdata(dev, NULL); 455 456 /* Unregister DSI host */ 457 kmb_dsi_host_unregister(kmb->kmb_dsi); 458 drm_atomic_helper_shutdown(drm); 459 return 0; 460 } 461 462 static int kmb_probe(struct platform_device *pdev) 463 { 464 struct device *dev = get_device(&pdev->dev); 465 struct kmb_drm_private *kmb; 466 int ret = 0; 467 struct device_node *dsi_in; 468 struct device_node *dsi_node; 469 struct platform_device *dsi_pdev; 470 471 /* The bridge (ADV 7535) will return -EPROBE_DEFER until it 472 * has a mipi_dsi_host to register its device to. So, we 473 * first register the DSI host during probe time, and then return 474 * -EPROBE_DEFER until the bridge is loaded. Probe will be called again 475 * and then the rest of the driver initialization can proceed 476 * afterwards and the bridge can be successfully attached. 477 */ 478 dsi_in = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0); 479 if (!dsi_in) { 480 DRM_ERROR("Failed to get dsi_in node info from DT"); 481 return -EINVAL; 482 } 483 dsi_node = of_graph_get_remote_port_parent(dsi_in); 484 if (!dsi_node) { 485 of_node_put(dsi_in); 486 DRM_ERROR("Failed to get dsi node from DT\n"); 487 return -EINVAL; 488 } 489 490 dsi_pdev = of_find_device_by_node(dsi_node); 491 if (!dsi_pdev) { 492 of_node_put(dsi_in); 493 of_node_put(dsi_node); 494 DRM_ERROR("Failed to get dsi platform device\n"); 495 return -EINVAL; 496 } 497 498 of_node_put(dsi_in); 499 of_node_put(dsi_node); 500 ret = kmb_dsi_host_bridge_init(get_device(&dsi_pdev->dev)); 501 502 if (ret == -EPROBE_DEFER) { 503 return -EPROBE_DEFER; 504 } else if (ret) { 505 DRM_ERROR("probe failed to initialize DSI host bridge\n"); 506 return ret; 507 } 508 509 /* Create DRM device */ 510 kmb = devm_drm_dev_alloc(dev, &kmb_driver, 511 struct kmb_drm_private, drm); 512 if (IS_ERR(kmb)) 513 return PTR_ERR(kmb); 514 515 dev_set_drvdata(dev, &kmb->drm); 516 517 /* Initialize MIPI DSI */ 518 kmb->kmb_dsi = kmb_dsi_init(dsi_pdev); 519 if (IS_ERR(kmb->kmb_dsi)) { 520 drm_err(&kmb->drm, "failed to initialize DSI\n"); 521 ret = PTR_ERR(kmb->kmb_dsi); 522 goto err_free1; 523 } 524 525 kmb->kmb_dsi->dev = &dsi_pdev->dev; 526 kmb->kmb_dsi->pdev = dsi_pdev; 527 ret = kmb_hw_init(&kmb->drm, 0); 528 if (ret) 529 goto err_free1; 530 531 ret = kmb_setup_mode_config(&kmb->drm); 532 if (ret) 533 goto err_free; 534 535 ret = drm_irq_install(&kmb->drm, kmb->irq_lcd); 536 if (ret < 0) { 537 drm_err(&kmb->drm, "failed to install IRQ handler\n"); 538 goto err_irq; 539 } 540 541 drm_kms_helper_poll_init(&kmb->drm); 542 543 /* Register graphics device with the kernel */ 544 ret = drm_dev_register(&kmb->drm, 0); 545 if (ret) 546 goto err_register; 547 548 return 0; 549 550 err_register: 551 drm_kms_helper_poll_fini(&kmb->drm); 552 err_irq: 553 pm_runtime_disable(kmb->drm.dev); 554 err_free: 555 drm_crtc_cleanup(&kmb->crtc); 556 drm_mode_config_cleanup(&kmb->drm); 557 err_free1: 558 dev_set_drvdata(dev, NULL); 559 kmb_dsi_host_unregister(kmb->kmb_dsi); 560 561 return ret; 562 } 563 564 static const struct of_device_id kmb_of_match[] = { 565 {.compatible = "intel,keembay-display"}, 566 {}, 567 }; 568 569 MODULE_DEVICE_TABLE(of, kmb_of_match); 570 571 static int __maybe_unused kmb_pm_suspend(struct device *dev) 572 { 573 struct drm_device *drm = dev_get_drvdata(dev); 574 struct kmb_drm_private *kmb = to_kmb(drm); 575 576 drm_kms_helper_poll_disable(drm); 577 578 kmb->state = drm_atomic_helper_suspend(drm); 579 if (IS_ERR(kmb->state)) { 580 drm_kms_helper_poll_enable(drm); 581 return PTR_ERR(kmb->state); 582 } 583 584 return 0; 585 } 586 587 static int __maybe_unused kmb_pm_resume(struct device *dev) 588 { 589 struct drm_device *drm = dev_get_drvdata(dev); 590 struct kmb_drm_private *kmb = drm ? to_kmb(drm) : NULL; 591 592 if (!kmb) 593 return 0; 594 595 drm_atomic_helper_resume(drm, kmb->state); 596 drm_kms_helper_poll_enable(drm); 597 598 return 0; 599 } 600 601 static SIMPLE_DEV_PM_OPS(kmb_pm_ops, kmb_pm_suspend, kmb_pm_resume); 602 603 static struct platform_driver kmb_platform_driver = { 604 .probe = kmb_probe, 605 .remove = kmb_remove, 606 .driver = { 607 .name = "kmb-drm", 608 .pm = &kmb_pm_ops, 609 .of_match_table = kmb_of_match, 610 }, 611 }; 612 613 module_platform_driver(kmb_platform_driver); 614 615 MODULE_AUTHOR("Intel Corporation"); 616 MODULE_DESCRIPTION("Keembay Display driver"); 617 MODULE_LICENSE("GPL v2"); 618