1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Ingenic JZ47xx IPU driver 4 // 5 // Copyright (C) 2020, Paul Cercueil <paul@crapouillou.net> 6 // Copyright (C) 2020, Daniel Silsby <dansilsby@gmail.com> 7 8 #include "ingenic-drm.h" 9 #include "ingenic-ipu.h" 10 11 #include <linux/clk.h> 12 #include <linux/component.h> 13 #include <linux/gcd.h> 14 #include <linux/interrupt.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/of_device.h> 18 #include <linux/regmap.h> 19 #include <linux/time.h> 20 21 #include <drm/drm_atomic.h> 22 #include <drm/drm_atomic_helper.h> 23 #include <drm/drm_damage_helper.h> 24 #include <drm/drm_drv.h> 25 #include <drm/drm_fb_cma_helper.h> 26 #include <drm/drm_fourcc.h> 27 #include <drm/drm_framebuffer.h> 28 #include <drm/drm_gem_atomic_helper.h> 29 #include <drm/drm_gem_cma_helper.h> 30 #include <drm/drm_gem_framebuffer_helper.h> 31 #include <drm/drm_plane.h> 32 #include <drm/drm_plane_helper.h> 33 #include <drm/drm_property.h> 34 #include <drm/drm_vblank.h> 35 36 struct ingenic_ipu; 37 38 struct soc_info { 39 const u32 *formats; 40 size_t num_formats; 41 bool has_bicubic; 42 bool manual_restart; 43 44 void (*set_coefs)(struct ingenic_ipu *ipu, unsigned int reg, 45 unsigned int sharpness, bool downscale, 46 unsigned int weight, unsigned int offset); 47 }; 48 49 struct ingenic_ipu_private_state { 50 struct drm_private_state base; 51 52 unsigned int num_w, num_h, denom_w, denom_h; 53 }; 54 55 struct ingenic_ipu { 56 struct drm_plane plane; 57 struct drm_device *drm; 58 struct device *dev, *master; 59 struct regmap *map; 60 struct clk *clk; 61 const struct soc_info *soc_info; 62 bool clk_enabled; 63 64 dma_addr_t addr_y, addr_u, addr_v; 65 66 struct drm_property *sharpness_prop; 67 unsigned int sharpness; 68 69 struct drm_private_obj private_obj; 70 }; 71 72 /* Signed 15.16 fixed-point math (for bicubic scaling coefficients) */ 73 #define I2F(i) ((s32)(i) * 65536) 74 #define F2I(f) ((f) / 65536) 75 #define FMUL(fa, fb) ((s32)(((s64)(fa) * (s64)(fb)) / 65536)) 76 #define SHARPNESS_INCR (I2F(-1) / 8) 77 78 static inline struct ingenic_ipu *plane_to_ingenic_ipu(struct drm_plane *plane) 79 { 80 return container_of(plane, struct ingenic_ipu, plane); 81 } 82 83 static inline struct ingenic_ipu_private_state * 84 to_ingenic_ipu_priv_state(struct drm_private_state *state) 85 { 86 return container_of(state, struct ingenic_ipu_private_state, base); 87 } 88 89 static struct ingenic_ipu_private_state * 90 ingenic_ipu_get_priv_state(struct ingenic_ipu *priv, struct drm_atomic_state *state) 91 { 92 struct drm_private_state *priv_state; 93 94 priv_state = drm_atomic_get_private_obj_state(state, &priv->private_obj); 95 if (IS_ERR(priv_state)) 96 return ERR_CAST(priv_state); 97 98 return to_ingenic_ipu_priv_state(priv_state); 99 } 100 101 static struct ingenic_ipu_private_state * 102 ingenic_ipu_get_new_priv_state(struct ingenic_ipu *priv, struct drm_atomic_state *state) 103 { 104 struct drm_private_state *priv_state; 105 106 priv_state = drm_atomic_get_new_private_obj_state(state, &priv->private_obj); 107 if (!priv_state) 108 return NULL; 109 110 return to_ingenic_ipu_priv_state(priv_state); 111 } 112 113 /* 114 * Apply conventional cubic convolution kernel. Both parameters 115 * and return value are 15.16 signed fixed-point. 116 * 117 * @f_a: Sharpness factor, typically in range [-4.0, -0.25]. 118 * A larger magnitude increases perceived sharpness, but going past 119 * -2.0 might cause ringing artifacts to outweigh any improvement. 120 * Nice values on a 320x240 LCD are between -0.75 and -2.0. 121 * 122 * @f_x: Absolute distance in pixels from 'pixel 0' sample position 123 * along horizontal (or vertical) source axis. Range is [0, +2.0]. 124 * 125 * returns: Weight of this pixel within 4-pixel sample group. Range is 126 * [-2.0, +2.0]. For moderate (i.e. > -3.0) sharpness factors, 127 * range is within [-1.0, +1.0]. 128 */ 129 static inline s32 cubic_conv(s32 f_a, s32 f_x) 130 { 131 const s32 f_1 = I2F(1); 132 const s32 f_2 = I2F(2); 133 const s32 f_3 = I2F(3); 134 const s32 f_4 = I2F(4); 135 const s32 f_x2 = FMUL(f_x, f_x); 136 const s32 f_x3 = FMUL(f_x, f_x2); 137 138 if (f_x <= f_1) 139 return FMUL((f_a + f_2), f_x3) - FMUL((f_a + f_3), f_x2) + f_1; 140 else if (f_x <= f_2) 141 return FMUL(f_a, (f_x3 - 5 * f_x2 + 8 * f_x - f_4)); 142 else 143 return 0; 144 } 145 146 /* 147 * On entry, "weight" is a coefficient suitable for bilinear mode, 148 * which is converted to a set of four suitable for bicubic mode. 149 * 150 * "weight 512" means all of pixel 0; 151 * "weight 256" means half of pixel 0 and half of pixel 1; 152 * "weight 0" means all of pixel 1; 153 * 154 * "offset" is increment to next source pixel sample location. 155 */ 156 static void jz4760_set_coefs(struct ingenic_ipu *ipu, unsigned int reg, 157 unsigned int sharpness, bool downscale, 158 unsigned int weight, unsigned int offset) 159 { 160 u32 val; 161 s32 w0, w1, w2, w3; /* Pixel weights at X (or Y) offsets -1,0,1,2 */ 162 163 weight = clamp_val(weight, 0, 512); 164 165 if (sharpness < 2) { 166 /* 167 * When sharpness setting is 0, emulate nearest-neighbor. 168 * When sharpness setting is 1, emulate bilinear. 169 */ 170 171 if (sharpness == 0) 172 weight = weight >= 256 ? 512 : 0; 173 w0 = 0; 174 w1 = weight; 175 w2 = 512 - weight; 176 w3 = 0; 177 } else { 178 const s32 f_a = SHARPNESS_INCR * sharpness; 179 const s32 f_h = I2F(1) / 2; /* Round up 0.5 */ 180 181 /* 182 * Note that always rounding towards +infinity here is intended. 183 * The resulting coefficients match a round-to-nearest-int 184 * double floating-point implementation. 185 */ 186 187 weight = 512 - weight; 188 w0 = F2I(f_h + 512 * cubic_conv(f_a, I2F(512 + weight) / 512)); 189 w1 = F2I(f_h + 512 * cubic_conv(f_a, I2F(0 + weight) / 512)); 190 w2 = F2I(f_h + 512 * cubic_conv(f_a, I2F(512 - weight) / 512)); 191 w3 = F2I(f_h + 512 * cubic_conv(f_a, I2F(1024 - weight) / 512)); 192 w0 = clamp_val(w0, -1024, 1023); 193 w1 = clamp_val(w1, -1024, 1023); 194 w2 = clamp_val(w2, -1024, 1023); 195 w3 = clamp_val(w3, -1024, 1023); 196 } 197 198 val = ((w1 & JZ4760_IPU_RSZ_COEF_MASK) << JZ4760_IPU_RSZ_COEF31_LSB) | 199 ((w0 & JZ4760_IPU_RSZ_COEF_MASK) << JZ4760_IPU_RSZ_COEF20_LSB); 200 regmap_write(ipu->map, reg, val); 201 202 val = ((w3 & JZ4760_IPU_RSZ_COEF_MASK) << JZ4760_IPU_RSZ_COEF31_LSB) | 203 ((w2 & JZ4760_IPU_RSZ_COEF_MASK) << JZ4760_IPU_RSZ_COEF20_LSB) | 204 ((offset & JZ4760_IPU_RSZ_OFFSET_MASK) << JZ4760_IPU_RSZ_OFFSET_LSB); 205 regmap_write(ipu->map, reg, val); 206 } 207 208 static void jz4725b_set_coefs(struct ingenic_ipu *ipu, unsigned int reg, 209 unsigned int sharpness, bool downscale, 210 unsigned int weight, unsigned int offset) 211 { 212 u32 val = JZ4725B_IPU_RSZ_LUT_OUT_EN; 213 unsigned int i; 214 215 weight = clamp_val(weight, 0, 512); 216 217 if (sharpness == 0) 218 weight = weight >= 256 ? 512 : 0; 219 220 val |= (weight & JZ4725B_IPU_RSZ_LUT_COEF_MASK) << JZ4725B_IPU_RSZ_LUT_COEF_LSB; 221 if (downscale || !!offset) 222 val |= JZ4725B_IPU_RSZ_LUT_IN_EN; 223 224 regmap_write(ipu->map, reg, val); 225 226 if (downscale) { 227 for (i = 1; i < offset; i++) 228 regmap_write(ipu->map, reg, JZ4725B_IPU_RSZ_LUT_IN_EN); 229 } 230 } 231 232 static void ingenic_ipu_set_downscale_coefs(struct ingenic_ipu *ipu, 233 unsigned int reg, 234 unsigned int num, 235 unsigned int denom) 236 { 237 unsigned int i, offset, weight, weight_num = denom; 238 239 for (i = 0; i < num; i++) { 240 weight_num = num + (weight_num - num) % (num * 2); 241 weight = 512 - 512 * (weight_num - num) / (num * 2); 242 weight_num += denom * 2; 243 offset = (weight_num - num) / (num * 2); 244 245 ipu->soc_info->set_coefs(ipu, reg, ipu->sharpness, 246 true, weight, offset); 247 } 248 } 249 250 static void ingenic_ipu_set_integer_upscale_coefs(struct ingenic_ipu *ipu, 251 unsigned int reg, 252 unsigned int num) 253 { 254 /* 255 * Force nearest-neighbor scaling and use simple math when upscaling 256 * by an integer ratio. It looks better, and fixes a few problem cases. 257 */ 258 unsigned int i; 259 260 for (i = 0; i < num; i++) 261 ipu->soc_info->set_coefs(ipu, reg, 0, false, 512, i == num - 1); 262 } 263 264 static void ingenic_ipu_set_upscale_coefs(struct ingenic_ipu *ipu, 265 unsigned int reg, 266 unsigned int num, 267 unsigned int denom) 268 { 269 unsigned int i, offset, weight, weight_num = 0; 270 271 for (i = 0; i < num; i++) { 272 weight = 512 - 512 * weight_num / num; 273 weight_num += denom; 274 offset = weight_num >= num; 275 276 if (offset) 277 weight_num -= num; 278 279 ipu->soc_info->set_coefs(ipu, reg, ipu->sharpness, 280 false, weight, offset); 281 } 282 } 283 284 static void ingenic_ipu_set_coefs(struct ingenic_ipu *ipu, unsigned int reg, 285 unsigned int num, unsigned int denom) 286 { 287 /* Begin programming the LUT */ 288 regmap_write(ipu->map, reg, -1); 289 290 if (denom > num) 291 ingenic_ipu_set_downscale_coefs(ipu, reg, num, denom); 292 else if (denom == 1) 293 ingenic_ipu_set_integer_upscale_coefs(ipu, reg, num); 294 else 295 ingenic_ipu_set_upscale_coefs(ipu, reg, num, denom); 296 } 297 298 static int reduce_fraction(unsigned int *num, unsigned int *denom) 299 { 300 unsigned long d = gcd(*num, *denom); 301 302 /* The scaling table has only 31 entries */ 303 if (*num > 31 * d) 304 return -EINVAL; 305 306 *num /= d; 307 *denom /= d; 308 return 0; 309 } 310 311 static inline bool osd_changed(struct drm_plane_state *state, 312 struct drm_plane_state *oldstate) 313 { 314 return state->src_x != oldstate->src_x || 315 state->src_y != oldstate->src_y || 316 state->src_w != oldstate->src_w || 317 state->src_h != oldstate->src_h || 318 state->crtc_x != oldstate->crtc_x || 319 state->crtc_y != oldstate->crtc_y || 320 state->crtc_w != oldstate->crtc_w || 321 state->crtc_h != oldstate->crtc_h; 322 } 323 324 static void ingenic_ipu_plane_atomic_update(struct drm_plane *plane, 325 struct drm_atomic_state *state) 326 { 327 struct ingenic_ipu *ipu = plane_to_ingenic_ipu(plane); 328 struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state, plane); 329 struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state, plane); 330 const struct drm_format_info *finfo; 331 u32 ctrl, stride = 0, coef_index = 0, format = 0; 332 bool needs_modeset, upscaling_w, upscaling_h; 333 struct ingenic_ipu_private_state *ipu_state; 334 int err; 335 336 if (!newstate || !newstate->fb) 337 return; 338 339 ipu_state = ingenic_ipu_get_new_priv_state(ipu, state); 340 if (WARN_ON(!ipu_state)) 341 return; 342 343 finfo = drm_format_info(newstate->fb->format->format); 344 345 if (!ipu->clk_enabled) { 346 err = clk_enable(ipu->clk); 347 if (err) { 348 dev_err(ipu->dev, "Unable to enable clock: %d\n", err); 349 return; 350 } 351 352 ipu->clk_enabled = true; 353 } 354 355 /* Reset all the registers if needed */ 356 needs_modeset = drm_atomic_crtc_needs_modeset(newstate->crtc->state); 357 if (needs_modeset) { 358 regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_RST); 359 360 /* Enable the chip */ 361 regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, 362 JZ_IPU_CTRL_CHIP_EN | JZ_IPU_CTRL_LCDC_SEL); 363 } 364 365 if (ingenic_drm_map_noncoherent(ipu->master)) 366 drm_fb_cma_sync_non_coherent(ipu->drm, oldstate, newstate); 367 368 /* New addresses will be committed in vblank handler... */ 369 ipu->addr_y = drm_fb_cma_get_gem_addr(newstate->fb, newstate, 0); 370 if (finfo->num_planes > 1) 371 ipu->addr_u = drm_fb_cma_get_gem_addr(newstate->fb, newstate, 372 1); 373 if (finfo->num_planes > 2) 374 ipu->addr_v = drm_fb_cma_get_gem_addr(newstate->fb, newstate, 375 2); 376 377 if (!needs_modeset) 378 return; 379 380 /* Or right here if we're doing a full modeset. */ 381 regmap_write(ipu->map, JZ_REG_IPU_Y_ADDR, ipu->addr_y); 382 regmap_write(ipu->map, JZ_REG_IPU_U_ADDR, ipu->addr_u); 383 regmap_write(ipu->map, JZ_REG_IPU_V_ADDR, ipu->addr_v); 384 385 if (finfo->num_planes == 1) 386 regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_SPKG_SEL); 387 388 ingenic_drm_plane_config(ipu->master, plane, DRM_FORMAT_XRGB8888); 389 390 /* Set the input height/width/strides */ 391 if (finfo->num_planes > 2) 392 stride = ((newstate->src_w >> 16) * finfo->cpp[2] / finfo->hsub) 393 << JZ_IPU_UV_STRIDE_V_LSB; 394 395 if (finfo->num_planes > 1) 396 stride |= ((newstate->src_w >> 16) * finfo->cpp[1] / finfo->hsub) 397 << JZ_IPU_UV_STRIDE_U_LSB; 398 399 regmap_write(ipu->map, JZ_REG_IPU_UV_STRIDE, stride); 400 401 stride = ((newstate->src_w >> 16) * finfo->cpp[0]) << JZ_IPU_Y_STRIDE_Y_LSB; 402 regmap_write(ipu->map, JZ_REG_IPU_Y_STRIDE, stride); 403 404 regmap_write(ipu->map, JZ_REG_IPU_IN_GS, 405 (stride << JZ_IPU_IN_GS_W_LSB) | 406 ((newstate->src_h >> 16) << JZ_IPU_IN_GS_H_LSB)); 407 408 switch (finfo->format) { 409 case DRM_FORMAT_XRGB1555: 410 format = JZ_IPU_D_FMT_IN_FMT_RGB555 | 411 JZ_IPU_D_FMT_RGB_OUT_OFT_RGB; 412 break; 413 case DRM_FORMAT_XBGR1555: 414 format = JZ_IPU_D_FMT_IN_FMT_RGB555 | 415 JZ_IPU_D_FMT_RGB_OUT_OFT_BGR; 416 break; 417 case DRM_FORMAT_RGB565: 418 format = JZ_IPU_D_FMT_IN_FMT_RGB565 | 419 JZ_IPU_D_FMT_RGB_OUT_OFT_RGB; 420 break; 421 case DRM_FORMAT_BGR565: 422 format = JZ_IPU_D_FMT_IN_FMT_RGB565 | 423 JZ_IPU_D_FMT_RGB_OUT_OFT_BGR; 424 break; 425 case DRM_FORMAT_XRGB8888: 426 case DRM_FORMAT_XYUV8888: 427 format = JZ_IPU_D_FMT_IN_FMT_RGB888 | 428 JZ_IPU_D_FMT_RGB_OUT_OFT_RGB; 429 break; 430 case DRM_FORMAT_XBGR8888: 431 format = JZ_IPU_D_FMT_IN_FMT_RGB888 | 432 JZ_IPU_D_FMT_RGB_OUT_OFT_BGR; 433 break; 434 case DRM_FORMAT_YUYV: 435 format = JZ_IPU_D_FMT_IN_FMT_YUV422 | 436 JZ_IPU_D_FMT_YUV_VY1UY0; 437 break; 438 case DRM_FORMAT_YVYU: 439 format = JZ_IPU_D_FMT_IN_FMT_YUV422 | 440 JZ_IPU_D_FMT_YUV_UY1VY0; 441 break; 442 case DRM_FORMAT_UYVY: 443 format = JZ_IPU_D_FMT_IN_FMT_YUV422 | 444 JZ_IPU_D_FMT_YUV_Y1VY0U; 445 break; 446 case DRM_FORMAT_VYUY: 447 format = JZ_IPU_D_FMT_IN_FMT_YUV422 | 448 JZ_IPU_D_FMT_YUV_Y1UY0V; 449 break; 450 case DRM_FORMAT_YUV411: 451 format = JZ_IPU_D_FMT_IN_FMT_YUV411; 452 break; 453 case DRM_FORMAT_YUV420: 454 format = JZ_IPU_D_FMT_IN_FMT_YUV420; 455 break; 456 case DRM_FORMAT_YUV422: 457 format = JZ_IPU_D_FMT_IN_FMT_YUV422; 458 break; 459 case DRM_FORMAT_YUV444: 460 format = JZ_IPU_D_FMT_IN_FMT_YUV444; 461 break; 462 default: 463 WARN_ONCE(1, "Unsupported format"); 464 break; 465 } 466 467 /* Fix output to RGB888 */ 468 format |= JZ_IPU_D_FMT_OUT_FMT_RGB888; 469 470 /* Set pixel format */ 471 regmap_write(ipu->map, JZ_REG_IPU_D_FMT, format); 472 473 /* Set the output height/width/stride */ 474 regmap_write(ipu->map, JZ_REG_IPU_OUT_GS, 475 ((newstate->crtc_w * 4) << JZ_IPU_OUT_GS_W_LSB) 476 | newstate->crtc_h << JZ_IPU_OUT_GS_H_LSB); 477 regmap_write(ipu->map, JZ_REG_IPU_OUT_STRIDE, newstate->crtc_w * 4); 478 479 if (finfo->is_yuv) { 480 regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_CSC_EN); 481 482 /* 483 * Offsets for Chroma/Luma. 484 * y = source Y - LUMA, 485 * u = source Cb - CHROMA, 486 * v = source Cr - CHROMA 487 */ 488 regmap_write(ipu->map, JZ_REG_IPU_CSC_OFFSET, 489 128 << JZ_IPU_CSC_OFFSET_CHROMA_LSB | 490 0 << JZ_IPU_CSC_OFFSET_LUMA_LSB); 491 492 /* 493 * YUV422 to RGB conversion table. 494 * R = C0 / 0x400 * y + C1 / 0x400 * v 495 * G = C0 / 0x400 * y - C2 / 0x400 * u - C3 / 0x400 * v 496 * B = C0 / 0x400 * y + C4 / 0x400 * u 497 */ 498 regmap_write(ipu->map, JZ_REG_IPU_CSC_C0_COEF, 0x4a8); 499 regmap_write(ipu->map, JZ_REG_IPU_CSC_C1_COEF, 0x662); 500 regmap_write(ipu->map, JZ_REG_IPU_CSC_C2_COEF, 0x191); 501 regmap_write(ipu->map, JZ_REG_IPU_CSC_C3_COEF, 0x341); 502 regmap_write(ipu->map, JZ_REG_IPU_CSC_C4_COEF, 0x811); 503 } 504 505 ctrl = 0; 506 507 /* 508 * Must set ZOOM_SEL before programming bicubic LUTs. 509 * If the IPU supports bicubic, we enable it unconditionally, since it 510 * can do anything bilinear can and more. 511 */ 512 if (ipu->soc_info->has_bicubic) 513 ctrl |= JZ_IPU_CTRL_ZOOM_SEL; 514 515 upscaling_w = ipu_state->num_w > ipu_state->denom_w; 516 if (upscaling_w) 517 ctrl |= JZ_IPU_CTRL_HSCALE; 518 519 if (ipu_state->num_w != 1 || ipu_state->denom_w != 1) { 520 if (!ipu->soc_info->has_bicubic && !upscaling_w) 521 coef_index |= (ipu_state->denom_w - 1) << 16; 522 else 523 coef_index |= (ipu_state->num_w - 1) << 16; 524 ctrl |= JZ_IPU_CTRL_HRSZ_EN; 525 } 526 527 upscaling_h = ipu_state->num_h > ipu_state->denom_h; 528 if (upscaling_h) 529 ctrl |= JZ_IPU_CTRL_VSCALE; 530 531 if (ipu_state->num_h != 1 || ipu_state->denom_h != 1) { 532 if (!ipu->soc_info->has_bicubic && !upscaling_h) 533 coef_index |= ipu_state->denom_h - 1; 534 else 535 coef_index |= ipu_state->num_h - 1; 536 ctrl |= JZ_IPU_CTRL_VRSZ_EN; 537 } 538 539 regmap_update_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_ZOOM_SEL | 540 JZ_IPU_CTRL_HRSZ_EN | JZ_IPU_CTRL_VRSZ_EN | 541 JZ_IPU_CTRL_HSCALE | JZ_IPU_CTRL_VSCALE, ctrl); 542 543 /* Set the LUT index register */ 544 regmap_write(ipu->map, JZ_REG_IPU_RSZ_COEF_INDEX, coef_index); 545 546 if (ipu_state->num_w != 1 || ipu_state->denom_w != 1) 547 ingenic_ipu_set_coefs(ipu, JZ_REG_IPU_HRSZ_COEF_LUT, 548 ipu_state->num_w, ipu_state->denom_w); 549 550 if (ipu_state->num_h != 1 || ipu_state->denom_h != 1) 551 ingenic_ipu_set_coefs(ipu, JZ_REG_IPU_VRSZ_COEF_LUT, 552 ipu_state->num_h, ipu_state->denom_h); 553 554 /* Clear STATUS register */ 555 regmap_write(ipu->map, JZ_REG_IPU_STATUS, 0); 556 557 /* Start IPU */ 558 regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, 559 JZ_IPU_CTRL_RUN | JZ_IPU_CTRL_FM_IRQ_EN); 560 561 dev_dbg(ipu->dev, "Scaling %ux%u to %ux%u (%u:%u horiz, %u:%u vert)\n", 562 newstate->src_w >> 16, newstate->src_h >> 16, 563 newstate->crtc_w, newstate->crtc_h, 564 ipu_state->num_w, ipu_state->denom_w, 565 ipu_state->num_h, ipu_state->denom_h); 566 } 567 568 static int ingenic_ipu_plane_atomic_check(struct drm_plane *plane, 569 struct drm_atomic_state *state) 570 { 571 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, 572 plane); 573 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 574 plane); 575 unsigned int num_w, denom_w, num_h, denom_h, xres, yres, max_w, max_h; 576 struct ingenic_ipu *ipu = plane_to_ingenic_ipu(plane); 577 struct drm_crtc *crtc = new_plane_state->crtc ?: old_plane_state->crtc; 578 struct drm_crtc_state *crtc_state; 579 struct ingenic_ipu_private_state *ipu_state; 580 581 if (!crtc) 582 return 0; 583 584 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc); 585 if (WARN_ON(!crtc_state)) 586 return -EINVAL; 587 588 ipu_state = ingenic_ipu_get_priv_state(ipu, state); 589 if (IS_ERR(ipu_state)) 590 return PTR_ERR(ipu_state); 591 592 /* Request a full modeset if we are enabling or disabling the IPU. */ 593 if (!old_plane_state->crtc ^ !new_plane_state->crtc) 594 crtc_state->mode_changed = true; 595 596 if (!new_plane_state->crtc || 597 !crtc_state->mode.hdisplay || !crtc_state->mode.vdisplay) 598 goto out_check_damage; 599 600 /* Plane must be fully visible */ 601 if (new_plane_state->crtc_x < 0 || new_plane_state->crtc_y < 0 || 602 new_plane_state->crtc_x + new_plane_state->crtc_w > crtc_state->mode.hdisplay || 603 new_plane_state->crtc_y + new_plane_state->crtc_h > crtc_state->mode.vdisplay) 604 return -EINVAL; 605 606 /* Minimum size is 4x4 */ 607 if ((new_plane_state->src_w >> 16) < 4 || (new_plane_state->src_h >> 16) < 4) 608 return -EINVAL; 609 610 /* Input and output lines must have an even number of pixels. */ 611 if (((new_plane_state->src_w >> 16) & 1) || (new_plane_state->crtc_w & 1)) 612 return -EINVAL; 613 614 if (!osd_changed(new_plane_state, old_plane_state)) 615 goto out_check_damage; 616 617 crtc_state->mode_changed = true; 618 619 xres = new_plane_state->src_w >> 16; 620 yres = new_plane_state->src_h >> 16; 621 622 /* 623 * Increase the scaled image's theorical width/height until we find a 624 * configuration that has valid scaling coefficients, up to 102% of the 625 * screen's resolution. This makes sure that we can scale from almost 626 * every resolution possible at the cost of a very small distorsion. 627 * The CRTC_W / CRTC_H are not modified. 628 */ 629 max_w = crtc_state->mode.hdisplay * 102 / 100; 630 max_h = crtc_state->mode.vdisplay * 102 / 100; 631 632 for (denom_w = xres, num_w = new_plane_state->crtc_w; num_w <= max_w; num_w++) 633 if (!reduce_fraction(&num_w, &denom_w)) 634 break; 635 if (num_w > max_w) 636 return -EINVAL; 637 638 for (denom_h = yres, num_h = new_plane_state->crtc_h; num_h <= max_h; num_h++) 639 if (!reduce_fraction(&num_h, &denom_h)) 640 break; 641 if (num_h > max_h) 642 return -EINVAL; 643 644 ipu_state->num_w = num_w; 645 ipu_state->num_h = num_h; 646 ipu_state->denom_w = denom_w; 647 ipu_state->denom_h = denom_h; 648 649 out_check_damage: 650 if (ingenic_drm_map_noncoherent(ipu->master)) 651 drm_atomic_helper_check_plane_damage(state, new_plane_state); 652 653 return 0; 654 } 655 656 static void ingenic_ipu_plane_atomic_disable(struct drm_plane *plane, 657 struct drm_atomic_state *state) 658 { 659 struct ingenic_ipu *ipu = plane_to_ingenic_ipu(plane); 660 661 regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_STOP); 662 regmap_clear_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_CHIP_EN); 663 664 ingenic_drm_plane_disable(ipu->master, plane); 665 666 if (ipu->clk_enabled) { 667 clk_disable(ipu->clk); 668 ipu->clk_enabled = false; 669 } 670 } 671 672 static const struct drm_plane_helper_funcs ingenic_ipu_plane_helper_funcs = { 673 .atomic_update = ingenic_ipu_plane_atomic_update, 674 .atomic_check = ingenic_ipu_plane_atomic_check, 675 .atomic_disable = ingenic_ipu_plane_atomic_disable, 676 }; 677 678 static int 679 ingenic_ipu_plane_atomic_get_property(struct drm_plane *plane, 680 const struct drm_plane_state *state, 681 struct drm_property *property, u64 *val) 682 { 683 struct ingenic_ipu *ipu = plane_to_ingenic_ipu(plane); 684 685 if (property != ipu->sharpness_prop) 686 return -EINVAL; 687 688 *val = ipu->sharpness; 689 690 return 0; 691 } 692 693 static int 694 ingenic_ipu_plane_atomic_set_property(struct drm_plane *plane, 695 struct drm_plane_state *state, 696 struct drm_property *property, u64 val) 697 { 698 struct ingenic_ipu *ipu = plane_to_ingenic_ipu(plane); 699 struct drm_crtc_state *crtc_state; 700 701 if (property != ipu->sharpness_prop) 702 return -EINVAL; 703 704 ipu->sharpness = val; 705 706 if (state->crtc) { 707 crtc_state = drm_atomic_get_existing_crtc_state(state->state, state->crtc); 708 if (WARN_ON(!crtc_state)) 709 return -EINVAL; 710 711 crtc_state->mode_changed = true; 712 } 713 714 return 0; 715 } 716 717 static const struct drm_plane_funcs ingenic_ipu_plane_funcs = { 718 .update_plane = drm_atomic_helper_update_plane, 719 .disable_plane = drm_atomic_helper_disable_plane, 720 .reset = drm_atomic_helper_plane_reset, 721 .destroy = drm_plane_cleanup, 722 723 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 724 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 725 726 .atomic_get_property = ingenic_ipu_plane_atomic_get_property, 727 .atomic_set_property = ingenic_ipu_plane_atomic_set_property, 728 }; 729 730 static struct drm_private_state * 731 ingenic_ipu_duplicate_state(struct drm_private_obj *obj) 732 { 733 struct ingenic_ipu_private_state *state = to_ingenic_ipu_priv_state(obj->state); 734 735 state = kmemdup(state, sizeof(*state), GFP_KERNEL); 736 if (!state) 737 return NULL; 738 739 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); 740 741 return &state->base; 742 } 743 744 static void ingenic_ipu_destroy_state(struct drm_private_obj *obj, 745 struct drm_private_state *state) 746 { 747 struct ingenic_ipu_private_state *priv_state = to_ingenic_ipu_priv_state(state); 748 749 kfree(priv_state); 750 } 751 752 static const struct drm_private_state_funcs ingenic_ipu_private_state_funcs = { 753 .atomic_duplicate_state = ingenic_ipu_duplicate_state, 754 .atomic_destroy_state = ingenic_ipu_destroy_state, 755 }; 756 757 static irqreturn_t ingenic_ipu_irq_handler(int irq, void *arg) 758 { 759 struct ingenic_ipu *ipu = arg; 760 struct drm_crtc *crtc = drm_crtc_from_index(ipu->drm, 0); 761 unsigned int dummy; 762 763 /* dummy read allows CPU to reconfigure IPU */ 764 if (ipu->soc_info->manual_restart) 765 regmap_read(ipu->map, JZ_REG_IPU_STATUS, &dummy); 766 767 /* ACK interrupt */ 768 regmap_write(ipu->map, JZ_REG_IPU_STATUS, 0); 769 770 /* Set previously cached addresses */ 771 regmap_write(ipu->map, JZ_REG_IPU_Y_ADDR, ipu->addr_y); 772 regmap_write(ipu->map, JZ_REG_IPU_U_ADDR, ipu->addr_u); 773 regmap_write(ipu->map, JZ_REG_IPU_V_ADDR, ipu->addr_v); 774 775 /* Run IPU for the new frame */ 776 if (ipu->soc_info->manual_restart) 777 regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_RUN); 778 779 drm_crtc_handle_vblank(crtc); 780 781 return IRQ_HANDLED; 782 } 783 784 static const struct regmap_config ingenic_ipu_regmap_config = { 785 .reg_bits = 32, 786 .val_bits = 32, 787 .reg_stride = 4, 788 789 .max_register = JZ_REG_IPU_OUT_PHY_T_ADDR, 790 }; 791 792 static int ingenic_ipu_bind(struct device *dev, struct device *master, void *d) 793 { 794 struct platform_device *pdev = to_platform_device(dev); 795 struct ingenic_ipu_private_state *private_state; 796 const struct soc_info *soc_info; 797 struct drm_device *drm = d; 798 struct drm_plane *plane; 799 struct ingenic_ipu *ipu; 800 void __iomem *base; 801 unsigned int sharpness_max; 802 int err, irq; 803 804 ipu = devm_kzalloc(dev, sizeof(*ipu), GFP_KERNEL); 805 if (!ipu) 806 return -ENOMEM; 807 808 soc_info = of_device_get_match_data(dev); 809 if (!soc_info) { 810 dev_err(dev, "Missing platform data\n"); 811 return -EINVAL; 812 } 813 814 ipu->dev = dev; 815 ipu->drm = drm; 816 ipu->master = master; 817 ipu->soc_info = soc_info; 818 819 base = devm_platform_ioremap_resource(pdev, 0); 820 if (IS_ERR(base)) { 821 dev_err(dev, "Failed to get memory resource\n"); 822 return PTR_ERR(base); 823 } 824 825 ipu->map = devm_regmap_init_mmio(dev, base, &ingenic_ipu_regmap_config); 826 if (IS_ERR(ipu->map)) { 827 dev_err(dev, "Failed to create regmap\n"); 828 return PTR_ERR(ipu->map); 829 } 830 831 irq = platform_get_irq(pdev, 0); 832 if (irq < 0) 833 return irq; 834 835 ipu->clk = devm_clk_get(dev, "ipu"); 836 if (IS_ERR(ipu->clk)) { 837 dev_err(dev, "Failed to get pixel clock\n"); 838 return PTR_ERR(ipu->clk); 839 } 840 841 err = devm_request_irq(dev, irq, ingenic_ipu_irq_handler, 0, 842 dev_name(dev), ipu); 843 if (err) { 844 dev_err(dev, "Unable to request IRQ\n"); 845 return err; 846 } 847 848 plane = &ipu->plane; 849 dev_set_drvdata(dev, plane); 850 851 drm_plane_helper_add(plane, &ingenic_ipu_plane_helper_funcs); 852 853 err = drm_universal_plane_init(drm, plane, 1, &ingenic_ipu_plane_funcs, 854 soc_info->formats, soc_info->num_formats, 855 NULL, DRM_PLANE_TYPE_OVERLAY, NULL); 856 if (err) { 857 dev_err(dev, "Failed to init plane: %i\n", err); 858 return err; 859 } 860 861 if (ingenic_drm_map_noncoherent(master)) 862 drm_plane_enable_fb_damage_clips(plane); 863 864 /* 865 * Sharpness settings range is [0,32] 866 * 0 : nearest-neighbor 867 * 1 : bilinear 868 * 2 .. 32 : bicubic (translated to sharpness factor -0.25 .. -4.0) 869 */ 870 sharpness_max = soc_info->has_bicubic ? 32 : 1; 871 ipu->sharpness_prop = drm_property_create_range(drm, 0, "sharpness", 872 0, sharpness_max); 873 if (!ipu->sharpness_prop) { 874 dev_err(dev, "Unable to create sharpness property\n"); 875 return -ENOMEM; 876 } 877 878 /* Default sharpness factor: -0.125 * 8 = -1.0 */ 879 ipu->sharpness = soc_info->has_bicubic ? 8 : 1; 880 drm_object_attach_property(&plane->base, ipu->sharpness_prop, 881 ipu->sharpness); 882 883 err = clk_prepare(ipu->clk); 884 if (err) { 885 dev_err(dev, "Unable to prepare clock\n"); 886 return err; 887 } 888 889 private_state = kzalloc(sizeof(*private_state), GFP_KERNEL); 890 if (!private_state) { 891 err = -ENOMEM; 892 goto err_clk_unprepare; 893 } 894 895 drm_atomic_private_obj_init(drm, &ipu->private_obj, &private_state->base, 896 &ingenic_ipu_private_state_funcs); 897 898 return 0; 899 900 err_clk_unprepare: 901 clk_unprepare(ipu->clk); 902 return err; 903 } 904 905 static void ingenic_ipu_unbind(struct device *dev, 906 struct device *master, void *d) 907 { 908 struct ingenic_ipu *ipu = dev_get_drvdata(dev); 909 910 drm_atomic_private_obj_fini(&ipu->private_obj); 911 clk_unprepare(ipu->clk); 912 } 913 914 static const struct component_ops ingenic_ipu_ops = { 915 .bind = ingenic_ipu_bind, 916 .unbind = ingenic_ipu_unbind, 917 }; 918 919 static int ingenic_ipu_probe(struct platform_device *pdev) 920 { 921 return component_add(&pdev->dev, &ingenic_ipu_ops); 922 } 923 924 static int ingenic_ipu_remove(struct platform_device *pdev) 925 { 926 component_del(&pdev->dev, &ingenic_ipu_ops); 927 return 0; 928 } 929 930 static const u32 jz4725b_ipu_formats[] = { 931 /* 932 * While officially supported, packed YUV 4:2:2 formats can cause 933 * random hardware crashes on JZ4725B under certain circumstances. 934 * It seems to happen with some specific resize ratios. 935 * Until a proper workaround or fix is found, disable these formats. 936 DRM_FORMAT_YUYV, 937 DRM_FORMAT_YVYU, 938 DRM_FORMAT_UYVY, 939 DRM_FORMAT_VYUY, 940 */ 941 DRM_FORMAT_YUV411, 942 DRM_FORMAT_YUV420, 943 DRM_FORMAT_YUV422, 944 DRM_FORMAT_YUV444, 945 }; 946 947 static const struct soc_info jz4725b_soc_info = { 948 .formats = jz4725b_ipu_formats, 949 .num_formats = ARRAY_SIZE(jz4725b_ipu_formats), 950 .has_bicubic = false, 951 .manual_restart = true, 952 .set_coefs = jz4725b_set_coefs, 953 }; 954 955 static const u32 jz4760_ipu_formats[] = { 956 DRM_FORMAT_XRGB1555, 957 DRM_FORMAT_XBGR1555, 958 DRM_FORMAT_RGB565, 959 DRM_FORMAT_BGR565, 960 DRM_FORMAT_XRGB8888, 961 DRM_FORMAT_XBGR8888, 962 DRM_FORMAT_YUYV, 963 DRM_FORMAT_YVYU, 964 DRM_FORMAT_UYVY, 965 DRM_FORMAT_VYUY, 966 DRM_FORMAT_YUV411, 967 DRM_FORMAT_YUV420, 968 DRM_FORMAT_YUV422, 969 DRM_FORMAT_YUV444, 970 DRM_FORMAT_XYUV8888, 971 }; 972 973 static const struct soc_info jz4760_soc_info = { 974 .formats = jz4760_ipu_formats, 975 .num_formats = ARRAY_SIZE(jz4760_ipu_formats), 976 .has_bicubic = true, 977 .manual_restart = false, 978 .set_coefs = jz4760_set_coefs, 979 }; 980 981 static const struct of_device_id ingenic_ipu_of_match[] = { 982 { .compatible = "ingenic,jz4725b-ipu", .data = &jz4725b_soc_info }, 983 { .compatible = "ingenic,jz4760-ipu", .data = &jz4760_soc_info }, 984 { /* sentinel */ }, 985 }; 986 MODULE_DEVICE_TABLE(of, ingenic_ipu_of_match); 987 988 static struct platform_driver ingenic_ipu_driver = { 989 .driver = { 990 .name = "ingenic-ipu", 991 .of_match_table = ingenic_ipu_of_match, 992 }, 993 .probe = ingenic_ipu_probe, 994 .remove = ingenic_ipu_remove, 995 }; 996 997 struct platform_driver *ingenic_ipu_driver_ptr = &ingenic_ipu_driver; 998