1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * i.MX drm driver - Television Encoder (TVEv2) 4 * 5 * Copyright (C) 2013 Philipp Zabel, Pengutronix 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/clk.h> 10 #include <linux/component.h> 11 #include <linux/i2c.h> 12 #include <linux/module.h> 13 #include <linux/platform_device.h> 14 #include <linux/regmap.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/videodev2.h> 17 18 #include <video/imx-ipu-v3.h> 19 20 #include <drm/drm_atomic_helper.h> 21 #include <drm/drm_edid.h> 22 #include <drm/drm_managed.h> 23 #include <drm/drm_probe_helper.h> 24 #include <drm/drm_simple_kms_helper.h> 25 26 #include "imx-drm.h" 27 28 #define TVE_COM_CONF_REG 0x00 29 #define TVE_TVDAC0_CONT_REG 0x28 30 #define TVE_TVDAC1_CONT_REG 0x2c 31 #define TVE_TVDAC2_CONT_REG 0x30 32 #define TVE_CD_CONT_REG 0x34 33 #define TVE_INT_CONT_REG 0x64 34 #define TVE_STAT_REG 0x68 35 #define TVE_TST_MODE_REG 0x6c 36 #define TVE_MV_CONT_REG 0xdc 37 38 /* TVE_COM_CONF_REG */ 39 #define TVE_SYNC_CH_2_EN BIT(22) 40 #define TVE_SYNC_CH_1_EN BIT(21) 41 #define TVE_SYNC_CH_0_EN BIT(20) 42 #define TVE_TV_OUT_MODE_MASK (0x7 << 12) 43 #define TVE_TV_OUT_DISABLE (0x0 << 12) 44 #define TVE_TV_OUT_CVBS_0 (0x1 << 12) 45 #define TVE_TV_OUT_CVBS_2 (0x2 << 12) 46 #define TVE_TV_OUT_CVBS_0_2 (0x3 << 12) 47 #define TVE_TV_OUT_SVIDEO_0_1 (0x4 << 12) 48 #define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2 (0x5 << 12) 49 #define TVE_TV_OUT_YPBPR (0x6 << 12) 50 #define TVE_TV_OUT_RGB (0x7 << 12) 51 #define TVE_TV_STAND_MASK (0xf << 8) 52 #define TVE_TV_STAND_HD_1080P30 (0xc << 8) 53 #define TVE_P2I_CONV_EN BIT(7) 54 #define TVE_INP_VIDEO_FORM BIT(6) 55 #define TVE_INP_YCBCR_422 (0x0 << 6) 56 #define TVE_INP_YCBCR_444 (0x1 << 6) 57 #define TVE_DATA_SOURCE_MASK (0x3 << 4) 58 #define TVE_DATA_SOURCE_BUS1 (0x0 << 4) 59 #define TVE_DATA_SOURCE_BUS2 (0x1 << 4) 60 #define TVE_DATA_SOURCE_EXT (0x2 << 4) 61 #define TVE_DATA_SOURCE_TESTGEN (0x3 << 4) 62 #define TVE_IPU_CLK_EN_OFS 3 63 #define TVE_IPU_CLK_EN BIT(3) 64 #define TVE_DAC_SAMP_RATE_OFS 1 65 #define TVE_DAC_SAMP_RATE_WIDTH 2 66 #define TVE_DAC_SAMP_RATE_MASK (0x3 << 1) 67 #define TVE_DAC_FULL_RATE (0x0 << 1) 68 #define TVE_DAC_DIV2_RATE (0x1 << 1) 69 #define TVE_DAC_DIV4_RATE (0x2 << 1) 70 #define TVE_EN BIT(0) 71 72 /* TVE_TVDACx_CONT_REG */ 73 #define TVE_TVDAC_GAIN_MASK (0x3f << 0) 74 75 /* TVE_CD_CONT_REG */ 76 #define TVE_CD_CH_2_SM_EN BIT(22) 77 #define TVE_CD_CH_1_SM_EN BIT(21) 78 #define TVE_CD_CH_0_SM_EN BIT(20) 79 #define TVE_CD_CH_2_LM_EN BIT(18) 80 #define TVE_CD_CH_1_LM_EN BIT(17) 81 #define TVE_CD_CH_0_LM_EN BIT(16) 82 #define TVE_CD_CH_2_REF_LVL BIT(10) 83 #define TVE_CD_CH_1_REF_LVL BIT(9) 84 #define TVE_CD_CH_0_REF_LVL BIT(8) 85 #define TVE_CD_EN BIT(0) 86 87 /* TVE_INT_CONT_REG */ 88 #define TVE_FRAME_END_IEN BIT(13) 89 #define TVE_CD_MON_END_IEN BIT(2) 90 #define TVE_CD_SM_IEN BIT(1) 91 #define TVE_CD_LM_IEN BIT(0) 92 93 /* TVE_TST_MODE_REG */ 94 #define TVE_TVDAC_TEST_MODE_MASK (0x7 << 0) 95 96 #define IMX_TVE_DAC_VOLTAGE 2750000 97 98 enum { 99 TVE_MODE_TVOUT, 100 TVE_MODE_VGA, 101 }; 102 103 struct imx_tve_encoder { 104 struct drm_connector connector; 105 struct drm_encoder encoder; 106 struct imx_tve *tve; 107 }; 108 109 struct imx_tve { 110 struct device *dev; 111 int mode; 112 int di_hsync_pin; 113 int di_vsync_pin; 114 115 struct regmap *regmap; 116 struct regulator *dac_reg; 117 struct i2c_adapter *ddc; 118 struct clk *clk; 119 struct clk *di_sel_clk; 120 struct clk_hw clk_hw_di; 121 struct clk *di_clk; 122 }; 123 124 static inline struct imx_tve *con_to_tve(struct drm_connector *c) 125 { 126 return container_of(c, struct imx_tve_encoder, connector)->tve; 127 } 128 129 static inline struct imx_tve *enc_to_tve(struct drm_encoder *e) 130 { 131 return container_of(e, struct imx_tve_encoder, encoder)->tve; 132 } 133 134 static void tve_enable(struct imx_tve *tve) 135 { 136 clk_prepare_enable(tve->clk); 137 regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_EN, TVE_EN); 138 139 /* clear interrupt status register */ 140 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff); 141 142 /* cable detection irq disabled in VGA mode, enabled in TVOUT mode */ 143 if (tve->mode == TVE_MODE_VGA) 144 regmap_write(tve->regmap, TVE_INT_CONT_REG, 0); 145 else 146 regmap_write(tve->regmap, TVE_INT_CONT_REG, 147 TVE_CD_SM_IEN | 148 TVE_CD_LM_IEN | 149 TVE_CD_MON_END_IEN); 150 } 151 152 static void tve_disable(struct imx_tve *tve) 153 { 154 regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_EN, 0); 155 clk_disable_unprepare(tve->clk); 156 } 157 158 static int tve_setup_tvout(struct imx_tve *tve) 159 { 160 return -ENOTSUPP; 161 } 162 163 static int tve_setup_vga(struct imx_tve *tve) 164 { 165 unsigned int mask; 166 unsigned int val; 167 int ret; 168 169 /* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */ 170 ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG, 171 TVE_TVDAC_GAIN_MASK, 0x0a); 172 if (ret) 173 return ret; 174 175 ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG, 176 TVE_TVDAC_GAIN_MASK, 0x0a); 177 if (ret) 178 return ret; 179 180 ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG, 181 TVE_TVDAC_GAIN_MASK, 0x0a); 182 if (ret) 183 return ret; 184 185 /* set configuration register */ 186 mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM; 187 val = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444; 188 mask |= TVE_TV_STAND_MASK | TVE_P2I_CONV_EN; 189 val |= TVE_TV_STAND_HD_1080P30 | 0; 190 mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN; 191 val |= TVE_TV_OUT_RGB | TVE_SYNC_CH_0_EN; 192 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val); 193 if (ret) 194 return ret; 195 196 /* set test mode (as documented) */ 197 return regmap_update_bits(tve->regmap, TVE_TST_MODE_REG, 198 TVE_TVDAC_TEST_MODE_MASK, 1); 199 } 200 201 static int imx_tve_connector_get_modes(struct drm_connector *connector) 202 { 203 struct imx_tve *tve = con_to_tve(connector); 204 const struct drm_edid *drm_edid; 205 int ret; 206 207 if (!tve->ddc) 208 return 0; 209 210 drm_edid = drm_edid_read_ddc(connector, tve->ddc); 211 drm_edid_connector_update(connector, drm_edid); 212 ret = drm_edid_connector_add_modes(connector); 213 drm_edid_free(drm_edid); 214 215 return ret; 216 } 217 218 static enum drm_mode_status 219 imx_tve_connector_mode_valid(struct drm_connector *connector, 220 const struct drm_display_mode *mode) 221 { 222 struct imx_tve *tve = con_to_tve(connector); 223 unsigned long rate; 224 225 /* pixel clock with 2x oversampling */ 226 rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000; 227 if (rate == mode->clock) 228 return MODE_OK; 229 230 /* pixel clock without oversampling */ 231 rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000; 232 if (rate == mode->clock) 233 return MODE_OK; 234 235 dev_warn(tve->dev, "ignoring mode %dx%d\n", 236 mode->hdisplay, mode->vdisplay); 237 238 return MODE_BAD; 239 } 240 241 static void imx_tve_encoder_mode_set(struct drm_encoder *encoder, 242 struct drm_display_mode *orig_mode, 243 struct drm_display_mode *mode) 244 { 245 struct imx_tve *tve = enc_to_tve(encoder); 246 unsigned long rounded_rate; 247 unsigned long rate; 248 int div = 1; 249 int ret; 250 251 /* 252 * FIXME 253 * we should try 4k * mode->clock first, 254 * and enable 4x oversampling for lower resolutions 255 */ 256 rate = 2000UL * mode->clock; 257 clk_set_rate(tve->clk, rate); 258 rounded_rate = clk_get_rate(tve->clk); 259 if (rounded_rate >= rate) 260 div = 2; 261 clk_set_rate(tve->di_clk, rounded_rate / div); 262 263 ret = clk_set_parent(tve->di_sel_clk, tve->di_clk); 264 if (ret < 0) { 265 dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n", 266 ret); 267 } 268 269 regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, 270 TVE_IPU_CLK_EN, TVE_IPU_CLK_EN); 271 272 if (tve->mode == TVE_MODE_VGA) 273 ret = tve_setup_vga(tve); 274 else 275 ret = tve_setup_tvout(tve); 276 if (ret) 277 dev_err(tve->dev, "failed to set configuration: %d\n", ret); 278 } 279 280 static void imx_tve_encoder_enable(struct drm_encoder *encoder) 281 { 282 struct imx_tve *tve = enc_to_tve(encoder); 283 284 tve_enable(tve); 285 } 286 287 static void imx_tve_encoder_disable(struct drm_encoder *encoder) 288 { 289 struct imx_tve *tve = enc_to_tve(encoder); 290 291 tve_disable(tve); 292 } 293 294 static int imx_tve_atomic_check(struct drm_encoder *encoder, 295 struct drm_crtc_state *crtc_state, 296 struct drm_connector_state *conn_state) 297 { 298 struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state); 299 struct imx_tve *tve = enc_to_tve(encoder); 300 301 imx_crtc_state->bus_format = MEDIA_BUS_FMT_GBR888_1X24; 302 imx_crtc_state->di_hsync_pin = tve->di_hsync_pin; 303 imx_crtc_state->di_vsync_pin = tve->di_vsync_pin; 304 305 return 0; 306 } 307 308 static void imx_tve_connector_destroy(struct drm_connector *connector) 309 { 310 drm_connector_unregister(connector); 311 drm_connector_cleanup(connector); 312 } 313 314 static const struct drm_connector_funcs imx_tve_connector_funcs = { 315 .fill_modes = drm_helper_probe_single_connector_modes, 316 .destroy = imx_tve_connector_destroy, 317 .reset = drm_atomic_helper_connector_reset, 318 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 319 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 320 }; 321 322 static const struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = { 323 .get_modes = imx_tve_connector_get_modes, 324 .mode_valid = imx_tve_connector_mode_valid, 325 }; 326 327 static const struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = { 328 .mode_set = imx_tve_encoder_mode_set, 329 .enable = imx_tve_encoder_enable, 330 .disable = imx_tve_encoder_disable, 331 .atomic_check = imx_tve_atomic_check, 332 }; 333 334 static irqreturn_t imx_tve_irq_handler(int irq, void *data) 335 { 336 struct imx_tve *tve = data; 337 unsigned int val; 338 339 regmap_read(tve->regmap, TVE_STAT_REG, &val); 340 341 /* clear interrupt status register */ 342 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff); 343 344 return IRQ_HANDLED; 345 } 346 347 static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw, 348 unsigned long parent_rate) 349 { 350 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di); 351 unsigned int val; 352 int ret; 353 354 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val); 355 if (ret < 0) 356 return 0; 357 358 switch (val & TVE_DAC_SAMP_RATE_MASK) { 359 case TVE_DAC_DIV4_RATE: 360 return parent_rate / 4; 361 case TVE_DAC_DIV2_RATE: 362 return parent_rate / 2; 363 case TVE_DAC_FULL_RATE: 364 default: 365 return parent_rate; 366 } 367 368 return 0; 369 } 370 371 static int clk_tve_di_determine_rate(struct clk_hw *hw, 372 struct clk_rate_request *req) 373 { 374 unsigned long div; 375 376 div = req->best_parent_rate / req->rate; 377 if (div >= 4) 378 req->rate = req->best_parent_rate / 4; 379 else if (div >= 2) 380 req->rate = req->best_parent_rate / 2; 381 else 382 req->rate = req->best_parent_rate; 383 384 return 0; 385 } 386 387 static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate, 388 unsigned long parent_rate) 389 { 390 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di); 391 unsigned long div; 392 u32 val; 393 int ret; 394 395 div = parent_rate / rate; 396 if (div >= 4) 397 val = TVE_DAC_DIV4_RATE; 398 else if (div >= 2) 399 val = TVE_DAC_DIV2_RATE; 400 else 401 val = TVE_DAC_FULL_RATE; 402 403 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, 404 TVE_DAC_SAMP_RATE_MASK, val); 405 406 if (ret < 0) { 407 dev_err(tve->dev, "failed to set divider: %d\n", ret); 408 return ret; 409 } 410 411 return 0; 412 } 413 414 static const struct clk_ops clk_tve_di_ops = { 415 .determine_rate = clk_tve_di_determine_rate, 416 .set_rate = clk_tve_di_set_rate, 417 .recalc_rate = clk_tve_di_recalc_rate, 418 }; 419 420 static int tve_clk_init(struct imx_tve *tve, void __iomem *base) 421 { 422 const char *tve_di_parent[1]; 423 struct clk_init_data init = { 424 .name = "tve_di", 425 .ops = &clk_tve_di_ops, 426 .num_parents = 1, 427 .flags = 0, 428 }; 429 430 tve_di_parent[0] = __clk_get_name(tve->clk); 431 init.parent_names = (const char **)&tve_di_parent; 432 433 tve->clk_hw_di.init = &init; 434 tve->di_clk = devm_clk_register(tve->dev, &tve->clk_hw_di); 435 if (IS_ERR(tve->di_clk)) { 436 dev_err(tve->dev, "failed to register TVE output clock: %ld\n", 437 PTR_ERR(tve->di_clk)); 438 return PTR_ERR(tve->di_clk); 439 } 440 441 return 0; 442 } 443 444 static void imx_tve_disable_regulator(void *data) 445 { 446 struct imx_tve *tve = data; 447 448 regulator_disable(tve->dac_reg); 449 } 450 451 static bool imx_tve_readable_reg(struct device *dev, unsigned int reg) 452 { 453 return (reg % 4 == 0) && (reg <= 0xdc); 454 } 455 456 static struct regmap_config tve_regmap_config = { 457 .reg_bits = 32, 458 .val_bits = 32, 459 .reg_stride = 4, 460 461 .readable_reg = imx_tve_readable_reg, 462 463 .fast_io = true, 464 465 .max_register = 0xdc, 466 }; 467 468 static const char * const imx_tve_modes[] = { 469 [TVE_MODE_TVOUT] = "tvout", 470 [TVE_MODE_VGA] = "vga", 471 }; 472 473 static int of_get_tve_mode(struct device_node *np) 474 { 475 const char *bm; 476 int ret, i; 477 478 ret = of_property_read_string(np, "fsl,tve-mode", &bm); 479 if (ret < 0) 480 return ret; 481 482 for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++) 483 if (!strcasecmp(bm, imx_tve_modes[i])) 484 return i; 485 486 return -EINVAL; 487 } 488 489 static int imx_tve_bind(struct device *dev, struct device *master, void *data) 490 { 491 struct drm_device *drm = data; 492 struct imx_tve *tve = dev_get_drvdata(dev); 493 struct imx_tve_encoder *tvee; 494 struct drm_encoder *encoder; 495 struct drm_connector *connector; 496 int encoder_type; 497 int ret; 498 499 encoder_type = tve->mode == TVE_MODE_VGA ? 500 DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC; 501 502 tvee = drmm_simple_encoder_alloc(drm, struct imx_tve_encoder, encoder, 503 encoder_type); 504 if (IS_ERR(tvee)) 505 return PTR_ERR(tvee); 506 507 tvee->tve = tve; 508 encoder = &tvee->encoder; 509 connector = &tvee->connector; 510 511 ret = imx_drm_encoder_parse_of(drm, encoder, tve->dev->of_node); 512 if (ret) 513 return ret; 514 515 drm_encoder_helper_add(encoder, &imx_tve_encoder_helper_funcs); 516 517 drm_connector_helper_add(connector, &imx_tve_connector_helper_funcs); 518 ret = drm_connector_init_with_ddc(drm, connector, 519 &imx_tve_connector_funcs, 520 DRM_MODE_CONNECTOR_VGA, tve->ddc); 521 if (ret) 522 return ret; 523 524 return drm_connector_attach_encoder(connector, encoder); 525 } 526 527 static const struct component_ops imx_tve_ops = { 528 .bind = imx_tve_bind, 529 }; 530 531 static int imx_tve_probe(struct platform_device *pdev) 532 { 533 struct device *dev = &pdev->dev; 534 struct device_node *np = dev->of_node; 535 struct device_node *ddc_node; 536 struct imx_tve *tve; 537 void __iomem *base; 538 unsigned int val; 539 int irq; 540 int ret; 541 542 tve = devm_kzalloc(dev, sizeof(*tve), GFP_KERNEL); 543 if (!tve) 544 return -ENOMEM; 545 546 tve->dev = dev; 547 548 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0); 549 if (ddc_node) { 550 tve->ddc = of_find_i2c_adapter_by_node(ddc_node); 551 of_node_put(ddc_node); 552 } 553 554 tve->mode = of_get_tve_mode(np); 555 if (tve->mode != TVE_MODE_VGA) { 556 dev_err(dev, "only VGA mode supported, currently\n"); 557 return -EINVAL; 558 } 559 560 if (tve->mode == TVE_MODE_VGA) { 561 ret = of_property_read_u32(np, "fsl,hsync-pin", 562 &tve->di_hsync_pin); 563 564 if (ret < 0) { 565 dev_err(dev, "failed to get hsync pin\n"); 566 return ret; 567 } 568 569 ret = of_property_read_u32(np, "fsl,vsync-pin", 570 &tve->di_vsync_pin); 571 572 if (ret < 0) { 573 dev_err(dev, "failed to get vsync pin\n"); 574 return ret; 575 } 576 } 577 578 base = devm_platform_ioremap_resource(pdev, 0); 579 if (IS_ERR(base)) 580 return PTR_ERR(base); 581 582 tve_regmap_config.lock_arg = tve; 583 tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base, 584 &tve_regmap_config); 585 if (IS_ERR(tve->regmap)) { 586 dev_err(dev, "failed to init regmap: %ld\n", 587 PTR_ERR(tve->regmap)); 588 return PTR_ERR(tve->regmap); 589 } 590 591 irq = platform_get_irq(pdev, 0); 592 if (irq < 0) 593 return irq; 594 595 ret = devm_request_threaded_irq(dev, irq, NULL, 596 imx_tve_irq_handler, IRQF_ONESHOT, 597 "imx-tve", tve); 598 if (ret < 0) { 599 dev_err(dev, "failed to request irq: %d\n", ret); 600 return ret; 601 } 602 603 tve->dac_reg = devm_regulator_get(dev, "dac"); 604 if (!IS_ERR(tve->dac_reg)) { 605 if (regulator_get_voltage(tve->dac_reg) != IMX_TVE_DAC_VOLTAGE) 606 dev_warn(dev, "dac voltage is not %d uV\n", IMX_TVE_DAC_VOLTAGE); 607 ret = regulator_enable(tve->dac_reg); 608 if (ret) 609 return ret; 610 ret = devm_add_action_or_reset(dev, imx_tve_disable_regulator, tve); 611 if (ret) 612 return ret; 613 } 614 615 tve->clk = devm_clk_get(dev, "tve"); 616 if (IS_ERR(tve->clk)) { 617 dev_err(dev, "failed to get high speed tve clock: %ld\n", 618 PTR_ERR(tve->clk)); 619 return PTR_ERR(tve->clk); 620 } 621 622 /* this is the IPU DI clock input selector, can be parented to tve_di */ 623 tve->di_sel_clk = devm_clk_get(dev, "di_sel"); 624 if (IS_ERR(tve->di_sel_clk)) { 625 dev_err(dev, "failed to get ipu di mux clock: %ld\n", 626 PTR_ERR(tve->di_sel_clk)); 627 return PTR_ERR(tve->di_sel_clk); 628 } 629 630 ret = tve_clk_init(tve, base); 631 if (ret < 0) 632 return ret; 633 634 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val); 635 if (ret < 0) { 636 dev_err(dev, "failed to read configuration register: %d\n", 637 ret); 638 return ret; 639 } 640 if (val != 0x00100000) { 641 dev_err(dev, "configuration register default value indicates this is not a TVEv2\n"); 642 return -ENODEV; 643 } 644 645 /* disable cable detection for VGA mode */ 646 ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0); 647 if (ret) 648 return ret; 649 650 platform_set_drvdata(pdev, tve); 651 652 return component_add(dev, &imx_tve_ops); 653 } 654 655 static void imx_tve_remove(struct platform_device *pdev) 656 { 657 component_del(&pdev->dev, &imx_tve_ops); 658 } 659 660 static const struct of_device_id imx_tve_dt_ids[] = { 661 { .compatible = "fsl,imx53-tve", }, 662 { /* sentinel */ } 663 }; 664 MODULE_DEVICE_TABLE(of, imx_tve_dt_ids); 665 666 static struct platform_driver imx_tve_driver = { 667 .probe = imx_tve_probe, 668 .remove = imx_tve_remove, 669 .driver = { 670 .of_match_table = imx_tve_dt_ids, 671 .name = "imx-tve", 672 }, 673 }; 674 675 module_platform_driver(imx_tve_driver); 676 677 MODULE_DESCRIPTION("i.MX Television Encoder driver"); 678 MODULE_AUTHOR("Philipp Zabel, Pengutronix"); 679 MODULE_LICENSE("GPL"); 680 MODULE_ALIAS("platform:imx-tve"); 681