1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * i.MX drm driver - LVDS display bridge 4 * 5 * Copyright (C) 2012 Sascha Hauer, Pengutronix 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/component.h> 10 #include <linux/i2c.h> 11 #include <linux/media-bus-format.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_graph.h> 17 #include <linux/platform_device.h> 18 #include <linux/property.h> 19 #include <linux/regmap.h> 20 #include <linux/videodev2.h> 21 22 #include <drm/drm_atomic.h> 23 #include <drm/drm_atomic_helper.h> 24 #include <drm/drm_bridge.h> 25 #include <drm/drm_bridge_connector.h> 26 #include <drm/drm_managed.h> 27 #include <drm/drm_of.h> 28 #include <drm/drm_print.h> 29 #include <drm/drm_probe_helper.h> 30 #include <drm/drm_simple_kms_helper.h> 31 #include <drm/bridge/of-display-mode-bridge.h> 32 33 #include "imx-drm.h" 34 35 #define DRIVER_NAME "imx-ldb" 36 37 #define LDB_CH0_MODE_EN_TO_DI0 (1 << 0) 38 #define LDB_CH0_MODE_EN_TO_DI1 (3 << 0) 39 #define LDB_CH0_MODE_EN_MASK (3 << 0) 40 #define LDB_CH1_MODE_EN_TO_DI0 (1 << 2) 41 #define LDB_CH1_MODE_EN_TO_DI1 (3 << 2) 42 #define LDB_CH1_MODE_EN_MASK (3 << 2) 43 #define LDB_SPLIT_MODE_EN (1 << 4) 44 #define LDB_DATA_WIDTH_CH0_24 (1 << 5) 45 #define LDB_BIT_MAP_CH0_JEIDA (1 << 6) 46 #define LDB_DATA_WIDTH_CH1_24 (1 << 7) 47 #define LDB_BIT_MAP_CH1_JEIDA (1 << 8) 48 #define LDB_DI0_VS_POL_ACT_LOW (1 << 9) 49 #define LDB_DI1_VS_POL_ACT_LOW (1 << 10) 50 #define LDB_BGREF_RMODE_INT (1 << 15) 51 52 struct imx_ldb_channel; 53 54 struct imx_ldb_encoder { 55 struct drm_encoder encoder; 56 struct imx_ldb_channel *channel; 57 }; 58 59 struct imx_ldb; 60 61 struct imx_ldb_channel { 62 struct imx_ldb *ldb; 63 64 struct drm_bridge *bridge; 65 66 struct device_node *child; 67 int chno; 68 u32 bus_format; 69 }; 70 71 static inline struct imx_ldb_channel *enc_to_imx_ldb_ch(struct drm_encoder *e) 72 { 73 return container_of(e, struct imx_ldb_encoder, encoder)->channel; 74 } 75 76 struct bus_mux { 77 int reg; 78 int shift; 79 int mask; 80 }; 81 82 struct imx_ldb { 83 struct regmap *regmap; 84 struct device *dev; 85 struct imx_ldb_channel channel[2]; 86 struct clk *clk[2]; /* our own clock */ 87 struct clk *clk_sel[4]; /* parent of display clock */ 88 struct clk *clk_parent[4]; /* original parent of clk_sel */ 89 struct clk *clk_pll[2]; /* upstream clock we can adjust */ 90 u32 ldb_ctrl; 91 const struct bus_mux *lvds_mux; 92 }; 93 94 static void imx_ldb_ch_set_bus_format(struct imx_ldb_channel *imx_ldb_ch, 95 u32 bus_format) 96 { 97 struct imx_ldb *ldb = imx_ldb_ch->ldb; 98 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN; 99 100 switch (bus_format) { 101 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 102 break; 103 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 104 if (imx_ldb_ch->chno == 0 || dual) 105 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24; 106 if (imx_ldb_ch->chno == 1 || dual) 107 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24; 108 break; 109 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 110 if (imx_ldb_ch->chno == 0 || dual) 111 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 | 112 LDB_BIT_MAP_CH0_JEIDA; 113 if (imx_ldb_ch->chno == 1 || dual) 114 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 | 115 LDB_BIT_MAP_CH1_JEIDA; 116 break; 117 } 118 } 119 120 static void imx_ldb_set_clock(struct imx_ldb *ldb, int mux, int chno, 121 unsigned long serial_clk, unsigned long di_clk) 122 { 123 int ret; 124 125 dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__, 126 clk_get_rate(ldb->clk_pll[chno]), serial_clk); 127 clk_set_rate(ldb->clk_pll[chno], serial_clk); 128 129 dev_dbg(ldb->dev, "%s after: %ld\n", __func__, 130 clk_get_rate(ldb->clk_pll[chno])); 131 132 dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__, 133 clk_get_rate(ldb->clk[chno]), 134 (long int)di_clk); 135 clk_set_rate(ldb->clk[chno], di_clk); 136 137 dev_dbg(ldb->dev, "%s after: %ld\n", __func__, 138 clk_get_rate(ldb->clk[chno])); 139 140 /* set display clock mux to LDB input clock */ 141 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]); 142 if (ret) 143 dev_err(ldb->dev, 144 "unable to set di%d parent clock to ldb_di%d\n", mux, 145 chno); 146 } 147 148 static void imx_ldb_encoder_enable(struct drm_encoder *encoder) 149 { 150 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); 151 struct imx_ldb *ldb = imx_ldb_ch->ldb; 152 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN; 153 int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder); 154 155 if (mux < 0 || mux >= ARRAY_SIZE(ldb->clk_sel)) { 156 dev_warn(ldb->dev, "%s: invalid mux %d\n", __func__, mux); 157 return; 158 } 159 160 if (dual) { 161 clk_set_parent(ldb->clk_sel[mux], ldb->clk[0]); 162 clk_set_parent(ldb->clk_sel[mux], ldb->clk[1]); 163 164 clk_prepare_enable(ldb->clk[0]); 165 clk_prepare_enable(ldb->clk[1]); 166 } else { 167 clk_set_parent(ldb->clk_sel[mux], ldb->clk[imx_ldb_ch->chno]); 168 } 169 170 if (imx_ldb_ch == &ldb->channel[0] || dual) { 171 ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK; 172 if (mux == 0 || ldb->lvds_mux) 173 ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0; 174 else if (mux == 1) 175 ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI1; 176 } 177 if (imx_ldb_ch == &ldb->channel[1] || dual) { 178 ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK; 179 if (mux == 1 || ldb->lvds_mux) 180 ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI1; 181 else if (mux == 0) 182 ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0; 183 } 184 185 if (ldb->lvds_mux) { 186 const struct bus_mux *lvds_mux = NULL; 187 188 if (imx_ldb_ch == &ldb->channel[0]) 189 lvds_mux = &ldb->lvds_mux[0]; 190 else if (imx_ldb_ch == &ldb->channel[1]) 191 lvds_mux = &ldb->lvds_mux[1]; 192 193 regmap_update_bits(ldb->regmap, lvds_mux->reg, lvds_mux->mask, 194 mux << lvds_mux->shift); 195 } 196 197 regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl); 198 } 199 200 static void 201 imx_ldb_encoder_atomic_mode_set(struct drm_encoder *encoder, 202 struct drm_crtc_state *crtc_state, 203 struct drm_connector_state *connector_state) 204 { 205 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); 206 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 207 struct imx_ldb *ldb = imx_ldb_ch->ldb; 208 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN; 209 unsigned long serial_clk; 210 unsigned long di_clk = mode->clock * 1000; 211 int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder); 212 u32 bus_format = imx_ldb_ch->bus_format; 213 214 if (mux < 0 || mux >= ARRAY_SIZE(ldb->clk_sel)) { 215 dev_warn(ldb->dev, "%s: invalid mux %d\n", __func__, mux); 216 return; 217 } 218 219 if (mode->clock > 170000) { 220 dev_warn(ldb->dev, 221 "%s: mode exceeds 170 MHz pixel clock\n", __func__); 222 } 223 if (mode->clock > 85000 && !dual) { 224 dev_warn(ldb->dev, 225 "%s: mode exceeds 85 MHz pixel clock\n", __func__); 226 } 227 228 if (!IS_ALIGNED(mode->hdisplay, 8)) { 229 dev_warn(ldb->dev, 230 "%s: hdisplay does not align to 8 byte\n", __func__); 231 } 232 233 if (dual) { 234 serial_clk = 3500UL * mode->clock; 235 imx_ldb_set_clock(ldb, mux, 0, serial_clk, di_clk); 236 imx_ldb_set_clock(ldb, mux, 1, serial_clk, di_clk); 237 } else { 238 serial_clk = 7000UL * mode->clock; 239 imx_ldb_set_clock(ldb, mux, imx_ldb_ch->chno, serial_clk, 240 di_clk); 241 } 242 243 /* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */ 244 if (imx_ldb_ch == &ldb->channel[0] || dual) { 245 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 246 ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW; 247 else if (mode->flags & DRM_MODE_FLAG_PVSYNC) 248 ldb->ldb_ctrl &= ~LDB_DI0_VS_POL_ACT_LOW; 249 } 250 if (imx_ldb_ch == &ldb->channel[1] || dual) { 251 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 252 ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW; 253 else if (mode->flags & DRM_MODE_FLAG_PVSYNC) 254 ldb->ldb_ctrl &= ~LDB_DI1_VS_POL_ACT_LOW; 255 } 256 257 if (!bus_format) { 258 struct drm_connector *connector = connector_state->connector; 259 struct drm_display_info *di = &connector->display_info; 260 261 if (di->num_bus_formats) 262 bus_format = di->bus_formats[0]; 263 } 264 imx_ldb_ch_set_bus_format(imx_ldb_ch, bus_format); 265 } 266 267 static void imx_ldb_encoder_disable(struct drm_encoder *encoder) 268 { 269 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); 270 struct imx_ldb *ldb = imx_ldb_ch->ldb; 271 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN; 272 int mux, ret; 273 274 if (imx_ldb_ch == &ldb->channel[0] || dual) 275 ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK; 276 if (imx_ldb_ch == &ldb->channel[1] || dual) 277 ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK; 278 279 regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl); 280 281 if (dual) { 282 clk_disable_unprepare(ldb->clk[0]); 283 clk_disable_unprepare(ldb->clk[1]); 284 } 285 286 if (ldb->lvds_mux) { 287 const struct bus_mux *lvds_mux = NULL; 288 289 if (imx_ldb_ch == &ldb->channel[0]) 290 lvds_mux = &ldb->lvds_mux[0]; 291 else if (imx_ldb_ch == &ldb->channel[1]) 292 lvds_mux = &ldb->lvds_mux[1]; 293 294 regmap_read(ldb->regmap, lvds_mux->reg, &mux); 295 mux &= lvds_mux->mask; 296 mux >>= lvds_mux->shift; 297 } else { 298 mux = (imx_ldb_ch == &ldb->channel[0]) ? 0 : 1; 299 } 300 301 /* set display clock mux back to original input clock */ 302 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk_parent[mux]); 303 if (ret) 304 dev_err(ldb->dev, 305 "unable to set di%d parent clock to original parent\n", 306 mux); 307 } 308 309 static int imx_ldb_encoder_atomic_check(struct drm_encoder *encoder, 310 struct drm_crtc_state *crtc_state, 311 struct drm_connector_state *conn_state) 312 { 313 struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state); 314 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); 315 struct drm_display_info *di = &conn_state->connector->display_info; 316 u32 bus_format = imx_ldb_ch->bus_format; 317 318 /* Bus format description in DT overrides connector display info. */ 319 if (!bus_format && di->num_bus_formats) { 320 bus_format = di->bus_formats[0]; 321 } else { 322 bus_format = imx_ldb_ch->bus_format; 323 } 324 325 imx_crtc_state->bus_flags = di->bus_flags; 326 327 switch (bus_format) { 328 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 329 imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB666_1X18; 330 break; 331 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 332 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 333 imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB888_1X24; 334 break; 335 default: 336 return -EINVAL; 337 } 338 339 imx_crtc_state->di_hsync_pin = 2; 340 imx_crtc_state->di_vsync_pin = 3; 341 342 return 0; 343 } 344 345 346 static const struct drm_encoder_helper_funcs imx_ldb_encoder_helper_funcs = { 347 .atomic_mode_set = imx_ldb_encoder_atomic_mode_set, 348 .enable = imx_ldb_encoder_enable, 349 .disable = imx_ldb_encoder_disable, 350 .atomic_check = imx_ldb_encoder_atomic_check, 351 }; 352 353 static int imx_ldb_get_clk(struct imx_ldb *ldb, int chno) 354 { 355 char clkname[16]; 356 357 snprintf(clkname, sizeof(clkname), "di%d", chno); 358 ldb->clk[chno] = devm_clk_get(ldb->dev, clkname); 359 if (IS_ERR(ldb->clk[chno])) 360 return PTR_ERR(ldb->clk[chno]); 361 362 snprintf(clkname, sizeof(clkname), "di%d_pll", chno); 363 ldb->clk_pll[chno] = devm_clk_get(ldb->dev, clkname); 364 365 return PTR_ERR_OR_ZERO(ldb->clk_pll[chno]); 366 } 367 368 static int imx_ldb_register(struct drm_device *drm, 369 struct imx_ldb_channel *imx_ldb_ch) 370 { 371 struct imx_ldb *ldb = imx_ldb_ch->ldb; 372 struct imx_ldb_encoder *ldb_encoder; 373 struct drm_connector *connector; 374 struct drm_encoder *encoder; 375 int ret; 376 377 ldb_encoder = drmm_simple_encoder_alloc(drm, struct imx_ldb_encoder, 378 encoder, DRM_MODE_ENCODER_LVDS); 379 if (IS_ERR(ldb_encoder)) 380 return PTR_ERR(ldb_encoder); 381 382 ldb_encoder->channel = imx_ldb_ch; 383 encoder = &ldb_encoder->encoder; 384 385 ret = imx_drm_encoder_parse_of(drm, encoder, imx_ldb_ch->child); 386 if (ret) 387 return ret; 388 389 ret = imx_ldb_get_clk(ldb, imx_ldb_ch->chno); 390 if (ret) 391 return ret; 392 393 if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) { 394 ret = imx_ldb_get_clk(ldb, 1); 395 if (ret) 396 return ret; 397 } 398 399 drm_encoder_helper_add(encoder, &imx_ldb_encoder_helper_funcs); 400 401 ret = drm_bridge_attach(encoder, imx_ldb_ch->bridge, NULL, 402 DRM_BRIDGE_ATTACH_NO_CONNECTOR); 403 if (ret) 404 return ret; 405 406 connector = drm_bridge_connector_init(drm, encoder); 407 if (IS_ERR(connector)) 408 return PTR_ERR(connector); 409 410 return 0; 411 } 412 413 struct imx_ldb_bit_mapping { 414 u32 bus_format; 415 u32 datawidth; 416 const char * const mapping; 417 }; 418 419 static const struct imx_ldb_bit_mapping imx_ldb_bit_mappings[] = { 420 { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, "spwg" }, 421 { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, "spwg" }, 422 { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, "jeida" }, 423 }; 424 425 static u32 of_get_bus_format(struct device *dev, struct device_node *np) 426 { 427 const char *bm; 428 u32 datawidth = 0; 429 int ret, i; 430 431 ret = of_property_read_string(np, "fsl,data-mapping", &bm); 432 if (ret < 0) 433 return ret; 434 435 of_property_read_u32(np, "fsl,data-width", &datawidth); 436 437 for (i = 0; i < ARRAY_SIZE(imx_ldb_bit_mappings); i++) { 438 if (!strcasecmp(bm, imx_ldb_bit_mappings[i].mapping) && 439 datawidth == imx_ldb_bit_mappings[i].datawidth) 440 return imx_ldb_bit_mappings[i].bus_format; 441 } 442 443 dev_err(dev, "invalid data mapping: %d-bit \"%s\"\n", datawidth, bm); 444 445 return -ENOENT; 446 } 447 448 static struct bus_mux imx6q_lvds_mux[2] = { 449 { 450 .reg = IOMUXC_GPR3, 451 .shift = 6, 452 .mask = IMX6Q_GPR3_LVDS0_MUX_CTL_MASK, 453 }, { 454 .reg = IOMUXC_GPR3, 455 .shift = 8, 456 .mask = IMX6Q_GPR3_LVDS1_MUX_CTL_MASK, 457 } 458 }; 459 460 /* 461 * For a device declaring compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb", 462 * of_match_device will walk through this list and take the first entry 463 * matching any of its compatible values. Therefore, the more generic 464 * entries (in this case fsl,imx53-ldb) need to be ordered last. 465 */ 466 static const struct of_device_id imx_ldb_dt_ids[] = { 467 { .compatible = "fsl,imx6q-ldb", .data = imx6q_lvds_mux, }, 468 { .compatible = "fsl,imx53-ldb", .data = NULL, }, 469 { } 470 }; 471 MODULE_DEVICE_TABLE(of, imx_ldb_dt_ids); 472 473 static int imx_ldb_bind(struct device *dev, struct device *master, void *data) 474 { 475 struct drm_device *drm = data; 476 struct imx_ldb *imx_ldb = dev_get_drvdata(dev); 477 int ret; 478 int i; 479 480 for (i = 0; i < 2; i++) { 481 struct imx_ldb_channel *channel = &imx_ldb->channel[i]; 482 483 if (!channel->ldb) 484 continue; 485 486 ret = imx_ldb_register(drm, channel); 487 if (ret) 488 return ret; 489 } 490 491 return 0; 492 } 493 494 static const struct component_ops imx_ldb_ops = { 495 .bind = imx_ldb_bind, 496 }; 497 498 static int imx_ldb_probe(struct platform_device *pdev) 499 { 500 struct device *dev = &pdev->dev; 501 struct device_node *np = dev->of_node; 502 struct device_node *child; 503 struct imx_ldb *imx_ldb; 504 int dual; 505 int ret; 506 int i; 507 508 imx_ldb = devm_kzalloc(dev, sizeof(*imx_ldb), GFP_KERNEL); 509 if (!imx_ldb) 510 return -ENOMEM; 511 512 imx_ldb->regmap = syscon_regmap_lookup_by_phandle(np, "gpr"); 513 if (IS_ERR(imx_ldb->regmap)) { 514 dev_err(dev, "failed to get parent regmap\n"); 515 return PTR_ERR(imx_ldb->regmap); 516 } 517 518 /* disable LDB by resetting the control register to POR default */ 519 regmap_write(imx_ldb->regmap, IOMUXC_GPR2, 0); 520 521 imx_ldb->dev = dev; 522 imx_ldb->lvds_mux = device_get_match_data(dev); 523 524 dual = of_property_read_bool(np, "fsl,dual-channel"); 525 if (dual) 526 imx_ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN; 527 528 /* 529 * There are three different possible clock mux configurations: 530 * i.MX53: ipu1_di0_sel, ipu1_di1_sel 531 * i.MX6q: ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, ipu2_di1_sel 532 * i.MX6dl: ipu1_di0_sel, ipu1_di1_sel, lcdif_sel 533 * Map them all to di0_sel...di3_sel. 534 */ 535 for (i = 0; i < 4; i++) { 536 char clkname[16]; 537 538 snprintf(clkname, sizeof(clkname), "di%d_sel", i); 539 imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname); 540 if (IS_ERR(imx_ldb->clk_sel[i])) { 541 ret = PTR_ERR(imx_ldb->clk_sel[i]); 542 imx_ldb->clk_sel[i] = NULL; 543 break; 544 } 545 546 imx_ldb->clk_parent[i] = clk_get_parent(imx_ldb->clk_sel[i]); 547 } 548 if (i == 0) 549 return ret; 550 551 for_each_child_of_node(np, child) { 552 struct imx_ldb_channel *channel; 553 int bus_format; 554 555 ret = of_property_read_u32(child, "reg", &i); 556 if (ret || i < 0 || i > 1) { 557 ret = -EINVAL; 558 goto free_child; 559 } 560 561 if (!of_device_is_available(child)) 562 continue; 563 564 if (dual && i > 0) { 565 dev_warn(dev, "dual-channel mode, ignoring second output\n"); 566 continue; 567 } 568 569 channel = &imx_ldb->channel[i]; 570 channel->ldb = imx_ldb; 571 channel->chno = i; 572 573 /* 574 * The output port is port@4 with an external 4-port mux or 575 * port@2 with the internal 2-port mux. 576 */ 577 channel->bridge = devm_drm_of_get_bridge(dev, child, 578 imx_ldb->lvds_mux ? 4 : 2, 0); 579 if (IS_ERR(channel->bridge)) { 580 ret = PTR_ERR(channel->bridge); 581 if (ret != -ENODEV) 582 goto free_child; 583 channel->bridge = NULL; 584 } 585 586 bus_format = of_get_bus_format(dev, child); 587 /* 588 * If no bus format was specified in the device tree, 589 * we can still get it from the connected panel later. 590 */ 591 if (bus_format == -EINVAL && channel->bridge) 592 bus_format = 0; 593 if (bus_format < 0) { 594 dev_err(dev, "could not determine data mapping: %d\n", 595 bus_format); 596 ret = bus_format; 597 goto free_child; 598 } 599 channel->bus_format = bus_format; 600 601 /* 602 * legacy bridge doesn't handle bus_format, so create it after 603 * checking the bus_format property. 604 */ 605 if (!channel->bridge) { 606 channel->bridge = devm_drm_of_display_mode_bridge(dev, child, 607 DRM_MODE_CONNECTOR_LVDS); 608 if (IS_ERR(channel->bridge)) { 609 ret = PTR_ERR(channel->bridge); 610 goto free_child; 611 } 612 } 613 614 channel->child = child; 615 } 616 617 platform_set_drvdata(pdev, imx_ldb); 618 619 return component_add(&pdev->dev, &imx_ldb_ops); 620 621 free_child: 622 of_node_put(child); 623 return ret; 624 } 625 626 static void imx_ldb_remove(struct platform_device *pdev) 627 { 628 component_del(&pdev->dev, &imx_ldb_ops); 629 } 630 631 static struct platform_driver imx_ldb_driver = { 632 .probe = imx_ldb_probe, 633 .remove = imx_ldb_remove, 634 .driver = { 635 .of_match_table = imx_ldb_dt_ids, 636 .name = DRIVER_NAME, 637 }, 638 }; 639 640 module_platform_driver(imx_ldb_driver); 641 642 MODULE_DESCRIPTION("i.MX LVDS driver"); 643 MODULE_AUTHOR("Sascha Hauer, Pengutronix"); 644 MODULE_LICENSE("GPL"); 645