1*711a3b87SLiu Ying /* SPDX-License-Identifier: GPL-2.0+ */ 2*711a3b87SLiu Ying /* 3*711a3b87SLiu Ying * Copyright 2024 NXP 4*711a3b87SLiu Ying */ 5*711a3b87SLiu Ying 6*711a3b87SLiu Ying #ifndef __DC_KMS_H__ 7*711a3b87SLiu Ying #define __DC_KMS_H__ 8*711a3b87SLiu Ying 9*711a3b87SLiu Ying #include <linux/completion.h> 10*711a3b87SLiu Ying 11*711a3b87SLiu Ying #include <drm/drm_crtc.h> 12*711a3b87SLiu Ying #include <drm/drm_plane.h> 13*711a3b87SLiu Ying #include <drm/drm_vblank.h> 14*711a3b87SLiu Ying 15*711a3b87SLiu Ying #include "dc-de.h" 16*711a3b87SLiu Ying #include "dc-fu.h" 17*711a3b87SLiu Ying #include "dc-pe.h" 18*711a3b87SLiu Ying 19*711a3b87SLiu Ying #define DC_CRTC_IRQS 5 20*711a3b87SLiu Ying 21*711a3b87SLiu Ying struct dc_crtc_irq { 22*711a3b87SLiu Ying struct dc_crtc *dc_crtc; 23*711a3b87SLiu Ying unsigned int irq; 24*711a3b87SLiu Ying }; 25*711a3b87SLiu Ying 26*711a3b87SLiu Ying /** 27*711a3b87SLiu Ying * struct dc_crtc - DC specific drm_crtc 28*711a3b87SLiu Ying * 29*711a3b87SLiu Ying * Each display controller contains one content stream and one safety stream. 30*711a3b87SLiu Ying * In general, the two streams have the same functionality. One stream is 31*711a3b87SLiu Ying * overlaid on the other by @fg. This driver chooses to generate black constant 32*711a3b87SLiu Ying * color from the content stream as background color, build plane(s) on the 33*711a3b87SLiu Ying * content stream by using layerblend(s) and always generate a constant color 34*711a3b87SLiu Ying * from the safety stream. Note that due to the decoupled timing, the safety 35*711a3b87SLiu Ying * stream still works to show the constant color properly even when the content 36*711a3b87SLiu Ying * stream has completely hung up due to mal-function of this driver. 37*711a3b87SLiu Ying */ 38*711a3b87SLiu Ying struct dc_crtc { 39*711a3b87SLiu Ying /** @base: base drm_crtc structure */ 40*711a3b87SLiu Ying struct drm_crtc base; 41*711a3b87SLiu Ying /** @de: display engine */ 42*711a3b87SLiu Ying struct dc_de *de; 43*711a3b87SLiu Ying /** @cf_cont: content stream constframe */ 44*711a3b87SLiu Ying struct dc_cf *cf_cont; 45*711a3b87SLiu Ying /** @cf_safe: safety stream constframe */ 46*711a3b87SLiu Ying struct dc_cf *cf_safe; 47*711a3b87SLiu Ying /** @ed_cont: content stream extdst */ 48*711a3b87SLiu Ying struct dc_ed *ed_cont; 49*711a3b87SLiu Ying /** @ed_safe: safety stream extdst */ 50*711a3b87SLiu Ying struct dc_ed *ed_safe; 51*711a3b87SLiu Ying /** @fg: framegen */ 52*711a3b87SLiu Ying struct dc_fg *fg; 53*711a3b87SLiu Ying /** 54*711a3b87SLiu Ying * @irq_dec_framecomplete: 55*711a3b87SLiu Ying * 56*711a3b87SLiu Ying * display engine configuration frame complete interrupt 57*711a3b87SLiu Ying */ 58*711a3b87SLiu Ying unsigned int irq_dec_framecomplete; 59*711a3b87SLiu Ying /** 60*711a3b87SLiu Ying * @irq_dec_seqcomplete: 61*711a3b87SLiu Ying * 62*711a3b87SLiu Ying * display engine configuration sequence complete interrupt 63*711a3b87SLiu Ying */ 64*711a3b87SLiu Ying unsigned int irq_dec_seqcomplete; 65*711a3b87SLiu Ying /** 66*711a3b87SLiu Ying * @irq_dec_shdload: 67*711a3b87SLiu Ying * 68*711a3b87SLiu Ying * display engine configuration shadow load interrupt 69*711a3b87SLiu Ying */ 70*711a3b87SLiu Ying unsigned int irq_dec_shdload; 71*711a3b87SLiu Ying /** 72*711a3b87SLiu Ying * @irq_ed_cont_shdload: 73*711a3b87SLiu Ying * 74*711a3b87SLiu Ying * content stream extdst shadow load interrupt 75*711a3b87SLiu Ying */ 76*711a3b87SLiu Ying unsigned int irq_ed_cont_shdload; 77*711a3b87SLiu Ying /** 78*711a3b87SLiu Ying * @irq_ed_safe_shdload: 79*711a3b87SLiu Ying * 80*711a3b87SLiu Ying * safety stream extdst shadow load interrupt 81*711a3b87SLiu Ying */ 82*711a3b87SLiu Ying unsigned int irq_ed_safe_shdload; 83*711a3b87SLiu Ying /** 84*711a3b87SLiu Ying * @dec_seqcomplete_done: 85*711a3b87SLiu Ying * 86*711a3b87SLiu Ying * display engine configuration sequence completion 87*711a3b87SLiu Ying */ 88*711a3b87SLiu Ying struct completion dec_seqcomplete_done; 89*711a3b87SLiu Ying /** 90*711a3b87SLiu Ying * @dec_shdload_done: 91*711a3b87SLiu Ying * 92*711a3b87SLiu Ying * display engine configuration shadow load completion 93*711a3b87SLiu Ying */ 94*711a3b87SLiu Ying struct completion dec_shdload_done; 95*711a3b87SLiu Ying /** 96*711a3b87SLiu Ying * @ed_cont_shdload_done: 97*711a3b87SLiu Ying * 98*711a3b87SLiu Ying * content stream extdst shadow load completion 99*711a3b87SLiu Ying */ 100*711a3b87SLiu Ying struct completion ed_cont_shdload_done; 101*711a3b87SLiu Ying /** 102*711a3b87SLiu Ying * @ed_safe_shdload_done: 103*711a3b87SLiu Ying * 104*711a3b87SLiu Ying * safety stream extdst shadow load completion 105*711a3b87SLiu Ying */ 106*711a3b87SLiu Ying struct completion ed_safe_shdload_done; 107*711a3b87SLiu Ying /** @event: cached pending vblank event */ 108*711a3b87SLiu Ying struct drm_pending_vblank_event *event; 109*711a3b87SLiu Ying /** @irqs: interrupt list */ 110*711a3b87SLiu Ying struct dc_crtc_irq irqs[DC_CRTC_IRQS]; 111*711a3b87SLiu Ying }; 112*711a3b87SLiu Ying 113*711a3b87SLiu Ying /** 114*711a3b87SLiu Ying * struct dc_plane - DC specific drm_plane 115*711a3b87SLiu Ying * 116*711a3b87SLiu Ying * Build a plane on content stream with a fetchunit and a layerblend. 117*711a3b87SLiu Ying */ 118*711a3b87SLiu Ying struct dc_plane { 119*711a3b87SLiu Ying /** @base: base drm_plane structure */ 120*711a3b87SLiu Ying struct drm_plane base; 121*711a3b87SLiu Ying /** @fu: fetchunit */ 122*711a3b87SLiu Ying struct dc_fu *fu; 123*711a3b87SLiu Ying /** @cf: content stream constframe */ 124*711a3b87SLiu Ying struct dc_cf *cf; 125*711a3b87SLiu Ying /** @lb: layerblend */ 126*711a3b87SLiu Ying struct dc_lb *lb; 127*711a3b87SLiu Ying /** @ed: content stream extdst */ 128*711a3b87SLiu Ying struct dc_ed *ed; 129*711a3b87SLiu Ying }; 130*711a3b87SLiu Ying 131*711a3b87SLiu Ying #endif /* __DC_KMS_H__ */ 132