1*9f09e317SLiu Ying /* SPDX-License-Identifier: GPL-2.0+ */ 2*9f09e317SLiu Ying /* 3*9f09e317SLiu Ying * Copyright 2024 NXP 4*9f09e317SLiu Ying */ 5*9f09e317SLiu Ying 6*9f09e317SLiu Ying #ifndef __DC_DISPLAY_ENGINE_H__ 7*9f09e317SLiu Ying #define __DC_DISPLAY_ENGINE_H__ 8*9f09e317SLiu Ying 9*9f09e317SLiu Ying #include <linux/clk.h> 10*9f09e317SLiu Ying #include <linux/device.h> 11*9f09e317SLiu Ying #include <linux/regmap.h> 12*9f09e317SLiu Ying #include <drm/drm_modes.h> 13*9f09e317SLiu Ying 14*9f09e317SLiu Ying #define DC_DISPLAYS 2 15*9f09e317SLiu Ying 16*9f09e317SLiu Ying struct dc_fg { 17*9f09e317SLiu Ying struct device *dev; 18*9f09e317SLiu Ying struct regmap *reg; 19*9f09e317SLiu Ying struct clk *clk_disp; 20*9f09e317SLiu Ying }; 21*9f09e317SLiu Ying 22*9f09e317SLiu Ying struct dc_tc { 23*9f09e317SLiu Ying struct device *dev; 24*9f09e317SLiu Ying struct regmap *reg; 25*9f09e317SLiu Ying }; 26*9f09e317SLiu Ying 27*9f09e317SLiu Ying struct dc_de { 28*9f09e317SLiu Ying struct device *dev; 29*9f09e317SLiu Ying struct regmap *reg_top; 30*9f09e317SLiu Ying struct dc_fg *fg; 31*9f09e317SLiu Ying struct dc_tc *tc; 32*9f09e317SLiu Ying int irq_shdload; 33*9f09e317SLiu Ying int irq_framecomplete; 34*9f09e317SLiu Ying int irq_seqcomplete; 35*9f09e317SLiu Ying }; 36*9f09e317SLiu Ying 37*9f09e317SLiu Ying /* Frame Generator Unit */ 38*9f09e317SLiu Ying void dc_fg_cfg_videomode(struct dc_fg *fg, struct drm_display_mode *m); 39*9f09e317SLiu Ying void dc_fg_enable(struct dc_fg *fg); 40*9f09e317SLiu Ying void dc_fg_disable(struct dc_fg *fg); 41*9f09e317SLiu Ying void dc_fg_shdtokgen(struct dc_fg *fg); 42*9f09e317SLiu Ying u32 dc_fg_get_frame_index(struct dc_fg *fg); 43*9f09e317SLiu Ying u32 dc_fg_get_line_index(struct dc_fg *fg); 44*9f09e317SLiu Ying bool dc_fg_wait_for_frame_index_moving(struct dc_fg *fg); 45*9f09e317SLiu Ying bool dc_fg_secondary_requests_to_read_empty_fifo(struct dc_fg *fg); 46*9f09e317SLiu Ying void dc_fg_secondary_clear_channel_status(struct dc_fg *fg); 47*9f09e317SLiu Ying int dc_fg_wait_for_secondary_syncup(struct dc_fg *fg); 48*9f09e317SLiu Ying void dc_fg_enable_clock(struct dc_fg *fg); 49*9f09e317SLiu Ying void dc_fg_disable_clock(struct dc_fg *fg); 50*9f09e317SLiu Ying enum drm_mode_status dc_fg_check_clock(struct dc_fg *fg, int clk_khz); 51*9f09e317SLiu Ying void dc_fg_init(struct dc_fg *fg); 52*9f09e317SLiu Ying 53*9f09e317SLiu Ying /* Timing Controller Unit */ 54*9f09e317SLiu Ying void dc_tc_init(struct dc_tc *tc); 55*9f09e317SLiu Ying 56*9f09e317SLiu Ying #endif /* __DC_DISPLAY_ENGINE_H__ */ 57