19f09e317SLiu Ying /* SPDX-License-Identifier: GPL-2.0+ */ 29f09e317SLiu Ying /* 39f09e317SLiu Ying * Copyright 2024 NXP 49f09e317SLiu Ying */ 59f09e317SLiu Ying 69f09e317SLiu Ying #ifndef __DC_DISPLAY_ENGINE_H__ 79f09e317SLiu Ying #define __DC_DISPLAY_ENGINE_H__ 89f09e317SLiu Ying 99f09e317SLiu Ying #include <linux/clk.h> 109f09e317SLiu Ying #include <linux/device.h> 119f09e317SLiu Ying #include <linux/regmap.h> 129f09e317SLiu Ying #include <drm/drm_modes.h> 139f09e317SLiu Ying 149f09e317SLiu Ying #define DC_DISPLAYS 2 159f09e317SLiu Ying 16*711a3b87SLiu Ying #define DC_FRAMEGEN_MAX_FRAME_INDEX 0x3ffff 17*711a3b87SLiu Ying #define DC_FRAMEGEN_MAX_CLOCK_KHZ 300000 18*711a3b87SLiu Ying 199f09e317SLiu Ying struct dc_fg { 209f09e317SLiu Ying struct device *dev; 219f09e317SLiu Ying struct regmap *reg; 229f09e317SLiu Ying struct clk *clk_disp; 239f09e317SLiu Ying }; 249f09e317SLiu Ying 259f09e317SLiu Ying struct dc_tc { 269f09e317SLiu Ying struct device *dev; 279f09e317SLiu Ying struct regmap *reg; 289f09e317SLiu Ying }; 299f09e317SLiu Ying 309f09e317SLiu Ying struct dc_de { 319f09e317SLiu Ying struct device *dev; 329f09e317SLiu Ying struct regmap *reg_top; 339f09e317SLiu Ying struct dc_fg *fg; 349f09e317SLiu Ying struct dc_tc *tc; 359f09e317SLiu Ying int irq_shdload; 369f09e317SLiu Ying int irq_framecomplete; 379f09e317SLiu Ying int irq_seqcomplete; 389f09e317SLiu Ying }; 399f09e317SLiu Ying 409f09e317SLiu Ying /* Frame Generator Unit */ 419f09e317SLiu Ying void dc_fg_cfg_videomode(struct dc_fg *fg, struct drm_display_mode *m); 429f09e317SLiu Ying void dc_fg_enable(struct dc_fg *fg); 439f09e317SLiu Ying void dc_fg_disable(struct dc_fg *fg); 449f09e317SLiu Ying void dc_fg_shdtokgen(struct dc_fg *fg); 459f09e317SLiu Ying u32 dc_fg_get_frame_index(struct dc_fg *fg); 469f09e317SLiu Ying u32 dc_fg_get_line_index(struct dc_fg *fg); 479f09e317SLiu Ying bool dc_fg_wait_for_frame_index_moving(struct dc_fg *fg); 489f09e317SLiu Ying bool dc_fg_secondary_requests_to_read_empty_fifo(struct dc_fg *fg); 499f09e317SLiu Ying void dc_fg_secondary_clear_channel_status(struct dc_fg *fg); 509f09e317SLiu Ying int dc_fg_wait_for_secondary_syncup(struct dc_fg *fg); 519f09e317SLiu Ying void dc_fg_enable_clock(struct dc_fg *fg); 529f09e317SLiu Ying void dc_fg_disable_clock(struct dc_fg *fg); 539f09e317SLiu Ying enum drm_mode_status dc_fg_check_clock(struct dc_fg *fg, int clk_khz); 549f09e317SLiu Ying void dc_fg_init(struct dc_fg *fg); 559f09e317SLiu Ying 569f09e317SLiu Ying /* Timing Controller Unit */ 579f09e317SLiu Ying void dc_tc_init(struct dc_tc *tc); 589f09e317SLiu Ying 599f09e317SLiu Ying #endif /* __DC_DISPLAY_ENGINE_H__ */ 60