1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ 2 /* Copyright (c) 2023 Imagination Technologies Ltd. */ 3 4 #ifndef PVR_ROGUE_FWIF_SHARED_H 5 #define PVR_ROGUE_FWIF_SHARED_H 6 7 #include <linux/compiler.h> 8 #include <linux/types.h> 9 10 #define ROGUE_FWIF_NUM_RTDATAS 2U 11 #define ROGUE_FWIF_NUM_GEOMDATAS 1U 12 #define ROGUE_FWIF_NUM_RTDATA_FREELISTS 2U 13 #define ROGUE_NUM_GEOM_CORES 1U 14 15 #define ROGUE_NUM_GEOM_CORES_SIZE 2U 16 17 /* Maximum number of UFOs in a CCB command. */ 18 #define ROGUE_FWIF_CCB_CMD_MAX_UFOS (32U + 32U) 19 20 /* 21 * This is a generic limit imposed on any DM (GEOMETRY,FRAGMENT,CDM,TDM,2D,TRANSFER) 22 * command passed through the bridge. 23 * Just across the bridge in the server, any incoming kick command size is 24 * checked against this maximum limit. 25 * In case the incoming command size is larger than the specified limit, 26 * the bridge call is retired with error. 27 */ 28 #define ROGUE_FWIF_DM_INDEPENDENT_KICK_CMD_SIZE (1024U) 29 30 #define ROGUE_FWIF_PRBUFFER_START (0) 31 #define ROGUE_FWIF_PRBUFFER_ZSBUFFER (0) 32 #define ROGUE_FWIF_PRBUFFER_MSAABUFFER (1) 33 #define ROGUE_FWIF_PRBUFFER_MAXSUPPORTED (2) 34 35 struct rogue_fwif_dma_addr { 36 aligned_u64 dev_addr; 37 u32 fw_addr; 38 u32 padding; 39 } __aligned(8); 40 41 struct rogue_fwif_ufo { 42 u32 addr; 43 u32 value; 44 }; 45 46 #define ROGUE_FWIF_UFO_ADDR_IS_SYNC_CHECKPOINT (1) 47 48 struct rogue_fwif_sync_checkpoint { 49 u32 state; 50 u32 fw_ref_count; 51 }; 52 53 struct rogue_fwif_cleanup_ctl { 54 /* Number of commands received by the FW */ 55 u32 submitted_commands; 56 /* Number of commands executed by the FW */ 57 u32 executed_commands; 58 } __aligned(8); 59 60 /* 61 * Used to share frame numbers across UM-KM-FW, 62 * frame number is set in UM, 63 * frame number is required in both KM for HTB and FW for FW trace. 64 * 65 * May be used to house Kick flags in the future. 66 */ 67 struct rogue_fwif_cmd_common { 68 /* associated frame number */ 69 u32 frame_num; 70 }; 71 72 /* 73 * Geometry and fragment commands require set of firmware addresses that are stored in the Kernel. 74 * Client has handle(s) to Kernel containers storing these addresses, instead of raw addresses. We 75 * have to patch/write these addresses in KM to prevent UM from controlling FW addresses directly. 76 * Typedefs for geometry and fragment commands are shared between Client and Firmware (both 77 * single-BVNC). Kernel is implemented in a multi-BVNC manner, so it can't use geometry|fragment 78 * CMD type definitions directly. Therefore we have a SHARED block that is shared between UM-KM-FW 79 * across all BVNC configurations. 80 */ 81 struct rogue_fwif_cmd_geom_frag_shared { 82 /* Common command attributes */ 83 struct rogue_fwif_cmd_common cmn; 84 85 /* 86 * RTData associated with this command, this is used for context 87 * selection and for storing out HW-context, when TA is switched out for 88 * continuing later 89 */ 90 u32 hwrt_data_fw_addr; 91 92 /* Supported PR Buffers like Z/S/MSAA Scratch */ 93 u32 pr_buffer_fw_addr[ROGUE_FWIF_PRBUFFER_MAXSUPPORTED]; 94 }; 95 96 /* 97 * Client Circular Command Buffer (CCCB) control structure. 98 * This is shared between the Server and the Firmware and holds byte offsets 99 * into the CCCB as well as the wrapping mask to aid wrap around. A given 100 * snapshot of this queue with Cmd 1 running on the GPU might be: 101 * 102 * Roff Doff Woff 103 * [..........|-1----------|=2===|=3===|=4===|~5~~~~|~6~~~~|~7~~~~|..........] 104 * < runnable commands >< !ready to run > 105 * 106 * Cmd 1 : Currently executing on the GPU data master. 107 * Cmd 2,3,4: Fence dependencies met, commands runnable. 108 * Cmd 5... : Fence dependency not met yet. 109 */ 110 struct rogue_fwif_cccb_ctl { 111 /* Host write offset into CCB. This must be aligned to 16 bytes. */ 112 u32 write_offset; 113 /* 114 * Firmware read offset into CCB. Points to the command that is runnable 115 * on GPU, if R!=W 116 */ 117 u32 read_offset; 118 /* 119 * Firmware fence dependency offset. Points to commands not ready, i.e. 120 * fence dependencies are not met. 121 */ 122 u32 dep_offset; 123 /* Offset wrapping mask, total capacity in bytes of the CCB-1 */ 124 u32 wrap_mask; 125 126 /* Only used if SUPPORT_AGP is present. */ 127 u32 read_offset2; 128 129 /* Only used if SUPPORT_AGP4 is present. */ 130 u32 read_offset3; 131 /* Only used if SUPPORT_AGP4 is present. */ 132 u32 read_offset4; 133 134 u32 padding; 135 } __aligned(8); 136 137 #define ROGUE_FW_LOCAL_FREELIST (0) 138 #define ROGUE_FW_GLOBAL_FREELIST (1) 139 #define ROGUE_FW_FREELIST_TYPE_LAST ROGUE_FW_GLOBAL_FREELIST 140 #define ROGUE_FW_MAX_FREELISTS (ROGUE_FW_FREELIST_TYPE_LAST + 1U) 141 142 struct rogue_fwif_geom_registers_caswitch { 143 u64 geom_reg_vdm_context_state_base_addr; 144 u64 geom_reg_vdm_context_state_resume_addr; 145 u64 geom_reg_ta_context_state_base_addr; 146 147 struct { 148 u64 geom_reg_vdm_context_store_task0; 149 u64 geom_reg_vdm_context_store_task1; 150 u64 geom_reg_vdm_context_store_task2; 151 152 /* VDM resume state update controls */ 153 u64 geom_reg_vdm_context_resume_task0; 154 u64 geom_reg_vdm_context_resume_task1; 155 u64 geom_reg_vdm_context_resume_task2; 156 157 u64 geom_reg_vdm_context_store_task3; 158 u64 geom_reg_vdm_context_store_task4; 159 160 u64 geom_reg_vdm_context_resume_task3; 161 u64 geom_reg_vdm_context_resume_task4; 162 } geom_state[2]; 163 }; 164 165 #define ROGUE_FWIF_GEOM_REGISTERS_CSWITCH_SIZE \ 166 sizeof(struct rogue_fwif_geom_registers_caswitch) 167 168 struct rogue_fwif_cdm_registers_cswitch { 169 u64 cdmreg_cdm_context_pds0; 170 u64 cdmreg_cdm_context_pds1; 171 u64 cdmreg_cdm_terminate_pds; 172 u64 cdmreg_cdm_terminate_pds1; 173 174 /* CDM resume controls */ 175 u64 cdmreg_cdm_resume_pds0; 176 u64 cdmreg_cdm_context_pds0_b; 177 u64 cdmreg_cdm_resume_pds0_b; 178 }; 179 180 struct rogue_fwif_static_rendercontext_state { 181 /* Geom registers for ctx switch */ 182 struct rogue_fwif_geom_registers_caswitch ctxswitch_regs[ROGUE_NUM_GEOM_CORES_SIZE] 183 __aligned(8); 184 }; 185 186 #define ROGUE_FWIF_STATIC_RENDERCONTEXT_SIZE \ 187 sizeof(struct rogue_fwif_static_rendercontext_state) 188 189 struct rogue_fwif_static_computecontext_state { 190 /* CDM registers for ctx switch */ 191 struct rogue_fwif_cdm_registers_cswitch ctxswitch_regs __aligned(8); 192 }; 193 194 #define ROGUE_FWIF_STATIC_COMPUTECONTEXT_SIZE \ 195 sizeof(struct rogue_fwif_static_computecontext_state) 196 197 enum rogue_fwif_prbuffer_state { 198 ROGUE_FWIF_PRBUFFER_UNBACKED = 0, 199 ROGUE_FWIF_PRBUFFER_BACKED, 200 ROGUE_FWIF_PRBUFFER_BACKING_PENDING, 201 ROGUE_FWIF_PRBUFFER_UNBACKING_PENDING, 202 }; 203 204 struct rogue_fwif_prbuffer { 205 /* Buffer ID*/ 206 u32 buffer_id; 207 /* Needs On-demand Z/S/MSAA Buffer allocation */ 208 bool on_demand __aligned(4); 209 /* Z/S/MSAA -Buffer state */ 210 enum rogue_fwif_prbuffer_state state; 211 /* Cleanup state */ 212 struct rogue_fwif_cleanup_ctl cleanup_sate; 213 /* Compatibility and other flags */ 214 u32 prbuffer_flags; 215 } __aligned(8); 216 217 /* Last reset reason for a context. */ 218 enum rogue_context_reset_reason { 219 /* No reset reason recorded */ 220 ROGUE_CONTEXT_RESET_REASON_NONE = 0, 221 /* Caused a reset due to locking up */ 222 ROGUE_CONTEXT_RESET_REASON_GUILTY_LOCKUP = 1, 223 /* Affected by another context locking up */ 224 ROGUE_CONTEXT_RESET_REASON_INNOCENT_LOCKUP = 2, 225 /* Overran the global deadline */ 226 ROGUE_CONTEXT_RESET_REASON_GUILTY_OVERRUNING = 3, 227 /* Affected by another context overrunning */ 228 ROGUE_CONTEXT_RESET_REASON_INNOCENT_OVERRUNING = 4, 229 /* Forced reset to ensure scheduling requirements */ 230 ROGUE_CONTEXT_RESET_REASON_HARD_CONTEXT_SWITCH = 5, 231 /* CDM Mission/safety checksum mismatch */ 232 ROGUE_CONTEXT_RESET_REASON_WGP_CHECKSUM = 6, 233 /* TRP checksum mismatch */ 234 ROGUE_CONTEXT_RESET_REASON_TRP_CHECKSUM = 7, 235 /* GPU ECC error (corrected, OK) */ 236 ROGUE_CONTEXT_RESET_REASON_GPU_ECC_OK = 8, 237 /* GPU ECC error (uncorrected, HWR) */ 238 ROGUE_CONTEXT_RESET_REASON_GPU_ECC_HWR = 9, 239 /* FW ECC error (corrected, OK) */ 240 ROGUE_CONTEXT_RESET_REASON_FW_ECC_OK = 10, 241 /* FW ECC error (uncorrected, ERR) */ 242 ROGUE_CONTEXT_RESET_REASON_FW_ECC_ERR = 11, 243 /* FW Safety watchdog triggered */ 244 ROGUE_CONTEXT_RESET_REASON_FW_WATCHDOG = 12, 245 /* FW page fault (no HWR) */ 246 ROGUE_CONTEXT_RESET_REASON_FW_PAGEFAULT = 13, 247 /* FW execution error (GPU reset requested) */ 248 ROGUE_CONTEXT_RESET_REASON_FW_EXEC_ERR = 14, 249 /* Host watchdog detected FW error */ 250 ROGUE_CONTEXT_RESET_REASON_HOST_WDG_FW_ERR = 15, 251 /* Geometry DM OOM event is not allowed */ 252 ROGUE_CONTEXT_GEOM_OOM_DISABLED = 16, 253 }; 254 255 struct rogue_context_reset_reason_data { 256 /* 257 * The valid values for reset_reason are the ones from 258 * enum rogue_context_reset_reason 259 */ 260 u32 reset_reason; 261 u32 reset_ext_job_ref; 262 }; 263 264 #include "pvr_rogue_fwif_shared_check.h" 265 266 #endif /* PVR_ROGUE_FWIF_SHARED_H */ 267