1*a26f067fSSarah Walker /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ 2*a26f067fSSarah Walker /* Copyright (c) 2023 Imagination Technologies Ltd. */ 3*a26f067fSSarah Walker 4*a26f067fSSarah Walker #ifndef PVR_ROGUE_FWIF_COMMON_H 5*a26f067fSSarah Walker #define PVR_ROGUE_FWIF_COMMON_H 6*a26f067fSSarah Walker 7*a26f067fSSarah Walker #include <linux/build_bug.h> 8*a26f067fSSarah Walker 9*a26f067fSSarah Walker /* 10*a26f067fSSarah Walker * This macro represents a mask of LSBs that must be zero on data structure 11*a26f067fSSarah Walker * sizes and offsets to ensure they are 8-byte granular on types shared between 12*a26f067fSSarah Walker * the FW and host driver. 13*a26f067fSSarah Walker */ 14*a26f067fSSarah Walker #define PVR_FW_ALIGNMENT_LSB 7U 15*a26f067fSSarah Walker 16*a26f067fSSarah Walker /* Macro to test structure size alignment. */ 17*a26f067fSSarah Walker #define PVR_FW_STRUCT_SIZE_ASSERT(_a) \ 18*a26f067fSSarah Walker static_assert((sizeof(_a) & PVR_FW_ALIGNMENT_LSB) == 0U, \ 19*a26f067fSSarah Walker "Size of " #_a " is not properly aligned") 20*a26f067fSSarah Walker 21*a26f067fSSarah Walker /* The master definition for data masters known to the firmware. */ 22*a26f067fSSarah Walker 23*a26f067fSSarah Walker #define PVR_FWIF_DM_GP (0) 24*a26f067fSSarah Walker /* Either TDM or 2D DM is present. */ 25*a26f067fSSarah Walker /* When the 'tla' feature is present in the hw (as per @pvr_device_features). */ 26*a26f067fSSarah Walker #define PVR_FWIF_DM_2D (1) 27*a26f067fSSarah Walker /* 28*a26f067fSSarah Walker * When the 'fastrender_dm' feature is present in the hw (as per 29*a26f067fSSarah Walker * @pvr_device_features). 30*a26f067fSSarah Walker */ 31*a26f067fSSarah Walker #define PVR_FWIF_DM_TDM (1) 32*a26f067fSSarah Walker 33*a26f067fSSarah Walker #define PVR_FWIF_DM_GEOM (2) 34*a26f067fSSarah Walker #define PVR_FWIF_DM_FRAG (3) 35*a26f067fSSarah Walker #define PVR_FWIF_DM_CDM (4) 36*a26f067fSSarah Walker #define PVR_FWIF_DM_RAY (5) 37*a26f067fSSarah Walker #define PVR_FWIF_DM_GEOM2 (6) 38*a26f067fSSarah Walker #define PVR_FWIF_DM_GEOM3 (7) 39*a26f067fSSarah Walker #define PVR_FWIF_DM_GEOM4 (8) 40*a26f067fSSarah Walker 41*a26f067fSSarah Walker #define PVR_FWIF_DM_LAST PVR_FWIF_DM_GEOM4 42*a26f067fSSarah Walker 43*a26f067fSSarah Walker /* Maximum number of DM in use: GP, 2D/TDM, GEOM, 3D, CDM, RAY, GEOM2, GEOM3, GEOM4 */ 44*a26f067fSSarah Walker #define PVR_FWIF_DM_MAX (PVR_FWIF_DM_LAST + 1U) 45*a26f067fSSarah Walker 46*a26f067fSSarah Walker /* GPU Utilisation states */ 47*a26f067fSSarah Walker #define PVR_FWIF_GPU_UTIL_STATE_IDLE 0U 48*a26f067fSSarah Walker #define PVR_FWIF_GPU_UTIL_STATE_ACTIVE 1U 49*a26f067fSSarah Walker #define PVR_FWIF_GPU_UTIL_STATE_BLOCKED 2U 50*a26f067fSSarah Walker #define PVR_FWIF_GPU_UTIL_STATE_NUM 3U 51*a26f067fSSarah Walker #define PVR_FWIF_GPU_UTIL_STATE_MASK 0x3ULL 52*a26f067fSSarah Walker 53*a26f067fSSarah Walker /* 54*a26f067fSSarah Walker * Maximum amount of register writes that can be done by the register 55*a26f067fSSarah Walker * programmer (FW or META DMA). This is not a HW limitation, it is only 56*a26f067fSSarah Walker * a protection against malformed inputs to the register programmer. 57*a26f067fSSarah Walker */ 58*a26f067fSSarah Walker #define PVR_MAX_NUM_REGISTER_PROGRAMMER_WRITES 128U 59*a26f067fSSarah Walker 60*a26f067fSSarah Walker #endif /* PVR_ROGUE_FWIF_COMMON_H */ 61