1*927f3e02SSarah Walker /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ 2*927f3e02SSarah Walker /* Copyright (c) 2023 Imagination Technologies Ltd. */ 3*927f3e02SSarah Walker 4*927f3e02SSarah Walker #ifndef PVR_FW_MIPS_H 5*927f3e02SSarah Walker #define PVR_FW_MIPS_H 6*927f3e02SSarah Walker 7*927f3e02SSarah Walker #include "pvr_rogue_mips.h" 8*927f3e02SSarah Walker 9*927f3e02SSarah Walker #include <asm/page.h> 10*927f3e02SSarah Walker #include <linux/types.h> 11*927f3e02SSarah Walker 12*927f3e02SSarah Walker /* Forward declaration from pvr_gem.h. */ 13*927f3e02SSarah Walker struct pvr_gem_object; 14*927f3e02SSarah Walker 15*927f3e02SSarah Walker #define PVR_MIPS_PT_PAGE_COUNT ((ROGUE_MIPSFW_MAX_NUM_PAGETABLE_PAGES * ROGUE_MIPSFW_PAGE_SIZE_4K) \ 16*927f3e02SSarah Walker >> PAGE_SHIFT) 17*927f3e02SSarah Walker /** 18*927f3e02SSarah Walker * struct pvr_fw_mips_data - MIPS-specific data 19*927f3e02SSarah Walker */ 20*927f3e02SSarah Walker struct pvr_fw_mips_data { 21*927f3e02SSarah Walker /** 22*927f3e02SSarah Walker * @pt_pages: Pages containing MIPS pagetable. 23*927f3e02SSarah Walker */ 24*927f3e02SSarah Walker struct page *pt_pages[PVR_MIPS_PT_PAGE_COUNT]; 25*927f3e02SSarah Walker 26*927f3e02SSarah Walker /** @pt: Pointer to CPU mapping of MIPS pagetable. */ 27*927f3e02SSarah Walker u32 *pt; 28*927f3e02SSarah Walker 29*927f3e02SSarah Walker /** @pt_dma_addr: DMA mappings of MIPS pagetable. */ 30*927f3e02SSarah Walker dma_addr_t pt_dma_addr[PVR_MIPS_PT_PAGE_COUNT]; 31*927f3e02SSarah Walker 32*927f3e02SSarah Walker /** @boot_code_dma_addr: DMA address of MIPS boot code. */ 33*927f3e02SSarah Walker dma_addr_t boot_code_dma_addr; 34*927f3e02SSarah Walker 35*927f3e02SSarah Walker /** @boot_data_dma_addr: DMA address of MIPS boot data. */ 36*927f3e02SSarah Walker dma_addr_t boot_data_dma_addr; 37*927f3e02SSarah Walker 38*927f3e02SSarah Walker /** @exception_code_dma_addr: DMA address of MIPS exception code. */ 39*927f3e02SSarah Walker dma_addr_t exception_code_dma_addr; 40*927f3e02SSarah Walker 41*927f3e02SSarah Walker /** @cache_policy: Cache policy for this processor. */ 42*927f3e02SSarah Walker u32 cache_policy; 43*927f3e02SSarah Walker 44*927f3e02SSarah Walker /** @pfn_mask: PFN mask for MIPS pagetable. */ 45*927f3e02SSarah Walker u32 pfn_mask; 46*927f3e02SSarah Walker }; 47*927f3e02SSarah Walker 48*927f3e02SSarah Walker #endif /* PVR_FW_MIPS_H */ 49