1 // SPDX-License-Identifier: GPL-2.0-only OR MIT 2 /* Copyright (c) 2023 Imagination Technologies Ltd. */ 3 4 #include "pvr_device.h" 5 #include "pvr_fw.h" 6 #include "pvr_fw_mips.h" 7 #include "pvr_gem.h" 8 #include "pvr_rogue_mips.h" 9 #include "pvr_vm_mips.h" 10 11 #include <linux/err.h> 12 #include <linux/types.h> 13 14 #define ROGUE_FW_HEAP_MIPS_BASE 0xC0000000 15 #define ROGUE_FW_HEAP_MIPS_SHIFT 24 /* 16 MB */ 16 #define ROGUE_FW_HEAP_MIPS_RESERVED_SIZE SZ_1M 17 18 static int 19 pvr_mips_init(struct pvr_device *pvr_dev) 20 { 21 pvr_fw_heap_info_init(pvr_dev, ROGUE_FW_HEAP_MIPS_SHIFT, ROGUE_FW_HEAP_MIPS_RESERVED_SIZE); 22 23 return pvr_vm_mips_init(pvr_dev); 24 } 25 26 static void 27 pvr_mips_fini(struct pvr_device *pvr_dev) 28 { 29 pvr_vm_mips_fini(pvr_dev); 30 } 31 32 static int 33 pvr_mips_fw_process(struct pvr_device *pvr_dev, const u8 *fw, 34 u8 *fw_code_ptr, u8 *fw_data_ptr, u8 *fw_core_code_ptr, u8 *fw_core_data_ptr, 35 u32 core_code_alloc_size) 36 { 37 struct pvr_fw_device *fw_dev = &pvr_dev->fw_dev; 38 struct pvr_fw_mips_data *mips_data = fw_dev->processor_data.mips_data; 39 const struct pvr_fw_layout_entry *boot_code_entry; 40 const struct pvr_fw_layout_entry *boot_data_entry; 41 const struct pvr_fw_layout_entry *exception_code_entry; 42 const struct pvr_fw_layout_entry *stack_entry; 43 struct rogue_mipsfw_boot_data *boot_data; 44 dma_addr_t dma_addr; 45 int err; 46 47 err = pvr_fw_process_elf_command_stream(pvr_dev, fw, fw_code_ptr, fw_data_ptr, 48 fw_core_code_ptr, fw_core_data_ptr); 49 if (err) 50 return err; 51 52 boot_code_entry = pvr_fw_find_layout_entry(pvr_dev, MIPS_BOOT_CODE); 53 boot_data_entry = pvr_fw_find_layout_entry(pvr_dev, MIPS_BOOT_DATA); 54 exception_code_entry = pvr_fw_find_layout_entry(pvr_dev, MIPS_EXCEPTIONS_CODE); 55 if (!boot_code_entry || !boot_data_entry || !exception_code_entry) 56 return -EINVAL; 57 58 WARN_ON(pvr_gem_get_dma_addr(fw_dev->mem.code_obj->gem, boot_code_entry->alloc_offset, 59 &mips_data->boot_code_dma_addr)); 60 WARN_ON(pvr_gem_get_dma_addr(fw_dev->mem.data_obj->gem, boot_data_entry->alloc_offset, 61 &mips_data->boot_data_dma_addr)); 62 WARN_ON(pvr_gem_get_dma_addr(fw_dev->mem.code_obj->gem, 63 exception_code_entry->alloc_offset, 64 &mips_data->exception_code_dma_addr)); 65 66 stack_entry = pvr_fw_find_layout_entry(pvr_dev, MIPS_STACK); 67 if (!stack_entry) 68 return -EINVAL; 69 70 boot_data = (struct rogue_mipsfw_boot_data *)(fw_data_ptr + boot_data_entry->alloc_offset + 71 ROGUE_MIPSFW_BOOTLDR_CONF_OFFSET); 72 73 WARN_ON(pvr_fw_object_get_dma_addr(fw_dev->mem.data_obj, stack_entry->alloc_offset, 74 &dma_addr)); 75 boot_data->stack_phys_addr = dma_addr; 76 77 boot_data->reg_base = pvr_dev->regs_resource->start; 78 79 for (u32 page_nr = 0; page_nr < ARRAY_SIZE(boot_data->pt_phys_addr); page_nr++) { 80 /* Firmware expects 4k pages, but host page size might be different. */ 81 u32 src_page_nr = (page_nr * ROGUE_MIPSFW_PAGE_SIZE_4K) >> PAGE_SHIFT; 82 u32 page_offset = (page_nr * ROGUE_MIPSFW_PAGE_SIZE_4K) & ~PAGE_MASK; 83 84 boot_data->pt_phys_addr[page_nr] = mips_data->pt_dma_addr[src_page_nr] + 85 page_offset; 86 } 87 88 boot_data->pt_log2_page_size = ROGUE_MIPSFW_LOG2_PAGE_SIZE_4K; 89 boot_data->pt_num_pages = ROGUE_MIPSFW_MAX_NUM_PAGETABLE_PAGES; 90 boot_data->reserved1 = 0; 91 boot_data->reserved2 = 0; 92 93 return 0; 94 } 95 96 static int 97 pvr_mips_wrapper_init(struct pvr_device *pvr_dev) 98 { 99 struct pvr_fw_mips_data *mips_data = pvr_dev->fw_dev.processor_data.mips_data; 100 const u64 remap_settings = ROGUE_MIPSFW_BOOT_REMAP_LOG2_SEGMENT_SIZE; 101 u32 phys_bus_width; 102 103 int err = PVR_FEATURE_VALUE(pvr_dev, phys_bus_width, &phys_bus_width); 104 105 if (WARN_ON(err)) 106 return err; 107 108 /* Currently MIPS FW only supported with physical bus width > 32 bits. */ 109 if (WARN_ON(phys_bus_width <= 32)) 110 return -EINVAL; 111 112 pvr_cr_write32(pvr_dev, ROGUE_CR_MIPS_WRAPPER_CONFIG, 113 (ROGUE_MIPSFW_REGISTERS_VIRTUAL_BASE >> 114 ROGUE_MIPSFW_WRAPPER_CONFIG_REGBANK_ADDR_ALIGN) | 115 ROGUE_CR_MIPS_WRAPPER_CONFIG_BOOT_ISA_MODE_MICROMIPS); 116 117 /* Configure remap for boot code, boot data and exceptions code areas. */ 118 pvr_cr_write64(pvr_dev, ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1, 119 ROGUE_MIPSFW_BOOT_REMAP_PHYS_ADDR_IN | 120 ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1_MODE_ENABLE_EN); 121 pvr_cr_write64(pvr_dev, ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2, 122 (mips_data->boot_code_dma_addr & 123 ~ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_ADDR_OUT_CLRMSK) | remap_settings); 124 125 if (PVR_HAS_QUIRK(pvr_dev, 63553)) { 126 /* 127 * WA always required on 36 bit cores, to avoid continuous unmapped memory accesses 128 * to address 0x0. 129 */ 130 WARN_ON(phys_bus_width != 36); 131 132 pvr_cr_write64(pvr_dev, ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1, 133 ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1_MODE_ENABLE_EN); 134 pvr_cr_write64(pvr_dev, ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2, 135 (mips_data->boot_code_dma_addr & 136 ~ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_ADDR_OUT_CLRMSK) | 137 remap_settings); 138 } 139 140 pvr_cr_write64(pvr_dev, ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1, 141 ROGUE_MIPSFW_DATA_REMAP_PHYS_ADDR_IN | 142 ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1_MODE_ENABLE_EN); 143 pvr_cr_write64(pvr_dev, ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2, 144 (mips_data->boot_data_dma_addr & 145 ~ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_ADDR_OUT_CLRMSK) | remap_settings); 146 147 pvr_cr_write64(pvr_dev, ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1, 148 ROGUE_MIPSFW_CODE_REMAP_PHYS_ADDR_IN | 149 ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1_MODE_ENABLE_EN); 150 pvr_cr_write64(pvr_dev, ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2, 151 (mips_data->exception_code_dma_addr & 152 ~ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_ADDR_OUT_CLRMSK) | remap_settings); 153 154 /* Garten IDLE bit controlled by MIPS. */ 155 pvr_cr_write64(pvr_dev, ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG, 156 ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_IDLE_CTRL_META); 157 158 /* Turn on the EJTAG probe. */ 159 pvr_cr_write32(pvr_dev, ROGUE_CR_MIPS_DEBUG_CONFIG, 0); 160 161 return 0; 162 } 163 164 static u32 165 pvr_mips_get_fw_addr_with_offset(struct pvr_fw_object *fw_obj, u32 offset) 166 { 167 struct pvr_device *pvr_dev = to_pvr_device(gem_from_pvr_gem(fw_obj->gem)->dev); 168 169 /* MIPS cacheability is determined by page table. */ 170 return ((fw_obj->fw_addr_offset + offset) & pvr_dev->fw_dev.fw_heap_info.offset_mask) | 171 ROGUE_FW_HEAP_MIPS_BASE; 172 } 173 174 static bool 175 pvr_mips_irq_pending(struct pvr_device *pvr_dev) 176 { 177 return pvr_cr_read32(pvr_dev, ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS) & 178 ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_EN; 179 } 180 181 static void 182 pvr_mips_irq_clear(struct pvr_device *pvr_dev) 183 { 184 pvr_cr_write32(pvr_dev, ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR, 185 ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR_EVENT_EN); 186 } 187 188 const struct pvr_fw_defs pvr_fw_defs_mips = { 189 .init = pvr_mips_init, 190 .fini = pvr_mips_fini, 191 .fw_process = pvr_mips_fw_process, 192 .vm_map = pvr_vm_mips_map, 193 .vm_unmap = pvr_vm_mips_unmap, 194 .get_fw_addr_with_offset = pvr_mips_get_fw_addr_with_offset, 195 .wrapper_init = pvr_mips_wrapper_init, 196 .irq_pending = pvr_mips_irq_pending, 197 .irq_clear = pvr_mips_irq_clear, 198 .has_fixed_data_addr = true, 199 }; 200