1 // SPDX-License-Identifier: GPL-2.0-only OR MIT 2 /* Copyright (c) 2023 Imagination Technologies Ltd. */ 3 4 #include "pvr_device.h" 5 #include "pvr_fw.h" 6 #include "pvr_fw_info.h" 7 #include "pvr_gem.h" 8 #include "pvr_rogue_cr_defs.h" 9 #include "pvr_rogue_meta.h" 10 #include "pvr_vm.h" 11 12 #include <linux/compiler.h> 13 #include <linux/delay.h> 14 #include <linux/firmware.h> 15 #include <linux/ktime.h> 16 #include <linux/types.h> 17 18 #define ROGUE_FW_HEAP_META_SHIFT 25 /* 32 MB */ 19 20 #define POLL_TIMEOUT_USEC 1000000 21 22 /** 23 * pvr_meta_cr_read32() - Read a META register via the Slave Port 24 * @pvr_dev: Device pointer. 25 * @reg_addr: Address of register to read. 26 * @reg_value_out: Pointer to location to store register value. 27 * 28 * Returns: 29 * * 0 on success, or 30 * * Any error returned by pvr_cr_poll_reg32(). 31 */ 32 int 33 pvr_meta_cr_read32(struct pvr_device *pvr_dev, u32 reg_addr, u32 *reg_value_out) 34 { 35 int err; 36 37 /* Wait for Slave Port to be Ready. */ 38 err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_META_SP_MSLVCTRL1, 39 ROGUE_CR_META_SP_MSLVCTRL1_READY_EN | 40 ROGUE_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_EN, 41 ROGUE_CR_META_SP_MSLVCTRL1_READY_EN | 42 ROGUE_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_EN, 43 POLL_TIMEOUT_USEC); 44 if (err) 45 return err; 46 47 /* Issue a Read. */ 48 pvr_cr_write32(pvr_dev, ROGUE_CR_META_SP_MSLVCTRL0, 49 reg_addr | ROGUE_CR_META_SP_MSLVCTRL0_RD_EN); 50 (void)pvr_cr_read32(pvr_dev, ROGUE_CR_META_SP_MSLVCTRL0); /* Fence write. */ 51 52 /* Wait for Slave Port to be Ready. */ 53 err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_META_SP_MSLVCTRL1, 54 ROGUE_CR_META_SP_MSLVCTRL1_READY_EN | 55 ROGUE_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_EN, 56 ROGUE_CR_META_SP_MSLVCTRL1_READY_EN | 57 ROGUE_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_EN, 58 POLL_TIMEOUT_USEC); 59 if (err) 60 return err; 61 62 *reg_value_out = pvr_cr_read32(pvr_dev, ROGUE_CR_META_SP_MSLVDATAX); 63 64 return 0; 65 } 66 67 static int 68 pvr_meta_wrapper_init(struct pvr_device *pvr_dev) 69 { 70 u64 garten_config; 71 72 /* Configure META to Master boot. */ 73 pvr_cr_write64(pvr_dev, ROGUE_CR_META_BOOT, ROGUE_CR_META_BOOT_MODE_EN); 74 75 /* Set Garten IDLE to META idle and Set the Garten Wrapper BIF Fence address. */ 76 77 /* Garten IDLE bit controlled by META. */ 78 garten_config = ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_IDLE_CTRL_META; 79 80 /* The fence addr is set during the fw init sequence. */ 81 82 /* Set PC = 0 for fences. */ 83 garten_config &= 84 ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_PC_BASE_CLRMSK; 85 garten_config |= 86 (u64)MMU_CONTEXT_MAPPING_FWPRIV 87 << ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_PC_BASE_SHIFT; 88 89 /* Set SLC DM=META. */ 90 garten_config |= ((u64)ROGUE_FW_SEGMMU_META_BIFDM_ID) 91 << ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_DM_SHIFT; 92 93 pvr_cr_write64(pvr_dev, ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG, garten_config); 94 95 return 0; 96 } 97 98 static __always_inline void 99 add_boot_arg(u32 **boot_conf, u32 param, u32 data) 100 { 101 *(*boot_conf)++ = param; 102 *(*boot_conf)++ = data; 103 } 104 105 static int 106 meta_ldr_cmd_loadmem(struct drm_device *drm_dev, const u8 *fw, 107 struct rogue_meta_ldr_l1_data_blk *l1_data, u32 coremem_size, u8 *fw_code_ptr, 108 u8 *fw_data_ptr, u8 *fw_core_code_ptr, u8 *fw_core_data_ptr, const u32 fw_size) 109 { 110 struct rogue_meta_ldr_l2_data_blk *l2_block = 111 (struct rogue_meta_ldr_l2_data_blk *)(fw + 112 l1_data->cmd_data[1]); 113 struct pvr_device *pvr_dev = to_pvr_device(drm_dev); 114 u32 offset = l1_data->cmd_data[0]; 115 u32 data_size; 116 void *write_addr; 117 int err; 118 119 /* Verify header is within bounds. */ 120 if (((u8 *)l2_block - fw) >= fw_size || ((u8 *)(l2_block + 1) - fw) >= fw_size) 121 return -EINVAL; 122 123 data_size = l2_block->length - 6 /* L2 Tag length and checksum */; 124 125 /* Verify data is within bounds. */ 126 if (((u8 *)l2_block->block_data - fw) >= fw_size || 127 ((((u8 *)l2_block->block_data) + data_size) - fw) >= fw_size) 128 return -EINVAL; 129 130 if (!ROGUE_META_IS_COREMEM_CODE(offset, coremem_size) && 131 !ROGUE_META_IS_COREMEM_DATA(offset, coremem_size)) { 132 /* Global range is aliased to local range */ 133 offset &= ~META_MEM_GLOBAL_RANGE_BIT; 134 } 135 136 err = pvr_fw_find_mmu_segment(pvr_dev, offset, data_size, fw_code_ptr, fw_data_ptr, 137 fw_core_code_ptr, fw_core_data_ptr, &write_addr); 138 if (err) { 139 drm_err(drm_dev, 140 "Addr 0x%x (size: %d) not found in any firmware segment", 141 offset, data_size); 142 return err; 143 } 144 145 memcpy(write_addr, l2_block->block_data, data_size); 146 147 return 0; 148 } 149 150 static int 151 meta_ldr_cmd_zeromem(struct drm_device *drm_dev, 152 struct rogue_meta_ldr_l1_data_blk *l1_data, u32 coremem_size, 153 u8 *fw_code_ptr, u8 *fw_data_ptr, u8 *fw_core_code_ptr, u8 *fw_core_data_ptr) 154 { 155 struct pvr_device *pvr_dev = to_pvr_device(drm_dev); 156 u32 offset = l1_data->cmd_data[0]; 157 u32 byte_count = l1_data->cmd_data[1]; 158 void *write_addr; 159 int err; 160 161 if (ROGUE_META_IS_COREMEM_DATA(offset, coremem_size)) { 162 /* cannot zero coremem directly */ 163 return 0; 164 } 165 166 /* Global range is aliased to local range */ 167 offset &= ~META_MEM_GLOBAL_RANGE_BIT; 168 169 err = pvr_fw_find_mmu_segment(pvr_dev, offset, byte_count, fw_code_ptr, fw_data_ptr, 170 fw_core_code_ptr, fw_core_data_ptr, &write_addr); 171 if (err) { 172 drm_err(drm_dev, 173 "Addr 0x%x (size: %d) not found in any firmware segment", 174 offset, byte_count); 175 return err; 176 } 177 178 memset(write_addr, 0, byte_count); 179 180 return 0; 181 } 182 183 static int 184 meta_ldr_cmd_config(struct drm_device *drm_dev, const u8 *fw, 185 struct rogue_meta_ldr_l1_data_blk *l1_data, 186 const u32 fw_size, u32 **boot_conf_ptr) 187 { 188 struct rogue_meta_ldr_l2_data_blk *l2_block = 189 (struct rogue_meta_ldr_l2_data_blk *)(fw + 190 l1_data->cmd_data[0]); 191 struct rogue_meta_ldr_cfg_blk *config_command; 192 u32 l2_block_size; 193 u32 curr_block_size = 0; 194 u32 *boot_conf = boot_conf_ptr ? *boot_conf_ptr : NULL; 195 196 /* Verify block header is within bounds. */ 197 if (((u8 *)l2_block - fw) >= fw_size || ((u8 *)(l2_block + 1) - fw) >= fw_size) 198 return -EINVAL; 199 200 l2_block_size = l2_block->length - 6 /* L2 Tag length and checksum */; 201 config_command = (struct rogue_meta_ldr_cfg_blk *)l2_block->block_data; 202 203 if (((u8 *)config_command - fw) >= fw_size || 204 ((((u8 *)config_command) + l2_block_size) - fw) >= fw_size) 205 return -EINVAL; 206 207 while (l2_block_size >= 12) { 208 if (config_command->type != ROGUE_META_LDR_CFG_WRITE) 209 return -EINVAL; 210 211 /* 212 * Only write to bootloader if we got a valid pointer to the FW 213 * code allocation. 214 */ 215 if (boot_conf) { 216 u32 register_offset = config_command->block_data[0]; 217 u32 register_value = config_command->block_data[1]; 218 219 /* Do register write */ 220 add_boot_arg(&boot_conf, register_offset, 221 register_value); 222 } 223 224 curr_block_size = 12; 225 l2_block_size -= curr_block_size; 226 config_command = (struct rogue_meta_ldr_cfg_blk 227 *)((uintptr_t)config_command + 228 curr_block_size); 229 } 230 231 if (boot_conf_ptr) 232 *boot_conf_ptr = boot_conf; 233 234 return 0; 235 } 236 237 /** 238 * process_ldr_command_stream() - Process LDR firmware image and populate 239 * firmware sections 240 * @pvr_dev: Device pointer. 241 * @fw: Pointer to firmware image. 242 * @fw_code_ptr: Pointer to FW code section. 243 * @fw_data_ptr: Pointer to FW data section. 244 * @fw_core_code_ptr: Pointer to FW coremem code section. 245 * @fw_core_data_ptr: Pointer to FW coremem data section. 246 * @boot_conf_ptr: Pointer to boot config argument pointer. 247 * 248 * Returns : 249 * * 0 on success, or 250 * * -EINVAL on any error in LDR command stream. 251 */ 252 static int 253 process_ldr_command_stream(struct pvr_device *pvr_dev, const u8 *fw, u8 *fw_code_ptr, 254 u8 *fw_data_ptr, u8 *fw_core_code_ptr, 255 u8 *fw_core_data_ptr, u32 **boot_conf_ptr) 256 { 257 struct drm_device *drm_dev = from_pvr_device(pvr_dev); 258 struct rogue_meta_ldr_block_hdr *ldr_header = 259 (struct rogue_meta_ldr_block_hdr *)fw; 260 struct rogue_meta_ldr_l1_data_blk *l1_data = 261 (struct rogue_meta_ldr_l1_data_blk *)(fw + ldr_header->sl_data); 262 const u32 fw_size = pvr_dev->fw_dev.firmware->size; 263 int err; 264 265 u32 *boot_conf = boot_conf_ptr ? *boot_conf_ptr : NULL; 266 u32 coremem_size; 267 268 err = PVR_FEATURE_VALUE(pvr_dev, meta_coremem_size, &coremem_size); 269 if (err) 270 return err; 271 272 coremem_size *= SZ_1K; 273 274 while (l1_data) { 275 /* Verify block header is within bounds. */ 276 if (((u8 *)l1_data - fw) >= fw_size || ((u8 *)(l1_data + 1) - fw) >= fw_size) 277 return -EINVAL; 278 279 if (ROGUE_META_LDR_BLK_IS_COMMENT(l1_data->cmd)) { 280 /* Don't process comment blocks */ 281 goto next_block; 282 } 283 284 switch (l1_data->cmd & ROGUE_META_LDR_CMD_MASK) 285 case ROGUE_META_LDR_CMD_LOADMEM: { 286 err = meta_ldr_cmd_loadmem(drm_dev, fw, l1_data, 287 coremem_size, 288 fw_code_ptr, fw_data_ptr, 289 fw_core_code_ptr, 290 fw_core_data_ptr, fw_size); 291 if (err) 292 return err; 293 break; 294 295 case ROGUE_META_LDR_CMD_START_THREADS: 296 /* Don't process this block */ 297 break; 298 299 case ROGUE_META_LDR_CMD_ZEROMEM: 300 err = meta_ldr_cmd_zeromem(drm_dev, l1_data, 301 coremem_size, 302 fw_code_ptr, fw_data_ptr, 303 fw_core_code_ptr, 304 fw_core_data_ptr); 305 if (err) 306 return err; 307 break; 308 309 case ROGUE_META_LDR_CMD_CONFIG: 310 err = meta_ldr_cmd_config(drm_dev, fw, l1_data, fw_size, 311 &boot_conf); 312 if (err) 313 return err; 314 break; 315 316 default: 317 return -EINVAL; 318 } 319 320 next_block: 321 if (l1_data->next == 0xFFFFFFFF) 322 break; 323 324 l1_data = (struct rogue_meta_ldr_l1_data_blk *)(fw + 325 l1_data->next); 326 } 327 328 if (boot_conf_ptr) 329 *boot_conf_ptr = boot_conf; 330 331 return 0; 332 } 333 334 static void 335 configure_seg_id(u64 seg_out_addr, u32 seg_base, u32 seg_limit, u32 seg_id, 336 u32 **boot_conf_ptr) 337 { 338 u32 seg_out_addr0 = seg_out_addr & 0x00000000FFFFFFFFUL; 339 u32 seg_out_addr1 = (seg_out_addr >> 32) & 0x00000000FFFFFFFFUL; 340 u32 *boot_conf = *boot_conf_ptr; 341 342 /* META segments have a minimum size. */ 343 u32 limit_off = max(seg_limit, ROGUE_FW_SEGMMU_ALIGN); 344 345 /* The limit is an offset, therefore off = size - 1. */ 346 limit_off -= 1; 347 348 seg_base |= ROGUE_FW_SEGMMU_ALLTHRS_WRITEABLE; 349 350 add_boot_arg(&boot_conf, META_CR_MMCU_SEGMENT_N_BASE(seg_id), seg_base); 351 add_boot_arg(&boot_conf, META_CR_MMCU_SEGMENT_N_LIMIT(seg_id), limit_off); 352 add_boot_arg(&boot_conf, META_CR_MMCU_SEGMENT_N_OUTA0(seg_id), seg_out_addr0); 353 add_boot_arg(&boot_conf, META_CR_MMCU_SEGMENT_N_OUTA1(seg_id), seg_out_addr1); 354 355 *boot_conf_ptr = boot_conf; 356 } 357 358 static u64 get_fw_obj_gpu_addr(struct pvr_fw_object *fw_obj) 359 { 360 struct pvr_device *pvr_dev = to_pvr_device(gem_from_pvr_gem(fw_obj->gem)->dev); 361 struct pvr_fw_device *fw_dev = &pvr_dev->fw_dev; 362 363 return fw_obj->fw_addr_offset + fw_dev->fw_heap_info.gpu_addr; 364 } 365 366 static void 367 configure_seg_mmu(struct pvr_device *pvr_dev, u32 **boot_conf_ptr) 368 { 369 const struct pvr_fw_layout_entry *layout_entries = pvr_dev->fw_dev.layout_entries; 370 u32 num_layout_entries = pvr_dev->fw_dev.header->layout_entry_num; 371 u64 seg_out_addr_top; 372 u32 i; 373 374 seg_out_addr_top = 375 ROGUE_FW_SEGMMU_OUTADDR_TOP_SLC(MMU_CONTEXT_MAPPING_FWPRIV, 376 ROGUE_FW_SEGMMU_META_BIFDM_ID); 377 378 for (i = 0; i < num_layout_entries; i++) { 379 /* 380 * FW code is using the bootloader segment which is already 381 * configured on boot. FW coremem code and data don't use the 382 * segment MMU. Only the FW data segment needs to be configured. 383 */ 384 if (layout_entries[i].type == FW_DATA) { 385 u32 seg_id = ROGUE_FW_SEGMMU_DATA_ID; 386 u64 seg_out_addr = get_fw_obj_gpu_addr(pvr_dev->fw_dev.mem.data_obj); 387 388 seg_out_addr += layout_entries[i].alloc_offset; 389 seg_out_addr |= seg_out_addr_top; 390 391 /* Write the sequence to the bootldr. */ 392 configure_seg_id(seg_out_addr, 393 layout_entries[i].base_addr, 394 layout_entries[i].alloc_size, seg_id, 395 boot_conf_ptr); 396 397 break; 398 } 399 } 400 } 401 402 static void 403 configure_meta_caches(u32 **boot_conf_ptr) 404 { 405 u32 *boot_conf = *boot_conf_ptr; 406 u32 d_cache_t0, i_cache_t0; 407 u32 d_cache_t1, i_cache_t1; 408 u32 d_cache_t2, i_cache_t2; 409 u32 d_cache_t3, i_cache_t3; 410 411 /* Initialise I/Dcache settings */ 412 d_cache_t0 = META_CR_SYSC_DCPARTX_CACHED_WRITE_ENABLE; 413 d_cache_t1 = META_CR_SYSC_DCPARTX_CACHED_WRITE_ENABLE; 414 d_cache_t2 = META_CR_SYSC_DCPARTX_CACHED_WRITE_ENABLE; 415 d_cache_t3 = META_CR_SYSC_DCPARTX_CACHED_WRITE_ENABLE; 416 i_cache_t0 = 0; 417 i_cache_t1 = 0; 418 i_cache_t2 = 0; 419 i_cache_t3 = 0; 420 421 d_cache_t0 |= META_CR_SYSC_XCPARTX_LOCAL_ADDR_FULL_CACHE; 422 i_cache_t0 |= META_CR_SYSC_XCPARTX_LOCAL_ADDR_FULL_CACHE; 423 424 /* Local region MMU enhanced bypass: WIN-3 mode for code and data caches */ 425 add_boot_arg(&boot_conf, META_CR_MMCU_LOCAL_EBCTRL, 426 META_CR_MMCU_LOCAL_EBCTRL_ICWIN | 427 META_CR_MMCU_LOCAL_EBCTRL_DCWIN); 428 429 /* Data cache partitioning thread 0 to 3 */ 430 add_boot_arg(&boot_conf, META_CR_SYSC_DCPART(0), d_cache_t0); 431 add_boot_arg(&boot_conf, META_CR_SYSC_DCPART(1), d_cache_t1); 432 add_boot_arg(&boot_conf, META_CR_SYSC_DCPART(2), d_cache_t2); 433 add_boot_arg(&boot_conf, META_CR_SYSC_DCPART(3), d_cache_t3); 434 435 /* Enable data cache hits */ 436 add_boot_arg(&boot_conf, META_CR_MMCU_DCACHE_CTRL, 437 META_CR_MMCU_XCACHE_CTRL_CACHE_HITS_EN); 438 439 /* Instruction cache partitioning thread 0 to 3 */ 440 add_boot_arg(&boot_conf, META_CR_SYSC_ICPART(0), i_cache_t0); 441 add_boot_arg(&boot_conf, META_CR_SYSC_ICPART(1), i_cache_t1); 442 add_boot_arg(&boot_conf, META_CR_SYSC_ICPART(2), i_cache_t2); 443 add_boot_arg(&boot_conf, META_CR_SYSC_ICPART(3), i_cache_t3); 444 445 /* Enable instruction cache hits */ 446 add_boot_arg(&boot_conf, META_CR_MMCU_ICACHE_CTRL, 447 META_CR_MMCU_XCACHE_CTRL_CACHE_HITS_EN); 448 449 add_boot_arg(&boot_conf, 0x040000C0, 0); 450 451 *boot_conf_ptr = boot_conf; 452 } 453 454 static int 455 pvr_meta_fw_process(struct pvr_device *pvr_dev, const u8 *fw, 456 u8 *fw_code_ptr, u8 *fw_data_ptr, u8 *fw_core_code_ptr, u8 *fw_core_data_ptr, 457 u32 core_code_alloc_size) 458 { 459 struct pvr_fw_device *fw_dev = &pvr_dev->fw_dev; 460 u32 *boot_conf; 461 int err; 462 463 boot_conf = ((u32 *)fw_code_ptr) + ROGUE_FW_BOOTLDR_CONF_OFFSET; 464 465 /* Slave port and JTAG accesses are privileged. */ 466 add_boot_arg(&boot_conf, META_CR_SYSC_JTAG_THREAD, 467 META_CR_SYSC_JTAG_THREAD_PRIV_EN); 468 469 configure_seg_mmu(pvr_dev, &boot_conf); 470 471 /* Populate FW sections from LDR image. */ 472 err = process_ldr_command_stream(pvr_dev, fw, fw_code_ptr, fw_data_ptr, fw_core_code_ptr, 473 fw_core_data_ptr, &boot_conf); 474 if (err) 475 return err; 476 477 configure_meta_caches(&boot_conf); 478 479 /* End argument list. */ 480 add_boot_arg(&boot_conf, 0, 0); 481 482 if (fw_dev->mem.core_code_obj) { 483 u32 core_code_fw_addr; 484 485 pvr_fw_object_get_fw_addr(fw_dev->mem.core_code_obj, &core_code_fw_addr); 486 add_boot_arg(&boot_conf, core_code_fw_addr, core_code_alloc_size); 487 } else { 488 add_boot_arg(&boot_conf, 0, 0); 489 } 490 /* None of the cores supported by this driver have META DMA. */ 491 add_boot_arg(&boot_conf, 0, 0); 492 493 return 0; 494 } 495 496 static int 497 pvr_meta_init(struct pvr_device *pvr_dev) 498 { 499 pvr_fw_heap_info_init(pvr_dev, ROGUE_FW_HEAP_META_SHIFT, 0); 500 501 return 0; 502 } 503 504 static u32 505 pvr_meta_get_fw_addr_with_offset(struct pvr_fw_object *fw_obj, u32 offset) 506 { 507 u32 fw_addr = fw_obj->fw_addr_offset + offset + ROGUE_FW_SEGMMU_DATA_BASE_ADDRESS; 508 509 /* META cacheability is determined by address. */ 510 if (fw_obj->gem->flags & PVR_BO_FW_FLAGS_DEVICE_UNCACHED) 511 fw_addr |= ROGUE_FW_SEGMMU_DATA_META_UNCACHED | 512 ROGUE_FW_SEGMMU_DATA_VIVT_SLC_UNCACHED; 513 514 return fw_addr; 515 } 516 517 static int 518 pvr_meta_vm_map(struct pvr_device *pvr_dev, struct pvr_fw_object *fw_obj) 519 { 520 struct pvr_gem_object *pvr_obj = fw_obj->gem; 521 522 return pvr_vm_map(pvr_dev->kernel_vm_ctx, pvr_obj, 0, fw_obj->fw_mm_node.start, 523 pvr_gem_object_size(pvr_obj)); 524 } 525 526 static void 527 pvr_meta_vm_unmap(struct pvr_device *pvr_dev, struct pvr_fw_object *fw_obj) 528 { 529 pvr_vm_unmap(pvr_dev->kernel_vm_ctx, fw_obj->fw_mm_node.start, 530 fw_obj->fw_mm_node.size); 531 } 532 533 static bool 534 pvr_meta_has_fixed_data_addr(void) 535 { 536 return false; 537 } 538 539 const struct pvr_fw_defs pvr_fw_defs_meta = { 540 .init = pvr_meta_init, 541 .fw_process = pvr_meta_fw_process, 542 .vm_map = pvr_meta_vm_map, 543 .vm_unmap = pvr_meta_vm_unmap, 544 .get_fw_addr_with_offset = pvr_meta_get_fw_addr_with_offset, 545 .wrapper_init = pvr_meta_wrapper_init, 546 .has_fixed_data_addr = pvr_meta_has_fixed_data_addr, 547 .irq = { 548 .enable_reg = ROGUE_CR_META_SP_MSLVIRQENABLE, 549 .status_reg = ROGUE_CR_META_SP_MSLVIRQSTATUS, 550 .clear_reg = ROGUE_CR_META_SP_MSLVIRQSTATUS, 551 .event_mask = ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_EN, 552 .clear_mask = ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_CLRMSK, 553 }, 554 }; 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