1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 6 #include <linux/kernel.h> 7 8 #include <drm/drm_print.h> 9 10 #include "i915_drv.h" 11 #include "i915_reg.h" 12 #include "i915_trace.h" 13 #include "i915_utils.h" 14 #include "intel_pm.h" 15 #include "vlv_suspend.h" 16 17 #include "gt/intel_gt_regs.h" 18 19 struct vlv_s0ix_state { 20 /* GAM */ 21 u32 wr_watermark; 22 u32 gfx_prio_ctrl; 23 u32 arb_mode; 24 u32 gfx_pend_tlb0; 25 u32 gfx_pend_tlb1; 26 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; 27 u32 media_max_req_count; 28 u32 gfx_max_req_count; 29 u32 render_hwsp; 30 u32 ecochk; 31 u32 bsd_hwsp; 32 u32 blt_hwsp; 33 u32 tlb_rd_addr; 34 35 /* MBC */ 36 u32 g3dctl; 37 u32 gsckgctl; 38 u32 mbctl; 39 40 /* GCP */ 41 u32 ucgctl1; 42 u32 ucgctl3; 43 u32 rcgctl1; 44 u32 rcgctl2; 45 u32 rstctl; 46 u32 misccpctl; 47 48 /* GPM */ 49 u32 gfxpause; 50 u32 rpdeuhwtc; 51 u32 rpdeuc; 52 u32 ecobus; 53 u32 pwrdwnupctl; 54 u32 rp_down_timeout; 55 u32 rp_deucsw; 56 u32 rcubmabdtmr; 57 u32 rcedata; 58 u32 spare2gh; 59 60 /* Display 1 CZ domain */ 61 u32 gt_imr; 62 u32 gt_ier; 63 u32 pm_imr; 64 u32 pm_ier; 65 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; 66 67 /* GT SA CZ domain */ 68 u32 tilectl; 69 u32 gt_fifoctl; 70 u32 gtlc_wake_ctrl; 71 u32 gtlc_survive; 72 u32 pmwgicz; 73 74 /* Display 2 CZ domain */ 75 u32 gu_ctl0; 76 u32 gu_ctl1; 77 u32 pcbr; 78 u32 clock_gate_dis2; 79 }; 80 81 /* 82 * Save all Gunit registers that may be lost after a D3 and a subsequent 83 * S0i[R123] transition. The list of registers needing a save/restore is 84 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit 85 * registers in the following way: 86 * - Driver: saved/restored by the driver 87 * - Punit : saved/restored by the Punit firmware 88 * - No, w/o marking: no need to save/restore, since the register is R/O or 89 * used internally by the HW in a way that doesn't depend 90 * keeping the content across a suspend/resume. 91 * - Debug : used for debugging 92 * 93 * We save/restore all registers marked with 'Driver', with the following 94 * exceptions: 95 * - Registers out of use, including also registers marked with 'Debug'. 96 * These have no effect on the driver's operation, so we don't save/restore 97 * them to reduce the overhead. 98 * - Registers that are fully setup by an initialization function called from 99 * the resume path. For example many clock gating and RPS/RC6 registers. 100 * - Registers that provide the right functionality with their reset defaults. 101 * 102 * TODO: Except for registers that based on the above 3 criteria can be safely 103 * ignored, we save/restore all others, practically treating the HW context as 104 * a black-box for the driver. Further investigation is needed to reduce the 105 * saved/restored registers even further, by following the same 3 criteria. 106 */ 107 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *i915) 108 { 109 struct vlv_s0ix_state *s = i915->vlv_s0ix_state; 110 struct intel_uncore *uncore = &i915->uncore; 111 int i; 112 113 if (!s) 114 return; 115 116 /* GAM 0x4000-0x4770 */ 117 s->wr_watermark = intel_uncore_read(uncore, GEN7_WR_WATERMARK); 118 s->gfx_prio_ctrl = intel_uncore_read(uncore, GEN7_GFX_PRIO_CTRL); 119 s->arb_mode = intel_uncore_read(uncore, ARB_MODE); 120 s->gfx_pend_tlb0 = intel_uncore_read(uncore, GEN7_GFX_PEND_TLB0); 121 s->gfx_pend_tlb1 = intel_uncore_read(uncore, GEN7_GFX_PEND_TLB1); 122 123 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) 124 s->lra_limits[i] = intel_uncore_read(uncore, GEN7_LRA_LIMITS(i)); 125 126 s->media_max_req_count = intel_uncore_read(uncore, GEN7_MEDIA_MAX_REQ_COUNT); 127 s->gfx_max_req_count = intel_uncore_read(uncore, GEN7_GFX_MAX_REQ_COUNT); 128 129 s->render_hwsp = intel_uncore_read(uncore, RENDER_HWS_PGA_GEN7); 130 s->ecochk = intel_uncore_read(uncore, GAM_ECOCHK); 131 s->bsd_hwsp = intel_uncore_read(uncore, BSD_HWS_PGA_GEN7); 132 s->blt_hwsp = intel_uncore_read(uncore, BLT_HWS_PGA_GEN7); 133 134 s->tlb_rd_addr = intel_uncore_read(uncore, GEN7_TLB_RD_ADDR); 135 136 /* MBC 0x9024-0x91D0, 0x8500 */ 137 s->g3dctl = intel_uncore_read(uncore, VLV_G3DCTL); 138 s->gsckgctl = intel_uncore_read(uncore, VLV_GSCKGCTL); 139 s->mbctl = intel_uncore_read(uncore, GEN6_MBCTL); 140 141 /* GCP 0x9400-0x9424, 0x8100-0x810C */ 142 s->ucgctl1 = intel_uncore_read(uncore, GEN6_UCGCTL1); 143 s->ucgctl3 = intel_uncore_read(uncore, GEN6_UCGCTL3); 144 s->rcgctl1 = intel_uncore_read(uncore, GEN6_RCGCTL1); 145 s->rcgctl2 = intel_uncore_read(uncore, GEN6_RCGCTL2); 146 s->rstctl = intel_uncore_read(uncore, GEN6_RSTCTL); 147 s->misccpctl = intel_uncore_read(uncore, GEN7_MISCCPCTL); 148 149 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ 150 s->gfxpause = intel_uncore_read(uncore, GEN6_GFXPAUSE); 151 s->rpdeuhwtc = intel_uncore_read(uncore, GEN6_RPDEUHWTC); 152 s->rpdeuc = intel_uncore_read(uncore, GEN6_RPDEUC); 153 s->ecobus = intel_uncore_read(uncore, ECOBUS); 154 s->pwrdwnupctl = intel_uncore_read(uncore, VLV_PWRDWNUPCTL); 155 s->rp_down_timeout = intel_uncore_read(uncore, GEN6_RP_DOWN_TIMEOUT); 156 s->rp_deucsw = intel_uncore_read(uncore, GEN6_RPDEUCSW); 157 s->rcubmabdtmr = intel_uncore_read(uncore, GEN6_RCUBMABDTMR); 158 s->rcedata = intel_uncore_read(uncore, VLV_RCEDATA); 159 s->spare2gh = intel_uncore_read(uncore, VLV_SPAREG2H); 160 161 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ 162 s->gt_imr = intel_uncore_read(uncore, GTIMR); 163 s->gt_ier = intel_uncore_read(uncore, GTIER); 164 s->pm_imr = intel_uncore_read(uncore, GEN6_PMIMR); 165 s->pm_ier = intel_uncore_read(uncore, GEN6_PMIER); 166 167 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) 168 s->gt_scratch[i] = intel_uncore_read(uncore, GEN7_GT_SCRATCH(i)); 169 170 /* GT SA CZ domain, 0x100000-0x138124 */ 171 s->tilectl = intel_uncore_read(uncore, TILECTL); 172 s->gt_fifoctl = intel_uncore_read(uncore, GTFIFOCTL); 173 s->gtlc_wake_ctrl = intel_uncore_read(uncore, VLV_GTLC_WAKE_CTRL); 174 s->gtlc_survive = intel_uncore_read(uncore, VLV_GTLC_SURVIVABILITY_REG); 175 s->pmwgicz = intel_uncore_read(uncore, VLV_PMWGICZ); 176 177 /* Gunit-Display CZ domain, 0x182028-0x1821CF */ 178 s->gu_ctl0 = intel_uncore_read(uncore, VLV_GU_CTL0); 179 s->gu_ctl1 = intel_uncore_read(uncore, VLV_GU_CTL1); 180 s->pcbr = intel_uncore_read(uncore, VLV_PCBR); 181 s->clock_gate_dis2 = intel_uncore_read(uncore, VLV_GUNIT_CLOCK_GATE2); 182 183 /* 184 * Not saving any of: 185 * DFT, 0x9800-0x9EC0 186 * SARB, 0xB000-0xB1FC 187 * GAC, 0x5208-0x524C, 0x14000-0x14C000 188 * PCI CFG 189 */ 190 } 191 192 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *i915) 193 { 194 struct vlv_s0ix_state *s = i915->vlv_s0ix_state; 195 struct intel_uncore *uncore = &i915->uncore; 196 u32 val; 197 int i; 198 199 if (!s) 200 return; 201 202 /* GAM 0x4000-0x4770 */ 203 intel_uncore_write(uncore, GEN7_WR_WATERMARK, s->wr_watermark); 204 intel_uncore_write(uncore, GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl); 205 intel_uncore_write(uncore, ARB_MODE, s->arb_mode | (0xffff << 16)); 206 intel_uncore_write(uncore, GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0); 207 intel_uncore_write(uncore, GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1); 208 209 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) 210 intel_uncore_write(uncore, GEN7_LRA_LIMITS(i), s->lra_limits[i]); 211 212 intel_uncore_write(uncore, GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count); 213 intel_uncore_write(uncore, GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count); 214 215 intel_uncore_write(uncore, RENDER_HWS_PGA_GEN7, s->render_hwsp); 216 intel_uncore_write(uncore, GAM_ECOCHK, s->ecochk); 217 intel_uncore_write(uncore, BSD_HWS_PGA_GEN7, s->bsd_hwsp); 218 intel_uncore_write(uncore, BLT_HWS_PGA_GEN7, s->blt_hwsp); 219 220 intel_uncore_write(uncore, GEN7_TLB_RD_ADDR, s->tlb_rd_addr); 221 222 /* MBC 0x9024-0x91D0, 0x8500 */ 223 intel_uncore_write(uncore, VLV_G3DCTL, s->g3dctl); 224 intel_uncore_write(uncore, VLV_GSCKGCTL, s->gsckgctl); 225 intel_uncore_write(uncore, GEN6_MBCTL, s->mbctl); 226 227 /* GCP 0x9400-0x9424, 0x8100-0x810C */ 228 intel_uncore_write(uncore, GEN6_UCGCTL1, s->ucgctl1); 229 intel_uncore_write(uncore, GEN6_UCGCTL3, s->ucgctl3); 230 intel_uncore_write(uncore, GEN6_RCGCTL1, s->rcgctl1); 231 intel_uncore_write(uncore, GEN6_RCGCTL2, s->rcgctl2); 232 intel_uncore_write(uncore, GEN6_RSTCTL, s->rstctl); 233 intel_uncore_write(uncore, GEN7_MISCCPCTL, s->misccpctl); 234 235 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ 236 intel_uncore_write(uncore, GEN6_GFXPAUSE, s->gfxpause); 237 intel_uncore_write(uncore, GEN6_RPDEUHWTC, s->rpdeuhwtc); 238 intel_uncore_write(uncore, GEN6_RPDEUC, s->rpdeuc); 239 intel_uncore_write(uncore, ECOBUS, s->ecobus); 240 intel_uncore_write(uncore, VLV_PWRDWNUPCTL, s->pwrdwnupctl); 241 intel_uncore_write(uncore, GEN6_RP_DOWN_TIMEOUT, s->rp_down_timeout); 242 intel_uncore_write(uncore, GEN6_RPDEUCSW, s->rp_deucsw); 243 intel_uncore_write(uncore, GEN6_RCUBMABDTMR, s->rcubmabdtmr); 244 intel_uncore_write(uncore, VLV_RCEDATA, s->rcedata); 245 intel_uncore_write(uncore, VLV_SPAREG2H, s->spare2gh); 246 247 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ 248 intel_uncore_write(uncore, GTIMR, s->gt_imr); 249 intel_uncore_write(uncore, GTIER, s->gt_ier); 250 intel_uncore_write(uncore, GEN6_PMIMR, s->pm_imr); 251 intel_uncore_write(uncore, GEN6_PMIER, s->pm_ier); 252 253 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) 254 intel_uncore_write(uncore, GEN7_GT_SCRATCH(i), s->gt_scratch[i]); 255 256 /* GT SA CZ domain, 0x100000-0x138124 */ 257 intel_uncore_write(uncore, TILECTL, s->tilectl); 258 intel_uncore_write(uncore, GTFIFOCTL, s->gt_fifoctl); 259 /* 260 * Preserve the GT allow wake and GFX force clock bit, they are not 261 * be restored, as they are used to control the s0ix suspend/resume 262 * sequence by the caller. 263 */ 264 val = intel_uncore_read(uncore, VLV_GTLC_WAKE_CTRL); 265 val &= VLV_GTLC_ALLOWWAKEREQ; 266 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ; 267 intel_uncore_write(uncore, VLV_GTLC_WAKE_CTRL, val); 268 269 val = intel_uncore_read(uncore, VLV_GTLC_SURVIVABILITY_REG); 270 val &= VLV_GFX_CLK_FORCE_ON_BIT; 271 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT; 272 intel_uncore_write(uncore, VLV_GTLC_SURVIVABILITY_REG, val); 273 274 intel_uncore_write(uncore, VLV_PMWGICZ, s->pmwgicz); 275 276 /* Gunit-Display CZ domain, 0x182028-0x1821CF */ 277 intel_uncore_write(uncore, VLV_GU_CTL0, s->gu_ctl0); 278 intel_uncore_write(uncore, VLV_GU_CTL1, s->gu_ctl1); 279 intel_uncore_write(uncore, VLV_PCBR, s->pcbr); 280 intel_uncore_write(uncore, VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2); 281 } 282 283 static int vlv_wait_for_pw_status(struct drm_i915_private *i915, 284 u32 mask, u32 val) 285 { 286 i915_reg_t reg = VLV_GTLC_PW_STATUS; 287 u32 reg_value; 288 int ret; 289 290 /* The HW does not like us polling for PW_STATUS frequently, so 291 * use the sleeping loop rather than risk the busy spin within 292 * intel_wait_for_register(). 293 * 294 * Transitioning between RC6 states should be at most 2ms (see 295 * valleyview_enable_rps) so use a 3ms timeout. 296 */ 297 ret = wait_for(((reg_value = 298 intel_uncore_read_notrace(&i915->uncore, reg)) & mask) 299 == val, 3); 300 301 /* just trace the final value */ 302 trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true); 303 304 return ret; 305 } 306 307 static int vlv_force_gfx_clock(struct drm_i915_private *i915, bool force_on) 308 { 309 struct intel_uncore *uncore = &i915->uncore; 310 u32 val; 311 int err; 312 313 val = intel_uncore_read(uncore, VLV_GTLC_SURVIVABILITY_REG); 314 val &= ~VLV_GFX_CLK_FORCE_ON_BIT; 315 if (force_on) 316 val |= VLV_GFX_CLK_FORCE_ON_BIT; 317 intel_uncore_write(uncore, VLV_GTLC_SURVIVABILITY_REG, val); 318 319 if (!force_on) 320 return 0; 321 322 err = intel_wait_for_register(uncore, 323 VLV_GTLC_SURVIVABILITY_REG, 324 VLV_GFX_CLK_STATUS_BIT, 325 VLV_GFX_CLK_STATUS_BIT, 326 20); 327 if (err) 328 drm_err(&i915->drm, 329 "timeout waiting for GFX clock force-on (%08x)\n", 330 intel_uncore_read(uncore, VLV_GTLC_SURVIVABILITY_REG)); 331 332 return err; 333 } 334 335 static int vlv_allow_gt_wake(struct drm_i915_private *i915, bool allow) 336 { 337 struct intel_uncore *uncore = &i915->uncore; 338 u32 mask; 339 u32 val; 340 int err; 341 342 val = intel_uncore_read(uncore, VLV_GTLC_WAKE_CTRL); 343 val &= ~VLV_GTLC_ALLOWWAKEREQ; 344 if (allow) 345 val |= VLV_GTLC_ALLOWWAKEREQ; 346 intel_uncore_write(uncore, VLV_GTLC_WAKE_CTRL, val); 347 intel_uncore_posting_read(uncore, VLV_GTLC_WAKE_CTRL); 348 349 mask = VLV_GTLC_ALLOWWAKEACK; 350 val = allow ? mask : 0; 351 352 err = vlv_wait_for_pw_status(i915, mask, val); 353 if (err) 354 drm_err(&i915->drm, "timeout disabling GT waking\n"); 355 356 return err; 357 } 358 359 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv, 360 bool wait_for_on) 361 { 362 u32 mask; 363 u32 val; 364 365 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK; 366 val = wait_for_on ? mask : 0; 367 368 /* 369 * RC6 transitioning can be delayed up to 2 msec (see 370 * valleyview_enable_rps), use 3 msec for safety. 371 * 372 * This can fail to turn off the rc6 if the GPU is stuck after a failed 373 * reset and we are trying to force the machine to sleep. 374 */ 375 if (vlv_wait_for_pw_status(dev_priv, mask, val)) 376 drm_dbg(&dev_priv->drm, 377 "timeout waiting for GT wells to go %s\n", 378 onoff(wait_for_on)); 379 } 380 381 static void vlv_check_no_gt_access(struct drm_i915_private *i915) 382 { 383 struct intel_uncore *uncore = &i915->uncore; 384 385 if (!(intel_uncore_read(uncore, VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR)) 386 return; 387 388 drm_dbg(&i915->drm, "GT register access while GT waking disabled\n"); 389 intel_uncore_write(uncore, VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR); 390 } 391 392 int vlv_suspend_complete(struct drm_i915_private *dev_priv) 393 { 394 u32 mask; 395 int err; 396 397 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) 398 return 0; 399 400 /* 401 * Bspec defines the following GT well on flags as debug only, so 402 * don't treat them as hard failures. 403 */ 404 vlv_wait_for_gt_wells(dev_priv, false); 405 406 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS; 407 drm_WARN_ON(&dev_priv->drm, 408 (intel_uncore_read(&dev_priv->uncore, VLV_GTLC_WAKE_CTRL) & mask) != mask); 409 410 vlv_check_no_gt_access(dev_priv); 411 412 err = vlv_force_gfx_clock(dev_priv, true); 413 if (err) 414 goto err1; 415 416 err = vlv_allow_gt_wake(dev_priv, false); 417 if (err) 418 goto err2; 419 420 vlv_save_gunit_s0ix_state(dev_priv); 421 422 err = vlv_force_gfx_clock(dev_priv, false); 423 if (err) 424 goto err2; 425 426 return 0; 427 428 err2: 429 /* For safety always re-enable waking and disable gfx clock forcing */ 430 vlv_allow_gt_wake(dev_priv, true); 431 err1: 432 vlv_force_gfx_clock(dev_priv, false); 433 434 return err; 435 } 436 437 int vlv_resume_prepare(struct drm_i915_private *dev_priv, bool rpm_resume) 438 { 439 int err; 440 int ret; 441 442 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) 443 return 0; 444 445 /* 446 * If any of the steps fail just try to continue, that's the best we 447 * can do at this point. Return the first error code (which will also 448 * leave RPM permanently disabled). 449 */ 450 ret = vlv_force_gfx_clock(dev_priv, true); 451 452 vlv_restore_gunit_s0ix_state(dev_priv); 453 454 err = vlv_allow_gt_wake(dev_priv, true); 455 if (!ret) 456 ret = err; 457 458 err = vlv_force_gfx_clock(dev_priv, false); 459 if (!ret) 460 ret = err; 461 462 vlv_check_no_gt_access(dev_priv); 463 464 if (rpm_resume) 465 intel_init_clock_gating(dev_priv); 466 467 return ret; 468 } 469 470 int vlv_suspend_init(struct drm_i915_private *i915) 471 { 472 if (!IS_VALLEYVIEW(i915)) 473 return 0; 474 475 /* we write all the values in the struct, so no need to zero it out */ 476 i915->vlv_s0ix_state = kmalloc(sizeof(*i915->vlv_s0ix_state), 477 GFP_KERNEL); 478 if (!i915->vlv_s0ix_state) 479 return -ENOMEM; 480 481 return 0; 482 } 483 484 void vlv_suspend_cleanup(struct drm_i915_private *i915) 485 { 486 if (!i915->vlv_s0ix_state) 487 return; 488 489 kfree(i915->vlv_s0ix_state); 490 i915->vlv_s0ix_state = NULL; 491 } 492