1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 6 #include <linux/string_helpers.h> 7 #include <linux/kernel.h> 8 9 #include <drm/drm_print.h> 10 #include <drm/intel/intel_gmd_interrupt_regs.h> 11 12 #include "gt/intel_gt_regs.h" 13 14 #include "i915_drv.h" 15 #include "i915_reg.h" 16 #include "i915_trace.h" 17 #include "i915_utils.h" 18 #include "i915_wait_util.h" 19 #include "intel_clock_gating.h" 20 #include "intel_uncore_trace.h" 21 #include "vlv_suspend.h" 22 23 struct vlv_s0ix_state { 24 /* GAM */ 25 u32 wr_watermark; 26 u32 gfx_prio_ctrl; 27 u32 arb_mode; 28 u32 gfx_pend_tlb0; 29 u32 gfx_pend_tlb1; 30 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; 31 u32 media_max_req_count; 32 u32 gfx_max_req_count; 33 u32 render_hwsp; 34 u32 ecochk; 35 u32 bsd_hwsp; 36 u32 blt_hwsp; 37 u32 tlb_rd_addr; 38 39 /* MBC */ 40 u32 g3dctl; 41 u32 gsckgctl; 42 u32 mbctl; 43 44 /* GCP */ 45 u32 ucgctl1; 46 u32 ucgctl3; 47 u32 rcgctl1; 48 u32 rcgctl2; 49 u32 rstctl; 50 u32 misccpctl; 51 52 /* GPM */ 53 u32 gfxpause; 54 u32 rpdeuhwtc; 55 u32 rpdeuc; 56 u32 ecobus; 57 u32 pwrdwnupctl; 58 u32 rp_down_timeout; 59 u32 rp_deucsw; 60 u32 rcubmabdtmr; 61 u32 rcedata; 62 u32 spare2gh; 63 64 /* Display 1 CZ domain */ 65 u32 gt_imr; 66 u32 gt_ier; 67 u32 pm_imr; 68 u32 pm_ier; 69 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; 70 71 /* GT SA CZ domain */ 72 u32 tilectl; 73 u32 gt_fifoctl; 74 u32 gtlc_wake_ctrl; 75 u32 gtlc_survive; 76 u32 pmwgicz; 77 78 /* Display 2 CZ domain */ 79 u32 gu_ctl0; 80 u32 gu_ctl1; 81 u32 pcbr; 82 u32 clock_gate_dis2; 83 }; 84 85 /* 86 * Save all Gunit registers that may be lost after a D3 and a subsequent 87 * S0i[R123] transition. The list of registers needing a save/restore is 88 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit 89 * registers in the following way: 90 * - Driver: saved/restored by the driver 91 * - Punit : saved/restored by the Punit firmware 92 * - No, w/o marking: no need to save/restore, since the register is R/O or 93 * used internally by the HW in a way that doesn't depend 94 * keeping the content across a suspend/resume. 95 * - Debug : used for debugging 96 * 97 * We save/restore all registers marked with 'Driver', with the following 98 * exceptions: 99 * - Registers out of use, including also registers marked with 'Debug'. 100 * These have no effect on the driver's operation, so we don't save/restore 101 * them to reduce the overhead. 102 * - Registers that are fully setup by an initialization function called from 103 * the resume path. For example many clock gating and RPS/RC6 registers. 104 * - Registers that provide the right functionality with their reset defaults. 105 * 106 * TODO: Except for registers that based on the above 3 criteria can be safely 107 * ignored, we save/restore all others, practically treating the HW context as 108 * a black-box for the driver. Further investigation is needed to reduce the 109 * saved/restored registers even further, by following the same 3 criteria. 110 */ 111 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *i915) 112 { 113 struct vlv_s0ix_state *s = i915->vlv_s0ix_state; 114 struct intel_uncore *uncore = &i915->uncore; 115 int i; 116 117 if (!s) 118 return; 119 120 /* GAM 0x4000-0x4770 */ 121 s->wr_watermark = intel_uncore_read(uncore, GEN7_WR_WATERMARK); 122 s->gfx_prio_ctrl = intel_uncore_read(uncore, GEN7_GFX_PRIO_CTRL); 123 s->arb_mode = intel_uncore_read(uncore, ARB_MODE); 124 s->gfx_pend_tlb0 = intel_uncore_read(uncore, GEN7_GFX_PEND_TLB0); 125 s->gfx_pend_tlb1 = intel_uncore_read(uncore, GEN7_GFX_PEND_TLB1); 126 127 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) 128 s->lra_limits[i] = intel_uncore_read(uncore, GEN7_LRA_LIMITS(i)); 129 130 s->media_max_req_count = intel_uncore_read(uncore, GEN7_MEDIA_MAX_REQ_COUNT); 131 s->gfx_max_req_count = intel_uncore_read(uncore, GEN7_GFX_MAX_REQ_COUNT); 132 133 s->render_hwsp = intel_uncore_read(uncore, RENDER_HWS_PGA_GEN7); 134 s->ecochk = intel_uncore_read(uncore, GAM_ECOCHK); 135 s->bsd_hwsp = intel_uncore_read(uncore, BSD_HWS_PGA_GEN7); 136 s->blt_hwsp = intel_uncore_read(uncore, BLT_HWS_PGA_GEN7); 137 138 s->tlb_rd_addr = intel_uncore_read(uncore, GEN7_TLB_RD_ADDR); 139 140 /* MBC 0x9024-0x91D0, 0x8500 */ 141 s->g3dctl = intel_uncore_read(uncore, VLV_G3DCTL); 142 s->gsckgctl = intel_uncore_read(uncore, VLV_GSCKGCTL); 143 s->mbctl = intel_uncore_read(uncore, GEN6_MBCTL); 144 145 /* GCP 0x9400-0x9424, 0x8100-0x810C */ 146 s->ucgctl1 = intel_uncore_read(uncore, GEN6_UCGCTL1); 147 s->ucgctl3 = intel_uncore_read(uncore, GEN6_UCGCTL3); 148 s->rcgctl1 = intel_uncore_read(uncore, GEN6_RCGCTL1); 149 s->rcgctl2 = intel_uncore_read(uncore, GEN6_RCGCTL2); 150 s->rstctl = intel_uncore_read(uncore, GEN6_RSTCTL); 151 s->misccpctl = intel_uncore_read(uncore, GEN7_MISCCPCTL); 152 153 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ 154 s->gfxpause = intel_uncore_read(uncore, GEN6_GFXPAUSE); 155 s->rpdeuhwtc = intel_uncore_read(uncore, GEN6_RPDEUHWTC); 156 s->rpdeuc = intel_uncore_read(uncore, GEN6_RPDEUC); 157 s->ecobus = intel_uncore_read(uncore, ECOBUS); 158 s->pwrdwnupctl = intel_uncore_read(uncore, VLV_PWRDWNUPCTL); 159 s->rp_down_timeout = intel_uncore_read(uncore, GEN6_RP_DOWN_TIMEOUT); 160 s->rp_deucsw = intel_uncore_read(uncore, GEN6_RPDEUCSW); 161 s->rcubmabdtmr = intel_uncore_read(uncore, GEN6_RCUBMABDTMR); 162 s->rcedata = intel_uncore_read(uncore, VLV_RCEDATA); 163 s->spare2gh = intel_uncore_read(uncore, VLV_SPAREG2H); 164 165 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ 166 s->gt_imr = intel_uncore_read(uncore, GTIMR); 167 s->gt_ier = intel_uncore_read(uncore, GTIER); 168 s->pm_imr = intel_uncore_read(uncore, GEN6_PMIMR); 169 s->pm_ier = intel_uncore_read(uncore, GEN6_PMIER); 170 171 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) 172 s->gt_scratch[i] = intel_uncore_read(uncore, GEN7_GT_SCRATCH(i)); 173 174 /* GT SA CZ domain, 0x100000-0x138124 */ 175 s->tilectl = intel_uncore_read(uncore, TILECTL); 176 s->gt_fifoctl = intel_uncore_read(uncore, GTFIFOCTL); 177 s->gtlc_wake_ctrl = intel_uncore_read(uncore, VLV_GTLC_WAKE_CTRL); 178 s->gtlc_survive = intel_uncore_read(uncore, VLV_GTLC_SURVIVABILITY_REG); 179 s->pmwgicz = intel_uncore_read(uncore, VLV_PMWGICZ); 180 181 /* Gunit-Display CZ domain, 0x182028-0x1821CF */ 182 s->gu_ctl0 = intel_uncore_read(uncore, VLV_GU_CTL0); 183 s->gu_ctl1 = intel_uncore_read(uncore, VLV_GU_CTL1); 184 s->pcbr = intel_uncore_read(uncore, VLV_PCBR); 185 s->clock_gate_dis2 = intel_uncore_read(uncore, VLV_GUNIT_CLOCK_GATE2); 186 187 /* 188 * Not saving any of: 189 * DFT, 0x9800-0x9EC0 190 * SARB, 0xB000-0xB1FC 191 * GAC, 0x5208-0x524C, 0x14000-0x14C000 192 * PCI CFG 193 */ 194 } 195 196 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *i915) 197 { 198 struct vlv_s0ix_state *s = i915->vlv_s0ix_state; 199 struct intel_uncore *uncore = &i915->uncore; 200 int i; 201 202 if (!s) 203 return; 204 205 /* GAM 0x4000-0x4770 */ 206 intel_uncore_write(uncore, GEN7_WR_WATERMARK, s->wr_watermark); 207 intel_uncore_write(uncore, GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl); 208 intel_uncore_write(uncore, ARB_MODE, s->arb_mode | (0xffff << 16)); 209 intel_uncore_write(uncore, GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0); 210 intel_uncore_write(uncore, GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1); 211 212 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) 213 intel_uncore_write(uncore, GEN7_LRA_LIMITS(i), s->lra_limits[i]); 214 215 intel_uncore_write(uncore, GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count); 216 intel_uncore_write(uncore, GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count); 217 218 intel_uncore_write(uncore, RENDER_HWS_PGA_GEN7, s->render_hwsp); 219 intel_uncore_write(uncore, GAM_ECOCHK, s->ecochk); 220 intel_uncore_write(uncore, BSD_HWS_PGA_GEN7, s->bsd_hwsp); 221 intel_uncore_write(uncore, BLT_HWS_PGA_GEN7, s->blt_hwsp); 222 223 intel_uncore_write(uncore, GEN7_TLB_RD_ADDR, s->tlb_rd_addr); 224 225 /* MBC 0x9024-0x91D0, 0x8500 */ 226 intel_uncore_write(uncore, VLV_G3DCTL, s->g3dctl); 227 intel_uncore_write(uncore, VLV_GSCKGCTL, s->gsckgctl); 228 intel_uncore_write(uncore, GEN6_MBCTL, s->mbctl); 229 230 /* GCP 0x9400-0x9424, 0x8100-0x810C */ 231 intel_uncore_write(uncore, GEN6_UCGCTL1, s->ucgctl1); 232 intel_uncore_write(uncore, GEN6_UCGCTL3, s->ucgctl3); 233 intel_uncore_write(uncore, GEN6_RCGCTL1, s->rcgctl1); 234 intel_uncore_write(uncore, GEN6_RCGCTL2, s->rcgctl2); 235 intel_uncore_write(uncore, GEN6_RSTCTL, s->rstctl); 236 intel_uncore_write(uncore, GEN7_MISCCPCTL, s->misccpctl); 237 238 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ 239 intel_uncore_write(uncore, GEN6_GFXPAUSE, s->gfxpause); 240 intel_uncore_write(uncore, GEN6_RPDEUHWTC, s->rpdeuhwtc); 241 intel_uncore_write(uncore, GEN6_RPDEUC, s->rpdeuc); 242 intel_uncore_write(uncore, ECOBUS, s->ecobus); 243 intel_uncore_write(uncore, VLV_PWRDWNUPCTL, s->pwrdwnupctl); 244 intel_uncore_write(uncore, GEN6_RP_DOWN_TIMEOUT, s->rp_down_timeout); 245 intel_uncore_write(uncore, GEN6_RPDEUCSW, s->rp_deucsw); 246 intel_uncore_write(uncore, GEN6_RCUBMABDTMR, s->rcubmabdtmr); 247 intel_uncore_write(uncore, VLV_RCEDATA, s->rcedata); 248 intel_uncore_write(uncore, VLV_SPAREG2H, s->spare2gh); 249 250 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ 251 intel_uncore_write(uncore, GTIMR, s->gt_imr); 252 intel_uncore_write(uncore, GTIER, s->gt_ier); 253 intel_uncore_write(uncore, GEN6_PMIMR, s->pm_imr); 254 intel_uncore_write(uncore, GEN6_PMIER, s->pm_ier); 255 256 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) 257 intel_uncore_write(uncore, GEN7_GT_SCRATCH(i), s->gt_scratch[i]); 258 259 /* GT SA CZ domain, 0x100000-0x138124 */ 260 intel_uncore_write(uncore, TILECTL, s->tilectl); 261 intel_uncore_write(uncore, GTFIFOCTL, s->gt_fifoctl); 262 /* 263 * Preserve the GT allow wake and GFX force clock bit, they are not 264 * be restored, as they are used to control the s0ix suspend/resume 265 * sequence by the caller. 266 */ 267 intel_uncore_rmw(uncore, VLV_GTLC_WAKE_CTRL, ~VLV_GTLC_ALLOWWAKEREQ, 268 s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ); 269 270 intel_uncore_rmw(uncore, VLV_GTLC_SURVIVABILITY_REG, ~VLV_GFX_CLK_FORCE_ON_BIT, 271 s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT); 272 273 intel_uncore_write(uncore, VLV_PMWGICZ, s->pmwgicz); 274 275 /* Gunit-Display CZ domain, 0x182028-0x1821CF */ 276 intel_uncore_write(uncore, VLV_GU_CTL0, s->gu_ctl0); 277 intel_uncore_write(uncore, VLV_GU_CTL1, s->gu_ctl1); 278 intel_uncore_write(uncore, VLV_PCBR, s->pcbr); 279 intel_uncore_write(uncore, VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2); 280 } 281 282 static int vlv_wait_for_pw_status(struct drm_i915_private *i915, 283 u32 mask, u32 val) 284 { 285 i915_reg_t reg = VLV_GTLC_PW_STATUS; 286 u32 reg_value; 287 int ret; 288 289 /* The HW does not like us polling for PW_STATUS frequently, so 290 * use the sleeping loop rather than risk the busy spin within 291 * intel_wait_for_register(). 292 * 293 * Transitioning between RC6 states should be at most 2ms (see 294 * valleyview_enable_rps) so use a 3ms timeout. 295 */ 296 ret = wait_for(((reg_value = 297 intel_uncore_read_notrace(&i915->uncore, reg)) & mask) 298 == val, 3); 299 300 /* just trace the final value */ 301 trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true); 302 303 return ret; 304 } 305 306 static int vlv_force_gfx_clock(struct drm_i915_private *i915, bool force_on) 307 { 308 struct intel_uncore *uncore = &i915->uncore; 309 int err; 310 311 intel_uncore_rmw(uncore, VLV_GTLC_SURVIVABILITY_REG, VLV_GFX_CLK_FORCE_ON_BIT, 312 force_on ? VLV_GFX_CLK_FORCE_ON_BIT : 0); 313 314 if (!force_on) 315 return 0; 316 317 err = intel_wait_for_register(uncore, 318 VLV_GTLC_SURVIVABILITY_REG, 319 VLV_GFX_CLK_STATUS_BIT, 320 VLV_GFX_CLK_STATUS_BIT, 321 20); 322 if (err) 323 drm_err(&i915->drm, 324 "timeout waiting for GFX clock force-on (%08x)\n", 325 intel_uncore_read(uncore, VLV_GTLC_SURVIVABILITY_REG)); 326 327 return err; 328 } 329 330 static int vlv_allow_gt_wake(struct drm_i915_private *i915, bool allow) 331 { 332 struct intel_uncore *uncore = &i915->uncore; 333 u32 mask; 334 u32 val; 335 int err; 336 337 intel_uncore_rmw(uncore, VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ, 338 allow ? VLV_GTLC_ALLOWWAKEREQ : 0); 339 intel_uncore_posting_read(uncore, VLV_GTLC_WAKE_CTRL); 340 341 mask = VLV_GTLC_ALLOWWAKEACK; 342 val = allow ? mask : 0; 343 344 err = vlv_wait_for_pw_status(i915, mask, val); 345 if (err) 346 drm_err(&i915->drm, "timeout disabling GT waking\n"); 347 348 return err; 349 } 350 351 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv, 352 bool wait_for_on) 353 { 354 u32 mask; 355 u32 val; 356 357 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK; 358 val = wait_for_on ? mask : 0; 359 360 /* 361 * RC6 transitioning can be delayed up to 2 msec (see 362 * valleyview_enable_rps), use 3 msec for safety. 363 * 364 * This can fail to turn off the rc6 if the GPU is stuck after a failed 365 * reset and we are trying to force the machine to sleep. 366 */ 367 if (vlv_wait_for_pw_status(dev_priv, mask, val)) 368 drm_dbg(&dev_priv->drm, 369 "timeout waiting for GT wells to go %s\n", 370 str_on_off(wait_for_on)); 371 } 372 373 static void vlv_check_no_gt_access(struct drm_i915_private *i915) 374 { 375 struct intel_uncore *uncore = &i915->uncore; 376 377 if (!(intel_uncore_read(uncore, VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR)) 378 return; 379 380 drm_dbg(&i915->drm, "GT register access while GT waking disabled\n"); 381 intel_uncore_write(uncore, VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR); 382 } 383 384 int vlv_suspend_complete(struct drm_i915_private *dev_priv) 385 { 386 u32 mask; 387 int err; 388 389 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) 390 return 0; 391 392 /* 393 * Bspec defines the following GT well on flags as debug only, so 394 * don't treat them as hard failures. 395 */ 396 vlv_wait_for_gt_wells(dev_priv, false); 397 398 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS; 399 drm_WARN_ON(&dev_priv->drm, 400 (intel_uncore_read(&dev_priv->uncore, VLV_GTLC_WAKE_CTRL) & mask) != mask); 401 402 vlv_check_no_gt_access(dev_priv); 403 404 err = vlv_force_gfx_clock(dev_priv, true); 405 if (err) 406 goto err1; 407 408 err = vlv_allow_gt_wake(dev_priv, false); 409 if (err) 410 goto err2; 411 412 vlv_save_gunit_s0ix_state(dev_priv); 413 414 err = vlv_force_gfx_clock(dev_priv, false); 415 if (err) 416 goto err2; 417 418 return 0; 419 420 err2: 421 /* For safety always re-enable waking and disable gfx clock forcing */ 422 vlv_allow_gt_wake(dev_priv, true); 423 err1: 424 vlv_force_gfx_clock(dev_priv, false); 425 426 return err; 427 } 428 429 int vlv_resume_prepare(struct drm_i915_private *dev_priv, bool rpm_resume) 430 { 431 int err; 432 int ret; 433 434 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) 435 return 0; 436 437 /* 438 * If any of the steps fail just try to continue, that's the best we 439 * can do at this point. Return the first error code (which will also 440 * leave RPM permanently disabled). 441 */ 442 ret = vlv_force_gfx_clock(dev_priv, true); 443 444 vlv_restore_gunit_s0ix_state(dev_priv); 445 446 err = vlv_allow_gt_wake(dev_priv, true); 447 if (!ret) 448 ret = err; 449 450 err = vlv_force_gfx_clock(dev_priv, false); 451 if (!ret) 452 ret = err; 453 454 vlv_check_no_gt_access(dev_priv); 455 456 if (rpm_resume) 457 intel_clock_gating_init(&dev_priv->drm); 458 459 return ret; 460 } 461 462 int vlv_suspend_init(struct drm_i915_private *i915) 463 { 464 if (!IS_VALLEYVIEW(i915)) 465 return 0; 466 467 /* we write all the values in the struct, so no need to zero it out */ 468 i915->vlv_s0ix_state = kmalloc_obj(*i915->vlv_s0ix_state); 469 if (!i915->vlv_s0ix_state) 470 return -ENOMEM; 471 472 return 0; 473 } 474 475 void vlv_suspend_cleanup(struct drm_i915_private *i915) 476 { 477 if (!i915->vlv_s0ix_state) 478 return; 479 480 kfree(i915->vlv_s0ix_state); 481 i915->vlv_s0ix_state = NULL; 482 } 483