1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #include <linux/pci.h> 7 #include <linux/pnp.h> 8 #include <linux/vgaarb.h> 9 10 #include <drm/drm_managed.h> 11 #include <drm/intel/i915_drm.h> 12 13 #include "../display/intel_display_core.h" /* FIXME */ 14 15 #include "i915_drv.h" 16 #include "intel_gmch.h" 17 #include "intel_pci_config.h" 18 19 static void intel_gmch_bridge_release(struct drm_device *dev, void *bridge) 20 { 21 pci_dev_put(bridge); 22 } 23 24 int intel_gmch_bridge_setup(struct drm_i915_private *i915) 25 { 26 int domain = pci_domain_nr(to_pci_dev(i915->drm.dev)->bus); 27 28 i915->gmch.pdev = pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0)); 29 if (!i915->gmch.pdev) { 30 drm_err(&i915->drm, "bridge device not found\n"); 31 return -EIO; 32 } 33 34 return drmm_add_action_or_reset(&i915->drm, intel_gmch_bridge_release, 35 i915->gmch.pdev); 36 } 37 38 static int mchbar_reg(struct drm_i915_private *i915) 39 { 40 return GRAPHICS_VER(i915) >= 4 ? MCHBAR_I965 : MCHBAR_I915; 41 } 42 43 /* Allocate space for the MCH regs if needed, return nonzero on error */ 44 static int 45 intel_alloc_mchbar_resource(struct drm_i915_private *i915) 46 { 47 u32 temp_lo, temp_hi = 0; 48 u64 mchbar_addr; 49 int ret; 50 51 if (GRAPHICS_VER(i915) >= 4) 52 pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915) + 4, &temp_hi); 53 pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915), &temp_lo); 54 mchbar_addr = ((u64)temp_hi << 32) | temp_lo; 55 56 /* If ACPI doesn't have it, assume we need to allocate it ourselves */ 57 if (IS_ENABLED(CONFIG_PNP) && mchbar_addr && 58 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) 59 return 0; 60 61 /* Get some space for it */ 62 i915->gmch.mch_res.name = "i915 MCHBAR"; 63 i915->gmch.mch_res.flags = IORESOURCE_MEM; 64 ret = pci_bus_alloc_resource(i915->gmch.pdev->bus, 65 &i915->gmch.mch_res, 66 MCHBAR_SIZE, MCHBAR_SIZE, 67 PCIBIOS_MIN_MEM, 68 0, pcibios_align_resource, 69 i915->gmch.pdev); 70 if (ret) { 71 drm_dbg(&i915->drm, "failed bus alloc: %d\n", ret); 72 i915->gmch.mch_res.start = 0; 73 return ret; 74 } 75 76 if (GRAPHICS_VER(i915) >= 4) 77 pci_write_config_dword(i915->gmch.pdev, mchbar_reg(i915) + 4, 78 upper_32_bits(i915->gmch.mch_res.start)); 79 80 pci_write_config_dword(i915->gmch.pdev, mchbar_reg(i915), 81 lower_32_bits(i915->gmch.mch_res.start)); 82 return 0; 83 } 84 85 /* Setup MCHBAR if possible, return true if we should disable it again */ 86 void intel_gmch_bar_setup(struct drm_i915_private *i915) 87 { 88 u32 temp; 89 bool enabled; 90 91 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) 92 return; 93 94 i915->gmch.mchbar_need_disable = false; 95 96 if (IS_I915G(i915) || IS_I915GM(i915)) { 97 pci_read_config_dword(i915->gmch.pdev, DEVEN, &temp); 98 enabled = !!(temp & DEVEN_MCHBAR_EN); 99 } else { 100 pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915), &temp); 101 enabled = temp & 1; 102 } 103 104 /* If it's already enabled, don't have to do anything */ 105 if (enabled) 106 return; 107 108 if (intel_alloc_mchbar_resource(i915)) 109 return; 110 111 i915->gmch.mchbar_need_disable = true; 112 113 /* Space is allocated or reserved, so enable it. */ 114 if (IS_I915G(i915) || IS_I915GM(i915)) { 115 pci_write_config_dword(i915->gmch.pdev, DEVEN, 116 temp | DEVEN_MCHBAR_EN); 117 } else { 118 pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915), &temp); 119 pci_write_config_dword(i915->gmch.pdev, mchbar_reg(i915), temp | 1); 120 } 121 } 122 123 void intel_gmch_bar_teardown(struct drm_i915_private *i915) 124 { 125 if (i915->gmch.mchbar_need_disable) { 126 if (IS_I915G(i915) || IS_I915GM(i915)) { 127 u32 deven_val; 128 129 pci_read_config_dword(i915->gmch.pdev, DEVEN, 130 &deven_val); 131 deven_val &= ~DEVEN_MCHBAR_EN; 132 pci_write_config_dword(i915->gmch.pdev, DEVEN, 133 deven_val); 134 } else { 135 u32 mchbar_val; 136 137 pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915), 138 &mchbar_val); 139 mchbar_val &= ~1; 140 pci_write_config_dword(i915->gmch.pdev, mchbar_reg(i915), 141 mchbar_val); 142 } 143 } 144 145 if (i915->gmch.mch_res.start) 146 release_resource(&i915->gmch.mch_res); 147 } 148 149 int intel_gmch_vga_set_state(struct drm_i915_private *i915, bool enable_decode) 150 { 151 unsigned int reg = DISPLAY_VER(i915) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; 152 u16 gmch_ctrl; 153 154 if (pci_read_config_word(i915->gmch.pdev, reg, &gmch_ctrl)) { 155 drm_err(&i915->drm, "failed to read control word\n"); 156 return -EIO; 157 } 158 159 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !enable_decode) 160 return 0; 161 162 if (enable_decode) 163 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; 164 else 165 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; 166 167 if (pci_write_config_word(i915->gmch.pdev, reg, gmch_ctrl)) { 168 drm_err(&i915->drm, "failed to write control word\n"); 169 return -EIO; 170 } 171 172 return 0; 173 } 174 175 unsigned int intel_gmch_vga_set_decode(struct pci_dev *pdev, bool enable_decode) 176 { 177 struct drm_i915_private *i915 = pdev_to_i915(pdev); 178 179 intel_gmch_vga_set_state(i915, enable_decode); 180 181 if (enable_decode) 182 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | 183 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 184 else 185 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 186 } 187