1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #include <linux/pci.h> 7 #include <linux/pnp.h> 8 #include <linux/vgaarb.h> 9 10 #include <drm/drm_managed.h> 11 #include <drm/drm_print.h> 12 #include <drm/intel/i915_drm.h> 13 14 #include "../display/intel_display_core.h" /* FIXME */ 15 16 #include "i915_drv.h" 17 #include "intel_gmch.h" 18 #include "intel_pci_config.h" 19 20 static void intel_gmch_bridge_release(struct drm_device *dev, void *bridge) 21 { 22 pci_dev_put(bridge); 23 } 24 25 int intel_gmch_bridge_setup(struct drm_i915_private *i915) 26 { 27 int domain = pci_domain_nr(to_pci_dev(i915->drm.dev)->bus); 28 29 i915->gmch.pdev = pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0)); 30 if (!i915->gmch.pdev) { 31 drm_err(&i915->drm, "bridge device not found\n"); 32 return -EIO; 33 } 34 35 return drmm_add_action_or_reset(&i915->drm, intel_gmch_bridge_release, 36 i915->gmch.pdev); 37 } 38 39 static int mchbar_reg(struct drm_i915_private *i915) 40 { 41 return GRAPHICS_VER(i915) >= 4 ? MCHBAR_I965 : MCHBAR_I915; 42 } 43 44 /* Allocate space for the MCH regs if needed, return nonzero on error */ 45 static int 46 intel_alloc_mchbar_resource(struct drm_i915_private *i915) 47 { 48 u32 temp_lo, temp_hi = 0; 49 u64 mchbar_addr; 50 int ret; 51 52 if (GRAPHICS_VER(i915) >= 4) 53 pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915) + 4, &temp_hi); 54 pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915), &temp_lo); 55 mchbar_addr = ((u64)temp_hi << 32) | temp_lo; 56 57 /* If ACPI doesn't have it, assume we need to allocate it ourselves */ 58 if (IS_ENABLED(CONFIG_PNP) && mchbar_addr && 59 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) 60 return 0; 61 62 /* Get some space for it */ 63 i915->gmch.mch_res.name = "i915 MCHBAR"; 64 i915->gmch.mch_res.flags = IORESOURCE_MEM; 65 ret = pci_bus_alloc_resource(i915->gmch.pdev->bus, 66 &i915->gmch.mch_res, 67 MCHBAR_SIZE, MCHBAR_SIZE, 68 PCIBIOS_MIN_MEM, 69 0, pcibios_align_resource, 70 i915->gmch.pdev); 71 if (ret) { 72 drm_dbg(&i915->drm, "failed bus alloc: %d\n", ret); 73 i915->gmch.mch_res.start = 0; 74 return ret; 75 } 76 77 if (GRAPHICS_VER(i915) >= 4) 78 pci_write_config_dword(i915->gmch.pdev, mchbar_reg(i915) + 4, 79 upper_32_bits(i915->gmch.mch_res.start)); 80 81 pci_write_config_dword(i915->gmch.pdev, mchbar_reg(i915), 82 lower_32_bits(i915->gmch.mch_res.start)); 83 return 0; 84 } 85 86 /* Setup MCHBAR if possible, return true if we should disable it again */ 87 void intel_gmch_bar_setup(struct drm_i915_private *i915) 88 { 89 u32 temp; 90 bool enabled; 91 92 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) 93 return; 94 95 i915->gmch.mchbar_need_disable = false; 96 97 if (IS_I915G(i915) || IS_I915GM(i915)) { 98 pci_read_config_dword(i915->gmch.pdev, DEVEN, &temp); 99 enabled = !!(temp & DEVEN_MCHBAR_EN); 100 } else { 101 pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915), &temp); 102 enabled = temp & 1; 103 } 104 105 /* If it's already enabled, don't have to do anything */ 106 if (enabled) 107 return; 108 109 if (intel_alloc_mchbar_resource(i915)) 110 return; 111 112 i915->gmch.mchbar_need_disable = true; 113 114 /* Space is allocated or reserved, so enable it. */ 115 if (IS_I915G(i915) || IS_I915GM(i915)) { 116 pci_write_config_dword(i915->gmch.pdev, DEVEN, 117 temp | DEVEN_MCHBAR_EN); 118 } else { 119 pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915), &temp); 120 pci_write_config_dword(i915->gmch.pdev, mchbar_reg(i915), temp | 1); 121 } 122 } 123 124 void intel_gmch_bar_teardown(struct drm_i915_private *i915) 125 { 126 if (i915->gmch.mchbar_need_disable) { 127 if (IS_I915G(i915) || IS_I915GM(i915)) { 128 u32 deven_val; 129 130 pci_read_config_dword(i915->gmch.pdev, DEVEN, 131 &deven_val); 132 deven_val &= ~DEVEN_MCHBAR_EN; 133 pci_write_config_dword(i915->gmch.pdev, DEVEN, 134 deven_val); 135 } else { 136 u32 mchbar_val; 137 138 pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915), 139 &mchbar_val); 140 mchbar_val &= ~1; 141 pci_write_config_dword(i915->gmch.pdev, mchbar_reg(i915), 142 mchbar_val); 143 } 144 } 145 146 if (i915->gmch.mch_res.start) 147 release_resource(&i915->gmch.mch_res); 148 } 149 150 int intel_gmch_vga_set_state(struct drm_i915_private *i915, bool enable_decode) 151 { 152 struct intel_display *display = i915->display; 153 unsigned int reg = DISPLAY_VER(display) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; 154 u16 gmch_ctrl; 155 156 if (pci_read_config_word(i915->gmch.pdev, reg, &gmch_ctrl)) { 157 drm_err(&i915->drm, "failed to read control word\n"); 158 return -EIO; 159 } 160 161 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !enable_decode) 162 return 0; 163 164 if (enable_decode) 165 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; 166 else 167 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; 168 169 if (pci_write_config_word(i915->gmch.pdev, reg, gmch_ctrl)) { 170 drm_err(&i915->drm, "failed to write control word\n"); 171 return -EIO; 172 } 173 174 return 0; 175 } 176 177 unsigned int intel_gmch_vga_set_decode(struct pci_dev *pdev, bool enable_decode) 178 { 179 struct drm_i915_private *i915 = pdev_to_i915(pdev); 180 181 intel_gmch_vga_set_state(i915, enable_decode); 182 183 if (enable_decode) 184 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | 185 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 186 else 187 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 188 } 189