1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #include <linux/pci.h> 7 #include <linux/pnp.h> 8 #include <linux/vgaarb.h> 9 10 #include <drm/drm_managed.h> 11 #include <drm/i915_drm.h> 12 13 #include "i915_drv.h" 14 #include "intel_gmch.h" 15 #include "intel_pci_config.h" 16 17 static void intel_gmch_bridge_release(struct drm_device *dev, void *bridge) 18 { 19 pci_dev_put(bridge); 20 } 21 22 int intel_gmch_bridge_setup(struct drm_i915_private *i915) 23 { 24 int domain = pci_domain_nr(to_pci_dev(i915->drm.dev)->bus); 25 26 i915->gmch.pdev = pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0)); 27 if (!i915->gmch.pdev) { 28 drm_err(&i915->drm, "bridge device not found\n"); 29 return -EIO; 30 } 31 32 return drmm_add_action_or_reset(&i915->drm, intel_gmch_bridge_release, 33 i915->gmch.pdev); 34 } 35 36 /* Allocate space for the MCH regs if needed, return nonzero on error */ 37 static int 38 intel_alloc_mchbar_resource(struct drm_i915_private *i915) 39 { 40 int reg = GRAPHICS_VER(i915) >= 4 ? MCHBAR_I965 : MCHBAR_I915; 41 u32 temp_lo, temp_hi = 0; 42 u64 mchbar_addr; 43 int ret; 44 45 if (GRAPHICS_VER(i915) >= 4) 46 pci_read_config_dword(i915->gmch.pdev, reg + 4, &temp_hi); 47 pci_read_config_dword(i915->gmch.pdev, reg, &temp_lo); 48 mchbar_addr = ((u64)temp_hi << 32) | temp_lo; 49 50 /* If ACPI doesn't have it, assume we need to allocate it ourselves */ 51 if (IS_ENABLED(CONFIG_PNP) && mchbar_addr && 52 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) 53 return 0; 54 55 /* Get some space for it */ 56 i915->gmch.mch_res.name = "i915 MCHBAR"; 57 i915->gmch.mch_res.flags = IORESOURCE_MEM; 58 ret = pci_bus_alloc_resource(i915->gmch.pdev->bus, 59 &i915->gmch.mch_res, 60 MCHBAR_SIZE, MCHBAR_SIZE, 61 PCIBIOS_MIN_MEM, 62 0, pcibios_align_resource, 63 i915->gmch.pdev); 64 if (ret) { 65 drm_dbg(&i915->drm, "failed bus alloc: %d\n", ret); 66 i915->gmch.mch_res.start = 0; 67 return ret; 68 } 69 70 if (GRAPHICS_VER(i915) >= 4) 71 pci_write_config_dword(i915->gmch.pdev, reg + 4, 72 upper_32_bits(i915->gmch.mch_res.start)); 73 74 pci_write_config_dword(i915->gmch.pdev, reg, 75 lower_32_bits(i915->gmch.mch_res.start)); 76 return 0; 77 } 78 79 /* Setup MCHBAR if possible, return true if we should disable it again */ 80 void intel_gmch_bar_setup(struct drm_i915_private *i915) 81 { 82 int mchbar_reg = GRAPHICS_VER(i915) >= 4 ? MCHBAR_I965 : MCHBAR_I915; 83 u32 temp; 84 bool enabled; 85 86 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) 87 return; 88 89 i915->gmch.mchbar_need_disable = false; 90 91 if (IS_I915G(i915) || IS_I915GM(i915)) { 92 pci_read_config_dword(i915->gmch.pdev, DEVEN, &temp); 93 enabled = !!(temp & DEVEN_MCHBAR_EN); 94 } else { 95 pci_read_config_dword(i915->gmch.pdev, mchbar_reg, &temp); 96 enabled = temp & 1; 97 } 98 99 /* If it's already enabled, don't have to do anything */ 100 if (enabled) 101 return; 102 103 if (intel_alloc_mchbar_resource(i915)) 104 return; 105 106 i915->gmch.mchbar_need_disable = true; 107 108 /* Space is allocated or reserved, so enable it. */ 109 if (IS_I915G(i915) || IS_I915GM(i915)) { 110 pci_write_config_dword(i915->gmch.pdev, DEVEN, 111 temp | DEVEN_MCHBAR_EN); 112 } else { 113 pci_read_config_dword(i915->gmch.pdev, mchbar_reg, &temp); 114 pci_write_config_dword(i915->gmch.pdev, mchbar_reg, temp | 1); 115 } 116 } 117 118 void intel_gmch_bar_teardown(struct drm_i915_private *i915) 119 { 120 int mchbar_reg = GRAPHICS_VER(i915) >= 4 ? MCHBAR_I965 : MCHBAR_I915; 121 122 if (i915->gmch.mchbar_need_disable) { 123 if (IS_I915G(i915) || IS_I915GM(i915)) { 124 u32 deven_val; 125 126 pci_read_config_dword(i915->gmch.pdev, DEVEN, 127 &deven_val); 128 deven_val &= ~DEVEN_MCHBAR_EN; 129 pci_write_config_dword(i915->gmch.pdev, DEVEN, 130 deven_val); 131 } else { 132 u32 mchbar_val; 133 134 pci_read_config_dword(i915->gmch.pdev, mchbar_reg, 135 &mchbar_val); 136 mchbar_val &= ~1; 137 pci_write_config_dword(i915->gmch.pdev, mchbar_reg, 138 mchbar_val); 139 } 140 } 141 142 if (i915->gmch.mch_res.start) 143 release_resource(&i915->gmch.mch_res); 144 } 145 146 int intel_gmch_vga_set_state(struct drm_i915_private *i915, bool enable_decode) 147 { 148 unsigned int reg = DISPLAY_VER(i915) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; 149 u16 gmch_ctrl; 150 151 if (pci_read_config_word(i915->gmch.pdev, reg, &gmch_ctrl)) { 152 drm_err(&i915->drm, "failed to read control word\n"); 153 return -EIO; 154 } 155 156 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !enable_decode) 157 return 0; 158 159 if (enable_decode) 160 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; 161 else 162 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; 163 164 if (pci_write_config_word(i915->gmch.pdev, reg, gmch_ctrl)) { 165 drm_err(&i915->drm, "failed to write control word\n"); 166 return -EIO; 167 } 168 169 return 0; 170 } 171 172 unsigned int intel_gmch_vga_set_decode(struct pci_dev *pdev, bool enable_decode) 173 { 174 struct drm_i915_private *i915 = pdev_to_i915(pdev); 175 176 intel_gmch_vga_set_state(i915, enable_decode); 177 178 if (enable_decode) 179 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | 180 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 181 else 182 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 183 } 184