1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright(c) 2020 Intel Corporation. 4 */ 5 6 #include <linux/component.h> 7 8 #include <drm/i915_pxp_tee_interface.h> 9 #include <drm/i915_component.h> 10 11 #include "gem/i915_gem_lmem.h" 12 13 #include "i915_drv.h" 14 #include "gt/intel_gt.h" 15 16 #include "intel_pxp.h" 17 #include "intel_pxp_cmd_interface_42.h" 18 #include "intel_pxp_huc.h" 19 #include "intel_pxp_session.h" 20 #include "intel_pxp_tee.h" 21 #include "intel_pxp_types.h" 22 23 #define PXP_TRANSPORT_TIMEOUT_MS 5000 /* 5 sec */ 24 25 static bool 26 is_fw_err_platform_config(u32 type) 27 { 28 switch (type) { 29 case PXP_STATUS_ERROR_API_VERSION: 30 case PXP_STATUS_PLATFCONFIG_KF1_NOVERIF: 31 case PXP_STATUS_PLATFCONFIG_KF1_BAD: 32 return true; 33 default: 34 break; 35 } 36 return false; 37 } 38 39 static const char * 40 fw_err_to_string(u32 type) 41 { 42 switch (type) { 43 case PXP_STATUS_ERROR_API_VERSION: 44 return "ERR_API_VERSION"; 45 case PXP_STATUS_NOT_READY: 46 return "ERR_NOT_READY"; 47 case PXP_STATUS_PLATFCONFIG_KF1_NOVERIF: 48 case PXP_STATUS_PLATFCONFIG_KF1_BAD: 49 return "ERR_PLATFORM_CONFIG"; 50 default: 51 break; 52 } 53 return NULL; 54 } 55 56 static int intel_pxp_tee_io_message(struct intel_pxp *pxp, 57 void *msg_in, u32 msg_in_size, 58 void *msg_out, u32 msg_out_max_size, 59 u32 *msg_out_rcv_size) 60 { 61 struct drm_i915_private *i915 = pxp->ctrl_gt->i915; 62 struct i915_pxp_component *pxp_component = pxp->pxp_component; 63 int ret = 0; 64 65 mutex_lock(&pxp->tee_mutex); 66 67 /* 68 * The binding of the component is asynchronous from i915 probe, so we 69 * can't be sure it has happened. 70 */ 71 if (!pxp_component) { 72 ret = -ENODEV; 73 goto unlock; 74 } 75 76 ret = pxp_component->ops->send(pxp_component->tee_dev, msg_in, msg_in_size, 77 PXP_TRANSPORT_TIMEOUT_MS); 78 if (ret) { 79 drm_err(&i915->drm, "Failed to send PXP TEE message\n"); 80 goto unlock; 81 } 82 83 ret = pxp_component->ops->recv(pxp_component->tee_dev, msg_out, msg_out_max_size, 84 PXP_TRANSPORT_TIMEOUT_MS); 85 if (ret < 0) { 86 drm_err(&i915->drm, "Failed to receive PXP TEE message\n"); 87 goto unlock; 88 } 89 90 if (ret > msg_out_max_size) { 91 drm_err(&i915->drm, 92 "Failed to receive PXP TEE message due to unexpected output size\n"); 93 ret = -ENOSPC; 94 goto unlock; 95 } 96 97 if (msg_out_rcv_size) 98 *msg_out_rcv_size = ret; 99 100 ret = 0; 101 unlock: 102 mutex_unlock(&pxp->tee_mutex); 103 return ret; 104 } 105 106 int intel_pxp_tee_stream_message(struct intel_pxp *pxp, 107 u8 client_id, u32 fence_id, 108 void *msg_in, size_t msg_in_len, 109 void *msg_out, size_t msg_out_len) 110 { 111 /* TODO: for bigger objects we need to use a sg of 4k pages */ 112 const size_t max_msg_size = PAGE_SIZE; 113 struct drm_i915_private *i915 = pxp->ctrl_gt->i915; 114 struct i915_pxp_component *pxp_component = pxp->pxp_component; 115 unsigned int offset = 0; 116 struct scatterlist *sg; 117 int ret; 118 119 if (msg_in_len > max_msg_size || msg_out_len > max_msg_size) 120 return -ENOSPC; 121 122 mutex_lock(&pxp->tee_mutex); 123 124 if (unlikely(!pxp_component || !pxp_component->ops->gsc_command)) { 125 ret = -ENODEV; 126 goto unlock; 127 } 128 129 GEM_BUG_ON(!pxp->stream_cmd.obj); 130 131 sg = i915_gem_object_get_sg_dma(pxp->stream_cmd.obj, 0, &offset); 132 133 memcpy(pxp->stream_cmd.vaddr, msg_in, msg_in_len); 134 135 ret = pxp_component->ops->gsc_command(pxp_component->tee_dev, client_id, 136 fence_id, sg, msg_in_len, sg); 137 if (ret < 0) 138 drm_err(&i915->drm, "Failed to send PXP TEE gsc command\n"); 139 else 140 memcpy(msg_out, pxp->stream_cmd.vaddr, msg_out_len); 141 142 unlock: 143 mutex_unlock(&pxp->tee_mutex); 144 return ret; 145 } 146 147 /** 148 * i915_pxp_tee_component_bind - bind function to pass the function pointers to pxp_tee 149 * @i915_kdev: pointer to i915 kernel device 150 * @tee_kdev: pointer to tee kernel device 151 * @data: pointer to pxp_tee_master containing the function pointers 152 * 153 * This bind function is called during the system boot or resume from system sleep. 154 * 155 * Return: return 0 if successful. 156 */ 157 static int i915_pxp_tee_component_bind(struct device *i915_kdev, 158 struct device *tee_kdev, void *data) 159 { 160 struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); 161 struct intel_pxp *pxp = i915->pxp; 162 struct intel_uc *uc = &pxp->ctrl_gt->uc; 163 intel_wakeref_t wakeref; 164 int ret = 0; 165 166 if (!HAS_HECI_PXP(i915)) { 167 pxp->dev_link = device_link_add(i915_kdev, tee_kdev, DL_FLAG_STATELESS); 168 if (drm_WARN_ON(&i915->drm, !pxp->dev_link)) 169 return -ENODEV; 170 } 171 172 mutex_lock(&pxp->tee_mutex); 173 pxp->pxp_component = data; 174 pxp->pxp_component->tee_dev = tee_kdev; 175 mutex_unlock(&pxp->tee_mutex); 176 177 if (intel_uc_uses_huc(uc) && intel_huc_is_loaded_by_gsc(&uc->huc)) { 178 with_intel_runtime_pm(&i915->runtime_pm, wakeref) { 179 /* load huc via pxp */ 180 ret = intel_huc_fw_load_and_auth_via_gsc(&uc->huc); 181 if (ret < 0) 182 drm_err(&i915->drm, "failed to load huc via gsc %d\n", ret); 183 } 184 } 185 186 /* if we are suspended, the HW will be re-initialized on resume */ 187 wakeref = intel_runtime_pm_get_if_in_use(&i915->runtime_pm); 188 if (!wakeref) 189 return 0; 190 191 /* the component is required to fully start the PXP HW */ 192 if (intel_pxp_is_enabled(pxp)) 193 intel_pxp_init_hw(pxp); 194 195 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 196 197 return ret; 198 } 199 200 static void i915_pxp_tee_component_unbind(struct device *i915_kdev, 201 struct device *tee_kdev, void *data) 202 { 203 struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); 204 struct intel_pxp *pxp = i915->pxp; 205 intel_wakeref_t wakeref; 206 207 if (intel_pxp_is_enabled(pxp)) 208 with_intel_runtime_pm_if_in_use(&i915->runtime_pm, wakeref) 209 intel_pxp_fini_hw(pxp); 210 211 mutex_lock(&pxp->tee_mutex); 212 pxp->pxp_component = NULL; 213 mutex_unlock(&pxp->tee_mutex); 214 215 if (pxp->dev_link) { 216 device_link_del(pxp->dev_link); 217 pxp->dev_link = NULL; 218 } 219 } 220 221 static const struct component_ops i915_pxp_tee_component_ops = { 222 .bind = i915_pxp_tee_component_bind, 223 .unbind = i915_pxp_tee_component_unbind, 224 }; 225 226 static int alloc_streaming_command(struct intel_pxp *pxp) 227 { 228 struct drm_i915_private *i915 = pxp->ctrl_gt->i915; 229 struct drm_i915_gem_object *obj = NULL; 230 void *cmd; 231 int err; 232 233 pxp->stream_cmd.obj = NULL; 234 pxp->stream_cmd.vaddr = NULL; 235 236 if (!IS_DGFX(i915)) 237 return 0; 238 239 /* allocate lmem object of one page for PXP command memory and store it */ 240 obj = i915_gem_object_create_lmem(i915, PAGE_SIZE, I915_BO_ALLOC_CONTIGUOUS); 241 if (IS_ERR(obj)) { 242 drm_err(&i915->drm, "Failed to allocate pxp streaming command!\n"); 243 return PTR_ERR(obj); 244 } 245 246 err = i915_gem_object_pin_pages_unlocked(obj); 247 if (err) { 248 drm_err(&i915->drm, "Failed to pin gsc message page!\n"); 249 goto out_put; 250 } 251 252 /* map the lmem into the virtual memory pointer */ 253 cmd = i915_gem_object_pin_map_unlocked(obj, 254 intel_gt_coherent_map_type(pxp->ctrl_gt, 255 obj, true)); 256 if (IS_ERR(cmd)) { 257 drm_err(&i915->drm, "Failed to map gsc message page!\n"); 258 err = PTR_ERR(cmd); 259 goto out_unpin; 260 } 261 262 memset(cmd, 0, obj->base.size); 263 264 pxp->stream_cmd.obj = obj; 265 pxp->stream_cmd.vaddr = cmd; 266 267 return 0; 268 269 out_unpin: 270 i915_gem_object_unpin_pages(obj); 271 out_put: 272 i915_gem_object_put(obj); 273 return err; 274 } 275 276 static void free_streaming_command(struct intel_pxp *pxp) 277 { 278 struct drm_i915_gem_object *obj = fetch_and_zero(&pxp->stream_cmd.obj); 279 280 if (!obj) 281 return; 282 283 i915_gem_object_unpin_map(obj); 284 i915_gem_object_unpin_pages(obj); 285 i915_gem_object_put(obj); 286 } 287 288 int intel_pxp_tee_component_init(struct intel_pxp *pxp) 289 { 290 int ret; 291 struct intel_gt *gt = pxp->ctrl_gt; 292 struct drm_i915_private *i915 = gt->i915; 293 294 ret = alloc_streaming_command(pxp); 295 if (ret) 296 return ret; 297 298 ret = component_add_typed(i915->drm.dev, &i915_pxp_tee_component_ops, 299 I915_COMPONENT_PXP); 300 if (ret < 0) { 301 drm_err(&i915->drm, "Failed to add PXP component (%d)\n", ret); 302 goto out_free; 303 } 304 305 pxp->pxp_component_added = true; 306 307 return 0; 308 309 out_free: 310 free_streaming_command(pxp); 311 return ret; 312 } 313 314 void intel_pxp_tee_component_fini(struct intel_pxp *pxp) 315 { 316 struct drm_i915_private *i915 = pxp->ctrl_gt->i915; 317 318 if (!pxp->pxp_component_added) 319 return; 320 321 component_del(i915->drm.dev, &i915_pxp_tee_component_ops); 322 pxp->pxp_component_added = false; 323 324 free_streaming_command(pxp); 325 } 326 327 int intel_pxp_tee_cmd_create_arb_session(struct intel_pxp *pxp, 328 int arb_session_id) 329 { 330 struct drm_i915_private *i915 = pxp->ctrl_gt->i915; 331 struct pxp42_create_arb_in msg_in = {0}; 332 struct pxp42_create_arb_out msg_out = {0}; 333 int ret; 334 335 msg_in.header.api_version = PXP_APIVER(4, 2); 336 msg_in.header.command_id = PXP42_CMDID_INIT_SESSION; 337 msg_in.header.buffer_len = sizeof(msg_in) - sizeof(msg_in.header); 338 msg_in.protection_mode = PXP42_ARB_SESSION_MODE_HEAVY; 339 msg_in.session_id = arb_session_id; 340 341 ret = intel_pxp_tee_io_message(pxp, 342 &msg_in, sizeof(msg_in), 343 &msg_out, sizeof(msg_out), 344 NULL); 345 346 if (ret) { 347 drm_err(&i915->drm, "Failed to send tee msg init arb session, ret=[%d]\n", ret); 348 } else if (msg_out.header.status != 0) { 349 if (is_fw_err_platform_config(msg_out.header.status)) { 350 drm_info_once(&i915->drm, 351 "PXP init-arb-session-%d failed due to BIOS/SOC:0x%08x:%s\n", 352 arb_session_id, msg_out.header.status, 353 fw_err_to_string(msg_out.header.status)); 354 } else { 355 drm_dbg(&i915->drm, "PXP init-arb-session--%d failed 0x%08x:%st:\n", 356 arb_session_id, msg_out.header.status, 357 fw_err_to_string(msg_out.header.status)); 358 drm_dbg(&i915->drm, " cmd-detail: ID=[0x%08x],API-Ver-[0x%08x]\n", 359 msg_in.header.command_id, msg_in.header.api_version); 360 } 361 } 362 363 return ret; 364 } 365 366 void intel_pxp_tee_end_arb_fw_session(struct intel_pxp *pxp, u32 session_id) 367 { 368 struct drm_i915_private *i915 = pxp->ctrl_gt->i915; 369 struct pxp42_inv_stream_key_in msg_in = {0}; 370 struct pxp42_inv_stream_key_out msg_out = {0}; 371 int ret, trials = 0; 372 373 try_again: 374 memset(&msg_in, 0, sizeof(msg_in)); 375 memset(&msg_out, 0, sizeof(msg_out)); 376 msg_in.header.api_version = PXP_APIVER(4, 2); 377 msg_in.header.command_id = PXP42_CMDID_INVALIDATE_STREAM_KEY; 378 msg_in.header.buffer_len = sizeof(msg_in) - sizeof(msg_in.header); 379 380 msg_in.header.stream_id = FIELD_PREP(PXP_CMDHDR_EXTDATA_SESSION_VALID, 1); 381 msg_in.header.stream_id |= FIELD_PREP(PXP_CMDHDR_EXTDATA_APP_TYPE, 0); 382 msg_in.header.stream_id |= FIELD_PREP(PXP_CMDHDR_EXTDATA_SESSION_ID, session_id); 383 384 ret = intel_pxp_tee_io_message(pxp, 385 &msg_in, sizeof(msg_in), 386 &msg_out, sizeof(msg_out), 387 NULL); 388 389 /* Cleanup coherency between GT and Firmware is critical, so try again if it fails */ 390 if ((ret || msg_out.header.status != 0x0) && ++trials < 3) 391 goto try_again; 392 393 if (ret) { 394 drm_err(&i915->drm, "Failed to send tee msg for inv-stream-key-%u, ret=[%d]\n", 395 session_id, ret); 396 } else if (msg_out.header.status != 0) { 397 if (is_fw_err_platform_config(msg_out.header.status)) { 398 drm_info_once(&i915->drm, 399 "PXP inv-stream-key-%u failed due to BIOS/SOC :0x%08x:%s\n", 400 session_id, msg_out.header.status, 401 fw_err_to_string(msg_out.header.status)); 402 } else { 403 drm_dbg(&i915->drm, "PXP inv-stream-key-%u failed 0x%08x:%s:\n", 404 session_id, msg_out.header.status, 405 fw_err_to_string(msg_out.header.status)); 406 drm_dbg(&i915->drm, " cmd-detail: ID=[0x%08x],API-Ver-[0x%08x]\n", 407 msg_in.header.command_id, msg_in.header.api_version); 408 } 409 } 410 } 411