xref: /linux/drivers/gpu/drm/i915/intel_uncore.c (revision dd5b2498d845f925904cb2afabb6ba11bfc317c5)
1 /*
2  * Copyright © 2013 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  */
23 
24 #include "i915_drv.h"
25 #include "intel_drv.h"
26 #include "i915_vgpu.h"
27 
28 #include <asm/iosf_mbi.h>
29 #include <linux/pm_runtime.h>
30 
31 #define FORCEWAKE_ACK_TIMEOUT_MS 50
32 #define GT_FIFO_TIMEOUT_MS	 10
33 
34 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__))
35 
36 static const char * const forcewake_domain_names[] = {
37 	"render",
38 	"blitter",
39 	"media",
40 	"vdbox0",
41 	"vdbox1",
42 	"vdbox2",
43 	"vdbox3",
44 	"vebox0",
45 	"vebox1",
46 };
47 
48 const char *
49 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
50 {
51 	BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT);
52 
53 	if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
54 		return forcewake_domain_names[id];
55 
56 	WARN_ON(id);
57 
58 	return "unknown";
59 }
60 
61 static inline void
62 fw_domain_reset(struct drm_i915_private *i915,
63 		const struct intel_uncore_forcewake_domain *d)
64 {
65 	/*
66 	 * We don't really know if the powerwell for the forcewake domain we are
67 	 * trying to reset here does exist at this point (engines could be fused
68 	 * off in ICL+), so no waiting for acks
69 	 */
70 	__raw_i915_write32(i915, d->reg_set, i915->uncore.fw_reset);
71 }
72 
73 static inline void
74 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
75 {
76 	d->wake_count++;
77 	hrtimer_start_range_ns(&d->timer,
78 			       NSEC_PER_MSEC,
79 			       NSEC_PER_MSEC,
80 			       HRTIMER_MODE_REL);
81 }
82 
83 static inline int
84 __wait_for_ack(const struct drm_i915_private *i915,
85 	       const struct intel_uncore_forcewake_domain *d,
86 	       const u32 ack,
87 	       const u32 value)
88 {
89 	return wait_for_atomic((__raw_i915_read32(i915, d->reg_ack) & ack) == value,
90 			       FORCEWAKE_ACK_TIMEOUT_MS);
91 }
92 
93 static inline int
94 wait_ack_clear(const struct drm_i915_private *i915,
95 	       const struct intel_uncore_forcewake_domain *d,
96 	       const u32 ack)
97 {
98 	return __wait_for_ack(i915, d, ack, 0);
99 }
100 
101 static inline int
102 wait_ack_set(const struct drm_i915_private *i915,
103 	     const struct intel_uncore_forcewake_domain *d,
104 	     const u32 ack)
105 {
106 	return __wait_for_ack(i915, d, ack, ack);
107 }
108 
109 static inline void
110 fw_domain_wait_ack_clear(const struct drm_i915_private *i915,
111 			 const struct intel_uncore_forcewake_domain *d)
112 {
113 	if (wait_ack_clear(i915, d, FORCEWAKE_KERNEL))
114 		DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
115 			  intel_uncore_forcewake_domain_to_str(d->id));
116 }
117 
118 enum ack_type {
119 	ACK_CLEAR = 0,
120 	ACK_SET
121 };
122 
123 static int
124 fw_domain_wait_ack_with_fallback(const struct drm_i915_private *i915,
125 				 const struct intel_uncore_forcewake_domain *d,
126 				 const enum ack_type type)
127 {
128 	const u32 ack_bit = FORCEWAKE_KERNEL;
129 	const u32 value = type == ACK_SET ? ack_bit : 0;
130 	unsigned int pass;
131 	bool ack_detected;
132 
133 	/*
134 	 * There is a possibility of driver's wake request colliding
135 	 * with hardware's own wake requests and that can cause
136 	 * hardware to not deliver the driver's ack message.
137 	 *
138 	 * Use a fallback bit toggle to kick the gpu state machine
139 	 * in the hope that the original ack will be delivered along with
140 	 * the fallback ack.
141 	 *
142 	 * This workaround is described in HSDES #1604254524 and it's known as:
143 	 * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl
144 	 * although the name is a bit misleading.
145 	 */
146 
147 	pass = 1;
148 	do {
149 		wait_ack_clear(i915, d, FORCEWAKE_KERNEL_FALLBACK);
150 
151 		__raw_i915_write32(i915, d->reg_set,
152 				   _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL_FALLBACK));
153 		/* Give gt some time to relax before the polling frenzy */
154 		udelay(10 * pass);
155 		wait_ack_set(i915, d, FORCEWAKE_KERNEL_FALLBACK);
156 
157 		ack_detected = (__raw_i915_read32(i915, d->reg_ack) & ack_bit) == value;
158 
159 		__raw_i915_write32(i915, d->reg_set,
160 				   _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL_FALLBACK));
161 	} while (!ack_detected && pass++ < 10);
162 
163 	DRM_DEBUG_DRIVER("%s had to use fallback to %s ack, 0x%x (passes %u)\n",
164 			 intel_uncore_forcewake_domain_to_str(d->id),
165 			 type == ACK_SET ? "set" : "clear",
166 			 __raw_i915_read32(i915, d->reg_ack),
167 			 pass);
168 
169 	return ack_detected ? 0 : -ETIMEDOUT;
170 }
171 
172 static inline void
173 fw_domain_wait_ack_clear_fallback(const struct drm_i915_private *i915,
174 				  const struct intel_uncore_forcewake_domain *d)
175 {
176 	if (likely(!wait_ack_clear(i915, d, FORCEWAKE_KERNEL)))
177 		return;
178 
179 	if (fw_domain_wait_ack_with_fallback(i915, d, ACK_CLEAR))
180 		fw_domain_wait_ack_clear(i915, d);
181 }
182 
183 static inline void
184 fw_domain_get(struct drm_i915_private *i915,
185 	      const struct intel_uncore_forcewake_domain *d)
186 {
187 	__raw_i915_write32(i915, d->reg_set, i915->uncore.fw_set);
188 }
189 
190 static inline void
191 fw_domain_wait_ack_set(const struct drm_i915_private *i915,
192 		       const struct intel_uncore_forcewake_domain *d)
193 {
194 	if (wait_ack_set(i915, d, FORCEWAKE_KERNEL))
195 		DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
196 			  intel_uncore_forcewake_domain_to_str(d->id));
197 }
198 
199 static inline void
200 fw_domain_wait_ack_set_fallback(const struct drm_i915_private *i915,
201 				const struct intel_uncore_forcewake_domain *d)
202 {
203 	if (likely(!wait_ack_set(i915, d, FORCEWAKE_KERNEL)))
204 		return;
205 
206 	if (fw_domain_wait_ack_with_fallback(i915, d, ACK_SET))
207 		fw_domain_wait_ack_set(i915, d);
208 }
209 
210 static inline void
211 fw_domain_put(const struct drm_i915_private *i915,
212 	      const struct intel_uncore_forcewake_domain *d)
213 {
214 	__raw_i915_write32(i915, d->reg_set, i915->uncore.fw_clear);
215 }
216 
217 static void
218 fw_domains_get(struct drm_i915_private *i915, enum forcewake_domains fw_domains)
219 {
220 	struct intel_uncore_forcewake_domain *d;
221 	unsigned int tmp;
222 
223 	GEM_BUG_ON(fw_domains & ~i915->uncore.fw_domains);
224 
225 	for_each_fw_domain_masked(d, fw_domains, i915, tmp) {
226 		fw_domain_wait_ack_clear(i915, d);
227 		fw_domain_get(i915, d);
228 	}
229 
230 	for_each_fw_domain_masked(d, fw_domains, i915, tmp)
231 		fw_domain_wait_ack_set(i915, d);
232 
233 	i915->uncore.fw_domains_active |= fw_domains;
234 }
235 
236 static void
237 fw_domains_get_with_fallback(struct drm_i915_private *i915,
238 			     enum forcewake_domains fw_domains)
239 {
240 	struct intel_uncore_forcewake_domain *d;
241 	unsigned int tmp;
242 
243 	GEM_BUG_ON(fw_domains & ~i915->uncore.fw_domains);
244 
245 	for_each_fw_domain_masked(d, fw_domains, i915, tmp) {
246 		fw_domain_wait_ack_clear_fallback(i915, d);
247 		fw_domain_get(i915, d);
248 	}
249 
250 	for_each_fw_domain_masked(d, fw_domains, i915, tmp)
251 		fw_domain_wait_ack_set_fallback(i915, d);
252 
253 	i915->uncore.fw_domains_active |= fw_domains;
254 }
255 
256 static void
257 fw_domains_put(struct drm_i915_private *i915, enum forcewake_domains fw_domains)
258 {
259 	struct intel_uncore_forcewake_domain *d;
260 	unsigned int tmp;
261 
262 	GEM_BUG_ON(fw_domains & ~i915->uncore.fw_domains);
263 
264 	for_each_fw_domain_masked(d, fw_domains, i915, tmp)
265 		fw_domain_put(i915, d);
266 
267 	i915->uncore.fw_domains_active &= ~fw_domains;
268 }
269 
270 static void
271 fw_domains_reset(struct drm_i915_private *i915,
272 		 enum forcewake_domains fw_domains)
273 {
274 	struct intel_uncore_forcewake_domain *d;
275 	unsigned int tmp;
276 
277 	if (!fw_domains)
278 		return;
279 
280 	GEM_BUG_ON(fw_domains & ~i915->uncore.fw_domains);
281 
282 	for_each_fw_domain_masked(d, fw_domains, i915, tmp)
283 		fw_domain_reset(i915, d);
284 }
285 
286 static inline u32 gt_thread_status(struct drm_i915_private *dev_priv)
287 {
288 	u32 val;
289 
290 	val = __raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG);
291 	val &= GEN6_GT_THREAD_STATUS_CORE_MASK;
292 
293 	return val;
294 }
295 
296 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
297 {
298 	/*
299 	 * w/a for a sporadic read returning 0 by waiting for the GT
300 	 * thread to wake up.
301 	 */
302 	WARN_ONCE(wait_for_atomic_us(gt_thread_status(dev_priv) == 0, 5000),
303 		  "GT thread status wait timed out\n");
304 }
305 
306 static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv,
307 					      enum forcewake_domains fw_domains)
308 {
309 	fw_domains_get(dev_priv, fw_domains);
310 
311 	/* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
312 	__gen6_gt_wait_for_thread_c0(dev_priv);
313 }
314 
315 static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv)
316 {
317 	u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL);
318 
319 	return count & GT_FIFO_FREE_ENTRIES_MASK;
320 }
321 
322 static void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
323 {
324 	u32 n;
325 
326 	/* On VLV, FIFO will be shared by both SW and HW.
327 	 * So, we need to read the FREE_ENTRIES everytime */
328 	if (IS_VALLEYVIEW(dev_priv))
329 		n = fifo_free_entries(dev_priv);
330 	else
331 		n = dev_priv->uncore.fifo_count;
332 
333 	if (n <= GT_FIFO_NUM_RESERVED_ENTRIES) {
334 		if (wait_for_atomic((n = fifo_free_entries(dev_priv)) >
335 				    GT_FIFO_NUM_RESERVED_ENTRIES,
336 				    GT_FIFO_TIMEOUT_MS)) {
337 			DRM_DEBUG("GT_FIFO timeout, entries: %u\n", n);
338 			return;
339 		}
340 	}
341 
342 	dev_priv->uncore.fifo_count = n - 1;
343 }
344 
345 static enum hrtimer_restart
346 intel_uncore_fw_release_timer(struct hrtimer *timer)
347 {
348 	struct intel_uncore_forcewake_domain *domain =
349 	       container_of(timer, struct intel_uncore_forcewake_domain, timer);
350 	struct drm_i915_private *dev_priv =
351 		container_of(domain, struct drm_i915_private, uncore.fw_domain[domain->id]);
352 	unsigned long irqflags;
353 
354 	assert_rpm_device_not_suspended(dev_priv);
355 
356 	if (xchg(&domain->active, false))
357 		return HRTIMER_RESTART;
358 
359 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
360 	if (WARN_ON(domain->wake_count == 0))
361 		domain->wake_count++;
362 
363 	if (--domain->wake_count == 0)
364 		dev_priv->uncore.funcs.force_wake_put(dev_priv, domain->mask);
365 
366 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
367 
368 	return HRTIMER_NORESTART;
369 }
370 
371 /* Note callers must have acquired the PUNIT->PMIC bus, before calling this. */
372 static unsigned int
373 intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv)
374 {
375 	unsigned long irqflags;
376 	struct intel_uncore_forcewake_domain *domain;
377 	int retry_count = 100;
378 	enum forcewake_domains fw, active_domains;
379 
380 	iosf_mbi_assert_punit_acquired();
381 
382 	/* Hold uncore.lock across reset to prevent any register access
383 	 * with forcewake not set correctly. Wait until all pending
384 	 * timers are run before holding.
385 	 */
386 	while (1) {
387 		unsigned int tmp;
388 
389 		active_domains = 0;
390 
391 		for_each_fw_domain(domain, dev_priv, tmp) {
392 			smp_store_mb(domain->active, false);
393 			if (hrtimer_cancel(&domain->timer) == 0)
394 				continue;
395 
396 			intel_uncore_fw_release_timer(&domain->timer);
397 		}
398 
399 		spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
400 
401 		for_each_fw_domain(domain, dev_priv, tmp) {
402 			if (hrtimer_active(&domain->timer))
403 				active_domains |= domain->mask;
404 		}
405 
406 		if (active_domains == 0)
407 			break;
408 
409 		if (--retry_count == 0) {
410 			DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
411 			break;
412 		}
413 
414 		spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
415 		cond_resched();
416 	}
417 
418 	WARN_ON(active_domains);
419 
420 	fw = dev_priv->uncore.fw_domains_active;
421 	if (fw)
422 		dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
423 
424 	fw_domains_reset(dev_priv, dev_priv->uncore.fw_domains);
425 	assert_forcewakes_inactive(dev_priv);
426 
427 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
428 
429 	return fw; /* track the lost user forcewake domains */
430 }
431 
432 static u64 gen9_edram_size(struct drm_i915_private *dev_priv)
433 {
434 	const unsigned int ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
435 	const unsigned int sets[4] = { 1, 1, 2, 2 };
436 	const u32 cap = dev_priv->edram_cap;
437 
438 	return EDRAM_NUM_BANKS(cap) *
439 		ways[EDRAM_WAYS_IDX(cap)] *
440 		sets[EDRAM_SETS_IDX(cap)] *
441 		1024 * 1024;
442 }
443 
444 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv)
445 {
446 	if (!HAS_EDRAM(dev_priv))
447 		return 0;
448 
449 	/* The needed capability bits for size calculation
450 	 * are not there with pre gen9 so return 128MB always.
451 	 */
452 	if (INTEL_GEN(dev_priv) < 9)
453 		return 128 * 1024 * 1024;
454 
455 	return gen9_edram_size(dev_priv);
456 }
457 
458 static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv)
459 {
460 	if (IS_HASWELL(dev_priv) ||
461 	    IS_BROADWELL(dev_priv) ||
462 	    INTEL_GEN(dev_priv) >= 9) {
463 		dev_priv->edram_cap = __raw_i915_read32(dev_priv,
464 							HSW_EDRAM_CAP);
465 
466 		/* NB: We can't write IDICR yet because we do not have gt funcs
467 		 * set up */
468 	} else {
469 		dev_priv->edram_cap = 0;
470 	}
471 
472 	if (HAS_EDRAM(dev_priv))
473 		DRM_INFO("Found %lluMB of eDRAM\n",
474 			 intel_uncore_edram_size(dev_priv) / (1024 * 1024));
475 }
476 
477 static bool
478 fpga_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
479 {
480 	u32 dbg;
481 
482 	dbg = __raw_i915_read32(dev_priv, FPGA_DBG);
483 	if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
484 		return false;
485 
486 	__raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
487 
488 	return true;
489 }
490 
491 static bool
492 vlv_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
493 {
494 	u32 cer;
495 
496 	cer = __raw_i915_read32(dev_priv, CLAIM_ER);
497 	if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
498 		return false;
499 
500 	__raw_i915_write32(dev_priv, CLAIM_ER, CLAIM_ER_CLR);
501 
502 	return true;
503 }
504 
505 static bool
506 gen6_check_for_fifo_debug(struct drm_i915_private *dev_priv)
507 {
508 	u32 fifodbg;
509 
510 	fifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
511 
512 	if (unlikely(fifodbg)) {
513 		DRM_DEBUG_DRIVER("GTFIFODBG = 0x08%x\n", fifodbg);
514 		__raw_i915_write32(dev_priv, GTFIFODBG, fifodbg);
515 	}
516 
517 	return fifodbg;
518 }
519 
520 static bool
521 check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
522 {
523 	bool ret = false;
524 
525 	if (HAS_FPGA_DBG_UNCLAIMED(dev_priv))
526 		ret |= fpga_check_for_unclaimed_mmio(dev_priv);
527 
528 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
529 		ret |= vlv_check_for_unclaimed_mmio(dev_priv);
530 
531 	if (IS_GEN_RANGE(dev_priv, 6, 7))
532 		ret |= gen6_check_for_fifo_debug(dev_priv);
533 
534 	return ret;
535 }
536 
537 static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
538 					  unsigned int restore_forcewake)
539 {
540 	/* clear out unclaimed reg detection bit */
541 	if (check_for_unclaimed_mmio(dev_priv))
542 		DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
543 
544 	/* WaDisableShadowRegForCpd:chv */
545 	if (IS_CHERRYVIEW(dev_priv)) {
546 		__raw_i915_write32(dev_priv, GTFIFOCTL,
547 				   __raw_i915_read32(dev_priv, GTFIFOCTL) |
548 				   GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
549 				   GT_FIFO_CTL_RC6_POLICY_STALL);
550 	}
551 
552 	iosf_mbi_punit_acquire();
553 	intel_uncore_forcewake_reset(dev_priv);
554 	if (restore_forcewake) {
555 		spin_lock_irq(&dev_priv->uncore.lock);
556 		dev_priv->uncore.funcs.force_wake_get(dev_priv,
557 						      restore_forcewake);
558 
559 		if (IS_GEN_RANGE(dev_priv, 6, 7))
560 			dev_priv->uncore.fifo_count =
561 				fifo_free_entries(dev_priv);
562 		spin_unlock_irq(&dev_priv->uncore.lock);
563 	}
564 	iosf_mbi_punit_release();
565 }
566 
567 void intel_uncore_suspend(struct drm_i915_private *dev_priv)
568 {
569 	iosf_mbi_punit_acquire();
570 	iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
571 		&dev_priv->uncore.pmic_bus_access_nb);
572 	dev_priv->uncore.fw_domains_saved =
573 		intel_uncore_forcewake_reset(dev_priv);
574 	iosf_mbi_punit_release();
575 }
576 
577 void intel_uncore_resume_early(struct drm_i915_private *dev_priv)
578 {
579 	unsigned int restore_forcewake;
580 
581 	restore_forcewake = fetch_and_zero(&dev_priv->uncore.fw_domains_saved);
582 	__intel_uncore_early_sanitize(dev_priv, restore_forcewake);
583 
584 	iosf_mbi_register_pmic_bus_access_notifier(
585 		&dev_priv->uncore.pmic_bus_access_nb);
586 	i915_check_and_clear_faults(dev_priv);
587 }
588 
589 void intel_uncore_runtime_resume(struct drm_i915_private *dev_priv)
590 {
591 	iosf_mbi_register_pmic_bus_access_notifier(
592 		&dev_priv->uncore.pmic_bus_access_nb);
593 }
594 
595 void intel_uncore_sanitize(struct drm_i915_private *dev_priv)
596 {
597 	/* BIOS often leaves RC6 enabled, but disable it for hw init */
598 	intel_sanitize_gt_powersave(dev_priv);
599 }
600 
601 static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
602 					 enum forcewake_domains fw_domains)
603 {
604 	struct intel_uncore_forcewake_domain *domain;
605 	unsigned int tmp;
606 
607 	fw_domains &= dev_priv->uncore.fw_domains;
608 
609 	for_each_fw_domain_masked(domain, fw_domains, dev_priv, tmp) {
610 		if (domain->wake_count++) {
611 			fw_domains &= ~domain->mask;
612 			domain->active = true;
613 		}
614 	}
615 
616 	if (fw_domains)
617 		dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
618 }
619 
620 /**
621  * intel_uncore_forcewake_get - grab forcewake domain references
622  * @dev_priv: i915 device instance
623  * @fw_domains: forcewake domains to get reference on
624  *
625  * This function can be used get GT's forcewake domain references.
626  * Normal register access will handle the forcewake domains automatically.
627  * However if some sequence requires the GT to not power down a particular
628  * forcewake domains this function should be called at the beginning of the
629  * sequence. And subsequently the reference should be dropped by symmetric
630  * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
631  * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
632  */
633 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
634 				enum forcewake_domains fw_domains)
635 {
636 	unsigned long irqflags;
637 
638 	if (!dev_priv->uncore.funcs.force_wake_get)
639 		return;
640 
641 	assert_rpm_wakelock_held(dev_priv);
642 
643 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
644 	__intel_uncore_forcewake_get(dev_priv, fw_domains);
645 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
646 }
647 
648 /**
649  * intel_uncore_forcewake_user_get - claim forcewake on behalf of userspace
650  * @dev_priv: i915 device instance
651  *
652  * This function is a wrapper around intel_uncore_forcewake_get() to acquire
653  * the GT powerwell and in the process disable our debugging for the
654  * duration of userspace's bypass.
655  */
656 void intel_uncore_forcewake_user_get(struct drm_i915_private *dev_priv)
657 {
658 	spin_lock_irq(&dev_priv->uncore.lock);
659 	if (!dev_priv->uncore.user_forcewake.count++) {
660 		intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL);
661 
662 		/* Save and disable mmio debugging for the user bypass */
663 		dev_priv->uncore.user_forcewake.saved_mmio_check =
664 			dev_priv->uncore.unclaimed_mmio_check;
665 		dev_priv->uncore.user_forcewake.saved_mmio_debug =
666 			i915_modparams.mmio_debug;
667 
668 		dev_priv->uncore.unclaimed_mmio_check = 0;
669 		i915_modparams.mmio_debug = 0;
670 	}
671 	spin_unlock_irq(&dev_priv->uncore.lock);
672 }
673 
674 /**
675  * intel_uncore_forcewake_user_put - release forcewake on behalf of userspace
676  * @dev_priv: i915 device instance
677  *
678  * This function complements intel_uncore_forcewake_user_get() and releases
679  * the GT powerwell taken on behalf of the userspace bypass.
680  */
681 void intel_uncore_forcewake_user_put(struct drm_i915_private *dev_priv)
682 {
683 	spin_lock_irq(&dev_priv->uncore.lock);
684 	if (!--dev_priv->uncore.user_forcewake.count) {
685 		if (intel_uncore_unclaimed_mmio(dev_priv))
686 			dev_info(dev_priv->drm.dev,
687 				 "Invalid mmio detected during user access\n");
688 
689 		dev_priv->uncore.unclaimed_mmio_check =
690 			dev_priv->uncore.user_forcewake.saved_mmio_check;
691 		i915_modparams.mmio_debug =
692 			dev_priv->uncore.user_forcewake.saved_mmio_debug;
693 
694 		intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
695 	}
696 	spin_unlock_irq(&dev_priv->uncore.lock);
697 }
698 
699 /**
700  * intel_uncore_forcewake_get__locked - grab forcewake domain references
701  * @dev_priv: i915 device instance
702  * @fw_domains: forcewake domains to get reference on
703  *
704  * See intel_uncore_forcewake_get(). This variant places the onus
705  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
706  */
707 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
708 					enum forcewake_domains fw_domains)
709 {
710 	lockdep_assert_held(&dev_priv->uncore.lock);
711 
712 	if (!dev_priv->uncore.funcs.force_wake_get)
713 		return;
714 
715 	__intel_uncore_forcewake_get(dev_priv, fw_domains);
716 }
717 
718 static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
719 					 enum forcewake_domains fw_domains)
720 {
721 	struct intel_uncore_forcewake_domain *domain;
722 	unsigned int tmp;
723 
724 	fw_domains &= dev_priv->uncore.fw_domains;
725 
726 	for_each_fw_domain_masked(domain, fw_domains, dev_priv, tmp) {
727 		if (WARN_ON(domain->wake_count == 0))
728 			continue;
729 
730 		if (--domain->wake_count) {
731 			domain->active = true;
732 			continue;
733 		}
734 
735 		fw_domain_arm_timer(domain);
736 	}
737 }
738 
739 /**
740  * intel_uncore_forcewake_put - release a forcewake domain reference
741  * @dev_priv: i915 device instance
742  * @fw_domains: forcewake domains to put references
743  *
744  * This function drops the device-level forcewakes for specified
745  * domains obtained by intel_uncore_forcewake_get().
746  */
747 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
748 				enum forcewake_domains fw_domains)
749 {
750 	unsigned long irqflags;
751 
752 	if (!dev_priv->uncore.funcs.force_wake_put)
753 		return;
754 
755 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
756 	__intel_uncore_forcewake_put(dev_priv, fw_domains);
757 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
758 }
759 
760 /**
761  * intel_uncore_forcewake_put__locked - grab forcewake domain references
762  * @dev_priv: i915 device instance
763  * @fw_domains: forcewake domains to get reference on
764  *
765  * See intel_uncore_forcewake_put(). This variant places the onus
766  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
767  */
768 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
769 					enum forcewake_domains fw_domains)
770 {
771 	lockdep_assert_held(&dev_priv->uncore.lock);
772 
773 	if (!dev_priv->uncore.funcs.force_wake_put)
774 		return;
775 
776 	__intel_uncore_forcewake_put(dev_priv, fw_domains);
777 }
778 
779 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
780 {
781 	if (!dev_priv->uncore.funcs.force_wake_get)
782 		return;
783 
784 	WARN(dev_priv->uncore.fw_domains_active,
785 	     "Expected all fw_domains to be inactive, but %08x are still on\n",
786 	     dev_priv->uncore.fw_domains_active);
787 }
788 
789 void assert_forcewakes_active(struct drm_i915_private *dev_priv,
790 			      enum forcewake_domains fw_domains)
791 {
792 	if (!dev_priv->uncore.funcs.force_wake_get)
793 		return;
794 
795 	assert_rpm_wakelock_held(dev_priv);
796 
797 	fw_domains &= dev_priv->uncore.fw_domains;
798 	WARN(fw_domains & ~dev_priv->uncore.fw_domains_active,
799 	     "Expected %08x fw_domains to be active, but %08x are off\n",
800 	     fw_domains, fw_domains & ~dev_priv->uncore.fw_domains_active);
801 }
802 
803 /* We give fast paths for the really cool registers */
804 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)
805 
806 #define GEN11_NEEDS_FORCE_WAKE(reg) \
807 	((reg) < 0x40000 || ((reg) >= 0x1c0000 && (reg) < 0x1dc000))
808 
809 #define __gen6_reg_read_fw_domains(offset) \
810 ({ \
811 	enum forcewake_domains __fwd; \
812 	if (NEEDS_FORCE_WAKE(offset)) \
813 		__fwd = FORCEWAKE_RENDER; \
814 	else \
815 		__fwd = 0; \
816 	__fwd; \
817 })
818 
819 static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry)
820 {
821 	if (offset < entry->start)
822 		return -1;
823 	else if (offset > entry->end)
824 		return 1;
825 	else
826 		return 0;
827 }
828 
829 /* Copied and "macroized" from lib/bsearch.c */
830 #define BSEARCH(key, base, num, cmp) ({                                 \
831 	unsigned int start__ = 0, end__ = (num);                        \
832 	typeof(base) result__ = NULL;                                   \
833 	while (start__ < end__) {                                       \
834 		unsigned int mid__ = start__ + (end__ - start__) / 2;   \
835 		int ret__ = (cmp)((key), (base) + mid__);               \
836 		if (ret__ < 0) {                                        \
837 			end__ = mid__;                                  \
838 		} else if (ret__ > 0) {                                 \
839 			start__ = mid__ + 1;                            \
840 		} else {                                                \
841 			result__ = (base) + mid__;                      \
842 			break;                                          \
843 		}                                                       \
844 	}                                                               \
845 	result__;                                                       \
846 })
847 
848 static enum forcewake_domains
849 find_fw_domain(struct drm_i915_private *dev_priv, u32 offset)
850 {
851 	const struct intel_forcewake_range *entry;
852 
853 	entry = BSEARCH(offset,
854 			dev_priv->uncore.fw_domains_table,
855 			dev_priv->uncore.fw_domains_table_entries,
856 			fw_range_cmp);
857 
858 	if (!entry)
859 		return 0;
860 
861 	/*
862 	 * The list of FW domains depends on the SKU in gen11+ so we
863 	 * can't determine it statically. We use FORCEWAKE_ALL and
864 	 * translate it here to the list of available domains.
865 	 */
866 	if (entry->domains == FORCEWAKE_ALL)
867 		return dev_priv->uncore.fw_domains;
868 
869 	WARN(entry->domains & ~dev_priv->uncore.fw_domains,
870 	     "Uninitialized forcewake domain(s) 0x%x accessed at 0x%x\n",
871 	     entry->domains & ~dev_priv->uncore.fw_domains, offset);
872 
873 	return entry->domains;
874 }
875 
876 #define GEN_FW_RANGE(s, e, d) \
877 	{ .start = (s), .end = (e), .domains = (d) }
878 
879 #define HAS_FWTABLE(dev_priv) \
880 	(INTEL_GEN(dev_priv) >= 9 || \
881 	 IS_CHERRYVIEW(dev_priv) || \
882 	 IS_VALLEYVIEW(dev_priv))
883 
884 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
885 static const struct intel_forcewake_range __vlv_fw_ranges[] = {
886 	GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
887 	GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER),
888 	GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER),
889 	GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
890 	GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA),
891 	GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER),
892 	GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
893 };
894 
895 #define __fwtable_reg_read_fw_domains(offset) \
896 ({ \
897 	enum forcewake_domains __fwd = 0; \
898 	if (NEEDS_FORCE_WAKE((offset))) \
899 		__fwd = find_fw_domain(dev_priv, offset); \
900 	__fwd; \
901 })
902 
903 #define __gen11_fwtable_reg_read_fw_domains(offset) \
904 ({ \
905 	enum forcewake_domains __fwd = 0; \
906 	if (GEN11_NEEDS_FORCE_WAKE((offset))) \
907 		__fwd = find_fw_domain(dev_priv, offset); \
908 	__fwd; \
909 })
910 
911 /* *Must* be sorted by offset! See intel_shadow_table_check(). */
912 static const i915_reg_t gen8_shadowed_regs[] = {
913 	RING_TAIL(RENDER_RING_BASE),	/* 0x2000 (base) */
914 	GEN6_RPNSWREQ,			/* 0xA008 */
915 	GEN6_RC_VIDEO_FREQ,		/* 0xA00C */
916 	RING_TAIL(GEN6_BSD_RING_BASE),	/* 0x12000 (base) */
917 	RING_TAIL(VEBOX_RING_BASE),	/* 0x1a000 (base) */
918 	RING_TAIL(BLT_RING_BASE),	/* 0x22000 (base) */
919 	/* TODO: Other registers are not yet used */
920 };
921 
922 static const i915_reg_t gen11_shadowed_regs[] = {
923 	RING_TAIL(RENDER_RING_BASE),		/* 0x2000 (base) */
924 	GEN6_RPNSWREQ,				/* 0xA008 */
925 	GEN6_RC_VIDEO_FREQ,			/* 0xA00C */
926 	RING_TAIL(BLT_RING_BASE),		/* 0x22000 (base) */
927 	RING_TAIL(GEN11_BSD_RING_BASE),		/* 0x1C0000 (base) */
928 	RING_TAIL(GEN11_BSD2_RING_BASE),	/* 0x1C4000 (base) */
929 	RING_TAIL(GEN11_VEBOX_RING_BASE),	/* 0x1C8000 (base) */
930 	RING_TAIL(GEN11_BSD3_RING_BASE),	/* 0x1D0000 (base) */
931 	RING_TAIL(GEN11_BSD4_RING_BASE),	/* 0x1D4000 (base) */
932 	RING_TAIL(GEN11_VEBOX2_RING_BASE),	/* 0x1D8000 (base) */
933 	/* TODO: Other registers are not yet used */
934 };
935 
936 static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)
937 {
938 	u32 offset = i915_mmio_reg_offset(*reg);
939 
940 	if (key < offset)
941 		return -1;
942 	else if (key > offset)
943 		return 1;
944 	else
945 		return 0;
946 }
947 
948 #define __is_genX_shadowed(x) \
949 static bool is_gen##x##_shadowed(u32 offset) \
950 { \
951 	const i915_reg_t *regs = gen##x##_shadowed_regs; \
952 	return BSEARCH(offset, regs, ARRAY_SIZE(gen##x##_shadowed_regs), \
953 		       mmio_reg_cmp); \
954 }
955 
956 __is_genX_shadowed(8)
957 __is_genX_shadowed(11)
958 
959 #define __gen8_reg_write_fw_domains(offset) \
960 ({ \
961 	enum forcewake_domains __fwd; \
962 	if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \
963 		__fwd = FORCEWAKE_RENDER; \
964 	else \
965 		__fwd = 0; \
966 	__fwd; \
967 })
968 
969 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
970 static const struct intel_forcewake_range __chv_fw_ranges[] = {
971 	GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
972 	GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
973 	GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
974 	GEN_FW_RANGE(0x8000, 0x82ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
975 	GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
976 	GEN_FW_RANGE(0x8500, 0x85ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
977 	GEN_FW_RANGE(0x8800, 0x88ff, FORCEWAKE_MEDIA),
978 	GEN_FW_RANGE(0x9000, 0xafff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
979 	GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
980 	GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
981 	GEN_FW_RANGE(0xe000, 0xe7ff, FORCEWAKE_RENDER),
982 	GEN_FW_RANGE(0xf000, 0xffff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
983 	GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
984 	GEN_FW_RANGE(0x1a000, 0x1bfff, FORCEWAKE_MEDIA),
985 	GEN_FW_RANGE(0x1e800, 0x1e9ff, FORCEWAKE_MEDIA),
986 	GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA),
987 };
988 
989 #define __fwtable_reg_write_fw_domains(offset) \
990 ({ \
991 	enum forcewake_domains __fwd = 0; \
992 	if (NEEDS_FORCE_WAKE((offset)) && !is_gen8_shadowed(offset)) \
993 		__fwd = find_fw_domain(dev_priv, offset); \
994 	__fwd; \
995 })
996 
997 #define __gen11_fwtable_reg_write_fw_domains(offset) \
998 ({ \
999 	enum forcewake_domains __fwd = 0; \
1000 	if (GEN11_NEEDS_FORCE_WAKE((offset)) && !is_gen11_shadowed(offset)) \
1001 		__fwd = find_fw_domain(dev_priv, offset); \
1002 	__fwd; \
1003 })
1004 
1005 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
1006 static const struct intel_forcewake_range __gen9_fw_ranges[] = {
1007 	GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
1008 	GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
1009 	GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
1010 	GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
1011 	GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
1012 	GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
1013 	GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
1014 	GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_BLITTER),
1015 	GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA),
1016 	GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
1017 	GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
1018 	GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1019 	GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER),
1020 	GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA),
1021 	GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_BLITTER),
1022 	GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
1023 	GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
1024 	GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1025 	GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
1026 	GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1027 	GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_BLITTER),
1028 	GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
1029 	GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_BLITTER),
1030 	GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
1031 	GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_BLITTER),
1032 	GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
1033 	GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_BLITTER),
1034 	GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA),
1035 	GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_BLITTER),
1036 	GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
1037 	GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_BLITTER),
1038 	GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
1039 };
1040 
1041 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
1042 static const struct intel_forcewake_range __gen11_fw_ranges[] = {
1043 	GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
1044 	GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
1045 	GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
1046 	GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
1047 	GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
1048 	GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
1049 	GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
1050 	GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER),
1051 	GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
1052 	GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
1053 	GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1054 	GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_BLITTER),
1055 	GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
1056 	GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
1057 	GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL),
1058 	GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
1059 	GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1060 	GEN_FW_RANGE(0xb480, 0xdfff, FORCEWAKE_BLITTER),
1061 	GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
1062 	GEN_FW_RANGE(0xe900, 0x243ff, FORCEWAKE_BLITTER),
1063 	GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
1064 	GEN_FW_RANGE(0x24800, 0x3ffff, FORCEWAKE_BLITTER),
1065 	GEN_FW_RANGE(0x40000, 0x1bffff, 0),
1066 	GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0),
1067 	GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1),
1068 	GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0),
1069 	GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_BLITTER),
1070 	GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2),
1071 	GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3),
1072 	GEN_FW_RANGE(0x1d8000, 0x1dbfff, FORCEWAKE_MEDIA_VEBOX1)
1073 };
1074 
1075 static void
1076 ilk_dummy_write(struct drm_i915_private *dev_priv)
1077 {
1078 	/* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
1079 	 * the chip from rc6 before touching it for real. MI_MODE is masked,
1080 	 * hence harmless to write 0 into. */
1081 	__raw_i915_write32(dev_priv, MI_MODE, 0);
1082 }
1083 
1084 static void
1085 __unclaimed_reg_debug(struct drm_i915_private *dev_priv,
1086 		      const i915_reg_t reg,
1087 		      const bool read,
1088 		      const bool before)
1089 {
1090 	if (WARN(check_for_unclaimed_mmio(dev_priv) && !before,
1091 		 "Unclaimed %s register 0x%x\n",
1092 		 read ? "read from" : "write to",
1093 		 i915_mmio_reg_offset(reg)))
1094 		/* Only report the first N failures */
1095 		i915_modparams.mmio_debug--;
1096 }
1097 
1098 static inline void
1099 unclaimed_reg_debug(struct drm_i915_private *dev_priv,
1100 		    const i915_reg_t reg,
1101 		    const bool read,
1102 		    const bool before)
1103 {
1104 	if (likely(!i915_modparams.mmio_debug))
1105 		return;
1106 
1107 	__unclaimed_reg_debug(dev_priv, reg, read, before);
1108 }
1109 
1110 #define GEN2_READ_HEADER(x) \
1111 	u##x val = 0; \
1112 	assert_rpm_wakelock_held(dev_priv);
1113 
1114 #define GEN2_READ_FOOTER \
1115 	trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
1116 	return val
1117 
1118 #define __gen2_read(x) \
1119 static u##x \
1120 gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
1121 	GEN2_READ_HEADER(x); \
1122 	val = __raw_i915_read##x(dev_priv, reg); \
1123 	GEN2_READ_FOOTER; \
1124 }
1125 
1126 #define __gen5_read(x) \
1127 static u##x \
1128 gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
1129 	GEN2_READ_HEADER(x); \
1130 	ilk_dummy_write(dev_priv); \
1131 	val = __raw_i915_read##x(dev_priv, reg); \
1132 	GEN2_READ_FOOTER; \
1133 }
1134 
1135 __gen5_read(8)
1136 __gen5_read(16)
1137 __gen5_read(32)
1138 __gen5_read(64)
1139 __gen2_read(8)
1140 __gen2_read(16)
1141 __gen2_read(32)
1142 __gen2_read(64)
1143 
1144 #undef __gen5_read
1145 #undef __gen2_read
1146 
1147 #undef GEN2_READ_FOOTER
1148 #undef GEN2_READ_HEADER
1149 
1150 #define GEN6_READ_HEADER(x) \
1151 	u32 offset = i915_mmio_reg_offset(reg); \
1152 	unsigned long irqflags; \
1153 	u##x val = 0; \
1154 	assert_rpm_wakelock_held(dev_priv); \
1155 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
1156 	unclaimed_reg_debug(dev_priv, reg, true, true)
1157 
1158 #define GEN6_READ_FOOTER \
1159 	unclaimed_reg_debug(dev_priv, reg, true, false); \
1160 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
1161 	trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
1162 	return val
1163 
1164 static noinline void ___force_wake_auto(struct drm_i915_private *dev_priv,
1165 					enum forcewake_domains fw_domains)
1166 {
1167 	struct intel_uncore_forcewake_domain *domain;
1168 	unsigned int tmp;
1169 
1170 	GEM_BUG_ON(fw_domains & ~dev_priv->uncore.fw_domains);
1171 
1172 	for_each_fw_domain_masked(domain, fw_domains, dev_priv, tmp)
1173 		fw_domain_arm_timer(domain);
1174 
1175 	dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
1176 }
1177 
1178 static inline void __force_wake_auto(struct drm_i915_private *dev_priv,
1179 				     enum forcewake_domains fw_domains)
1180 {
1181 	if (WARN_ON(!fw_domains))
1182 		return;
1183 
1184 	/* Turn on all requested but inactive supported forcewake domains. */
1185 	fw_domains &= dev_priv->uncore.fw_domains;
1186 	fw_domains &= ~dev_priv->uncore.fw_domains_active;
1187 
1188 	if (fw_domains)
1189 		___force_wake_auto(dev_priv, fw_domains);
1190 }
1191 
1192 #define __gen_read(func, x) \
1193 static u##x \
1194 func##_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
1195 	enum forcewake_domains fw_engine; \
1196 	GEN6_READ_HEADER(x); \
1197 	fw_engine = __##func##_reg_read_fw_domains(offset); \
1198 	if (fw_engine) \
1199 		__force_wake_auto(dev_priv, fw_engine); \
1200 	val = __raw_i915_read##x(dev_priv, reg); \
1201 	GEN6_READ_FOOTER; \
1202 }
1203 #define __gen6_read(x) __gen_read(gen6, x)
1204 #define __fwtable_read(x) __gen_read(fwtable, x)
1205 #define __gen11_fwtable_read(x) __gen_read(gen11_fwtable, x)
1206 
1207 __gen11_fwtable_read(8)
1208 __gen11_fwtable_read(16)
1209 __gen11_fwtable_read(32)
1210 __gen11_fwtable_read(64)
1211 __fwtable_read(8)
1212 __fwtable_read(16)
1213 __fwtable_read(32)
1214 __fwtable_read(64)
1215 __gen6_read(8)
1216 __gen6_read(16)
1217 __gen6_read(32)
1218 __gen6_read(64)
1219 
1220 #undef __gen11_fwtable_read
1221 #undef __fwtable_read
1222 #undef __gen6_read
1223 #undef GEN6_READ_FOOTER
1224 #undef GEN6_READ_HEADER
1225 
1226 #define GEN2_WRITE_HEADER \
1227 	trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1228 	assert_rpm_wakelock_held(dev_priv); \
1229 
1230 #define GEN2_WRITE_FOOTER
1231 
1232 #define __gen2_write(x) \
1233 static void \
1234 gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1235 	GEN2_WRITE_HEADER; \
1236 	__raw_i915_write##x(dev_priv, reg, val); \
1237 	GEN2_WRITE_FOOTER; \
1238 }
1239 
1240 #define __gen5_write(x) \
1241 static void \
1242 gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1243 	GEN2_WRITE_HEADER; \
1244 	ilk_dummy_write(dev_priv); \
1245 	__raw_i915_write##x(dev_priv, reg, val); \
1246 	GEN2_WRITE_FOOTER; \
1247 }
1248 
1249 __gen5_write(8)
1250 __gen5_write(16)
1251 __gen5_write(32)
1252 __gen2_write(8)
1253 __gen2_write(16)
1254 __gen2_write(32)
1255 
1256 #undef __gen5_write
1257 #undef __gen2_write
1258 
1259 #undef GEN2_WRITE_FOOTER
1260 #undef GEN2_WRITE_HEADER
1261 
1262 #define GEN6_WRITE_HEADER \
1263 	u32 offset = i915_mmio_reg_offset(reg); \
1264 	unsigned long irqflags; \
1265 	trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1266 	assert_rpm_wakelock_held(dev_priv); \
1267 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
1268 	unclaimed_reg_debug(dev_priv, reg, false, true)
1269 
1270 #define GEN6_WRITE_FOOTER \
1271 	unclaimed_reg_debug(dev_priv, reg, false, false); \
1272 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
1273 
1274 #define __gen6_write(x) \
1275 static void \
1276 gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1277 	GEN6_WRITE_HEADER; \
1278 	if (NEEDS_FORCE_WAKE(offset)) \
1279 		__gen6_gt_wait_for_fifo(dev_priv); \
1280 	__raw_i915_write##x(dev_priv, reg, val); \
1281 	GEN6_WRITE_FOOTER; \
1282 }
1283 
1284 #define __gen_write(func, x) \
1285 static void \
1286 func##_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1287 	enum forcewake_domains fw_engine; \
1288 	GEN6_WRITE_HEADER; \
1289 	fw_engine = __##func##_reg_write_fw_domains(offset); \
1290 	if (fw_engine) \
1291 		__force_wake_auto(dev_priv, fw_engine); \
1292 	__raw_i915_write##x(dev_priv, reg, val); \
1293 	GEN6_WRITE_FOOTER; \
1294 }
1295 #define __gen8_write(x) __gen_write(gen8, x)
1296 #define __fwtable_write(x) __gen_write(fwtable, x)
1297 #define __gen11_fwtable_write(x) __gen_write(gen11_fwtable, x)
1298 
1299 __gen11_fwtable_write(8)
1300 __gen11_fwtable_write(16)
1301 __gen11_fwtable_write(32)
1302 __fwtable_write(8)
1303 __fwtable_write(16)
1304 __fwtable_write(32)
1305 __gen8_write(8)
1306 __gen8_write(16)
1307 __gen8_write(32)
1308 __gen6_write(8)
1309 __gen6_write(16)
1310 __gen6_write(32)
1311 
1312 #undef __gen11_fwtable_write
1313 #undef __fwtable_write
1314 #undef __gen8_write
1315 #undef __gen6_write
1316 #undef GEN6_WRITE_FOOTER
1317 #undef GEN6_WRITE_HEADER
1318 
1319 #define ASSIGN_WRITE_MMIO_VFUNCS(i915, x) \
1320 do { \
1321 	(i915)->uncore.funcs.mmio_writeb = x##_write8; \
1322 	(i915)->uncore.funcs.mmio_writew = x##_write16; \
1323 	(i915)->uncore.funcs.mmio_writel = x##_write32; \
1324 } while (0)
1325 
1326 #define ASSIGN_READ_MMIO_VFUNCS(i915, x) \
1327 do { \
1328 	(i915)->uncore.funcs.mmio_readb = x##_read8; \
1329 	(i915)->uncore.funcs.mmio_readw = x##_read16; \
1330 	(i915)->uncore.funcs.mmio_readl = x##_read32; \
1331 	(i915)->uncore.funcs.mmio_readq = x##_read64; \
1332 } while (0)
1333 
1334 
1335 static void fw_domain_init(struct drm_i915_private *dev_priv,
1336 			   enum forcewake_domain_id domain_id,
1337 			   i915_reg_t reg_set,
1338 			   i915_reg_t reg_ack)
1339 {
1340 	struct intel_uncore_forcewake_domain *d;
1341 
1342 	if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
1343 		return;
1344 
1345 	d = &dev_priv->uncore.fw_domain[domain_id];
1346 
1347 	WARN_ON(d->wake_count);
1348 
1349 	WARN_ON(!i915_mmio_reg_valid(reg_set));
1350 	WARN_ON(!i915_mmio_reg_valid(reg_ack));
1351 
1352 	d->wake_count = 0;
1353 	d->reg_set = reg_set;
1354 	d->reg_ack = reg_ack;
1355 
1356 	d->id = domain_id;
1357 
1358 	BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER));
1359 	BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER));
1360 	BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA));
1361 	BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX0));
1362 	BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX1));
1363 	BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX2));
1364 	BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX3));
1365 	BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX0));
1366 	BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX1));
1367 
1368 
1369 	d->mask = BIT(domain_id);
1370 
1371 	hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1372 	d->timer.function = intel_uncore_fw_release_timer;
1373 
1374 	dev_priv->uncore.fw_domains |= BIT(domain_id);
1375 
1376 	fw_domain_reset(dev_priv, d);
1377 }
1378 
1379 static void fw_domain_fini(struct drm_i915_private *dev_priv,
1380 			   enum forcewake_domain_id domain_id)
1381 {
1382 	struct intel_uncore_forcewake_domain *d;
1383 
1384 	if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
1385 		return;
1386 
1387 	d = &dev_priv->uncore.fw_domain[domain_id];
1388 
1389 	WARN_ON(d->wake_count);
1390 	WARN_ON(hrtimer_cancel(&d->timer));
1391 	memset(d, 0, sizeof(*d));
1392 
1393 	dev_priv->uncore.fw_domains &= ~BIT(domain_id);
1394 }
1395 
1396 static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
1397 {
1398 	if (INTEL_GEN(dev_priv) <= 5 || intel_vgpu_active(dev_priv))
1399 		return;
1400 
1401 	if (IS_GEN(dev_priv, 6)) {
1402 		dev_priv->uncore.fw_reset = 0;
1403 		dev_priv->uncore.fw_set = FORCEWAKE_KERNEL;
1404 		dev_priv->uncore.fw_clear = 0;
1405 	} else {
1406 		/* WaRsClearFWBitsAtReset:bdw,skl */
1407 		dev_priv->uncore.fw_reset = _MASKED_BIT_DISABLE(0xffff);
1408 		dev_priv->uncore.fw_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
1409 		dev_priv->uncore.fw_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
1410 	}
1411 
1412 	if (INTEL_GEN(dev_priv) >= 11) {
1413 		int i;
1414 
1415 		dev_priv->uncore.funcs.force_wake_get =
1416 			fw_domains_get_with_fallback;
1417 		dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1418 		fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1419 			       FORCEWAKE_RENDER_GEN9,
1420 			       FORCEWAKE_ACK_RENDER_GEN9);
1421 		fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
1422 			       FORCEWAKE_BLITTER_GEN9,
1423 			       FORCEWAKE_ACK_BLITTER_GEN9);
1424 		for (i = 0; i < I915_MAX_VCS; i++) {
1425 			if (!HAS_ENGINE(dev_priv, _VCS(i)))
1426 				continue;
1427 
1428 			fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA_VDBOX0 + i,
1429 				       FORCEWAKE_MEDIA_VDBOX_GEN11(i),
1430 				       FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(i));
1431 		}
1432 		for (i = 0; i < I915_MAX_VECS; i++) {
1433 			if (!HAS_ENGINE(dev_priv, _VECS(i)))
1434 				continue;
1435 
1436 			fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA_VEBOX0 + i,
1437 				       FORCEWAKE_MEDIA_VEBOX_GEN11(i),
1438 				       FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i));
1439 		}
1440 	} else if (IS_GEN_RANGE(dev_priv, 9, 10)) {
1441 		dev_priv->uncore.funcs.force_wake_get =
1442 			fw_domains_get_with_fallback;
1443 		dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1444 		fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1445 			       FORCEWAKE_RENDER_GEN9,
1446 			       FORCEWAKE_ACK_RENDER_GEN9);
1447 		fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
1448 			       FORCEWAKE_BLITTER_GEN9,
1449 			       FORCEWAKE_ACK_BLITTER_GEN9);
1450 		fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1451 			       FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1452 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1453 		dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1454 		dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1455 		fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1456 			       FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1457 		fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1458 			       FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1459 	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1460 		dev_priv->uncore.funcs.force_wake_get =
1461 			fw_domains_get_with_thread_status;
1462 		dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1463 		fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1464 			       FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1465 	} else if (IS_IVYBRIDGE(dev_priv)) {
1466 		u32 ecobus;
1467 
1468 		/* IVB configs may use multi-threaded forcewake */
1469 
1470 		/* A small trick here - if the bios hasn't configured
1471 		 * MT forcewake, and if the device is in RC6, then
1472 		 * force_wake_mt_get will not wake the device and the
1473 		 * ECOBUS read will return zero. Which will be
1474 		 * (correctly) interpreted by the test below as MT
1475 		 * forcewake being disabled.
1476 		 */
1477 		dev_priv->uncore.funcs.force_wake_get =
1478 			fw_domains_get_with_thread_status;
1479 		dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1480 
1481 		/* We need to init first for ECOBUS access and then
1482 		 * determine later if we want to reinit, in case of MT access is
1483 		 * not working. In this stage we don't know which flavour this
1484 		 * ivb is, so it is better to reset also the gen6 fw registers
1485 		 * before the ecobus check.
1486 		 */
1487 
1488 		__raw_i915_write32(dev_priv, FORCEWAKE, 0);
1489 		__raw_posting_read(dev_priv, ECOBUS);
1490 
1491 		fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1492 			       FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1493 
1494 		spin_lock_irq(&dev_priv->uncore.lock);
1495 		fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_RENDER);
1496 		ecobus = __raw_i915_read32(dev_priv, ECOBUS);
1497 		fw_domains_put(dev_priv, FORCEWAKE_RENDER);
1498 		spin_unlock_irq(&dev_priv->uncore.lock);
1499 
1500 		if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1501 			DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1502 			DRM_INFO("when using vblank-synced partial screen updates.\n");
1503 			fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1504 				       FORCEWAKE, FORCEWAKE_ACK);
1505 		}
1506 	} else if (IS_GEN(dev_priv, 6)) {
1507 		dev_priv->uncore.funcs.force_wake_get =
1508 			fw_domains_get_with_thread_status;
1509 		dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1510 		fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1511 			       FORCEWAKE, FORCEWAKE_ACK);
1512 	}
1513 
1514 	/* All future platforms are expected to require complex power gating */
1515 	WARN_ON(dev_priv->uncore.fw_domains == 0);
1516 }
1517 
1518 #define ASSIGN_FW_DOMAINS_TABLE(d) \
1519 { \
1520 	dev_priv->uncore.fw_domains_table = \
1521 			(struct intel_forcewake_range *)(d); \
1522 	dev_priv->uncore.fw_domains_table_entries = ARRAY_SIZE((d)); \
1523 }
1524 
1525 static int i915_pmic_bus_access_notifier(struct notifier_block *nb,
1526 					 unsigned long action, void *data)
1527 {
1528 	struct drm_i915_private *dev_priv = container_of(nb,
1529 			struct drm_i915_private, uncore.pmic_bus_access_nb);
1530 
1531 	switch (action) {
1532 	case MBI_PMIC_BUS_ACCESS_BEGIN:
1533 		/*
1534 		 * forcewake all now to make sure that we don't need to do a
1535 		 * forcewake later which on systems where this notifier gets
1536 		 * called requires the punit to access to the shared pmic i2c
1537 		 * bus, which will be busy after this notification, leading to:
1538 		 * "render: timed out waiting for forcewake ack request."
1539 		 * errors.
1540 		 *
1541 		 * The notifier is unregistered during intel_runtime_suspend(),
1542 		 * so it's ok to access the HW here without holding a RPM
1543 		 * wake reference -> disable wakeref asserts for the time of
1544 		 * the access.
1545 		 */
1546 		disable_rpm_wakeref_asserts(dev_priv);
1547 		intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1548 		enable_rpm_wakeref_asserts(dev_priv);
1549 		break;
1550 	case MBI_PMIC_BUS_ACCESS_END:
1551 		intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1552 		break;
1553 	}
1554 
1555 	return NOTIFY_OK;
1556 }
1557 
1558 void intel_uncore_init(struct drm_i915_private *dev_priv)
1559 {
1560 	i915_check_vgpu(dev_priv);
1561 
1562 	intel_uncore_edram_detect(dev_priv);
1563 	intel_uncore_fw_domains_init(dev_priv);
1564 	__intel_uncore_early_sanitize(dev_priv, 0);
1565 
1566 	dev_priv->uncore.unclaimed_mmio_check = 1;
1567 	dev_priv->uncore.pmic_bus_access_nb.notifier_call =
1568 		i915_pmic_bus_access_notifier;
1569 
1570 	if (IS_GEN_RANGE(dev_priv, 2, 4) || intel_vgpu_active(dev_priv)) {
1571 		ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen2);
1572 		ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen2);
1573 	} else if (IS_GEN(dev_priv, 5)) {
1574 		ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen5);
1575 		ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen5);
1576 	} else if (IS_GEN_RANGE(dev_priv, 6, 7)) {
1577 		ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen6);
1578 
1579 		if (IS_VALLEYVIEW(dev_priv)) {
1580 			ASSIGN_FW_DOMAINS_TABLE(__vlv_fw_ranges);
1581 			ASSIGN_READ_MMIO_VFUNCS(dev_priv, fwtable);
1582 		} else {
1583 			ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen6);
1584 		}
1585 	} else if (IS_GEN(dev_priv, 8)) {
1586 		if (IS_CHERRYVIEW(dev_priv)) {
1587 			ASSIGN_FW_DOMAINS_TABLE(__chv_fw_ranges);
1588 			ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, fwtable);
1589 			ASSIGN_READ_MMIO_VFUNCS(dev_priv, fwtable);
1590 
1591 		} else {
1592 			ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen8);
1593 			ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen6);
1594 		}
1595 	} else if (IS_GEN_RANGE(dev_priv, 9, 10)) {
1596 		ASSIGN_FW_DOMAINS_TABLE(__gen9_fw_ranges);
1597 		ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, fwtable);
1598 		ASSIGN_READ_MMIO_VFUNCS(dev_priv, fwtable);
1599 	} else {
1600 		ASSIGN_FW_DOMAINS_TABLE(__gen11_fw_ranges);
1601 		ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen11_fwtable);
1602 		ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen11_fwtable);
1603 	}
1604 
1605 	iosf_mbi_register_pmic_bus_access_notifier(
1606 		&dev_priv->uncore.pmic_bus_access_nb);
1607 }
1608 
1609 /*
1610  * We might have detected that some engines are fused off after we initialized
1611  * the forcewake domains. Prune them, to make sure they only reference existing
1612  * engines.
1613  */
1614 void intel_uncore_prune(struct drm_i915_private *dev_priv)
1615 {
1616 	if (INTEL_GEN(dev_priv) >= 11) {
1617 		enum forcewake_domains fw_domains = dev_priv->uncore.fw_domains;
1618 		enum forcewake_domain_id domain_id;
1619 		int i;
1620 
1621 		for (i = 0; i < I915_MAX_VCS; i++) {
1622 			domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i;
1623 
1624 			if (HAS_ENGINE(dev_priv, _VCS(i)))
1625 				continue;
1626 
1627 			if (fw_domains & BIT(domain_id))
1628 				fw_domain_fini(dev_priv, domain_id);
1629 		}
1630 
1631 		for (i = 0; i < I915_MAX_VECS; i++) {
1632 			domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i;
1633 
1634 			if (HAS_ENGINE(dev_priv, _VECS(i)))
1635 				continue;
1636 
1637 			if (fw_domains & BIT(domain_id))
1638 				fw_domain_fini(dev_priv, domain_id);
1639 		}
1640 	}
1641 }
1642 
1643 void intel_uncore_fini(struct drm_i915_private *dev_priv)
1644 {
1645 	/* Paranoia: make sure we have disabled everything before we exit. */
1646 	intel_uncore_sanitize(dev_priv);
1647 
1648 	iosf_mbi_punit_acquire();
1649 	iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
1650 		&dev_priv->uncore.pmic_bus_access_nb);
1651 	intel_uncore_forcewake_reset(dev_priv);
1652 	iosf_mbi_punit_release();
1653 }
1654 
1655 static const struct reg_whitelist {
1656 	i915_reg_t offset_ldw;
1657 	i915_reg_t offset_udw;
1658 	u16 gen_mask;
1659 	u8 size;
1660 } reg_read_whitelist[] = { {
1661 	.offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
1662 	.offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
1663 	.gen_mask = INTEL_GEN_MASK(4, 11),
1664 	.size = 8
1665 } };
1666 
1667 int i915_reg_read_ioctl(struct drm_device *dev,
1668 			void *data, struct drm_file *file)
1669 {
1670 	struct drm_i915_private *dev_priv = to_i915(dev);
1671 	struct drm_i915_reg_read *reg = data;
1672 	struct reg_whitelist const *entry;
1673 	intel_wakeref_t wakeref;
1674 	unsigned int flags;
1675 	int remain;
1676 	int ret = 0;
1677 
1678 	entry = reg_read_whitelist;
1679 	remain = ARRAY_SIZE(reg_read_whitelist);
1680 	while (remain) {
1681 		u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw);
1682 
1683 		GEM_BUG_ON(!is_power_of_2(entry->size));
1684 		GEM_BUG_ON(entry->size > 8);
1685 		GEM_BUG_ON(entry_offset & (entry->size - 1));
1686 
1687 		if (INTEL_INFO(dev_priv)->gen_mask & entry->gen_mask &&
1688 		    entry_offset == (reg->offset & -entry->size))
1689 			break;
1690 		entry++;
1691 		remain--;
1692 	}
1693 
1694 	if (!remain)
1695 		return -EINVAL;
1696 
1697 	flags = reg->offset & (entry->size - 1);
1698 
1699 	with_intel_runtime_pm(dev_priv, wakeref) {
1700 		if (entry->size == 8 && flags == I915_REG_READ_8B_WA)
1701 			reg->val = I915_READ64_2x32(entry->offset_ldw,
1702 						    entry->offset_udw);
1703 		else if (entry->size == 8 && flags == 0)
1704 			reg->val = I915_READ64(entry->offset_ldw);
1705 		else if (entry->size == 4 && flags == 0)
1706 			reg->val = I915_READ(entry->offset_ldw);
1707 		else if (entry->size == 2 && flags == 0)
1708 			reg->val = I915_READ16(entry->offset_ldw);
1709 		else if (entry->size == 1 && flags == 0)
1710 			reg->val = I915_READ8(entry->offset_ldw);
1711 		else
1712 			ret = -EINVAL;
1713 	}
1714 
1715 	return ret;
1716 }
1717 
1718 /**
1719  * __intel_wait_for_register_fw - wait until register matches expected state
1720  * @dev_priv: the i915 device
1721  * @reg: the register to read
1722  * @mask: mask to apply to register value
1723  * @value: expected value
1724  * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait
1725  * @slow_timeout_ms: slow timeout in millisecond
1726  * @out_value: optional placeholder to hold registry value
1727  *
1728  * This routine waits until the target register @reg contains the expected
1729  * @value after applying the @mask, i.e. it waits until ::
1730  *
1731  *     (I915_READ_FW(reg) & mask) == value
1732  *
1733  * Otherwise, the wait will timeout after @slow_timeout_ms milliseconds.
1734  * For atomic context @slow_timeout_ms must be zero and @fast_timeout_us
1735  * must be not larger than 20,0000 microseconds.
1736  *
1737  * Note that this routine assumes the caller holds forcewake asserted, it is
1738  * not suitable for very long waits. See intel_wait_for_register() if you
1739  * wish to wait without holding forcewake for the duration (i.e. you expect
1740  * the wait to be slow).
1741  *
1742  * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
1743  */
1744 int __intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
1745 				 i915_reg_t reg,
1746 				 u32 mask,
1747 				 u32 value,
1748 				 unsigned int fast_timeout_us,
1749 				 unsigned int slow_timeout_ms,
1750 				 u32 *out_value)
1751 {
1752 	u32 uninitialized_var(reg_value);
1753 #define done (((reg_value = I915_READ_FW(reg)) & mask) == value)
1754 	int ret;
1755 
1756 	/* Catch any overuse of this function */
1757 	might_sleep_if(slow_timeout_ms);
1758 	GEM_BUG_ON(fast_timeout_us > 20000);
1759 
1760 	ret = -ETIMEDOUT;
1761 	if (fast_timeout_us && fast_timeout_us <= 20000)
1762 		ret = _wait_for_atomic(done, fast_timeout_us, 0);
1763 	if (ret && slow_timeout_ms)
1764 		ret = wait_for(done, slow_timeout_ms);
1765 
1766 	if (out_value)
1767 		*out_value = reg_value;
1768 
1769 	return ret;
1770 #undef done
1771 }
1772 
1773 /**
1774  * __intel_wait_for_register - wait until register matches expected state
1775  * @dev_priv: the i915 device
1776  * @reg: the register to read
1777  * @mask: mask to apply to register value
1778  * @value: expected value
1779  * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait
1780  * @slow_timeout_ms: slow timeout in millisecond
1781  * @out_value: optional placeholder to hold registry value
1782  *
1783  * This routine waits until the target register @reg contains the expected
1784  * @value after applying the @mask, i.e. it waits until ::
1785  *
1786  *     (I915_READ(reg) & mask) == value
1787  *
1788  * Otherwise, the wait will timeout after @timeout_ms milliseconds.
1789  *
1790  * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
1791  */
1792 int __intel_wait_for_register(struct drm_i915_private *dev_priv,
1793 			    i915_reg_t reg,
1794 			    u32 mask,
1795 			    u32 value,
1796 			    unsigned int fast_timeout_us,
1797 			    unsigned int slow_timeout_ms,
1798 			    u32 *out_value)
1799 {
1800 	unsigned fw =
1801 		intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ);
1802 	u32 reg_value;
1803 	int ret;
1804 
1805 	might_sleep_if(slow_timeout_ms);
1806 
1807 	spin_lock_irq(&dev_priv->uncore.lock);
1808 	intel_uncore_forcewake_get__locked(dev_priv, fw);
1809 
1810 	ret = __intel_wait_for_register_fw(dev_priv,
1811 					   reg, mask, value,
1812 					   fast_timeout_us, 0, &reg_value);
1813 
1814 	intel_uncore_forcewake_put__locked(dev_priv, fw);
1815 	spin_unlock_irq(&dev_priv->uncore.lock);
1816 
1817 	if (ret && slow_timeout_ms)
1818 		ret = __wait_for(reg_value = I915_READ_NOTRACE(reg),
1819 				 (reg_value & mask) == value,
1820 				 slow_timeout_ms * 1000, 10, 1000);
1821 
1822 	/* just trace the final value */
1823 	trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
1824 
1825 	if (out_value)
1826 		*out_value = reg_value;
1827 
1828 	return ret;
1829 }
1830 
1831 bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv)
1832 {
1833 	return check_for_unclaimed_mmio(dev_priv);
1834 }
1835 
1836 bool
1837 intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
1838 {
1839 	bool ret = false;
1840 
1841 	spin_lock_irq(&dev_priv->uncore.lock);
1842 
1843 	if (unlikely(dev_priv->uncore.unclaimed_mmio_check <= 0))
1844 		goto out;
1845 
1846 	if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) {
1847 		if (!i915_modparams.mmio_debug) {
1848 			DRM_DEBUG("Unclaimed register detected, "
1849 				  "enabling oneshot unclaimed register reporting. "
1850 				  "Please use i915.mmio_debug=N for more information.\n");
1851 			i915_modparams.mmio_debug++;
1852 		}
1853 		dev_priv->uncore.unclaimed_mmio_check--;
1854 		ret = true;
1855 	}
1856 
1857 out:
1858 	spin_unlock_irq(&dev_priv->uncore.lock);
1859 
1860 	return ret;
1861 }
1862 
1863 static enum forcewake_domains
1864 intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv,
1865 				i915_reg_t reg)
1866 {
1867 	u32 offset = i915_mmio_reg_offset(reg);
1868 	enum forcewake_domains fw_domains;
1869 
1870 	if (INTEL_GEN(dev_priv) >= 11) {
1871 		fw_domains = __gen11_fwtable_reg_read_fw_domains(offset);
1872 	} else if (HAS_FWTABLE(dev_priv)) {
1873 		fw_domains = __fwtable_reg_read_fw_domains(offset);
1874 	} else if (INTEL_GEN(dev_priv) >= 6) {
1875 		fw_domains = __gen6_reg_read_fw_domains(offset);
1876 	} else {
1877 		WARN_ON(!IS_GEN_RANGE(dev_priv, 2, 5));
1878 		fw_domains = 0;
1879 	}
1880 
1881 	WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains);
1882 
1883 	return fw_domains;
1884 }
1885 
1886 static enum forcewake_domains
1887 intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv,
1888 				 i915_reg_t reg)
1889 {
1890 	u32 offset = i915_mmio_reg_offset(reg);
1891 	enum forcewake_domains fw_domains;
1892 
1893 	if (INTEL_GEN(dev_priv) >= 11) {
1894 		fw_domains = __gen11_fwtable_reg_write_fw_domains(offset);
1895 	} else if (HAS_FWTABLE(dev_priv) && !IS_VALLEYVIEW(dev_priv)) {
1896 		fw_domains = __fwtable_reg_write_fw_domains(offset);
1897 	} else if (IS_GEN(dev_priv, 8)) {
1898 		fw_domains = __gen8_reg_write_fw_domains(offset);
1899 	} else if (IS_GEN_RANGE(dev_priv, 6, 7)) {
1900 		fw_domains = FORCEWAKE_RENDER;
1901 	} else {
1902 		WARN_ON(!IS_GEN_RANGE(dev_priv, 2, 5));
1903 		fw_domains = 0;
1904 	}
1905 
1906 	WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains);
1907 
1908 	return fw_domains;
1909 }
1910 
1911 /**
1912  * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
1913  * 				    a register
1914  * @dev_priv: pointer to struct drm_i915_private
1915  * @reg: register in question
1916  * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE
1917  *
1918  * Returns a set of forcewake domains required to be taken with for example
1919  * intel_uncore_forcewake_get for the specified register to be accessible in the
1920  * specified mode (read, write or read/write) with raw mmio accessors.
1921  *
1922  * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the
1923  * callers to do FIFO management on their own or risk losing writes.
1924  */
1925 enum forcewake_domains
1926 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
1927 			       i915_reg_t reg, unsigned int op)
1928 {
1929 	enum forcewake_domains fw_domains = 0;
1930 
1931 	WARN_ON(!op);
1932 
1933 	if (intel_vgpu_active(dev_priv))
1934 		return 0;
1935 
1936 	if (op & FW_REG_READ)
1937 		fw_domains = intel_uncore_forcewake_for_read(dev_priv, reg);
1938 
1939 	if (op & FW_REG_WRITE)
1940 		fw_domains |= intel_uncore_forcewake_for_write(dev_priv, reg);
1941 
1942 	return fw_domains;
1943 }
1944 
1945 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1946 #include "selftests/mock_uncore.c"
1947 #include "selftests/intel_uncore.c"
1948 #endif
1949