1 /* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #include <linux/pm_runtime.h> 25 #include <asm/iosf_mbi.h> 26 27 #include "i915_drv.h" 28 #include "i915_trace.h" 29 #include "i915_vgpu.h" 30 #include "intel_pm.h" 31 32 #define FORCEWAKE_ACK_TIMEOUT_MS 50 33 #define GT_FIFO_TIMEOUT_MS 10 34 35 #define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__)) 36 37 void 38 intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug) 39 { 40 spin_lock_init(&mmio_debug->lock); 41 mmio_debug->unclaimed_mmio_check = 1; 42 } 43 44 static void mmio_debug_suspend(struct intel_uncore_mmio_debug *mmio_debug) 45 { 46 lockdep_assert_held(&mmio_debug->lock); 47 48 /* Save and disable mmio debugging for the user bypass */ 49 if (!mmio_debug->suspend_count++) { 50 mmio_debug->saved_mmio_check = mmio_debug->unclaimed_mmio_check; 51 mmio_debug->unclaimed_mmio_check = 0; 52 } 53 } 54 55 static void mmio_debug_resume(struct intel_uncore_mmio_debug *mmio_debug) 56 { 57 lockdep_assert_held(&mmio_debug->lock); 58 59 if (!--mmio_debug->suspend_count) 60 mmio_debug->unclaimed_mmio_check = mmio_debug->saved_mmio_check; 61 } 62 63 static const char * const forcewake_domain_names[] = { 64 "render", 65 "blitter", 66 "media", 67 "vdbox0", 68 "vdbox1", 69 "vdbox2", 70 "vdbox3", 71 "vebox0", 72 "vebox1", 73 }; 74 75 const char * 76 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id) 77 { 78 BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT); 79 80 if (id >= 0 && id < FW_DOMAIN_ID_COUNT) 81 return forcewake_domain_names[id]; 82 83 WARN_ON(id); 84 85 return "unknown"; 86 } 87 88 #define fw_ack(d) readl((d)->reg_ack) 89 #define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set) 90 #define fw_clear(d, val) writel(_MASKED_BIT_DISABLE((val)), (d)->reg_set) 91 92 static inline void 93 fw_domain_reset(const struct intel_uncore_forcewake_domain *d) 94 { 95 /* 96 * We don't really know if the powerwell for the forcewake domain we are 97 * trying to reset here does exist at this point (engines could be fused 98 * off in ICL+), so no waiting for acks 99 */ 100 /* WaRsClearFWBitsAtReset:bdw,skl */ 101 fw_clear(d, 0xffff); 102 } 103 104 static inline void 105 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d) 106 { 107 GEM_BUG_ON(d->uncore->fw_domains_timer & d->mask); 108 d->uncore->fw_domains_timer |= d->mask; 109 d->wake_count++; 110 hrtimer_start_range_ns(&d->timer, 111 NSEC_PER_MSEC, 112 NSEC_PER_MSEC, 113 HRTIMER_MODE_REL); 114 } 115 116 static inline int 117 __wait_for_ack(const struct intel_uncore_forcewake_domain *d, 118 const u32 ack, 119 const u32 value) 120 { 121 return wait_for_atomic((fw_ack(d) & ack) == value, 122 FORCEWAKE_ACK_TIMEOUT_MS); 123 } 124 125 static inline int 126 wait_ack_clear(const struct intel_uncore_forcewake_domain *d, 127 const u32 ack) 128 { 129 return __wait_for_ack(d, ack, 0); 130 } 131 132 static inline int 133 wait_ack_set(const struct intel_uncore_forcewake_domain *d, 134 const u32 ack) 135 { 136 return __wait_for_ack(d, ack, ack); 137 } 138 139 static inline void 140 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d) 141 { 142 if (wait_ack_clear(d, FORCEWAKE_KERNEL)) { 143 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n", 144 intel_uncore_forcewake_domain_to_str(d->id)); 145 add_taint_for_CI(d->uncore->i915, TAINT_WARN); /* CI now unreliable */ 146 } 147 } 148 149 enum ack_type { 150 ACK_CLEAR = 0, 151 ACK_SET 152 }; 153 154 static int 155 fw_domain_wait_ack_with_fallback(const struct intel_uncore_forcewake_domain *d, 156 const enum ack_type type) 157 { 158 const u32 ack_bit = FORCEWAKE_KERNEL; 159 const u32 value = type == ACK_SET ? ack_bit : 0; 160 unsigned int pass; 161 bool ack_detected; 162 163 /* 164 * There is a possibility of driver's wake request colliding 165 * with hardware's own wake requests and that can cause 166 * hardware to not deliver the driver's ack message. 167 * 168 * Use a fallback bit toggle to kick the gpu state machine 169 * in the hope that the original ack will be delivered along with 170 * the fallback ack. 171 * 172 * This workaround is described in HSDES #1604254524 and it's known as: 173 * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl 174 * although the name is a bit misleading. 175 */ 176 177 pass = 1; 178 do { 179 wait_ack_clear(d, FORCEWAKE_KERNEL_FALLBACK); 180 181 fw_set(d, FORCEWAKE_KERNEL_FALLBACK); 182 /* Give gt some time to relax before the polling frenzy */ 183 udelay(10 * pass); 184 wait_ack_set(d, FORCEWAKE_KERNEL_FALLBACK); 185 186 ack_detected = (fw_ack(d) & ack_bit) == value; 187 188 fw_clear(d, FORCEWAKE_KERNEL_FALLBACK); 189 } while (!ack_detected && pass++ < 10); 190 191 DRM_DEBUG_DRIVER("%s had to use fallback to %s ack, 0x%x (passes %u)\n", 192 intel_uncore_forcewake_domain_to_str(d->id), 193 type == ACK_SET ? "set" : "clear", 194 fw_ack(d), 195 pass); 196 197 return ack_detected ? 0 : -ETIMEDOUT; 198 } 199 200 static inline void 201 fw_domain_wait_ack_clear_fallback(const struct intel_uncore_forcewake_domain *d) 202 { 203 if (likely(!wait_ack_clear(d, FORCEWAKE_KERNEL))) 204 return; 205 206 if (fw_domain_wait_ack_with_fallback(d, ACK_CLEAR)) 207 fw_domain_wait_ack_clear(d); 208 } 209 210 static inline void 211 fw_domain_get(const struct intel_uncore_forcewake_domain *d) 212 { 213 fw_set(d, FORCEWAKE_KERNEL); 214 } 215 216 static inline void 217 fw_domain_wait_ack_set(const struct intel_uncore_forcewake_domain *d) 218 { 219 if (wait_ack_set(d, FORCEWAKE_KERNEL)) { 220 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n", 221 intel_uncore_forcewake_domain_to_str(d->id)); 222 add_taint_for_CI(d->uncore->i915, TAINT_WARN); /* CI now unreliable */ 223 } 224 } 225 226 static inline void 227 fw_domain_wait_ack_set_fallback(const struct intel_uncore_forcewake_domain *d) 228 { 229 if (likely(!wait_ack_set(d, FORCEWAKE_KERNEL))) 230 return; 231 232 if (fw_domain_wait_ack_with_fallback(d, ACK_SET)) 233 fw_domain_wait_ack_set(d); 234 } 235 236 static inline void 237 fw_domain_put(const struct intel_uncore_forcewake_domain *d) 238 { 239 fw_clear(d, FORCEWAKE_KERNEL); 240 } 241 242 static void 243 fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains) 244 { 245 struct intel_uncore_forcewake_domain *d; 246 unsigned int tmp; 247 248 GEM_BUG_ON(fw_domains & ~uncore->fw_domains); 249 250 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) { 251 fw_domain_wait_ack_clear(d); 252 fw_domain_get(d); 253 } 254 255 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) 256 fw_domain_wait_ack_set(d); 257 258 uncore->fw_domains_active |= fw_domains; 259 } 260 261 static void 262 fw_domains_get_with_fallback(struct intel_uncore *uncore, 263 enum forcewake_domains fw_domains) 264 { 265 struct intel_uncore_forcewake_domain *d; 266 unsigned int tmp; 267 268 GEM_BUG_ON(fw_domains & ~uncore->fw_domains); 269 270 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) { 271 fw_domain_wait_ack_clear_fallback(d); 272 fw_domain_get(d); 273 } 274 275 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) 276 fw_domain_wait_ack_set_fallback(d); 277 278 uncore->fw_domains_active |= fw_domains; 279 } 280 281 static void 282 fw_domains_put(struct intel_uncore *uncore, enum forcewake_domains fw_domains) 283 { 284 struct intel_uncore_forcewake_domain *d; 285 unsigned int tmp; 286 287 GEM_BUG_ON(fw_domains & ~uncore->fw_domains); 288 289 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) 290 fw_domain_put(d); 291 292 uncore->fw_domains_active &= ~fw_domains; 293 } 294 295 static void 296 fw_domains_reset(struct intel_uncore *uncore, 297 enum forcewake_domains fw_domains) 298 { 299 struct intel_uncore_forcewake_domain *d; 300 unsigned int tmp; 301 302 if (!fw_domains) 303 return; 304 305 GEM_BUG_ON(fw_domains & ~uncore->fw_domains); 306 307 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) 308 fw_domain_reset(d); 309 } 310 311 static inline u32 gt_thread_status(struct intel_uncore *uncore) 312 { 313 u32 val; 314 315 val = __raw_uncore_read32(uncore, GEN6_GT_THREAD_STATUS_REG); 316 val &= GEN6_GT_THREAD_STATUS_CORE_MASK; 317 318 return val; 319 } 320 321 static void __gen6_gt_wait_for_thread_c0(struct intel_uncore *uncore) 322 { 323 /* 324 * w/a for a sporadic read returning 0 by waiting for the GT 325 * thread to wake up. 326 */ 327 drm_WARN_ONCE(&uncore->i915->drm, 328 wait_for_atomic_us(gt_thread_status(uncore) == 0, 5000), 329 "GT thread status wait timed out\n"); 330 } 331 332 static void fw_domains_get_with_thread_status(struct intel_uncore *uncore, 333 enum forcewake_domains fw_domains) 334 { 335 fw_domains_get(uncore, fw_domains); 336 337 /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */ 338 __gen6_gt_wait_for_thread_c0(uncore); 339 } 340 341 static inline u32 fifo_free_entries(struct intel_uncore *uncore) 342 { 343 u32 count = __raw_uncore_read32(uncore, GTFIFOCTL); 344 345 return count & GT_FIFO_FREE_ENTRIES_MASK; 346 } 347 348 static void __gen6_gt_wait_for_fifo(struct intel_uncore *uncore) 349 { 350 u32 n; 351 352 /* On VLV, FIFO will be shared by both SW and HW. 353 * So, we need to read the FREE_ENTRIES everytime */ 354 if (IS_VALLEYVIEW(uncore->i915)) 355 n = fifo_free_entries(uncore); 356 else 357 n = uncore->fifo_count; 358 359 if (n <= GT_FIFO_NUM_RESERVED_ENTRIES) { 360 if (wait_for_atomic((n = fifo_free_entries(uncore)) > 361 GT_FIFO_NUM_RESERVED_ENTRIES, 362 GT_FIFO_TIMEOUT_MS)) { 363 drm_dbg(&uncore->i915->drm, 364 "GT_FIFO timeout, entries: %u\n", n); 365 return; 366 } 367 } 368 369 uncore->fifo_count = n - 1; 370 } 371 372 static enum hrtimer_restart 373 intel_uncore_fw_release_timer(struct hrtimer *timer) 374 { 375 struct intel_uncore_forcewake_domain *domain = 376 container_of(timer, struct intel_uncore_forcewake_domain, timer); 377 struct intel_uncore *uncore = domain->uncore; 378 unsigned long irqflags; 379 380 assert_rpm_device_not_suspended(uncore->rpm); 381 382 if (xchg(&domain->active, false)) 383 return HRTIMER_RESTART; 384 385 spin_lock_irqsave(&uncore->lock, irqflags); 386 387 uncore->fw_domains_timer &= ~domain->mask; 388 389 GEM_BUG_ON(!domain->wake_count); 390 if (--domain->wake_count == 0) 391 uncore->funcs.force_wake_put(uncore, domain->mask); 392 393 spin_unlock_irqrestore(&uncore->lock, irqflags); 394 395 return HRTIMER_NORESTART; 396 } 397 398 /* Note callers must have acquired the PUNIT->PMIC bus, before calling this. */ 399 static unsigned int 400 intel_uncore_forcewake_reset(struct intel_uncore *uncore) 401 { 402 unsigned long irqflags; 403 struct intel_uncore_forcewake_domain *domain; 404 int retry_count = 100; 405 enum forcewake_domains fw, active_domains; 406 407 iosf_mbi_assert_punit_acquired(); 408 409 /* Hold uncore.lock across reset to prevent any register access 410 * with forcewake not set correctly. Wait until all pending 411 * timers are run before holding. 412 */ 413 while (1) { 414 unsigned int tmp; 415 416 active_domains = 0; 417 418 for_each_fw_domain(domain, uncore, tmp) { 419 smp_store_mb(domain->active, false); 420 if (hrtimer_cancel(&domain->timer) == 0) 421 continue; 422 423 intel_uncore_fw_release_timer(&domain->timer); 424 } 425 426 spin_lock_irqsave(&uncore->lock, irqflags); 427 428 for_each_fw_domain(domain, uncore, tmp) { 429 if (hrtimer_active(&domain->timer)) 430 active_domains |= domain->mask; 431 } 432 433 if (active_domains == 0) 434 break; 435 436 if (--retry_count == 0) { 437 drm_err(&uncore->i915->drm, "Timed out waiting for forcewake timers to finish\n"); 438 break; 439 } 440 441 spin_unlock_irqrestore(&uncore->lock, irqflags); 442 cond_resched(); 443 } 444 445 drm_WARN_ON(&uncore->i915->drm, active_domains); 446 447 fw = uncore->fw_domains_active; 448 if (fw) 449 uncore->funcs.force_wake_put(uncore, fw); 450 451 fw_domains_reset(uncore, uncore->fw_domains); 452 assert_forcewakes_inactive(uncore); 453 454 spin_unlock_irqrestore(&uncore->lock, irqflags); 455 456 return fw; /* track the lost user forcewake domains */ 457 } 458 459 static bool 460 fpga_check_for_unclaimed_mmio(struct intel_uncore *uncore) 461 { 462 u32 dbg; 463 464 dbg = __raw_uncore_read32(uncore, FPGA_DBG); 465 if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM))) 466 return false; 467 468 /* 469 * Bugs in PCI programming (or failing hardware) can occasionally cause 470 * us to lose access to the MMIO BAR. When this happens, register 471 * reads will come back with 0xFFFFFFFF for every register and things 472 * go bad very quickly. Let's try to detect that special case and at 473 * least try to print a more informative message about what has 474 * happened. 475 * 476 * During normal operation the FPGA_DBG register has several unused 477 * bits that will always read back as 0's so we can use them as canaries 478 * to recognize when MMIO accesses are just busted. 479 */ 480 if (unlikely(dbg == ~0)) 481 drm_err(&uncore->i915->drm, 482 "Lost access to MMIO BAR; all registers now read back as 0xFFFFFFFF!\n"); 483 484 __raw_uncore_write32(uncore, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); 485 486 return true; 487 } 488 489 static bool 490 vlv_check_for_unclaimed_mmio(struct intel_uncore *uncore) 491 { 492 u32 cer; 493 494 cer = __raw_uncore_read32(uncore, CLAIM_ER); 495 if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK)))) 496 return false; 497 498 __raw_uncore_write32(uncore, CLAIM_ER, CLAIM_ER_CLR); 499 500 return true; 501 } 502 503 static bool 504 gen6_check_for_fifo_debug(struct intel_uncore *uncore) 505 { 506 u32 fifodbg; 507 508 fifodbg = __raw_uncore_read32(uncore, GTFIFODBG); 509 510 if (unlikely(fifodbg)) { 511 drm_dbg(&uncore->i915->drm, "GTFIFODBG = 0x08%x\n", fifodbg); 512 __raw_uncore_write32(uncore, GTFIFODBG, fifodbg); 513 } 514 515 return fifodbg; 516 } 517 518 static bool 519 check_for_unclaimed_mmio(struct intel_uncore *uncore) 520 { 521 bool ret = false; 522 523 lockdep_assert_held(&uncore->debug->lock); 524 525 if (uncore->debug->suspend_count) 526 return false; 527 528 if (intel_uncore_has_fpga_dbg_unclaimed(uncore)) 529 ret |= fpga_check_for_unclaimed_mmio(uncore); 530 531 if (intel_uncore_has_dbg_unclaimed(uncore)) 532 ret |= vlv_check_for_unclaimed_mmio(uncore); 533 534 if (intel_uncore_has_fifo(uncore)) 535 ret |= gen6_check_for_fifo_debug(uncore); 536 537 return ret; 538 } 539 540 static void forcewake_early_sanitize(struct intel_uncore *uncore, 541 unsigned int restore_forcewake) 542 { 543 GEM_BUG_ON(!intel_uncore_has_forcewake(uncore)); 544 545 /* WaDisableShadowRegForCpd:chv */ 546 if (IS_CHERRYVIEW(uncore->i915)) { 547 __raw_uncore_write32(uncore, GTFIFOCTL, 548 __raw_uncore_read32(uncore, GTFIFOCTL) | 549 GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL | 550 GT_FIFO_CTL_RC6_POLICY_STALL); 551 } 552 553 iosf_mbi_punit_acquire(); 554 intel_uncore_forcewake_reset(uncore); 555 if (restore_forcewake) { 556 spin_lock_irq(&uncore->lock); 557 uncore->funcs.force_wake_get(uncore, restore_forcewake); 558 559 if (intel_uncore_has_fifo(uncore)) 560 uncore->fifo_count = fifo_free_entries(uncore); 561 spin_unlock_irq(&uncore->lock); 562 } 563 iosf_mbi_punit_release(); 564 } 565 566 void intel_uncore_suspend(struct intel_uncore *uncore) 567 { 568 if (!intel_uncore_has_forcewake(uncore)) 569 return; 570 571 iosf_mbi_punit_acquire(); 572 iosf_mbi_unregister_pmic_bus_access_notifier_unlocked( 573 &uncore->pmic_bus_access_nb); 574 uncore->fw_domains_saved = intel_uncore_forcewake_reset(uncore); 575 iosf_mbi_punit_release(); 576 } 577 578 void intel_uncore_resume_early(struct intel_uncore *uncore) 579 { 580 unsigned int restore_forcewake; 581 582 if (intel_uncore_unclaimed_mmio(uncore)) 583 drm_dbg(&uncore->i915->drm, "unclaimed mmio detected on resume, clearing\n"); 584 585 if (!intel_uncore_has_forcewake(uncore)) 586 return; 587 588 restore_forcewake = fetch_and_zero(&uncore->fw_domains_saved); 589 forcewake_early_sanitize(uncore, restore_forcewake); 590 591 iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb); 592 } 593 594 void intel_uncore_runtime_resume(struct intel_uncore *uncore) 595 { 596 if (!intel_uncore_has_forcewake(uncore)) 597 return; 598 599 iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb); 600 } 601 602 static void __intel_uncore_forcewake_get(struct intel_uncore *uncore, 603 enum forcewake_domains fw_domains) 604 { 605 struct intel_uncore_forcewake_domain *domain; 606 unsigned int tmp; 607 608 fw_domains &= uncore->fw_domains; 609 610 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { 611 if (domain->wake_count++) { 612 fw_domains &= ~domain->mask; 613 domain->active = true; 614 } 615 } 616 617 if (fw_domains) 618 uncore->funcs.force_wake_get(uncore, fw_domains); 619 } 620 621 /** 622 * intel_uncore_forcewake_get - grab forcewake domain references 623 * @uncore: the intel_uncore structure 624 * @fw_domains: forcewake domains to get reference on 625 * 626 * This function can be used get GT's forcewake domain references. 627 * Normal register access will handle the forcewake domains automatically. 628 * However if some sequence requires the GT to not power down a particular 629 * forcewake domains this function should be called at the beginning of the 630 * sequence. And subsequently the reference should be dropped by symmetric 631 * call to intel_unforce_forcewake_put(). Usually caller wants all the domains 632 * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL. 633 */ 634 void intel_uncore_forcewake_get(struct intel_uncore *uncore, 635 enum forcewake_domains fw_domains) 636 { 637 unsigned long irqflags; 638 639 if (!uncore->funcs.force_wake_get) 640 return; 641 642 assert_rpm_wakelock_held(uncore->rpm); 643 644 spin_lock_irqsave(&uncore->lock, irqflags); 645 __intel_uncore_forcewake_get(uncore, fw_domains); 646 spin_unlock_irqrestore(&uncore->lock, irqflags); 647 } 648 649 /** 650 * intel_uncore_forcewake_user_get - claim forcewake on behalf of userspace 651 * @uncore: the intel_uncore structure 652 * 653 * This function is a wrapper around intel_uncore_forcewake_get() to acquire 654 * the GT powerwell and in the process disable our debugging for the 655 * duration of userspace's bypass. 656 */ 657 void intel_uncore_forcewake_user_get(struct intel_uncore *uncore) 658 { 659 spin_lock_irq(&uncore->lock); 660 if (!uncore->user_forcewake_count++) { 661 intel_uncore_forcewake_get__locked(uncore, FORCEWAKE_ALL); 662 spin_lock(&uncore->debug->lock); 663 mmio_debug_suspend(uncore->debug); 664 spin_unlock(&uncore->debug->lock); 665 } 666 spin_unlock_irq(&uncore->lock); 667 } 668 669 /** 670 * intel_uncore_forcewake_user_put - release forcewake on behalf of userspace 671 * @uncore: the intel_uncore structure 672 * 673 * This function complements intel_uncore_forcewake_user_get() and releases 674 * the GT powerwell taken on behalf of the userspace bypass. 675 */ 676 void intel_uncore_forcewake_user_put(struct intel_uncore *uncore) 677 { 678 spin_lock_irq(&uncore->lock); 679 if (!--uncore->user_forcewake_count) { 680 spin_lock(&uncore->debug->lock); 681 mmio_debug_resume(uncore->debug); 682 683 if (check_for_unclaimed_mmio(uncore)) 684 drm_info(&uncore->i915->drm, 685 "Invalid mmio detected during user access\n"); 686 spin_unlock(&uncore->debug->lock); 687 688 intel_uncore_forcewake_put__locked(uncore, FORCEWAKE_ALL); 689 } 690 spin_unlock_irq(&uncore->lock); 691 } 692 693 /** 694 * intel_uncore_forcewake_get__locked - grab forcewake domain references 695 * @uncore: the intel_uncore structure 696 * @fw_domains: forcewake domains to get reference on 697 * 698 * See intel_uncore_forcewake_get(). This variant places the onus 699 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. 700 */ 701 void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore, 702 enum forcewake_domains fw_domains) 703 { 704 lockdep_assert_held(&uncore->lock); 705 706 if (!uncore->funcs.force_wake_get) 707 return; 708 709 __intel_uncore_forcewake_get(uncore, fw_domains); 710 } 711 712 static void __intel_uncore_forcewake_put(struct intel_uncore *uncore, 713 enum forcewake_domains fw_domains) 714 { 715 struct intel_uncore_forcewake_domain *domain; 716 unsigned int tmp; 717 718 fw_domains &= uncore->fw_domains; 719 720 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { 721 GEM_BUG_ON(!domain->wake_count); 722 723 if (--domain->wake_count) { 724 domain->active = true; 725 continue; 726 } 727 728 uncore->funcs.force_wake_put(uncore, domain->mask); 729 } 730 } 731 732 /** 733 * intel_uncore_forcewake_put - release a forcewake domain reference 734 * @uncore: the intel_uncore structure 735 * @fw_domains: forcewake domains to put references 736 * 737 * This function drops the device-level forcewakes for specified 738 * domains obtained by intel_uncore_forcewake_get(). 739 */ 740 void intel_uncore_forcewake_put(struct intel_uncore *uncore, 741 enum forcewake_domains fw_domains) 742 { 743 unsigned long irqflags; 744 745 if (!uncore->funcs.force_wake_put) 746 return; 747 748 spin_lock_irqsave(&uncore->lock, irqflags); 749 __intel_uncore_forcewake_put(uncore, fw_domains); 750 spin_unlock_irqrestore(&uncore->lock, irqflags); 751 } 752 753 /** 754 * intel_uncore_forcewake_flush - flush the delayed release 755 * @uncore: the intel_uncore structure 756 * @fw_domains: forcewake domains to flush 757 */ 758 void intel_uncore_forcewake_flush(struct intel_uncore *uncore, 759 enum forcewake_domains fw_domains) 760 { 761 struct intel_uncore_forcewake_domain *domain; 762 unsigned int tmp; 763 764 if (!uncore->funcs.force_wake_put) 765 return; 766 767 fw_domains &= uncore->fw_domains; 768 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { 769 WRITE_ONCE(domain->active, false); 770 if (hrtimer_cancel(&domain->timer)) 771 intel_uncore_fw_release_timer(&domain->timer); 772 } 773 } 774 775 /** 776 * intel_uncore_forcewake_put__locked - grab forcewake domain references 777 * @uncore: the intel_uncore structure 778 * @fw_domains: forcewake domains to get reference on 779 * 780 * See intel_uncore_forcewake_put(). This variant places the onus 781 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. 782 */ 783 void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore, 784 enum forcewake_domains fw_domains) 785 { 786 lockdep_assert_held(&uncore->lock); 787 788 if (!uncore->funcs.force_wake_put) 789 return; 790 791 __intel_uncore_forcewake_put(uncore, fw_domains); 792 } 793 794 void assert_forcewakes_inactive(struct intel_uncore *uncore) 795 { 796 if (!uncore->funcs.force_wake_get) 797 return; 798 799 drm_WARN(&uncore->i915->drm, uncore->fw_domains_active, 800 "Expected all fw_domains to be inactive, but %08x are still on\n", 801 uncore->fw_domains_active); 802 } 803 804 void assert_forcewakes_active(struct intel_uncore *uncore, 805 enum forcewake_domains fw_domains) 806 { 807 struct intel_uncore_forcewake_domain *domain; 808 unsigned int tmp; 809 810 if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) 811 return; 812 813 if (!uncore->funcs.force_wake_get) 814 return; 815 816 spin_lock_irq(&uncore->lock); 817 818 assert_rpm_wakelock_held(uncore->rpm); 819 820 fw_domains &= uncore->fw_domains; 821 drm_WARN(&uncore->i915->drm, fw_domains & ~uncore->fw_domains_active, 822 "Expected %08x fw_domains to be active, but %08x are off\n", 823 fw_domains, fw_domains & ~uncore->fw_domains_active); 824 825 /* 826 * Check that the caller has an explicit wakeref and we don't mistake 827 * it for the auto wakeref. 828 */ 829 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { 830 unsigned int actual = READ_ONCE(domain->wake_count); 831 unsigned int expect = 1; 832 833 if (uncore->fw_domains_timer & domain->mask) 834 expect++; /* pending automatic release */ 835 836 if (drm_WARN(&uncore->i915->drm, actual < expect, 837 "Expected domain %d to be held awake by caller, count=%d\n", 838 domain->id, actual)) 839 break; 840 } 841 842 spin_unlock_irq(&uncore->lock); 843 } 844 845 /* We give fast paths for the really cool registers */ 846 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000) 847 848 #define __gen6_reg_read_fw_domains(uncore, offset) \ 849 ({ \ 850 enum forcewake_domains __fwd; \ 851 if (NEEDS_FORCE_WAKE(offset)) \ 852 __fwd = FORCEWAKE_RENDER; \ 853 else \ 854 __fwd = 0; \ 855 __fwd; \ 856 }) 857 858 static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry) 859 { 860 if (offset < entry->start) 861 return -1; 862 else if (offset > entry->end) 863 return 1; 864 else 865 return 0; 866 } 867 868 /* Copied and "macroized" from lib/bsearch.c */ 869 #define BSEARCH(key, base, num, cmp) ({ \ 870 unsigned int start__ = 0, end__ = (num); \ 871 typeof(base) result__ = NULL; \ 872 while (start__ < end__) { \ 873 unsigned int mid__ = start__ + (end__ - start__) / 2; \ 874 int ret__ = (cmp)((key), (base) + mid__); \ 875 if (ret__ < 0) { \ 876 end__ = mid__; \ 877 } else if (ret__ > 0) { \ 878 start__ = mid__ + 1; \ 879 } else { \ 880 result__ = (base) + mid__; \ 881 break; \ 882 } \ 883 } \ 884 result__; \ 885 }) 886 887 static enum forcewake_domains 888 find_fw_domain(struct intel_uncore *uncore, u32 offset) 889 { 890 const struct intel_forcewake_range *entry; 891 892 entry = BSEARCH(offset, 893 uncore->fw_domains_table, 894 uncore->fw_domains_table_entries, 895 fw_range_cmp); 896 897 if (!entry) 898 return 0; 899 900 /* 901 * The list of FW domains depends on the SKU in gen11+ so we 902 * can't determine it statically. We use FORCEWAKE_ALL and 903 * translate it here to the list of available domains. 904 */ 905 if (entry->domains == FORCEWAKE_ALL) 906 return uncore->fw_domains; 907 908 drm_WARN(&uncore->i915->drm, entry->domains & ~uncore->fw_domains, 909 "Uninitialized forcewake domain(s) 0x%x accessed at 0x%x\n", 910 entry->domains & ~uncore->fw_domains, offset); 911 912 return entry->domains; 913 } 914 915 #define GEN_FW_RANGE(s, e, d) \ 916 { .start = (s), .end = (e), .domains = (d) } 917 918 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ 919 static const struct intel_forcewake_range __vlv_fw_ranges[] = { 920 GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER), 921 GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER), 922 GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER), 923 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA), 924 GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA), 925 GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER), 926 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA), 927 }; 928 929 #define __fwtable_reg_read_fw_domains(uncore, offset) \ 930 ({ \ 931 enum forcewake_domains __fwd = 0; \ 932 if (NEEDS_FORCE_WAKE((offset))) \ 933 __fwd = find_fw_domain(uncore, offset); \ 934 __fwd; \ 935 }) 936 937 #define __gen11_fwtable_reg_read_fw_domains(uncore, offset) \ 938 find_fw_domain(uncore, offset) 939 940 #define __gen12_fwtable_reg_read_fw_domains(uncore, offset) \ 941 find_fw_domain(uncore, offset) 942 943 /* *Must* be sorted by offset! See intel_shadow_table_check(). */ 944 static const i915_reg_t gen8_shadowed_regs[] = { 945 RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */ 946 GEN6_RPNSWREQ, /* 0xA008 */ 947 GEN6_RC_VIDEO_FREQ, /* 0xA00C */ 948 RING_TAIL(GEN6_BSD_RING_BASE), /* 0x12000 (base) */ 949 RING_TAIL(VEBOX_RING_BASE), /* 0x1a000 (base) */ 950 RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */ 951 /* TODO: Other registers are not yet used */ 952 }; 953 954 static const i915_reg_t gen11_shadowed_regs[] = { 955 RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */ 956 GEN6_RPNSWREQ, /* 0xA008 */ 957 GEN6_RC_VIDEO_FREQ, /* 0xA00C */ 958 RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */ 959 RING_TAIL(GEN11_BSD_RING_BASE), /* 0x1C0000 (base) */ 960 RING_TAIL(GEN11_BSD2_RING_BASE), /* 0x1C4000 (base) */ 961 RING_TAIL(GEN11_VEBOX_RING_BASE), /* 0x1C8000 (base) */ 962 RING_TAIL(GEN11_BSD3_RING_BASE), /* 0x1D0000 (base) */ 963 RING_TAIL(GEN11_BSD4_RING_BASE), /* 0x1D4000 (base) */ 964 RING_TAIL(GEN11_VEBOX2_RING_BASE), /* 0x1D8000 (base) */ 965 /* TODO: Other registers are not yet used */ 966 }; 967 968 static const i915_reg_t gen12_shadowed_regs[] = { 969 RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */ 970 GEN6_RPNSWREQ, /* 0xA008 */ 971 GEN6_RC_VIDEO_FREQ, /* 0xA00C */ 972 RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */ 973 RING_TAIL(GEN11_BSD_RING_BASE), /* 0x1C0000 (base) */ 974 RING_TAIL(GEN11_BSD2_RING_BASE), /* 0x1C4000 (base) */ 975 RING_TAIL(GEN11_VEBOX_RING_BASE), /* 0x1C8000 (base) */ 976 RING_TAIL(GEN11_BSD3_RING_BASE), /* 0x1D0000 (base) */ 977 RING_TAIL(GEN11_BSD4_RING_BASE), /* 0x1D4000 (base) */ 978 RING_TAIL(GEN11_VEBOX2_RING_BASE), /* 0x1D8000 (base) */ 979 /* TODO: Other registers are not yet used */ 980 }; 981 982 static int mmio_reg_cmp(u32 key, const i915_reg_t *reg) 983 { 984 u32 offset = i915_mmio_reg_offset(*reg); 985 986 if (key < offset) 987 return -1; 988 else if (key > offset) 989 return 1; 990 else 991 return 0; 992 } 993 994 #define __is_genX_shadowed(x) \ 995 static bool is_gen##x##_shadowed(u32 offset) \ 996 { \ 997 const i915_reg_t *regs = gen##x##_shadowed_regs; \ 998 return BSEARCH(offset, regs, ARRAY_SIZE(gen##x##_shadowed_regs), \ 999 mmio_reg_cmp); \ 1000 } 1001 1002 __is_genX_shadowed(8) 1003 __is_genX_shadowed(11) 1004 __is_genX_shadowed(12) 1005 1006 static enum forcewake_domains 1007 gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) 1008 { 1009 return FORCEWAKE_RENDER; 1010 } 1011 1012 #define __gen8_reg_write_fw_domains(uncore, offset) \ 1013 ({ \ 1014 enum forcewake_domains __fwd; \ 1015 if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \ 1016 __fwd = FORCEWAKE_RENDER; \ 1017 else \ 1018 __fwd = 0; \ 1019 __fwd; \ 1020 }) 1021 1022 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ 1023 static const struct intel_forcewake_range __chv_fw_ranges[] = { 1024 GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER), 1025 GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), 1026 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), 1027 GEN_FW_RANGE(0x8000, 0x82ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), 1028 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), 1029 GEN_FW_RANGE(0x8500, 0x85ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), 1030 GEN_FW_RANGE(0x8800, 0x88ff, FORCEWAKE_MEDIA), 1031 GEN_FW_RANGE(0x9000, 0xafff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), 1032 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), 1033 GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA), 1034 GEN_FW_RANGE(0xe000, 0xe7ff, FORCEWAKE_RENDER), 1035 GEN_FW_RANGE(0xf000, 0xffff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), 1036 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA), 1037 GEN_FW_RANGE(0x1a000, 0x1bfff, FORCEWAKE_MEDIA), 1038 GEN_FW_RANGE(0x1e800, 0x1e9ff, FORCEWAKE_MEDIA), 1039 GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA), 1040 }; 1041 1042 #define __fwtable_reg_write_fw_domains(uncore, offset) \ 1043 ({ \ 1044 enum forcewake_domains __fwd = 0; \ 1045 if (NEEDS_FORCE_WAKE((offset)) && !is_gen8_shadowed(offset)) \ 1046 __fwd = find_fw_domain(uncore, offset); \ 1047 __fwd; \ 1048 }) 1049 1050 #define __gen11_fwtable_reg_write_fw_domains(uncore, offset) \ 1051 ({ \ 1052 enum forcewake_domains __fwd = 0; \ 1053 const u32 __offset = (offset); \ 1054 if (!is_gen11_shadowed(__offset)) \ 1055 __fwd = find_fw_domain(uncore, __offset); \ 1056 __fwd; \ 1057 }) 1058 1059 #define __gen12_fwtable_reg_write_fw_domains(uncore, offset) \ 1060 ({ \ 1061 enum forcewake_domains __fwd = 0; \ 1062 const u32 __offset = (offset); \ 1063 if (!is_gen12_shadowed(__offset)) \ 1064 __fwd = find_fw_domain(uncore, __offset); \ 1065 __fwd; \ 1066 }) 1067 1068 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ 1069 static const struct intel_forcewake_range __gen9_fw_ranges[] = { 1070 GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_GT), 1071 GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */ 1072 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), 1073 GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT), 1074 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), 1075 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT), 1076 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), 1077 GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_GT), 1078 GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA), 1079 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), 1080 GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_GT), 1081 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), 1082 GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_GT), 1083 GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA), 1084 GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_GT), 1085 GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER), 1086 GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_GT), 1087 GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), 1088 GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_GT), 1089 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), 1090 GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_GT), 1091 GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA), 1092 GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_GT), 1093 GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER), 1094 GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_GT), 1095 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA), 1096 GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_GT), 1097 GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA), 1098 GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_GT), 1099 GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER), 1100 GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_GT), 1101 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA), 1102 }; 1103 1104 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ 1105 static const struct intel_forcewake_range __gen11_fw_ranges[] = { 1106 GEN_FW_RANGE(0x0, 0x1fff, 0), /* uncore range */ 1107 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), 1108 GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT), 1109 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), 1110 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT), 1111 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), 1112 GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT), 1113 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), 1114 GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_GT), 1115 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), 1116 GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_GT), 1117 GEN_FW_RANGE(0x8800, 0x8bff, 0), 1118 GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER), 1119 GEN_FW_RANGE(0x8d00, 0x94cf, FORCEWAKE_GT), 1120 GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER), 1121 GEN_FW_RANGE(0x9560, 0x95ff, 0), 1122 GEN_FW_RANGE(0x9600, 0xafff, FORCEWAKE_GT), 1123 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), 1124 GEN_FW_RANGE(0xb480, 0xdeff, FORCEWAKE_GT), 1125 GEN_FW_RANGE(0xdf00, 0xe8ff, FORCEWAKE_RENDER), 1126 GEN_FW_RANGE(0xe900, 0x16dff, FORCEWAKE_GT), 1127 GEN_FW_RANGE(0x16e00, 0x19fff, FORCEWAKE_RENDER), 1128 GEN_FW_RANGE(0x1a000, 0x23fff, FORCEWAKE_GT), 1129 GEN_FW_RANGE(0x24000, 0x2407f, 0), 1130 GEN_FW_RANGE(0x24080, 0x2417f, FORCEWAKE_GT), 1131 GEN_FW_RANGE(0x24180, 0x242ff, FORCEWAKE_RENDER), 1132 GEN_FW_RANGE(0x24300, 0x243ff, FORCEWAKE_GT), 1133 GEN_FW_RANGE(0x24400, 0x24fff, FORCEWAKE_RENDER), 1134 GEN_FW_RANGE(0x25000, 0x3ffff, FORCEWAKE_GT), 1135 GEN_FW_RANGE(0x40000, 0x1bffff, 0), 1136 GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), 1137 GEN_FW_RANGE(0x1c4000, 0x1c7fff, 0), 1138 GEN_FW_RANGE(0x1c8000, 0x1cffff, FORCEWAKE_MEDIA_VEBOX0), 1139 GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), 1140 GEN_FW_RANGE(0x1d4000, 0x1dbfff, 0) 1141 }; 1142 1143 /* 1144 * *Must* be sorted by offset ranges! See intel_fw_table_check(). 1145 * 1146 * Note that the spec lists several reserved/unused ranges that don't 1147 * actually contain any registers. In the table below we'll combine those 1148 * reserved ranges with either the preceding or following range to keep the 1149 * table small and lookups fast. 1150 */ 1151 static const struct intel_forcewake_range __gen12_fw_ranges[] = { 1152 GEN_FW_RANGE(0x0, 0x1fff, 0), /* 1153 0x0 - 0xaff: reserved 1154 0xb00 - 0x1fff: always on */ 1155 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), 1156 GEN_FW_RANGE(0x2700, 0x27ff, FORCEWAKE_GT), 1157 GEN_FW_RANGE(0x2800, 0x2aff, FORCEWAKE_RENDER), 1158 GEN_FW_RANGE(0x2b00, 0x2fff, FORCEWAKE_GT), 1159 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), 1160 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT), /* 1161 0x4000 - 0x48ff: gt 1162 0x4900 - 0x51ff: reserved */ 1163 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), /* 1164 0x5200 - 0x53ff: render 1165 0x5400 - 0x54ff: reserved 1166 0x5500 - 0x7fff: render */ 1167 GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT), 1168 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), 1169 GEN_FW_RANGE(0x8160, 0x81ff, 0), /* 1170 0x8160 - 0x817f: reserved 1171 0x8180 - 0x81ff: always on */ 1172 GEN_FW_RANGE(0x8200, 0x82ff, FORCEWAKE_GT), 1173 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), 1174 GEN_FW_RANGE(0x8500, 0x94cf, FORCEWAKE_GT), /* 1175 0x8500 - 0x87ff: gt 1176 0x8800 - 0x8fff: reserved 1177 0x9000 - 0x947f: gt 1178 0x9480 - 0x94cf: reserved */ 1179 GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER), 1180 GEN_FW_RANGE(0x9560, 0x97ff, 0), /* 1181 0x9560 - 0x95ff: always on 1182 0x9600 - 0x97ff: reserved */ 1183 GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_GT), 1184 GEN_FW_RANGE(0xb000, 0xb3ff, FORCEWAKE_RENDER), 1185 GEN_FW_RANGE(0xb400, 0xcfff, FORCEWAKE_GT), /* 1186 0xb400 - 0xbf7f: gt 1187 0xb480 - 0xbfff: reserved 1188 0xc000 - 0xcfff: gt */ 1189 GEN_FW_RANGE(0xd000, 0xd7ff, 0), 1190 GEN_FW_RANGE(0xd800, 0xd8ff, FORCEWAKE_RENDER), 1191 GEN_FW_RANGE(0xd900, 0xdbff, FORCEWAKE_GT), 1192 GEN_FW_RANGE(0xdc00, 0xefff, FORCEWAKE_RENDER), /* 1193 0xdc00 - 0xddff: render 1194 0xde00 - 0xde7f: reserved 1195 0xde80 - 0xe8ff: render 1196 0xe900 - 0xefff: reserved */ 1197 GEN_FW_RANGE(0xf000, 0x147ff, FORCEWAKE_GT), /* 1198 0xf000 - 0xffff: gt 1199 0x10000 - 0x147ff: reserved */ 1200 GEN_FW_RANGE(0x14800, 0x1ffff, FORCEWAKE_RENDER), /* 1201 0x14800 - 0x14fff: render 1202 0x15000 - 0x16dff: reserved 1203 0x16e00 - 0x1bfff: render 1204 0x1c000 - 0x1ffff: reserved */ 1205 GEN_FW_RANGE(0x20000, 0x20fff, FORCEWAKE_MEDIA_VDBOX0), 1206 GEN_FW_RANGE(0x21000, 0x21fff, FORCEWAKE_MEDIA_VDBOX2), 1207 GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT), 1208 GEN_FW_RANGE(0x24000, 0x2417f, 0), /* 1209 0x24000 - 0x2407f: always on 1210 0x24080 - 0x2417f: reserved */ 1211 GEN_FW_RANGE(0x24180, 0x249ff, FORCEWAKE_GT), /* 1212 0x24180 - 0x241ff: gt 1213 0x24200 - 0x249ff: reserved */ 1214 GEN_FW_RANGE(0x24a00, 0x251ff, FORCEWAKE_RENDER), /* 1215 0x24a00 - 0x24a7f: render 1216 0x24a80 - 0x251ff: reserved */ 1217 GEN_FW_RANGE(0x25200, 0x255ff, FORCEWAKE_GT), /* 1218 0x25200 - 0x252ff: gt 1219 0x25300 - 0x255ff: reserved */ 1220 GEN_FW_RANGE(0x25600, 0x2567f, FORCEWAKE_MEDIA_VDBOX0), 1221 GEN_FW_RANGE(0x25680, 0x259ff, FORCEWAKE_MEDIA_VDBOX2), /* 1222 0x25680 - 0x256ff: VD2 1223 0x25700 - 0x259ff: reserved */ 1224 GEN_FW_RANGE(0x25a00, 0x25a7f, FORCEWAKE_MEDIA_VDBOX0), 1225 GEN_FW_RANGE(0x25a80, 0x2ffff, FORCEWAKE_MEDIA_VDBOX2), /* 1226 0x25a80 - 0x25aff: VD2 1227 0x25b00 - 0x2ffff: reserved */ 1228 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT), 1229 GEN_FW_RANGE(0x40000, 0x1bffff, 0), 1230 GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /* 1231 0x1c0000 - 0x1c2bff: VD0 1232 0x1c2c00 - 0x1c2cff: reserved 1233 0x1c2d00 - 0x1c2dff: VD0 1234 0x1c2e00 - 0x1c3eff: reserved 1235 0x1c3f00 - 0x1c3fff: VD0 */ 1236 GEN_FW_RANGE(0x1c4000, 0x1c7fff, 0), 1237 GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), /* 1238 0x1c8000 - 0x1ca0ff: VE0 1239 0x1ca100 - 0x1cbeff: reserved 1240 0x1cbf00 - 0x1cbfff: VE0 */ 1241 GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX0), /* 1242 0x1cc000 - 0x1ccfff: VD0 1243 0x1cd000 - 0x1cffff: reserved */ 1244 GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), /* 1245 0x1d0000 - 0x1d2bff: VD2 1246 0x1d2c00 - 0x1d2cff: reserved 1247 0x1d2d00 - 0x1d2dff: VD2 1248 0x1d2e00 - 0x1d3eff: reserved 1249 0x1d3f00 - 0x1d3fff: VD2 */ 1250 }; 1251 1252 static void 1253 ilk_dummy_write(struct intel_uncore *uncore) 1254 { 1255 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up 1256 * the chip from rc6 before touching it for real. MI_MODE is masked, 1257 * hence harmless to write 0 into. */ 1258 __raw_uncore_write32(uncore, MI_MODE, 0); 1259 } 1260 1261 static void 1262 __unclaimed_reg_debug(struct intel_uncore *uncore, 1263 const i915_reg_t reg, 1264 const bool read, 1265 const bool before) 1266 { 1267 if (drm_WARN(&uncore->i915->drm, 1268 check_for_unclaimed_mmio(uncore) && !before, 1269 "Unclaimed %s register 0x%x\n", 1270 read ? "read from" : "write to", 1271 i915_mmio_reg_offset(reg))) 1272 /* Only report the first N failures */ 1273 uncore->i915->params.mmio_debug--; 1274 } 1275 1276 static inline void 1277 unclaimed_reg_debug(struct intel_uncore *uncore, 1278 const i915_reg_t reg, 1279 const bool read, 1280 const bool before) 1281 { 1282 if (likely(!uncore->i915->params.mmio_debug)) 1283 return; 1284 1285 /* interrupts are disabled and re-enabled around uncore->lock usage */ 1286 lockdep_assert_held(&uncore->lock); 1287 1288 if (before) 1289 spin_lock(&uncore->debug->lock); 1290 1291 __unclaimed_reg_debug(uncore, reg, read, before); 1292 1293 if (!before) 1294 spin_unlock(&uncore->debug->lock); 1295 } 1296 1297 #define __vgpu_read(x) \ 1298 static u##x \ 1299 vgpu_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \ 1300 u##x val = __raw_uncore_read##x(uncore, reg); \ 1301 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ 1302 return val; \ 1303 } 1304 __vgpu_read(8) 1305 __vgpu_read(16) 1306 __vgpu_read(32) 1307 __vgpu_read(64) 1308 1309 #define GEN2_READ_HEADER(x) \ 1310 u##x val = 0; \ 1311 assert_rpm_wakelock_held(uncore->rpm); 1312 1313 #define GEN2_READ_FOOTER \ 1314 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ 1315 return val 1316 1317 #define __gen2_read(x) \ 1318 static u##x \ 1319 gen2_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \ 1320 GEN2_READ_HEADER(x); \ 1321 val = __raw_uncore_read##x(uncore, reg); \ 1322 GEN2_READ_FOOTER; \ 1323 } 1324 1325 #define __gen5_read(x) \ 1326 static u##x \ 1327 gen5_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \ 1328 GEN2_READ_HEADER(x); \ 1329 ilk_dummy_write(uncore); \ 1330 val = __raw_uncore_read##x(uncore, reg); \ 1331 GEN2_READ_FOOTER; \ 1332 } 1333 1334 __gen5_read(8) 1335 __gen5_read(16) 1336 __gen5_read(32) 1337 __gen5_read(64) 1338 __gen2_read(8) 1339 __gen2_read(16) 1340 __gen2_read(32) 1341 __gen2_read(64) 1342 1343 #undef __gen5_read 1344 #undef __gen2_read 1345 1346 #undef GEN2_READ_FOOTER 1347 #undef GEN2_READ_HEADER 1348 1349 #define GEN6_READ_HEADER(x) \ 1350 u32 offset = i915_mmio_reg_offset(reg); \ 1351 unsigned long irqflags; \ 1352 u##x val = 0; \ 1353 assert_rpm_wakelock_held(uncore->rpm); \ 1354 spin_lock_irqsave(&uncore->lock, irqflags); \ 1355 unclaimed_reg_debug(uncore, reg, true, true) 1356 1357 #define GEN6_READ_FOOTER \ 1358 unclaimed_reg_debug(uncore, reg, true, false); \ 1359 spin_unlock_irqrestore(&uncore->lock, irqflags); \ 1360 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ 1361 return val 1362 1363 static noinline void ___force_wake_auto(struct intel_uncore *uncore, 1364 enum forcewake_domains fw_domains) 1365 { 1366 struct intel_uncore_forcewake_domain *domain; 1367 unsigned int tmp; 1368 1369 GEM_BUG_ON(fw_domains & ~uncore->fw_domains); 1370 1371 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) 1372 fw_domain_arm_timer(domain); 1373 1374 uncore->funcs.force_wake_get(uncore, fw_domains); 1375 } 1376 1377 static inline void __force_wake_auto(struct intel_uncore *uncore, 1378 enum forcewake_domains fw_domains) 1379 { 1380 GEM_BUG_ON(!fw_domains); 1381 1382 /* Turn on all requested but inactive supported forcewake domains. */ 1383 fw_domains &= uncore->fw_domains; 1384 fw_domains &= ~uncore->fw_domains_active; 1385 1386 if (fw_domains) 1387 ___force_wake_auto(uncore, fw_domains); 1388 } 1389 1390 #define __gen_read(func, x) \ 1391 static u##x \ 1392 func##_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \ 1393 enum forcewake_domains fw_engine; \ 1394 GEN6_READ_HEADER(x); \ 1395 fw_engine = __##func##_reg_read_fw_domains(uncore, offset); \ 1396 if (fw_engine) \ 1397 __force_wake_auto(uncore, fw_engine); \ 1398 val = __raw_uncore_read##x(uncore, reg); \ 1399 GEN6_READ_FOOTER; \ 1400 } 1401 1402 #define __gen_reg_read_funcs(func) \ 1403 static enum forcewake_domains \ 1404 func##_reg_read_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { \ 1405 return __##func##_reg_read_fw_domains(uncore, i915_mmio_reg_offset(reg)); \ 1406 } \ 1407 \ 1408 __gen_read(func, 8) \ 1409 __gen_read(func, 16) \ 1410 __gen_read(func, 32) \ 1411 __gen_read(func, 64) 1412 1413 __gen_reg_read_funcs(gen12_fwtable); 1414 __gen_reg_read_funcs(gen11_fwtable); 1415 __gen_reg_read_funcs(fwtable); 1416 __gen_reg_read_funcs(gen6); 1417 1418 #undef __gen_reg_read_funcs 1419 #undef GEN6_READ_FOOTER 1420 #undef GEN6_READ_HEADER 1421 1422 #define GEN2_WRITE_HEADER \ 1423 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ 1424 assert_rpm_wakelock_held(uncore->rpm); \ 1425 1426 #define GEN2_WRITE_FOOTER 1427 1428 #define __gen2_write(x) \ 1429 static void \ 1430 gen2_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ 1431 GEN2_WRITE_HEADER; \ 1432 __raw_uncore_write##x(uncore, reg, val); \ 1433 GEN2_WRITE_FOOTER; \ 1434 } 1435 1436 #define __gen5_write(x) \ 1437 static void \ 1438 gen5_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ 1439 GEN2_WRITE_HEADER; \ 1440 ilk_dummy_write(uncore); \ 1441 __raw_uncore_write##x(uncore, reg, val); \ 1442 GEN2_WRITE_FOOTER; \ 1443 } 1444 1445 __gen5_write(8) 1446 __gen5_write(16) 1447 __gen5_write(32) 1448 __gen2_write(8) 1449 __gen2_write(16) 1450 __gen2_write(32) 1451 1452 #undef __gen5_write 1453 #undef __gen2_write 1454 1455 #undef GEN2_WRITE_FOOTER 1456 #undef GEN2_WRITE_HEADER 1457 1458 #define GEN6_WRITE_HEADER \ 1459 u32 offset = i915_mmio_reg_offset(reg); \ 1460 unsigned long irqflags; \ 1461 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ 1462 assert_rpm_wakelock_held(uncore->rpm); \ 1463 spin_lock_irqsave(&uncore->lock, irqflags); \ 1464 unclaimed_reg_debug(uncore, reg, false, true) 1465 1466 #define GEN6_WRITE_FOOTER \ 1467 unclaimed_reg_debug(uncore, reg, false, false); \ 1468 spin_unlock_irqrestore(&uncore->lock, irqflags) 1469 1470 #define __gen6_write(x) \ 1471 static void \ 1472 gen6_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ 1473 GEN6_WRITE_HEADER; \ 1474 if (NEEDS_FORCE_WAKE(offset)) \ 1475 __gen6_gt_wait_for_fifo(uncore); \ 1476 __raw_uncore_write##x(uncore, reg, val); \ 1477 GEN6_WRITE_FOOTER; \ 1478 } 1479 __gen6_write(8) 1480 __gen6_write(16) 1481 __gen6_write(32) 1482 1483 #define __gen_write(func, x) \ 1484 static void \ 1485 func##_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ 1486 enum forcewake_domains fw_engine; \ 1487 GEN6_WRITE_HEADER; \ 1488 fw_engine = __##func##_reg_write_fw_domains(uncore, offset); \ 1489 if (fw_engine) \ 1490 __force_wake_auto(uncore, fw_engine); \ 1491 __raw_uncore_write##x(uncore, reg, val); \ 1492 GEN6_WRITE_FOOTER; \ 1493 } 1494 1495 #define __gen_reg_write_funcs(func) \ 1496 static enum forcewake_domains \ 1497 func##_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { \ 1498 return __##func##_reg_write_fw_domains(uncore, i915_mmio_reg_offset(reg)); \ 1499 } \ 1500 \ 1501 __gen_write(func, 8) \ 1502 __gen_write(func, 16) \ 1503 __gen_write(func, 32) 1504 1505 __gen_reg_write_funcs(gen12_fwtable); 1506 __gen_reg_write_funcs(gen11_fwtable); 1507 __gen_reg_write_funcs(fwtable); 1508 __gen_reg_write_funcs(gen8); 1509 1510 #undef __gen_reg_write_funcs 1511 #undef GEN6_WRITE_FOOTER 1512 #undef GEN6_WRITE_HEADER 1513 1514 #define __vgpu_write(x) \ 1515 static void \ 1516 vgpu_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ 1517 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ 1518 __raw_uncore_write##x(uncore, reg, val); \ 1519 } 1520 __vgpu_write(8) 1521 __vgpu_write(16) 1522 __vgpu_write(32) 1523 1524 #define ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, x) \ 1525 do { \ 1526 (uncore)->funcs.mmio_writeb = x##_write8; \ 1527 (uncore)->funcs.mmio_writew = x##_write16; \ 1528 (uncore)->funcs.mmio_writel = x##_write32; \ 1529 } while (0) 1530 1531 #define ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x) \ 1532 do { \ 1533 (uncore)->funcs.mmio_readb = x##_read8; \ 1534 (uncore)->funcs.mmio_readw = x##_read16; \ 1535 (uncore)->funcs.mmio_readl = x##_read32; \ 1536 (uncore)->funcs.mmio_readq = x##_read64; \ 1537 } while (0) 1538 1539 #define ASSIGN_WRITE_MMIO_VFUNCS(uncore, x) \ 1540 do { \ 1541 ASSIGN_RAW_WRITE_MMIO_VFUNCS((uncore), x); \ 1542 (uncore)->funcs.write_fw_domains = x##_reg_write_fw_domains; \ 1543 } while (0) 1544 1545 #define ASSIGN_READ_MMIO_VFUNCS(uncore, x) \ 1546 do { \ 1547 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x); \ 1548 (uncore)->funcs.read_fw_domains = x##_reg_read_fw_domains; \ 1549 } while (0) 1550 1551 static int __fw_domain_init(struct intel_uncore *uncore, 1552 enum forcewake_domain_id domain_id, 1553 i915_reg_t reg_set, 1554 i915_reg_t reg_ack) 1555 { 1556 struct intel_uncore_forcewake_domain *d; 1557 1558 GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT); 1559 GEM_BUG_ON(uncore->fw_domain[domain_id]); 1560 1561 if (i915_inject_probe_failure(uncore->i915)) 1562 return -ENOMEM; 1563 1564 d = kzalloc(sizeof(*d), GFP_KERNEL); 1565 if (!d) 1566 return -ENOMEM; 1567 1568 drm_WARN_ON(&uncore->i915->drm, !i915_mmio_reg_valid(reg_set)); 1569 drm_WARN_ON(&uncore->i915->drm, !i915_mmio_reg_valid(reg_ack)); 1570 1571 d->uncore = uncore; 1572 d->wake_count = 0; 1573 d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set); 1574 d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack); 1575 1576 d->id = domain_id; 1577 1578 BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER)); 1579 BUILD_BUG_ON(FORCEWAKE_GT != (1 << FW_DOMAIN_ID_GT)); 1580 BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA)); 1581 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX0)); 1582 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX1)); 1583 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX2)); 1584 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX3)); 1585 BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX0)); 1586 BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX1)); 1587 1588 d->mask = BIT(domain_id); 1589 1590 hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 1591 d->timer.function = intel_uncore_fw_release_timer; 1592 1593 uncore->fw_domains |= BIT(domain_id); 1594 1595 fw_domain_reset(d); 1596 1597 uncore->fw_domain[domain_id] = d; 1598 1599 return 0; 1600 } 1601 1602 static void fw_domain_fini(struct intel_uncore *uncore, 1603 enum forcewake_domain_id domain_id) 1604 { 1605 struct intel_uncore_forcewake_domain *d; 1606 1607 GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT); 1608 1609 d = fetch_and_zero(&uncore->fw_domain[domain_id]); 1610 if (!d) 1611 return; 1612 1613 uncore->fw_domains &= ~BIT(domain_id); 1614 drm_WARN_ON(&uncore->i915->drm, d->wake_count); 1615 drm_WARN_ON(&uncore->i915->drm, hrtimer_cancel(&d->timer)); 1616 kfree(d); 1617 } 1618 1619 static void intel_uncore_fw_domains_fini(struct intel_uncore *uncore) 1620 { 1621 struct intel_uncore_forcewake_domain *d; 1622 int tmp; 1623 1624 for_each_fw_domain(d, uncore, tmp) 1625 fw_domain_fini(uncore, d->id); 1626 } 1627 1628 static int intel_uncore_fw_domains_init(struct intel_uncore *uncore) 1629 { 1630 struct drm_i915_private *i915 = uncore->i915; 1631 int ret = 0; 1632 1633 GEM_BUG_ON(!intel_uncore_has_forcewake(uncore)); 1634 1635 #define fw_domain_init(uncore__, id__, set__, ack__) \ 1636 (ret ?: (ret = __fw_domain_init((uncore__), (id__), (set__), (ack__)))) 1637 1638 if (GRAPHICS_VER(i915) >= 11) { 1639 /* we'll prune the domains of missing engines later */ 1640 intel_engine_mask_t emask = INTEL_INFO(i915)->platform_engine_mask; 1641 int i; 1642 1643 uncore->funcs.force_wake_get = fw_domains_get_with_fallback; 1644 uncore->funcs.force_wake_put = fw_domains_put; 1645 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, 1646 FORCEWAKE_RENDER_GEN9, 1647 FORCEWAKE_ACK_RENDER_GEN9); 1648 fw_domain_init(uncore, FW_DOMAIN_ID_GT, 1649 FORCEWAKE_GT_GEN9, 1650 FORCEWAKE_ACK_GT_GEN9); 1651 1652 for (i = 0; i < I915_MAX_VCS; i++) { 1653 if (!__HAS_ENGINE(emask, _VCS(i))) 1654 continue; 1655 1656 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VDBOX0 + i, 1657 FORCEWAKE_MEDIA_VDBOX_GEN11(i), 1658 FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(i)); 1659 } 1660 for (i = 0; i < I915_MAX_VECS; i++) { 1661 if (!__HAS_ENGINE(emask, _VECS(i))) 1662 continue; 1663 1664 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VEBOX0 + i, 1665 FORCEWAKE_MEDIA_VEBOX_GEN11(i), 1666 FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i)); 1667 } 1668 } else if (IS_GRAPHICS_VER(i915, 9, 10)) { 1669 uncore->funcs.force_wake_get = fw_domains_get_with_fallback; 1670 uncore->funcs.force_wake_put = fw_domains_put; 1671 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, 1672 FORCEWAKE_RENDER_GEN9, 1673 FORCEWAKE_ACK_RENDER_GEN9); 1674 fw_domain_init(uncore, FW_DOMAIN_ID_GT, 1675 FORCEWAKE_GT_GEN9, 1676 FORCEWAKE_ACK_GT_GEN9); 1677 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA, 1678 FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9); 1679 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 1680 uncore->funcs.force_wake_get = fw_domains_get; 1681 uncore->funcs.force_wake_put = fw_domains_put; 1682 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, 1683 FORCEWAKE_VLV, FORCEWAKE_ACK_VLV); 1684 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA, 1685 FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV); 1686 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 1687 uncore->funcs.force_wake_get = 1688 fw_domains_get_with_thread_status; 1689 uncore->funcs.force_wake_put = fw_domains_put; 1690 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, 1691 FORCEWAKE_MT, FORCEWAKE_ACK_HSW); 1692 } else if (IS_IVYBRIDGE(i915)) { 1693 u32 ecobus; 1694 1695 /* IVB configs may use multi-threaded forcewake */ 1696 1697 /* A small trick here - if the bios hasn't configured 1698 * MT forcewake, and if the device is in RC6, then 1699 * force_wake_mt_get will not wake the device and the 1700 * ECOBUS read will return zero. Which will be 1701 * (correctly) interpreted by the test below as MT 1702 * forcewake being disabled. 1703 */ 1704 uncore->funcs.force_wake_get = 1705 fw_domains_get_with_thread_status; 1706 uncore->funcs.force_wake_put = fw_domains_put; 1707 1708 /* We need to init first for ECOBUS access and then 1709 * determine later if we want to reinit, in case of MT access is 1710 * not working. In this stage we don't know which flavour this 1711 * ivb is, so it is better to reset also the gen6 fw registers 1712 * before the ecobus check. 1713 */ 1714 1715 __raw_uncore_write32(uncore, FORCEWAKE, 0); 1716 __raw_posting_read(uncore, ECOBUS); 1717 1718 ret = __fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, 1719 FORCEWAKE_MT, FORCEWAKE_MT_ACK); 1720 if (ret) 1721 goto out; 1722 1723 spin_lock_irq(&uncore->lock); 1724 fw_domains_get_with_thread_status(uncore, FORCEWAKE_RENDER); 1725 ecobus = __raw_uncore_read32(uncore, ECOBUS); 1726 fw_domains_put(uncore, FORCEWAKE_RENDER); 1727 spin_unlock_irq(&uncore->lock); 1728 1729 if (!(ecobus & FORCEWAKE_MT_ENABLE)) { 1730 drm_info(&i915->drm, "No MT forcewake available on Ivybridge, this can result in issues\n"); 1731 drm_info(&i915->drm, "when using vblank-synced partial screen updates.\n"); 1732 fw_domain_fini(uncore, FW_DOMAIN_ID_RENDER); 1733 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, 1734 FORCEWAKE, FORCEWAKE_ACK); 1735 } 1736 } else if (GRAPHICS_VER(i915) == 6) { 1737 uncore->funcs.force_wake_get = 1738 fw_domains_get_with_thread_status; 1739 uncore->funcs.force_wake_put = fw_domains_put; 1740 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, 1741 FORCEWAKE, FORCEWAKE_ACK); 1742 } 1743 1744 #undef fw_domain_init 1745 1746 /* All future platforms are expected to require complex power gating */ 1747 drm_WARN_ON(&i915->drm, !ret && uncore->fw_domains == 0); 1748 1749 out: 1750 if (ret) 1751 intel_uncore_fw_domains_fini(uncore); 1752 1753 return ret; 1754 } 1755 1756 #define ASSIGN_FW_DOMAINS_TABLE(uncore, d) \ 1757 { \ 1758 (uncore)->fw_domains_table = \ 1759 (struct intel_forcewake_range *)(d); \ 1760 (uncore)->fw_domains_table_entries = ARRAY_SIZE((d)); \ 1761 } 1762 1763 static int i915_pmic_bus_access_notifier(struct notifier_block *nb, 1764 unsigned long action, void *data) 1765 { 1766 struct intel_uncore *uncore = container_of(nb, 1767 struct intel_uncore, pmic_bus_access_nb); 1768 1769 switch (action) { 1770 case MBI_PMIC_BUS_ACCESS_BEGIN: 1771 /* 1772 * forcewake all now to make sure that we don't need to do a 1773 * forcewake later which on systems where this notifier gets 1774 * called requires the punit to access to the shared pmic i2c 1775 * bus, which will be busy after this notification, leading to: 1776 * "render: timed out waiting for forcewake ack request." 1777 * errors. 1778 * 1779 * The notifier is unregistered during intel_runtime_suspend(), 1780 * so it's ok to access the HW here without holding a RPM 1781 * wake reference -> disable wakeref asserts for the time of 1782 * the access. 1783 */ 1784 disable_rpm_wakeref_asserts(uncore->rpm); 1785 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 1786 enable_rpm_wakeref_asserts(uncore->rpm); 1787 break; 1788 case MBI_PMIC_BUS_ACCESS_END: 1789 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 1790 break; 1791 } 1792 1793 return NOTIFY_OK; 1794 } 1795 1796 static int uncore_mmio_setup(struct intel_uncore *uncore) 1797 { 1798 struct drm_i915_private *i915 = uncore->i915; 1799 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 1800 int mmio_bar; 1801 int mmio_size; 1802 1803 mmio_bar = GRAPHICS_VER(i915) == 2 ? 1 : 0; 1804 /* 1805 * Before gen4, the registers and the GTT are behind different BARs. 1806 * However, from gen4 onwards, the registers and the GTT are shared 1807 * in the same BAR, so we want to restrict this ioremap from 1808 * clobbering the GTT which we want ioremap_wc instead. Fortunately, 1809 * the register BAR remains the same size for all the earlier 1810 * generations up to Ironlake. 1811 * For dgfx chips register range is expanded to 4MB. 1812 */ 1813 if (GRAPHICS_VER(i915) < 5) 1814 mmio_size = 512 * 1024; 1815 else if (IS_DGFX(i915)) 1816 mmio_size = 4 * 1024 * 1024; 1817 else 1818 mmio_size = 2 * 1024 * 1024; 1819 1820 uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size); 1821 if (uncore->regs == NULL) { 1822 drm_err(&i915->drm, "failed to map registers\n"); 1823 return -EIO; 1824 } 1825 1826 return 0; 1827 } 1828 1829 static void uncore_mmio_cleanup(struct intel_uncore *uncore) 1830 { 1831 struct pci_dev *pdev = to_pci_dev(uncore->i915->drm.dev); 1832 1833 pci_iounmap(pdev, uncore->regs); 1834 } 1835 1836 void intel_uncore_init_early(struct intel_uncore *uncore, 1837 struct drm_i915_private *i915) 1838 { 1839 spin_lock_init(&uncore->lock); 1840 uncore->i915 = i915; 1841 uncore->rpm = &i915->runtime_pm; 1842 uncore->debug = &i915->mmio_debug; 1843 } 1844 1845 static void uncore_raw_init(struct intel_uncore *uncore) 1846 { 1847 GEM_BUG_ON(intel_uncore_has_forcewake(uncore)); 1848 1849 if (intel_vgpu_active(uncore->i915)) { 1850 ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, vgpu); 1851 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, vgpu); 1852 } else if (GRAPHICS_VER(uncore->i915) == 5) { 1853 ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen5); 1854 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen5); 1855 } else { 1856 ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen2); 1857 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen2); 1858 } 1859 } 1860 1861 static int uncore_forcewake_init(struct intel_uncore *uncore) 1862 { 1863 struct drm_i915_private *i915 = uncore->i915; 1864 int ret; 1865 1866 GEM_BUG_ON(!intel_uncore_has_forcewake(uncore)); 1867 1868 ret = intel_uncore_fw_domains_init(uncore); 1869 if (ret) 1870 return ret; 1871 forcewake_early_sanitize(uncore, 0); 1872 1873 if (IS_GRAPHICS_VER(i915, 6, 7)) { 1874 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6); 1875 1876 if (IS_VALLEYVIEW(i915)) { 1877 ASSIGN_FW_DOMAINS_TABLE(uncore, __vlv_fw_ranges); 1878 ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable); 1879 } else { 1880 ASSIGN_READ_MMIO_VFUNCS(uncore, gen6); 1881 } 1882 } else if (GRAPHICS_VER(i915) == 8) { 1883 if (IS_CHERRYVIEW(i915)) { 1884 ASSIGN_FW_DOMAINS_TABLE(uncore, __chv_fw_ranges); 1885 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); 1886 ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable); 1887 } else { 1888 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen8); 1889 ASSIGN_READ_MMIO_VFUNCS(uncore, gen6); 1890 } 1891 } else if (IS_GRAPHICS_VER(i915, 9, 10)) { 1892 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen9_fw_ranges); 1893 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); 1894 ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable); 1895 } else if (GRAPHICS_VER(i915) == 11) { 1896 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen11_fw_ranges); 1897 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen11_fwtable); 1898 ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable); 1899 } else { 1900 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen12_fw_ranges); 1901 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen12_fwtable); 1902 ASSIGN_READ_MMIO_VFUNCS(uncore, gen12_fwtable); 1903 } 1904 1905 uncore->pmic_bus_access_nb.notifier_call = i915_pmic_bus_access_notifier; 1906 iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb); 1907 1908 return 0; 1909 } 1910 1911 int intel_uncore_init_mmio(struct intel_uncore *uncore) 1912 { 1913 struct drm_i915_private *i915 = uncore->i915; 1914 int ret; 1915 1916 ret = uncore_mmio_setup(uncore); 1917 if (ret) 1918 return ret; 1919 1920 /* 1921 * The boot firmware initializes local memory and assesses its health. 1922 * If memory training fails, the punit will have been instructed to 1923 * keep the GT powered down; we won't be able to communicate with it 1924 * and we should not continue with driver initialization. 1925 */ 1926 if (IS_DGFX(i915) && 1927 !(__raw_uncore_read32(uncore, GU_CNTL) & LMEM_INIT)) { 1928 drm_err(&i915->drm, "LMEM not initialized by firmware\n"); 1929 return -ENODEV; 1930 } 1931 1932 if (INTEL_GEN(i915) > 5 && !intel_vgpu_active(i915)) 1933 uncore->flags |= UNCORE_HAS_FORCEWAKE; 1934 1935 if (!intel_uncore_has_forcewake(uncore)) { 1936 uncore_raw_init(uncore); 1937 } else { 1938 ret = uncore_forcewake_init(uncore); 1939 if (ret) 1940 goto out_mmio_cleanup; 1941 } 1942 1943 /* make sure fw funcs are set if and only if we have fw*/ 1944 GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.force_wake_get); 1945 GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.force_wake_put); 1946 GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.read_fw_domains); 1947 GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.write_fw_domains); 1948 1949 if (HAS_FPGA_DBG_UNCLAIMED(i915)) 1950 uncore->flags |= UNCORE_HAS_FPGA_DBG_UNCLAIMED; 1951 1952 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) 1953 uncore->flags |= UNCORE_HAS_DBG_UNCLAIMED; 1954 1955 if (IS_GRAPHICS_VER(i915, 6, 7)) 1956 uncore->flags |= UNCORE_HAS_FIFO; 1957 1958 /* clear out unclaimed reg detection bit */ 1959 if (intel_uncore_unclaimed_mmio(uncore)) 1960 drm_dbg(&i915->drm, "unclaimed mmio detected on uncore init, clearing\n"); 1961 1962 return 0; 1963 1964 out_mmio_cleanup: 1965 uncore_mmio_cleanup(uncore); 1966 1967 return ret; 1968 } 1969 1970 /* 1971 * We might have detected that some engines are fused off after we initialized 1972 * the forcewake domains. Prune them, to make sure they only reference existing 1973 * engines. 1974 */ 1975 void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore, 1976 struct intel_gt *gt) 1977 { 1978 enum forcewake_domains fw_domains = uncore->fw_domains; 1979 enum forcewake_domain_id domain_id; 1980 int i; 1981 1982 if (!intel_uncore_has_forcewake(uncore) || GRAPHICS_VER(uncore->i915) < 11) 1983 return; 1984 1985 for (i = 0; i < I915_MAX_VCS; i++) { 1986 domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i; 1987 1988 if (HAS_ENGINE(gt, _VCS(i))) 1989 continue; 1990 1991 if (fw_domains & BIT(domain_id)) 1992 fw_domain_fini(uncore, domain_id); 1993 } 1994 1995 for (i = 0; i < I915_MAX_VECS; i++) { 1996 domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i; 1997 1998 if (HAS_ENGINE(gt, _VECS(i))) 1999 continue; 2000 2001 if (fw_domains & BIT(domain_id)) 2002 fw_domain_fini(uncore, domain_id); 2003 } 2004 } 2005 2006 void intel_uncore_fini_mmio(struct intel_uncore *uncore) 2007 { 2008 if (intel_uncore_has_forcewake(uncore)) { 2009 iosf_mbi_punit_acquire(); 2010 iosf_mbi_unregister_pmic_bus_access_notifier_unlocked( 2011 &uncore->pmic_bus_access_nb); 2012 intel_uncore_forcewake_reset(uncore); 2013 intel_uncore_fw_domains_fini(uncore); 2014 iosf_mbi_punit_release(); 2015 } 2016 2017 uncore_mmio_cleanup(uncore); 2018 } 2019 2020 static const struct reg_whitelist { 2021 i915_reg_t offset_ldw; 2022 i915_reg_t offset_udw; 2023 u8 min_graphics_ver; 2024 u8 max_graphics_ver; 2025 u8 size; 2026 } reg_read_whitelist[] = { { 2027 .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE), 2028 .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE), 2029 .min_graphics_ver = 4, 2030 .max_graphics_ver = 12, 2031 .size = 8 2032 } }; 2033 2034 int i915_reg_read_ioctl(struct drm_device *dev, 2035 void *data, struct drm_file *file) 2036 { 2037 struct drm_i915_private *i915 = to_i915(dev); 2038 struct intel_uncore *uncore = &i915->uncore; 2039 struct drm_i915_reg_read *reg = data; 2040 struct reg_whitelist const *entry; 2041 intel_wakeref_t wakeref; 2042 unsigned int flags; 2043 int remain; 2044 int ret = 0; 2045 2046 entry = reg_read_whitelist; 2047 remain = ARRAY_SIZE(reg_read_whitelist); 2048 while (remain) { 2049 u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw); 2050 2051 GEM_BUG_ON(!is_power_of_2(entry->size)); 2052 GEM_BUG_ON(entry->size > 8); 2053 GEM_BUG_ON(entry_offset & (entry->size - 1)); 2054 2055 if (IS_GRAPHICS_VER(i915, entry->min_graphics_ver, entry->max_graphics_ver) && 2056 entry_offset == (reg->offset & -entry->size)) 2057 break; 2058 entry++; 2059 remain--; 2060 } 2061 2062 if (!remain) 2063 return -EINVAL; 2064 2065 flags = reg->offset & (entry->size - 1); 2066 2067 with_intel_runtime_pm(&i915->runtime_pm, wakeref) { 2068 if (entry->size == 8 && flags == I915_REG_READ_8B_WA) 2069 reg->val = intel_uncore_read64_2x32(uncore, 2070 entry->offset_ldw, 2071 entry->offset_udw); 2072 else if (entry->size == 8 && flags == 0) 2073 reg->val = intel_uncore_read64(uncore, 2074 entry->offset_ldw); 2075 else if (entry->size == 4 && flags == 0) 2076 reg->val = intel_uncore_read(uncore, entry->offset_ldw); 2077 else if (entry->size == 2 && flags == 0) 2078 reg->val = intel_uncore_read16(uncore, 2079 entry->offset_ldw); 2080 else if (entry->size == 1 && flags == 0) 2081 reg->val = intel_uncore_read8(uncore, 2082 entry->offset_ldw); 2083 else 2084 ret = -EINVAL; 2085 } 2086 2087 return ret; 2088 } 2089 2090 /** 2091 * __intel_wait_for_register_fw - wait until register matches expected state 2092 * @uncore: the struct intel_uncore 2093 * @reg: the register to read 2094 * @mask: mask to apply to register value 2095 * @value: expected value 2096 * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait 2097 * @slow_timeout_ms: slow timeout in millisecond 2098 * @out_value: optional placeholder to hold registry value 2099 * 2100 * This routine waits until the target register @reg contains the expected 2101 * @value after applying the @mask, i.e. it waits until :: 2102 * 2103 * (intel_uncore_read_fw(uncore, reg) & mask) == value 2104 * 2105 * Otherwise, the wait will timeout after @slow_timeout_ms milliseconds. 2106 * For atomic context @slow_timeout_ms must be zero and @fast_timeout_us 2107 * must be not larger than 20,0000 microseconds. 2108 * 2109 * Note that this routine assumes the caller holds forcewake asserted, it is 2110 * not suitable for very long waits. See intel_wait_for_register() if you 2111 * wish to wait without holding forcewake for the duration (i.e. you expect 2112 * the wait to be slow). 2113 * 2114 * Return: 0 if the register matches the desired condition, or -ETIMEDOUT. 2115 */ 2116 int __intel_wait_for_register_fw(struct intel_uncore *uncore, 2117 i915_reg_t reg, 2118 u32 mask, 2119 u32 value, 2120 unsigned int fast_timeout_us, 2121 unsigned int slow_timeout_ms, 2122 u32 *out_value) 2123 { 2124 u32 reg_value = 0; 2125 #define done (((reg_value = intel_uncore_read_fw(uncore, reg)) & mask) == value) 2126 int ret; 2127 2128 /* Catch any overuse of this function */ 2129 might_sleep_if(slow_timeout_ms); 2130 GEM_BUG_ON(fast_timeout_us > 20000); 2131 GEM_BUG_ON(!fast_timeout_us && !slow_timeout_ms); 2132 2133 ret = -ETIMEDOUT; 2134 if (fast_timeout_us && fast_timeout_us <= 20000) 2135 ret = _wait_for_atomic(done, fast_timeout_us, 0); 2136 if (ret && slow_timeout_ms) 2137 ret = wait_for(done, slow_timeout_ms); 2138 2139 if (out_value) 2140 *out_value = reg_value; 2141 2142 return ret; 2143 #undef done 2144 } 2145 2146 /** 2147 * __intel_wait_for_register - wait until register matches expected state 2148 * @uncore: the struct intel_uncore 2149 * @reg: the register to read 2150 * @mask: mask to apply to register value 2151 * @value: expected value 2152 * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait 2153 * @slow_timeout_ms: slow timeout in millisecond 2154 * @out_value: optional placeholder to hold registry value 2155 * 2156 * This routine waits until the target register @reg contains the expected 2157 * @value after applying the @mask, i.e. it waits until :: 2158 * 2159 * (intel_uncore_read(uncore, reg) & mask) == value 2160 * 2161 * Otherwise, the wait will timeout after @timeout_ms milliseconds. 2162 * 2163 * Return: 0 if the register matches the desired condition, or -ETIMEDOUT. 2164 */ 2165 int __intel_wait_for_register(struct intel_uncore *uncore, 2166 i915_reg_t reg, 2167 u32 mask, 2168 u32 value, 2169 unsigned int fast_timeout_us, 2170 unsigned int slow_timeout_ms, 2171 u32 *out_value) 2172 { 2173 unsigned fw = 2174 intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ); 2175 u32 reg_value; 2176 int ret; 2177 2178 might_sleep_if(slow_timeout_ms); 2179 2180 spin_lock_irq(&uncore->lock); 2181 intel_uncore_forcewake_get__locked(uncore, fw); 2182 2183 ret = __intel_wait_for_register_fw(uncore, 2184 reg, mask, value, 2185 fast_timeout_us, 0, ®_value); 2186 2187 intel_uncore_forcewake_put__locked(uncore, fw); 2188 spin_unlock_irq(&uncore->lock); 2189 2190 if (ret && slow_timeout_ms) 2191 ret = __wait_for(reg_value = intel_uncore_read_notrace(uncore, 2192 reg), 2193 (reg_value & mask) == value, 2194 slow_timeout_ms * 1000, 10, 1000); 2195 2196 /* just trace the final value */ 2197 trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true); 2198 2199 if (out_value) 2200 *out_value = reg_value; 2201 2202 return ret; 2203 } 2204 2205 bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore) 2206 { 2207 bool ret; 2208 2209 spin_lock_irq(&uncore->debug->lock); 2210 ret = check_for_unclaimed_mmio(uncore); 2211 spin_unlock_irq(&uncore->debug->lock); 2212 2213 return ret; 2214 } 2215 2216 bool 2217 intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore) 2218 { 2219 bool ret = false; 2220 2221 spin_lock_irq(&uncore->debug->lock); 2222 2223 if (unlikely(uncore->debug->unclaimed_mmio_check <= 0)) 2224 goto out; 2225 2226 if (unlikely(check_for_unclaimed_mmio(uncore))) { 2227 if (!uncore->i915->params.mmio_debug) { 2228 drm_dbg(&uncore->i915->drm, 2229 "Unclaimed register detected, " 2230 "enabling oneshot unclaimed register reporting. " 2231 "Please use i915.mmio_debug=N for more information.\n"); 2232 uncore->i915->params.mmio_debug++; 2233 } 2234 uncore->debug->unclaimed_mmio_check--; 2235 ret = true; 2236 } 2237 2238 out: 2239 spin_unlock_irq(&uncore->debug->lock); 2240 2241 return ret; 2242 } 2243 2244 /** 2245 * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access 2246 * a register 2247 * @uncore: pointer to struct intel_uncore 2248 * @reg: register in question 2249 * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE 2250 * 2251 * Returns a set of forcewake domains required to be taken with for example 2252 * intel_uncore_forcewake_get for the specified register to be accessible in the 2253 * specified mode (read, write or read/write) with raw mmio accessors. 2254 * 2255 * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the 2256 * callers to do FIFO management on their own or risk losing writes. 2257 */ 2258 enum forcewake_domains 2259 intel_uncore_forcewake_for_reg(struct intel_uncore *uncore, 2260 i915_reg_t reg, unsigned int op) 2261 { 2262 enum forcewake_domains fw_domains = 0; 2263 2264 drm_WARN_ON(&uncore->i915->drm, !op); 2265 2266 if (!intel_uncore_has_forcewake(uncore)) 2267 return 0; 2268 2269 if (op & FW_REG_READ) 2270 fw_domains = uncore->funcs.read_fw_domains(uncore, reg); 2271 2272 if (op & FW_REG_WRITE) 2273 fw_domains |= uncore->funcs.write_fw_domains(uncore, reg); 2274 2275 drm_WARN_ON(&uncore->i915->drm, fw_domains & ~uncore->fw_domains); 2276 2277 return fw_domains; 2278 } 2279 2280 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 2281 #include "selftests/mock_uncore.c" 2282 #include "selftests/intel_uncore.c" 2283 #endif 2284