1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020,2021 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "intel_step.h" 8 9 /* 10 * Some platforms have unusual ways of mapping PCI revision ID to GT/display 11 * steppings. E.g., in some cases a higher PCI revision may translate to a 12 * lower stepping of the GT and/or display IP. This file provides lookup 13 * tables to map the PCI revision into a standard set of stepping values that 14 * can be compared numerically. 15 * 16 * Also note that some revisions/steppings may have been set aside as 17 * placeholders but never materialized in real hardware; in those cases there 18 * may be jumps in the revision IDs or stepping values in the tables below. 19 */ 20 21 /* 22 * Some platforms always have the same stepping value for GT and display; 23 * use a macro to define these to make it easier to identify the platforms 24 * where the two steppings can deviate. 25 */ 26 #define COMMON_STEP(x) .graphics_step = STEP_##x, .display_step = STEP_##x, .media_step = STEP_##x 27 #define COMMON_GT_MEDIA_STEP(x) .graphics_step = STEP_##x, .media_step = STEP_##x 28 29 static const struct intel_step_info skl_revids[] = { 30 [0x6] = { COMMON_STEP(G0) }, 31 [0x7] = { COMMON_STEP(H0) }, 32 [0x9] = { COMMON_STEP(J0) }, 33 [0xA] = { COMMON_STEP(I1) }, 34 }; 35 36 static const struct intel_step_info kbl_revids[] = { 37 [1] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_B0 }, 38 [2] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_B0 }, 39 [3] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_B0 }, 40 [4] = { COMMON_GT_MEDIA_STEP(F0), .display_step = STEP_C0 }, 41 [5] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_B1 }, 42 [6] = { COMMON_GT_MEDIA_STEP(D1), .display_step = STEP_B1 }, 43 [7] = { COMMON_GT_MEDIA_STEP(G0), .display_step = STEP_C0 }, 44 }; 45 46 static const struct intel_step_info bxt_revids[] = { 47 [0xA] = { COMMON_STEP(C0) }, 48 [0xB] = { COMMON_STEP(C0) }, 49 [0xC] = { COMMON_STEP(D0) }, 50 [0xD] = { COMMON_STEP(E0) }, 51 }; 52 53 static const struct intel_step_info glk_revids[] = { 54 [3] = { COMMON_STEP(B0) }, 55 }; 56 57 static const struct intel_step_info icl_revids[] = { 58 [7] = { COMMON_STEP(D0) }, 59 }; 60 61 static const struct intel_step_info jsl_ehl_revids[] = { 62 [0] = { COMMON_STEP(A0) }, 63 [1] = { COMMON_STEP(B0) }, 64 }; 65 66 static const struct intel_step_info tgl_uy_revids[] = { 67 [0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_A0 }, 68 [1] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_C0 }, 69 [2] = { COMMON_GT_MEDIA_STEP(B1), .display_step = STEP_C0 }, 70 [3] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_D0 }, 71 }; 72 73 /* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */ 74 static const struct intel_step_info tgl_revids[] = { 75 [0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_B0 }, 76 [1] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_D0 }, 77 }; 78 79 static const struct intel_step_info rkl_revids[] = { 80 [0] = { COMMON_STEP(A0) }, 81 [1] = { COMMON_STEP(B0) }, 82 [4] = { COMMON_STEP(C0) }, 83 }; 84 85 static const struct intel_step_info dg1_revids[] = { 86 [0] = { COMMON_STEP(A0) }, 87 [1] = { COMMON_STEP(B0) }, 88 }; 89 90 static const struct intel_step_info adls_revids[] = { 91 [0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_A0 }, 92 [0x1] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_A2 }, 93 [0x4] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_B0 }, 94 [0x8] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_B0 }, 95 [0xC] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_C0 }, 96 }; 97 98 static const struct intel_step_info adlp_revids[] = { 99 [0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_A0 }, 100 [0x4] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_B0 }, 101 [0x8] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_C0 }, 102 [0xC] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_D0 }, 103 }; 104 105 static const struct intel_step_info dg2_g10_revid_step_tbl[] = { 106 [0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_A0 }, 107 [0x1] = { COMMON_GT_MEDIA_STEP(A1), .display_step = STEP_A0 }, 108 [0x4] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_B0 }, 109 [0x8] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_C0 }, 110 }; 111 112 static const struct intel_step_info dg2_g11_revid_step_tbl[] = { 113 [0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_B0 }, 114 [0x4] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_C0 }, 115 [0x5] = { COMMON_GT_MEDIA_STEP(B1), .display_step = STEP_C0 }, 116 }; 117 118 static const struct intel_step_info dg2_g12_revid_step_tbl[] = { 119 [0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_C0 }, 120 [0x1] = { COMMON_GT_MEDIA_STEP(A1), .display_step = STEP_C0 }, 121 }; 122 123 static const struct intel_step_info adls_rpls_revids[] = { 124 [0x4] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_D0 }, 125 [0xC] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_C0 }, 126 }; 127 128 static const struct intel_step_info adlp_rplp_revids[] = { 129 [0x4] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_E0 }, 130 }; 131 132 static const struct intel_step_info adlp_n_revids[] = { 133 [0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_D0 }, 134 }; 135 136 static u8 gmd_to_intel_step(struct drm_i915_private *i915, 137 struct intel_ip_version *gmd) 138 { 139 u8 step = gmd->step + STEP_A0; 140 141 if (step >= STEP_FUTURE) { 142 drm_dbg(&i915->drm, "Using future steppings\n"); 143 return STEP_FUTURE; 144 } 145 146 return step; 147 } 148 149 void intel_step_init(struct drm_i915_private *i915) 150 { 151 const struct intel_step_info *revids = NULL; 152 int size = 0; 153 int revid = INTEL_REVID(i915); 154 struct intel_step_info step = {}; 155 156 if (HAS_GMD_ID(i915)) { 157 step.graphics_step = gmd_to_intel_step(i915, 158 &RUNTIME_INFO(i915)->graphics.ip); 159 step.media_step = gmd_to_intel_step(i915, 160 &RUNTIME_INFO(i915)->media.ip); 161 step.display_step = STEP_A0 + DISPLAY_RUNTIME_INFO(i915)->ip.step; 162 if (step.display_step >= STEP_FUTURE) { 163 drm_dbg(&i915->drm, "Using future display steppings\n"); 164 step.display_step = STEP_FUTURE; 165 } 166 167 RUNTIME_INFO(i915)->step = step; 168 169 return; 170 } 171 172 if (IS_DG2_G10(i915)) { 173 revids = dg2_g10_revid_step_tbl; 174 size = ARRAY_SIZE(dg2_g10_revid_step_tbl); 175 } else if (IS_DG2_G11(i915)) { 176 revids = dg2_g11_revid_step_tbl; 177 size = ARRAY_SIZE(dg2_g11_revid_step_tbl); 178 } else if (IS_DG2_G12(i915)) { 179 revids = dg2_g12_revid_step_tbl; 180 size = ARRAY_SIZE(dg2_g12_revid_step_tbl); 181 } else if (IS_ALDERLAKE_P_N(i915)) { 182 revids = adlp_n_revids; 183 size = ARRAY_SIZE(adlp_n_revids); 184 } else if (IS_RAPTORLAKE_P(i915)) { 185 revids = adlp_rplp_revids; 186 size = ARRAY_SIZE(adlp_rplp_revids); 187 } else if (IS_ALDERLAKE_P(i915)) { 188 revids = adlp_revids; 189 size = ARRAY_SIZE(adlp_revids); 190 } else if (IS_RAPTORLAKE_S(i915)) { 191 revids = adls_rpls_revids; 192 size = ARRAY_SIZE(adls_rpls_revids); 193 } else if (IS_ALDERLAKE_S(i915)) { 194 revids = adls_revids; 195 size = ARRAY_SIZE(adls_revids); 196 } else if (IS_DG1(i915)) { 197 revids = dg1_revids; 198 size = ARRAY_SIZE(dg1_revids); 199 } else if (IS_ROCKETLAKE(i915)) { 200 revids = rkl_revids; 201 size = ARRAY_SIZE(rkl_revids); 202 } else if (IS_TIGERLAKE_UY(i915)) { 203 revids = tgl_uy_revids; 204 size = ARRAY_SIZE(tgl_uy_revids); 205 } else if (IS_TIGERLAKE(i915)) { 206 revids = tgl_revids; 207 size = ARRAY_SIZE(tgl_revids); 208 } else if (IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) { 209 revids = jsl_ehl_revids; 210 size = ARRAY_SIZE(jsl_ehl_revids); 211 } else if (IS_ICELAKE(i915)) { 212 revids = icl_revids; 213 size = ARRAY_SIZE(icl_revids); 214 } else if (IS_GEMINILAKE(i915)) { 215 revids = glk_revids; 216 size = ARRAY_SIZE(glk_revids); 217 } else if (IS_BROXTON(i915)) { 218 revids = bxt_revids; 219 size = ARRAY_SIZE(bxt_revids); 220 } else if (IS_KABYLAKE(i915)) { 221 revids = kbl_revids; 222 size = ARRAY_SIZE(kbl_revids); 223 } else if (IS_SKYLAKE(i915)) { 224 revids = skl_revids; 225 size = ARRAY_SIZE(skl_revids); 226 } 227 228 /* Not using the stepping scheme for the platform yet. */ 229 if (!revids) 230 return; 231 232 if (revid < size && revids[revid].graphics_step != STEP_NONE) { 233 step = revids[revid]; 234 } else { 235 drm_warn(&i915->drm, "Unknown revid 0x%02x\n", revid); 236 237 /* 238 * If we hit a gap in the revid array, use the information for 239 * the next revid. 240 * 241 * This may be wrong in all sorts of ways, especially if the 242 * steppings in the array are not monotonically increasing, but 243 * it's better than defaulting to 0. 244 */ 245 while (revid < size && revids[revid].graphics_step == STEP_NONE) 246 revid++; 247 248 if (revid < size) { 249 drm_dbg(&i915->drm, "Using steppings for revid 0x%02x\n", 250 revid); 251 step = revids[revid]; 252 } else { 253 drm_dbg(&i915->drm, "Using future steppings\n"); 254 step.graphics_step = STEP_FUTURE; 255 step.display_step = STEP_FUTURE; 256 } 257 } 258 259 if (drm_WARN_ON(&i915->drm, step.graphics_step == STEP_NONE)) 260 return; 261 262 RUNTIME_INFO(i915)->step = step; 263 } 264 265 #define STEP_NAME_CASE(name) \ 266 case STEP_##name: \ 267 return #name; 268 269 const char *intel_step_name(enum intel_step step) 270 { 271 switch (step) { 272 STEP_NAME_LIST(STEP_NAME_CASE); 273 274 default: 275 return "**"; 276 } 277 } 278 279 const char *intel_display_step_name(struct drm_i915_private *i915) 280 { 281 return intel_step_name(RUNTIME_INFO(i915)->step.display_step); 282 } 283