xref: /linux/drivers/gpu/drm/i915/intel_pcode.h (revision 260f6f4fda93c8485c8037865c941b42b9cba5d2)
1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2013-2021 Intel Corporation
4  */
5 
6 #ifndef _INTEL_PCODE_H_
7 #define _INTEL_PCODE_H_
8 
9 #include <linux/types.h>
10 
11 struct drm_device;
12 struct intel_uncore;
13 
14 int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1);
15 int snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val, int timeout_ms);
16 #define snb_pcode_write(uncore, mbox, val) \
17 	snb_pcode_write_timeout((uncore), (mbox), (val), 1)
18 
19 int skl_pcode_request(struct intel_uncore *uncore, u32 mbox, u32 request,
20 		      u32 reply_mask, u32 reply, int timeout_base_ms);
21 
22 int intel_pcode_init(struct intel_uncore *uncore);
23 
24 /*
25  * Helpers for dGfx PCODE mailbox command formatting
26  */
27 int snb_pcode_read_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 *val);
28 int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 val);
29 
30 /* Helpers with drm device */
31 int intel_pcode_read(struct drm_device *drm, u32 mbox, u32 *val, u32 *val1);
32 int intel_pcode_write_timeout(struct drm_device *drm, u32 mbox, u32 val, int timeout_ms);
33 #define intel_pcode_write(drm, mbox, val) \
34 	intel_pcode_write_timeout((drm), (mbox), (val), 1)
35 
36 int intel_pcode_request(struct drm_device *drm, u32 mbox, u32 request,
37 			u32 reply_mask, u32 reply, int timeout_base_ms);
38 
39 #endif /* _INTEL_PCODE_H */
40