1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 */ 23 24 #include <linux/vmalloc.h> 25 26 #include <drm/drm_print.h> 27 28 #include "gem/i915_gem_dmabuf.h" 29 30 #include "gt/intel_context.h" 31 #include "gt/intel_ring.h" 32 #include "gt/shmem_utils.h" 33 34 #include "i915_drv.h" 35 #include "i915_vgpu.h" 36 #include "intel_gvt.h" 37 38 /** 39 * DOC: Intel GVT-g host support 40 * 41 * Intel GVT-g is a graphics virtualization technology which shares the 42 * GPU among multiple virtual machines on a time-sharing basis. Each 43 * virtual machine is presented a virtual GPU (vGPU), which has equivalent 44 * features as the underlying physical GPU (pGPU), so i915 driver can run 45 * seamlessly in a virtual machine. 46 * 47 * To virtualize GPU resources GVT-g driver depends on hypervisor technology 48 * e.g KVM/VFIO/mdev, Xen, etc. to provide resource access trapping capability 49 * and be virtualized within GVT-g device module. More architectural design 50 * doc is available on https://github.com/intel/gvt-linux/wiki. 51 */ 52 53 static LIST_HEAD(intel_gvt_devices); 54 static const struct intel_vgpu_ops *intel_gvt_ops; 55 static DEFINE_MUTEX(intel_gvt_mutex); 56 57 static bool is_supported_device(struct drm_i915_private *dev_priv) 58 { 59 if (IS_BROADWELL(dev_priv)) 60 return true; 61 if (IS_SKYLAKE(dev_priv)) 62 return true; 63 if (IS_KABYLAKE(dev_priv)) 64 return true; 65 if (IS_BROXTON(dev_priv)) 66 return true; 67 if (IS_COFFEELAKE(dev_priv)) 68 return true; 69 if (IS_COMETLAKE(dev_priv)) 70 return true; 71 72 return false; 73 } 74 75 static void free_initial_hw_state(struct drm_i915_private *dev_priv) 76 { 77 struct i915_virtual_gpu *vgpu = &dev_priv->vgpu; 78 79 vfree(vgpu->initial_mmio); 80 vgpu->initial_mmio = NULL; 81 82 kfree(vgpu->initial_cfg_space); 83 vgpu->initial_cfg_space = NULL; 84 } 85 86 static void save_mmio(struct intel_gvt_mmio_table_iter *iter, u32 offset, 87 u32 size) 88 { 89 struct drm_i915_private *dev_priv = iter->i915; 90 u32 *mmio, i; 91 92 for (i = offset; i < offset + size; i += 4) { 93 mmio = iter->data + i; 94 *mmio = intel_uncore_read_notrace(to_gt(dev_priv)->uncore, 95 _MMIO(i)); 96 } 97 } 98 99 static int handle_mmio(struct intel_gvt_mmio_table_iter *iter, 100 u32 offset, u32 size) 101 { 102 if (WARN_ON(!IS_ALIGNED(offset, 4))) 103 return -EINVAL; 104 105 save_mmio(iter, offset, size); 106 return 0; 107 } 108 109 static int save_initial_hw_state(struct drm_i915_private *dev_priv) 110 { 111 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 112 struct i915_virtual_gpu *vgpu = &dev_priv->vgpu; 113 struct intel_gvt_mmio_table_iter iter; 114 void *mem; 115 int i, ret; 116 117 mem = kzalloc(PCI_CFG_SPACE_EXP_SIZE, GFP_KERNEL); 118 if (!mem) 119 return -ENOMEM; 120 121 vgpu->initial_cfg_space = mem; 122 123 for (i = 0; i < PCI_CFG_SPACE_EXP_SIZE; i += 4) 124 pci_read_config_dword(pdev, i, mem + i); 125 126 mem = vzalloc(2 * SZ_1M); 127 if (!mem) { 128 ret = -ENOMEM; 129 goto err_mmio; 130 } 131 132 vgpu->initial_mmio = mem; 133 134 iter.i915 = dev_priv; 135 iter.data = vgpu->initial_mmio; 136 iter.handle_mmio_cb = handle_mmio; 137 138 ret = intel_gvt_iterate_mmio_table(&iter); 139 if (ret) 140 goto err_iterate; 141 142 return 0; 143 144 err_iterate: 145 vfree(vgpu->initial_mmio); 146 vgpu->initial_mmio = NULL; 147 err_mmio: 148 kfree(vgpu->initial_cfg_space); 149 vgpu->initial_cfg_space = NULL; 150 151 return ret; 152 } 153 154 static void intel_gvt_init_device(struct drm_i915_private *dev_priv) 155 { 156 if (!dev_priv->params.enable_gvt) { 157 drm_dbg(&dev_priv->drm, 158 "GVT-g is disabled by kernel params\n"); 159 return; 160 } 161 162 if (intel_vgpu_active(dev_priv)) { 163 drm_info(&dev_priv->drm, "GVT-g is disabled for guest\n"); 164 return; 165 } 166 167 if (!is_supported_device(dev_priv)) { 168 drm_info(&dev_priv->drm, 169 "Unsupported device. GVT-g is disabled\n"); 170 return; 171 } 172 173 if (intel_uc_wants_guc_submission(&to_gt(dev_priv)->uc)) { 174 drm_err(&dev_priv->drm, 175 "Graphics virtualization is not yet supported with GuC submission\n"); 176 return; 177 } 178 179 if (save_initial_hw_state(dev_priv)) { 180 drm_dbg(&dev_priv->drm, "Failed to save initial HW state\n"); 181 return; 182 } 183 184 if (intel_gvt_ops->init_device(dev_priv)) 185 drm_dbg(&dev_priv->drm, "Fail to init GVT device\n"); 186 } 187 188 static void intel_gvt_clean_device(struct drm_i915_private *dev_priv) 189 { 190 if (dev_priv->gvt) 191 intel_gvt_ops->clean_device(dev_priv); 192 free_initial_hw_state(dev_priv); 193 } 194 195 int intel_gvt_set_ops(const struct intel_vgpu_ops *ops) 196 { 197 struct drm_i915_private *dev_priv; 198 199 mutex_lock(&intel_gvt_mutex); 200 if (intel_gvt_ops) { 201 mutex_unlock(&intel_gvt_mutex); 202 return -EINVAL; 203 } 204 intel_gvt_ops = ops; 205 206 list_for_each_entry(dev_priv, &intel_gvt_devices, vgpu.entry) 207 intel_gvt_init_device(dev_priv); 208 mutex_unlock(&intel_gvt_mutex); 209 210 return 0; 211 } 212 EXPORT_SYMBOL_NS_GPL(intel_gvt_set_ops, "I915_GVT"); 213 214 void intel_gvt_clear_ops(const struct intel_vgpu_ops *ops) 215 { 216 struct drm_i915_private *dev_priv; 217 218 mutex_lock(&intel_gvt_mutex); 219 if (intel_gvt_ops != ops) { 220 mutex_unlock(&intel_gvt_mutex); 221 return; 222 } 223 224 list_for_each_entry(dev_priv, &intel_gvt_devices, vgpu.entry) 225 intel_gvt_clean_device(dev_priv); 226 227 intel_gvt_ops = NULL; 228 mutex_unlock(&intel_gvt_mutex); 229 } 230 EXPORT_SYMBOL_NS_GPL(intel_gvt_clear_ops, "I915_GVT"); 231 232 /** 233 * intel_gvt_init - initialize GVT components 234 * @dev_priv: drm i915 private data 235 * 236 * This function is called at the initialization stage to create a GVT device. 237 * 238 * Returns: 239 * Zero on success, negative error code if failed. 240 * 241 */ 242 int intel_gvt_init(struct drm_i915_private *dev_priv) 243 { 244 mutex_lock(&intel_gvt_mutex); 245 list_add_tail(&dev_priv->vgpu.entry, &intel_gvt_devices); 246 if (intel_gvt_ops) 247 intel_gvt_init_device(dev_priv); 248 mutex_unlock(&intel_gvt_mutex); 249 250 return 0; 251 } 252 253 /** 254 * intel_gvt_driver_remove - cleanup GVT components when i915 driver is 255 * unbinding 256 * @dev_priv: drm i915 private * 257 * 258 * This function is called at the i915 driver unloading stage, to shutdown 259 * GVT components and release the related resources. 260 */ 261 void intel_gvt_driver_remove(struct drm_i915_private *dev_priv) 262 { 263 mutex_lock(&intel_gvt_mutex); 264 intel_gvt_clean_device(dev_priv); 265 list_del(&dev_priv->vgpu.entry); 266 mutex_unlock(&intel_gvt_mutex); 267 } 268 269 /** 270 * intel_gvt_resume - GVT resume routine wrapper 271 * 272 * @dev_priv: drm i915 private * 273 * 274 * This function is called at the i915 driver resume stage to restore required 275 * HW status for GVT so that vGPU can continue running after resumed. 276 */ 277 void intel_gvt_resume(struct drm_i915_private *dev_priv) 278 { 279 mutex_lock(&intel_gvt_mutex); 280 if (dev_priv->gvt) 281 intel_gvt_ops->pm_resume(dev_priv); 282 mutex_unlock(&intel_gvt_mutex); 283 } 284 285 /* 286 * Exported here so that the exports only get created when GVT support is 287 * actually enabled. 288 */ 289 EXPORT_SYMBOL_NS_GPL(i915_gem_object_alloc, "I915_GVT"); 290 EXPORT_SYMBOL_NS_GPL(i915_gem_object_create_shmem, "I915_GVT"); 291 EXPORT_SYMBOL_NS_GPL(i915_gem_object_init, "I915_GVT"); 292 EXPORT_SYMBOL_NS_GPL(i915_gem_object_ggtt_pin_ww, "I915_GVT"); 293 EXPORT_SYMBOL_NS_GPL(i915_gem_object_pin_map, "I915_GVT"); 294 EXPORT_SYMBOL_NS_GPL(i915_gem_object_set_to_cpu_domain, "I915_GVT"); 295 EXPORT_SYMBOL_NS_GPL(__i915_gem_object_flush_map, "I915_GVT"); 296 EXPORT_SYMBOL_NS_GPL(__i915_gem_object_set_pages, "I915_GVT"); 297 EXPORT_SYMBOL_NS_GPL(i915_gem_gtt_insert, "I915_GVT"); 298 EXPORT_SYMBOL_NS_GPL(i915_gem_prime_export, "I915_GVT"); 299 EXPORT_SYMBOL_NS_GPL(i915_gem_ww_ctx_init, "I915_GVT"); 300 EXPORT_SYMBOL_NS_GPL(i915_gem_ww_ctx_backoff, "I915_GVT"); 301 EXPORT_SYMBOL_NS_GPL(i915_gem_ww_ctx_fini, "I915_GVT"); 302 EXPORT_SYMBOL_NS_GPL(i915_ppgtt_create, "I915_GVT"); 303 EXPORT_SYMBOL_NS_GPL(i915_request_add, "I915_GVT"); 304 EXPORT_SYMBOL_NS_GPL(i915_request_create, "I915_GVT"); 305 EXPORT_SYMBOL_NS_GPL(i915_request_wait, "I915_GVT"); 306 EXPORT_SYMBOL_NS_GPL(i915_reserve_fence, "I915_GVT"); 307 EXPORT_SYMBOL_NS_GPL(i915_unreserve_fence, "I915_GVT"); 308 EXPORT_SYMBOL_NS_GPL(i915_vm_release, "I915_GVT"); 309 EXPORT_SYMBOL_NS_GPL(_i915_vma_move_to_active, "I915_GVT"); 310 EXPORT_SYMBOL_NS_GPL(intel_context_create, "I915_GVT"); 311 EXPORT_SYMBOL_NS_GPL(__intel_context_do_pin, "I915_GVT"); 312 EXPORT_SYMBOL_NS_GPL(__intel_context_do_unpin, "I915_GVT"); 313 EXPORT_SYMBOL_NS_GPL(intel_ring_begin, "I915_GVT"); 314 EXPORT_SYMBOL_NS_GPL(intel_runtime_pm_get, "I915_GVT"); 315 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 316 EXPORT_SYMBOL_NS_GPL(intel_runtime_pm_put, "I915_GVT"); 317 #endif 318 EXPORT_SYMBOL_NS_GPL(intel_runtime_pm_put_unchecked, "I915_GVT"); 319 EXPORT_SYMBOL_NS_GPL(intel_uncore_forcewake_for_reg, "I915_GVT"); 320 EXPORT_SYMBOL_NS_GPL(intel_uncore_forcewake_get, "I915_GVT"); 321 EXPORT_SYMBOL_NS_GPL(intel_uncore_forcewake_put, "I915_GVT"); 322 EXPORT_SYMBOL_NS_GPL(shmem_pin_map, "I915_GVT"); 323 EXPORT_SYMBOL_NS_GPL(shmem_unpin_map, "I915_GVT"); 324 EXPORT_SYMBOL_NS_GPL(__px_dma, "I915_GVT"); 325 EXPORT_SYMBOL_NS_GPL(i915_fence_ops, "I915_GVT"); 326