1 /* 2 * Copyright © 2014-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DEVICE_INFO_H_ 26 #define _INTEL_DEVICE_INFO_H_ 27 28 #include <uapi/drm/i915_drm.h> 29 30 #include "intel_step.h" 31 32 #include "display/intel_display.h" 33 34 #include "gt/intel_engine_types.h" 35 #include "gt/intel_context_types.h" 36 #include "gt/intel_sseu.h" 37 38 struct drm_printer; 39 struct drm_i915_private; 40 41 /* Keep in gen based order, and chronological order within a gen */ 42 enum intel_platform { 43 INTEL_PLATFORM_UNINITIALIZED = 0, 44 /* gen2 */ 45 INTEL_I830, 46 INTEL_I845G, 47 INTEL_I85X, 48 INTEL_I865G, 49 /* gen3 */ 50 INTEL_I915G, 51 INTEL_I915GM, 52 INTEL_I945G, 53 INTEL_I945GM, 54 INTEL_G33, 55 INTEL_PINEVIEW, 56 /* gen4 */ 57 INTEL_I965G, 58 INTEL_I965GM, 59 INTEL_G45, 60 INTEL_GM45, 61 /* gen5 */ 62 INTEL_IRONLAKE, 63 /* gen6 */ 64 INTEL_SANDYBRIDGE, 65 /* gen7 */ 66 INTEL_IVYBRIDGE, 67 INTEL_VALLEYVIEW, 68 INTEL_HASWELL, 69 /* gen8 */ 70 INTEL_BROADWELL, 71 INTEL_CHERRYVIEW, 72 /* gen9 */ 73 INTEL_SKYLAKE, 74 INTEL_BROXTON, 75 INTEL_KABYLAKE, 76 INTEL_GEMINILAKE, 77 INTEL_COFFEELAKE, 78 INTEL_COMETLAKE, 79 /* gen11 */ 80 INTEL_ICELAKE, 81 INTEL_ELKHARTLAKE, 82 INTEL_JASPERLAKE, 83 /* gen12 */ 84 INTEL_TIGERLAKE, 85 INTEL_ROCKETLAKE, 86 INTEL_DG1, 87 INTEL_ALDERLAKE_S, 88 INTEL_ALDERLAKE_P, 89 INTEL_XEHPSDV, 90 INTEL_DG2, 91 INTEL_PONTEVECCHIO, 92 INTEL_MAX_PLATFORMS 93 }; 94 95 /* 96 * Subplatform bits share the same namespace per parent platform. In other words 97 * it is fine for the same bit to be used on multiple parent platforms. 98 */ 99 100 #define INTEL_SUBPLATFORM_BITS (3) 101 #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1) 102 103 /* HSW/BDW/SKL/KBL/CFL */ 104 #define INTEL_SUBPLATFORM_ULT (0) 105 #define INTEL_SUBPLATFORM_ULX (1) 106 107 /* ICL */ 108 #define INTEL_SUBPLATFORM_PORTF (0) 109 110 /* TGL */ 111 #define INTEL_SUBPLATFORM_UY (0) 112 113 /* DG2 */ 114 #define INTEL_SUBPLATFORM_G10 0 115 #define INTEL_SUBPLATFORM_G11 1 116 #define INTEL_SUBPLATFORM_G12 2 117 118 /* ADL */ 119 #define INTEL_SUBPLATFORM_RPL 0 120 121 /* ADL-P */ 122 /* 123 * As #define INTEL_SUBPLATFORM_RPL 0 will apply 124 * here too, SUBPLATFORM_N will have different 125 * bit set 126 */ 127 #define INTEL_SUBPLATFORM_N 1 128 129 enum intel_ppgtt_type { 130 INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE, 131 INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING, 132 INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL, 133 }; 134 135 #define DEV_INFO_FOR_EACH_FLAG(func) \ 136 func(is_mobile); \ 137 func(is_lp); \ 138 func(require_force_probe); \ 139 func(is_dgfx); \ 140 /* Keep has_* in alphabetical order */ \ 141 func(has_64bit_reloc); \ 142 func(has_64k_pages); \ 143 func(needs_compact_pt); \ 144 func(gpu_reset_clobbers_display); \ 145 func(has_reset_engine); \ 146 func(has_4tile); \ 147 func(has_flat_ccs); \ 148 func(has_global_mocs); \ 149 func(has_gt_uc); \ 150 func(has_heci_pxp); \ 151 func(has_heci_gscfi); \ 152 func(has_guc_deprivilege); \ 153 func(has_l3_dpf); \ 154 func(has_llc); \ 155 func(has_logical_ring_contexts); \ 156 func(has_logical_ring_elsq); \ 157 func(has_mslices); \ 158 func(has_pooled_eu); \ 159 func(has_pxp); \ 160 func(has_rc6); \ 161 func(has_rc6p); \ 162 func(has_rps); \ 163 func(has_runtime_pm); \ 164 func(has_snoop); \ 165 func(has_coherent_ggtt); \ 166 func(unfenced_needs_alignment); \ 167 func(hws_needs_physical); 168 169 #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ 170 /* Keep in alphabetical order */ \ 171 func(cursor_needs_physical); \ 172 func(has_cdclk_crawl); \ 173 func(has_dmc); \ 174 func(has_ddi); \ 175 func(has_dp_mst); \ 176 func(has_dsb); \ 177 func(has_dsc); \ 178 func(has_fpga_dbg); \ 179 func(has_gmch); \ 180 func(has_hdcp); \ 181 func(has_hotplug); \ 182 func(has_hti); \ 183 func(has_ipc); \ 184 func(has_modular_fia); \ 185 func(has_overlay); \ 186 func(has_psr); \ 187 func(has_psr_hw_tracking); \ 188 func(overlay_needs_physical); \ 189 func(supports_tv); 190 191 struct ip_version { 192 u8 ver; 193 u8 rel; 194 }; 195 196 struct intel_device_info { 197 struct ip_version graphics; 198 struct ip_version media; 199 200 intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */ 201 202 enum intel_platform platform; 203 204 unsigned int dma_mask_size; /* available DMA address bits */ 205 206 enum intel_ppgtt_type ppgtt_type; 207 unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */ 208 209 unsigned int page_sizes; /* page sizes supported by the HW */ 210 211 u32 memory_regions; /* regions supported by the HW */ 212 213 u32 display_mmio_offset; 214 215 u8 gt; /* GT number, 0 if undefined */ 216 217 #define DEFINE_FLAG(name) u8 name:1 218 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG); 219 #undef DEFINE_FLAG 220 221 struct { 222 u8 ver; 223 u8 rel; 224 225 u8 pipe_mask; 226 u8 cpu_transcoder_mask; 227 u8 fbc_mask; 228 u8 abox_mask; 229 230 #define DEFINE_FLAG(name) u8 name:1 231 DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG); 232 #undef DEFINE_FLAG 233 } display; 234 235 struct { 236 u16 size; /* in blocks */ 237 u8 slice_mask; 238 } dbuf; 239 240 /* Register offsets for the various display pipes and transcoders */ 241 int pipe_offsets[I915_MAX_TRANSCODERS]; 242 int trans_offsets[I915_MAX_TRANSCODERS]; 243 int cursor_offsets[I915_MAX_PIPES]; 244 245 struct color_luts { 246 u32 degamma_lut_size; 247 u32 gamma_lut_size; 248 u32 degamma_lut_tests; 249 u32 gamma_lut_tests; 250 } color; 251 }; 252 253 struct intel_runtime_info { 254 /* 255 * Platform mask is used for optimizing or-ed IS_PLATFORM calls into 256 * into single runtime conditionals, and also to provide groundwork 257 * for future per platform, or per SKU build optimizations. 258 * 259 * Array can be extended when necessary if the corresponding 260 * BUILD_BUG_ON is hit. 261 */ 262 u32 platform_mask[2]; 263 264 u16 device_id; 265 266 u8 num_sprites[I915_MAX_PIPES]; 267 u8 num_scalers[I915_MAX_PIPES]; 268 269 u32 rawclk_freq; 270 271 struct intel_step_info step; 272 }; 273 274 struct intel_driver_caps { 275 unsigned int scheduler; 276 bool has_logical_contexts:1; 277 }; 278 279 const char *intel_platform_name(enum intel_platform platform); 280 281 void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv); 282 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv); 283 284 void intel_device_info_print_static(const struct intel_device_info *info, 285 struct drm_printer *p); 286 void intel_device_info_print_runtime(const struct intel_runtime_info *info, 287 struct drm_printer *p); 288 289 void intel_driver_caps_print(const struct intel_driver_caps *caps, 290 struct drm_printer *p); 291 292 #endif 293