1 /* 2 * Copyright © 2014-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DEVICE_INFO_H_ 26 #define _INTEL_DEVICE_INFO_H_ 27 28 #include <uapi/drm/i915_drm.h> 29 30 #include "display/intel_display.h" 31 32 #include "gt/intel_engine_types.h" 33 #include "gt/intel_context_types.h" 34 #include "gt/intel_sseu.h" 35 36 struct drm_printer; 37 struct drm_i915_private; 38 39 /* Keep in gen based order, and chronological order within a gen */ 40 enum intel_platform { 41 INTEL_PLATFORM_UNINITIALIZED = 0, 42 /* gen2 */ 43 INTEL_I830, 44 INTEL_I845G, 45 INTEL_I85X, 46 INTEL_I865G, 47 /* gen3 */ 48 INTEL_I915G, 49 INTEL_I915GM, 50 INTEL_I945G, 51 INTEL_I945GM, 52 INTEL_G33, 53 INTEL_PINEVIEW, 54 /* gen4 */ 55 INTEL_I965G, 56 INTEL_I965GM, 57 INTEL_G45, 58 INTEL_GM45, 59 /* gen5 */ 60 INTEL_IRONLAKE, 61 /* gen6 */ 62 INTEL_SANDYBRIDGE, 63 /* gen7 */ 64 INTEL_IVYBRIDGE, 65 INTEL_VALLEYVIEW, 66 INTEL_HASWELL, 67 /* gen8 */ 68 INTEL_BROADWELL, 69 INTEL_CHERRYVIEW, 70 /* gen9 */ 71 INTEL_SKYLAKE, 72 INTEL_BROXTON, 73 INTEL_KABYLAKE, 74 INTEL_GEMINILAKE, 75 INTEL_COFFEELAKE, 76 INTEL_COMETLAKE, 77 /* gen10 */ 78 INTEL_CANNONLAKE, 79 /* gen11 */ 80 INTEL_ICELAKE, 81 INTEL_ELKHARTLAKE, 82 /* gen12 */ 83 INTEL_TIGERLAKE, 84 INTEL_ROCKETLAKE, 85 INTEL_MAX_PLATFORMS 86 }; 87 88 /* 89 * Subplatform bits share the same namespace per parent platform. In other words 90 * it is fine for the same bit to be used on multiple parent platforms. 91 */ 92 93 #define INTEL_SUBPLATFORM_BITS (3) 94 95 /* HSW/BDW/SKL/KBL/CFL */ 96 #define INTEL_SUBPLATFORM_ULT (0) 97 #define INTEL_SUBPLATFORM_ULX (1) 98 99 /* CNL/ICL */ 100 #define INTEL_SUBPLATFORM_PORTF (0) 101 102 enum intel_ppgtt_type { 103 INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE, 104 INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING, 105 INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL, 106 }; 107 108 #define DEV_INFO_FOR_EACH_FLAG(func) \ 109 func(is_mobile); \ 110 func(is_lp); \ 111 func(require_force_probe); \ 112 func(is_dgfx); \ 113 /* Keep has_* in alphabetical order */ \ 114 func(has_64bit_reloc); \ 115 func(gpu_reset_clobbers_display); \ 116 func(has_reset_engine); \ 117 func(has_fpga_dbg); \ 118 func(has_global_mocs); \ 119 func(has_gt_uc); \ 120 func(has_l3_dpf); \ 121 func(has_llc); \ 122 func(has_logical_ring_contexts); \ 123 func(has_logical_ring_elsq); \ 124 func(has_logical_ring_preemption); \ 125 func(has_pooled_eu); \ 126 func(has_rc6); \ 127 func(has_rc6p); \ 128 func(has_rps); \ 129 func(has_runtime_pm); \ 130 func(has_snoop); \ 131 func(has_coherent_ggtt); \ 132 func(unfenced_needs_alignment); \ 133 func(hws_needs_physical); 134 135 #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ 136 /* Keep in alphabetical order */ \ 137 func(cursor_needs_physical); \ 138 func(has_csr); \ 139 func(has_ddi); \ 140 func(has_dp_mst); \ 141 func(has_dsb); \ 142 func(has_dsc); \ 143 func(has_fbc); \ 144 func(has_gmch); \ 145 func(has_hdcp); \ 146 func(has_hotplug); \ 147 func(has_ipc); \ 148 func(has_modular_fia); \ 149 func(has_overlay); \ 150 func(has_psr); \ 151 func(has_psr_hw_tracking); \ 152 func(overlay_needs_physical); \ 153 func(supports_tv); 154 155 struct intel_device_info { 156 u16 gen_mask; 157 158 u8 gen; 159 u8 gt; /* GT number, 0 if undefined */ 160 intel_engine_mask_t engine_mask; /* Engines supported by the HW */ 161 162 enum intel_platform platform; 163 164 unsigned int dma_mask_size; /* available DMA address bits */ 165 166 enum intel_ppgtt_type ppgtt_type; 167 unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */ 168 169 unsigned int page_sizes; /* page sizes supported by the HW */ 170 171 u32 memory_regions; /* regions supported by the HW */ 172 173 u32 display_mmio_offset; 174 175 u8 pipe_mask; 176 u8 cpu_transcoder_mask; 177 178 u8 abox_mask; 179 180 #define DEFINE_FLAG(name) u8 name:1 181 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG); 182 #undef DEFINE_FLAG 183 184 struct { 185 #define DEFINE_FLAG(name) u8 name:1 186 DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG); 187 #undef DEFINE_FLAG 188 } display; 189 190 u16 ddb_size; /* in blocks */ 191 u8 num_supported_dbuf_slices; /* number of DBuf slices */ 192 193 /* Register offsets for the various display pipes and transcoders */ 194 int pipe_offsets[I915_MAX_TRANSCODERS]; 195 int trans_offsets[I915_MAX_TRANSCODERS]; 196 int cursor_offsets[I915_MAX_PIPES]; 197 198 struct color_luts { 199 u32 degamma_lut_size; 200 u32 gamma_lut_size; 201 u32 degamma_lut_tests; 202 u32 gamma_lut_tests; 203 } color; 204 }; 205 206 struct intel_runtime_info { 207 /* 208 * Platform mask is used for optimizing or-ed IS_PLATFORM calls into 209 * into single runtime conditionals, and also to provide groundwork 210 * for future per platform, or per SKU build optimizations. 211 * 212 * Array can be extended when necessary if the corresponding 213 * BUILD_BUG_ON is hit. 214 */ 215 u32 platform_mask[2]; 216 217 u16 device_id; 218 219 u8 num_sprites[I915_MAX_PIPES]; 220 u8 num_scalers[I915_MAX_PIPES]; 221 222 u8 num_engines; 223 224 /* Slice/subslice/EU info */ 225 struct sseu_dev_info sseu; 226 227 u32 rawclk_freq; 228 229 u32 cs_timestamp_frequency_hz; 230 u32 cs_timestamp_period_ns; 231 232 /* Media engine access to SFC per instance */ 233 u8 vdbox_sfc_access; 234 }; 235 236 struct intel_driver_caps { 237 unsigned int scheduler; 238 bool has_logical_contexts:1; 239 }; 240 241 const char *intel_platform_name(enum intel_platform platform); 242 243 void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv); 244 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv); 245 246 void intel_device_info_print_static(const struct intel_device_info *info, 247 struct drm_printer *p); 248 void intel_device_info_print_runtime(const struct intel_runtime_info *info, 249 struct drm_printer *p); 250 void intel_device_info_print_topology(const struct sseu_dev_info *sseu, 251 struct drm_printer *p); 252 253 void intel_device_info_init_mmio(struct drm_i915_private *dev_priv); 254 255 void intel_driver_caps_print(const struct intel_driver_caps *caps, 256 struct drm_printer *p); 257 258 #endif 259