1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <drm/drm_print.h> 26 #include <drm/i915_pciids.h> 27 28 #include "display/intel_cdclk.h" 29 #include "intel_device_info.h" 30 #include "i915_drv.h" 31 32 #define PLATFORM_NAME(x) [INTEL_##x] = #x 33 static const char * const platform_names[] = { 34 PLATFORM_NAME(I830), 35 PLATFORM_NAME(I845G), 36 PLATFORM_NAME(I85X), 37 PLATFORM_NAME(I865G), 38 PLATFORM_NAME(I915G), 39 PLATFORM_NAME(I915GM), 40 PLATFORM_NAME(I945G), 41 PLATFORM_NAME(I945GM), 42 PLATFORM_NAME(G33), 43 PLATFORM_NAME(PINEVIEW), 44 PLATFORM_NAME(I965G), 45 PLATFORM_NAME(I965GM), 46 PLATFORM_NAME(G45), 47 PLATFORM_NAME(GM45), 48 PLATFORM_NAME(IRONLAKE), 49 PLATFORM_NAME(SANDYBRIDGE), 50 PLATFORM_NAME(IVYBRIDGE), 51 PLATFORM_NAME(VALLEYVIEW), 52 PLATFORM_NAME(HASWELL), 53 PLATFORM_NAME(BROADWELL), 54 PLATFORM_NAME(CHERRYVIEW), 55 PLATFORM_NAME(SKYLAKE), 56 PLATFORM_NAME(BROXTON), 57 PLATFORM_NAME(KABYLAKE), 58 PLATFORM_NAME(GEMINILAKE), 59 PLATFORM_NAME(COFFEELAKE), 60 PLATFORM_NAME(COMETLAKE), 61 PLATFORM_NAME(CANNONLAKE), 62 PLATFORM_NAME(ICELAKE), 63 PLATFORM_NAME(ELKHARTLAKE), 64 PLATFORM_NAME(TIGERLAKE), 65 PLATFORM_NAME(ROCKETLAKE), 66 }; 67 #undef PLATFORM_NAME 68 69 const char *intel_platform_name(enum intel_platform platform) 70 { 71 BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS); 72 73 if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) || 74 platform_names[platform] == NULL)) 75 return "<unknown>"; 76 77 return platform_names[platform]; 78 } 79 80 static const char *iommu_name(void) 81 { 82 const char *msg = "n/a"; 83 84 #ifdef CONFIG_INTEL_IOMMU 85 msg = enableddisabled(intel_iommu_gfx_mapped); 86 #endif 87 88 return msg; 89 } 90 91 void intel_device_info_print_static(const struct intel_device_info *info, 92 struct drm_printer *p) 93 { 94 drm_printf(p, "engines: %x\n", info->engine_mask); 95 drm_printf(p, "gen: %d\n", info->gen); 96 drm_printf(p, "gt: %d\n", info->gt); 97 drm_printf(p, "iommu: %s\n", iommu_name()); 98 drm_printf(p, "memory-regions: %x\n", info->memory_regions); 99 drm_printf(p, "page-sizes: %x\n", info->page_sizes); 100 drm_printf(p, "platform: %s\n", intel_platform_name(info->platform)); 101 drm_printf(p, "ppgtt-size: %d\n", info->ppgtt_size); 102 drm_printf(p, "ppgtt-type: %d\n", info->ppgtt_type); 103 drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size); 104 105 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name)); 106 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); 107 #undef PRINT_FLAG 108 109 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->display.name)); 110 DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG); 111 #undef PRINT_FLAG 112 } 113 114 static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p) 115 { 116 int s; 117 118 drm_printf(p, "slice total: %u, mask=%04x\n", 119 hweight8(sseu->slice_mask), sseu->slice_mask); 120 drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu)); 121 for (s = 0; s < sseu->max_slices; s++) { 122 drm_printf(p, "slice%d: %u subslices, mask=%08x\n", 123 s, intel_sseu_subslices_per_slice(sseu, s), 124 intel_sseu_get_subslices(sseu, s)); 125 } 126 drm_printf(p, "EU total: %u\n", sseu->eu_total); 127 drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice); 128 drm_printf(p, "has slice power gating: %s\n", 129 yesno(sseu->has_slice_pg)); 130 drm_printf(p, "has subslice power gating: %s\n", 131 yesno(sseu->has_subslice_pg)); 132 drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg)); 133 } 134 135 void intel_device_info_print_runtime(const struct intel_runtime_info *info, 136 struct drm_printer *p) 137 { 138 sseu_dump(&info->sseu, p); 139 140 drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq); 141 drm_printf(p, "CS timestamp frequency: %u Hz\n", 142 info->cs_timestamp_frequency_hz); 143 } 144 145 static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice, 146 int subslice) 147 { 148 int slice_stride = sseu->max_subslices * sseu->eu_stride; 149 150 return slice * slice_stride + subslice * sseu->eu_stride; 151 } 152 153 static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice, 154 int subslice) 155 { 156 int i, offset = sseu_eu_idx(sseu, slice, subslice); 157 u16 eu_mask = 0; 158 159 for (i = 0; i < sseu->eu_stride; i++) { 160 eu_mask |= ((u16)sseu->eu_mask[offset + i]) << 161 (i * BITS_PER_BYTE); 162 } 163 164 return eu_mask; 165 } 166 167 static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice, 168 u16 eu_mask) 169 { 170 int i, offset = sseu_eu_idx(sseu, slice, subslice); 171 172 for (i = 0; i < sseu->eu_stride; i++) { 173 sseu->eu_mask[offset + i] = 174 (eu_mask >> (BITS_PER_BYTE * i)) & 0xff; 175 } 176 } 177 178 void intel_device_info_print_topology(const struct sseu_dev_info *sseu, 179 struct drm_printer *p) 180 { 181 int s, ss; 182 183 if (sseu->max_slices == 0) { 184 drm_printf(p, "Unavailable\n"); 185 return; 186 } 187 188 for (s = 0; s < sseu->max_slices; s++) { 189 drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n", 190 s, intel_sseu_subslices_per_slice(sseu, s), 191 intel_sseu_get_subslices(sseu, s)); 192 193 for (ss = 0; ss < sseu->max_subslices; ss++) { 194 u16 enabled_eus = sseu_get_eus(sseu, s, ss); 195 196 drm_printf(p, "\tsubslice%d: %u EUs (0x%hx)\n", 197 ss, hweight16(enabled_eus), enabled_eus); 198 } 199 } 200 } 201 202 static u16 compute_eu_total(const struct sseu_dev_info *sseu) 203 { 204 u16 i, total = 0; 205 206 for (i = 0; i < ARRAY_SIZE(sseu->eu_mask); i++) 207 total += hweight8(sseu->eu_mask[i]); 208 209 return total; 210 } 211 212 static void gen11_compute_sseu_info(struct sseu_dev_info *sseu, 213 u8 s_en, u32 ss_en, u16 eu_en) 214 { 215 int s, ss; 216 217 /* ss_en represents entire subslice mask across all slices */ 218 GEM_BUG_ON(sseu->max_slices * sseu->max_subslices > 219 sizeof(ss_en) * BITS_PER_BYTE); 220 221 for (s = 0; s < sseu->max_slices; s++) { 222 if ((s_en & BIT(s)) == 0) 223 continue; 224 225 sseu->slice_mask |= BIT(s); 226 227 intel_sseu_set_subslices(sseu, s, ss_en); 228 229 for (ss = 0; ss < sseu->max_subslices; ss++) 230 if (intel_sseu_has_subslice(sseu, s, ss)) 231 sseu_set_eus(sseu, s, ss, eu_en); 232 } 233 sseu->eu_per_subslice = hweight16(eu_en); 234 sseu->eu_total = compute_eu_total(sseu); 235 } 236 237 static void gen12_sseu_info_init(struct drm_i915_private *dev_priv) 238 { 239 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; 240 u8 s_en; 241 u32 dss_en; 242 u16 eu_en = 0; 243 u8 eu_en_fuse; 244 int eu; 245 246 /* 247 * Gen12 has Dual-Subslices, which behave similarly to 2 gen11 SS. 248 * Instead of splitting these, provide userspace with an array 249 * of DSS to more closely represent the hardware resource. 250 */ 251 intel_sseu_set_info(sseu, 1, 6, 16); 252 253 s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK; 254 255 dss_en = I915_READ(GEN12_GT_DSS_ENABLE); 256 257 /* one bit per pair of EUs */ 258 eu_en_fuse = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK); 259 for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++) 260 if (eu_en_fuse & BIT(eu)) 261 eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1); 262 263 gen11_compute_sseu_info(sseu, s_en, dss_en, eu_en); 264 265 /* TGL only supports slice-level power gating */ 266 sseu->has_slice_pg = 1; 267 } 268 269 static void gen11_sseu_info_init(struct drm_i915_private *dev_priv) 270 { 271 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; 272 u8 s_en; 273 u32 ss_en; 274 u8 eu_en; 275 276 if (IS_ELKHARTLAKE(dev_priv)) 277 intel_sseu_set_info(sseu, 1, 4, 8); 278 else 279 intel_sseu_set_info(sseu, 1, 8, 8); 280 281 s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK; 282 ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE); 283 eu_en = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK); 284 285 gen11_compute_sseu_info(sseu, s_en, ss_en, eu_en); 286 287 /* ICL has no power gating restrictions. */ 288 sseu->has_slice_pg = 1; 289 sseu->has_subslice_pg = 1; 290 sseu->has_eu_pg = 1; 291 } 292 293 static void gen10_sseu_info_init(struct drm_i915_private *dev_priv) 294 { 295 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; 296 const u32 fuse2 = I915_READ(GEN8_FUSE2); 297 int s, ss; 298 const int eu_mask = 0xff; 299 u32 subslice_mask, eu_en; 300 301 intel_sseu_set_info(sseu, 6, 4, 8); 302 303 sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >> 304 GEN10_F2_S_ENA_SHIFT; 305 306 /* Slice0 */ 307 eu_en = ~I915_READ(GEN8_EU_DISABLE0); 308 for (ss = 0; ss < sseu->max_subslices; ss++) 309 sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask); 310 /* Slice1 */ 311 sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask); 312 eu_en = ~I915_READ(GEN8_EU_DISABLE1); 313 sseu_set_eus(sseu, 1, 1, eu_en & eu_mask); 314 /* Slice2 */ 315 sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask); 316 sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask); 317 /* Slice3 */ 318 sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask); 319 eu_en = ~I915_READ(GEN8_EU_DISABLE2); 320 sseu_set_eus(sseu, 3, 1, eu_en & eu_mask); 321 /* Slice4 */ 322 sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask); 323 sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask); 324 /* Slice5 */ 325 sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask); 326 eu_en = ~I915_READ(GEN10_EU_DISABLE3); 327 sseu_set_eus(sseu, 5, 1, eu_en & eu_mask); 328 329 subslice_mask = (1 << 4) - 1; 330 subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >> 331 GEN10_F2_SS_DIS_SHIFT); 332 333 for (s = 0; s < sseu->max_slices; s++) { 334 u32 subslice_mask_with_eus = subslice_mask; 335 336 for (ss = 0; ss < sseu->max_subslices; ss++) { 337 if (sseu_get_eus(sseu, s, ss) == 0) 338 subslice_mask_with_eus &= ~BIT(ss); 339 } 340 341 /* 342 * Slice0 can have up to 3 subslices, but there are only 2 in 343 * slice1/2. 344 */ 345 intel_sseu_set_subslices(sseu, s, s == 0 ? 346 subslice_mask_with_eus : 347 subslice_mask_with_eus & 0x3); 348 } 349 350 sseu->eu_total = compute_eu_total(sseu); 351 352 /* 353 * CNL is expected to always have a uniform distribution 354 * of EU across subslices with the exception that any one 355 * EU in any one subslice may be fused off for die 356 * recovery. 357 */ 358 sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? 359 DIV_ROUND_UP(sseu->eu_total, 360 intel_sseu_subslice_total(sseu)) : 361 0; 362 363 /* No restrictions on Power Gating */ 364 sseu->has_slice_pg = 1; 365 sseu->has_subslice_pg = 1; 366 sseu->has_eu_pg = 1; 367 } 368 369 static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv) 370 { 371 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; 372 u32 fuse; 373 u8 subslice_mask = 0; 374 375 fuse = I915_READ(CHV_FUSE_GT); 376 377 sseu->slice_mask = BIT(0); 378 intel_sseu_set_info(sseu, 1, 2, 8); 379 380 if (!(fuse & CHV_FGT_DISABLE_SS0)) { 381 u8 disabled_mask = 382 ((fuse & CHV_FGT_EU_DIS_SS0_R0_MASK) >> 383 CHV_FGT_EU_DIS_SS0_R0_SHIFT) | 384 (((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >> 385 CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4); 386 387 subslice_mask |= BIT(0); 388 sseu_set_eus(sseu, 0, 0, ~disabled_mask); 389 } 390 391 if (!(fuse & CHV_FGT_DISABLE_SS1)) { 392 u8 disabled_mask = 393 ((fuse & CHV_FGT_EU_DIS_SS1_R0_MASK) >> 394 CHV_FGT_EU_DIS_SS1_R0_SHIFT) | 395 (((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >> 396 CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4); 397 398 subslice_mask |= BIT(1); 399 sseu_set_eus(sseu, 0, 1, ~disabled_mask); 400 } 401 402 intel_sseu_set_subslices(sseu, 0, subslice_mask); 403 404 sseu->eu_total = compute_eu_total(sseu); 405 406 /* 407 * CHV expected to always have a uniform distribution of EU 408 * across subslices. 409 */ 410 sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? 411 sseu->eu_total / 412 intel_sseu_subslice_total(sseu) : 413 0; 414 /* 415 * CHV supports subslice power gating on devices with more than 416 * one subslice, and supports EU power gating on devices with 417 * more than one EU pair per subslice. 418 */ 419 sseu->has_slice_pg = 0; 420 sseu->has_subslice_pg = intel_sseu_subslice_total(sseu) > 1; 421 sseu->has_eu_pg = (sseu->eu_per_subslice > 2); 422 } 423 424 static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) 425 { 426 struct intel_device_info *info = mkwrite_device_info(dev_priv); 427 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; 428 int s, ss; 429 u32 fuse2, eu_disable, subslice_mask; 430 const u8 eu_mask = 0xff; 431 432 fuse2 = I915_READ(GEN8_FUSE2); 433 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; 434 435 /* BXT has a single slice and at most 3 subslices. */ 436 intel_sseu_set_info(sseu, IS_GEN9_LP(dev_priv) ? 1 : 3, 437 IS_GEN9_LP(dev_priv) ? 3 : 4, 8); 438 439 /* 440 * The subslice disable field is global, i.e. it applies 441 * to each of the enabled slices. 442 */ 443 subslice_mask = (1 << sseu->max_subslices) - 1; 444 subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >> 445 GEN9_F2_SS_DIS_SHIFT); 446 447 /* 448 * Iterate through enabled slices and subslices to 449 * count the total enabled EU. 450 */ 451 for (s = 0; s < sseu->max_slices; s++) { 452 if (!(sseu->slice_mask & BIT(s))) 453 /* skip disabled slice */ 454 continue; 455 456 intel_sseu_set_subslices(sseu, s, subslice_mask); 457 458 eu_disable = I915_READ(GEN9_EU_DISABLE(s)); 459 for (ss = 0; ss < sseu->max_subslices; ss++) { 460 int eu_per_ss; 461 u8 eu_disabled_mask; 462 463 if (!intel_sseu_has_subslice(sseu, s, ss)) 464 /* skip disabled subslice */ 465 continue; 466 467 eu_disabled_mask = (eu_disable >> (ss * 8)) & eu_mask; 468 469 sseu_set_eus(sseu, s, ss, ~eu_disabled_mask); 470 471 eu_per_ss = sseu->max_eus_per_subslice - 472 hweight8(eu_disabled_mask); 473 474 /* 475 * Record which subslice(s) has(have) 7 EUs. we 476 * can tune the hash used to spread work among 477 * subslices if they are unbalanced. 478 */ 479 if (eu_per_ss == 7) 480 sseu->subslice_7eu[s] |= BIT(ss); 481 } 482 } 483 484 sseu->eu_total = compute_eu_total(sseu); 485 486 /* 487 * SKL is expected to always have a uniform distribution 488 * of EU across subslices with the exception that any one 489 * EU in any one subslice may be fused off for die 490 * recovery. BXT is expected to be perfectly uniform in EU 491 * distribution. 492 */ 493 sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? 494 DIV_ROUND_UP(sseu->eu_total, 495 intel_sseu_subslice_total(sseu)) : 496 0; 497 /* 498 * SKL+ supports slice power gating on devices with more than 499 * one slice, and supports EU power gating on devices with 500 * more than one EU pair per subslice. BXT+ supports subslice 501 * power gating on devices with more than one subslice, and 502 * supports EU power gating on devices with more than one EU 503 * pair per subslice. 504 */ 505 sseu->has_slice_pg = 506 !IS_GEN9_LP(dev_priv) && hweight8(sseu->slice_mask) > 1; 507 sseu->has_subslice_pg = 508 IS_GEN9_LP(dev_priv) && intel_sseu_subslice_total(sseu) > 1; 509 sseu->has_eu_pg = sseu->eu_per_subslice > 2; 510 511 if (IS_GEN9_LP(dev_priv)) { 512 #define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss))) 513 info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3; 514 515 sseu->min_eu_in_pool = 0; 516 if (info->has_pooled_eu) { 517 if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0)) 518 sseu->min_eu_in_pool = 3; 519 else if (IS_SS_DISABLED(1)) 520 sseu->min_eu_in_pool = 6; 521 else 522 sseu->min_eu_in_pool = 9; 523 } 524 #undef IS_SS_DISABLED 525 } 526 } 527 528 static void bdw_sseu_info_init(struct drm_i915_private *dev_priv) 529 { 530 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; 531 int s, ss; 532 u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */ 533 534 fuse2 = I915_READ(GEN8_FUSE2); 535 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; 536 intel_sseu_set_info(sseu, 3, 3, 8); 537 538 /* 539 * The subslice disable field is global, i.e. it applies 540 * to each of the enabled slices. 541 */ 542 subslice_mask = GENMASK(sseu->max_subslices - 1, 0); 543 subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >> 544 GEN8_F2_SS_DIS_SHIFT); 545 546 eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK; 547 eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) | 548 ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) << 549 (32 - GEN8_EU_DIS0_S1_SHIFT)); 550 eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) | 551 ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) << 552 (32 - GEN8_EU_DIS1_S2_SHIFT)); 553 554 /* 555 * Iterate through enabled slices and subslices to 556 * count the total enabled EU. 557 */ 558 for (s = 0; s < sseu->max_slices; s++) { 559 if (!(sseu->slice_mask & BIT(s))) 560 /* skip disabled slice */ 561 continue; 562 563 intel_sseu_set_subslices(sseu, s, subslice_mask); 564 565 for (ss = 0; ss < sseu->max_subslices; ss++) { 566 u8 eu_disabled_mask; 567 u32 n_disabled; 568 569 if (!intel_sseu_has_subslice(sseu, s, ss)) 570 /* skip disabled subslice */ 571 continue; 572 573 eu_disabled_mask = 574 eu_disable[s] >> (ss * sseu->max_eus_per_subslice); 575 576 sseu_set_eus(sseu, s, ss, ~eu_disabled_mask); 577 578 n_disabled = hweight8(eu_disabled_mask); 579 580 /* 581 * Record which subslices have 7 EUs. 582 */ 583 if (sseu->max_eus_per_subslice - n_disabled == 7) 584 sseu->subslice_7eu[s] |= 1 << ss; 585 } 586 } 587 588 sseu->eu_total = compute_eu_total(sseu); 589 590 /* 591 * BDW is expected to always have a uniform distribution of EU across 592 * subslices with the exception that any one EU in any one subslice may 593 * be fused off for die recovery. 594 */ 595 sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? 596 DIV_ROUND_UP(sseu->eu_total, 597 intel_sseu_subslice_total(sseu)) : 598 0; 599 600 /* 601 * BDW supports slice power gating on devices with more than 602 * one slice. 603 */ 604 sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1; 605 sseu->has_subslice_pg = 0; 606 sseu->has_eu_pg = 0; 607 } 608 609 static void hsw_sseu_info_init(struct drm_i915_private *dev_priv) 610 { 611 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; 612 u32 fuse1; 613 u8 subslice_mask = 0; 614 int s, ss; 615 616 /* 617 * There isn't a register to tell us how many slices/subslices. We 618 * work off the PCI-ids here. 619 */ 620 switch (INTEL_INFO(dev_priv)->gt) { 621 default: 622 MISSING_CASE(INTEL_INFO(dev_priv)->gt); 623 /* fall through */ 624 case 1: 625 sseu->slice_mask = BIT(0); 626 subslice_mask = BIT(0); 627 break; 628 case 2: 629 sseu->slice_mask = BIT(0); 630 subslice_mask = BIT(0) | BIT(1); 631 break; 632 case 3: 633 sseu->slice_mask = BIT(0) | BIT(1); 634 subslice_mask = BIT(0) | BIT(1); 635 break; 636 } 637 638 fuse1 = I915_READ(HSW_PAVP_FUSE1); 639 switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) { 640 default: 641 MISSING_CASE((fuse1 & HSW_F1_EU_DIS_MASK) >> 642 HSW_F1_EU_DIS_SHIFT); 643 /* fall through */ 644 case HSW_F1_EU_DIS_10EUS: 645 sseu->eu_per_subslice = 10; 646 break; 647 case HSW_F1_EU_DIS_8EUS: 648 sseu->eu_per_subslice = 8; 649 break; 650 case HSW_F1_EU_DIS_6EUS: 651 sseu->eu_per_subslice = 6; 652 break; 653 } 654 655 intel_sseu_set_info(sseu, hweight8(sseu->slice_mask), 656 hweight8(subslice_mask), 657 sseu->eu_per_subslice); 658 659 for (s = 0; s < sseu->max_slices; s++) { 660 intel_sseu_set_subslices(sseu, s, subslice_mask); 661 662 for (ss = 0; ss < sseu->max_subslices; ss++) { 663 sseu_set_eus(sseu, s, ss, 664 (1UL << sseu->eu_per_subslice) - 1); 665 } 666 } 667 668 sseu->eu_total = compute_eu_total(sseu); 669 670 /* No powergating for you. */ 671 sseu->has_slice_pg = 0; 672 sseu->has_subslice_pg = 0; 673 sseu->has_eu_pg = 0; 674 } 675 676 static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv) 677 { 678 u32 ts_override = I915_READ(GEN9_TIMESTAMP_OVERRIDE); 679 u32 base_freq, frac_freq; 680 681 base_freq = ((ts_override & GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >> 682 GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1; 683 base_freq *= 1000000; 684 685 frac_freq = ((ts_override & 686 GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >> 687 GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT); 688 frac_freq = 1000000 / (frac_freq + 1); 689 690 return base_freq + frac_freq; 691 } 692 693 static u32 gen10_get_crystal_clock_freq(struct drm_i915_private *dev_priv, 694 u32 rpm_config_reg) 695 { 696 u32 f19_2_mhz = 19200000; 697 u32 f24_mhz = 24000000; 698 u32 crystal_clock = (rpm_config_reg & 699 GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >> 700 GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT; 701 702 switch (crystal_clock) { 703 case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ: 704 return f19_2_mhz; 705 case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ: 706 return f24_mhz; 707 default: 708 MISSING_CASE(crystal_clock); 709 return 0; 710 } 711 } 712 713 static u32 gen11_get_crystal_clock_freq(struct drm_i915_private *dev_priv, 714 u32 rpm_config_reg) 715 { 716 u32 f19_2_mhz = 19200000; 717 u32 f24_mhz = 24000000; 718 u32 f25_mhz = 25000000; 719 u32 f38_4_mhz = 38400000; 720 u32 crystal_clock = (rpm_config_reg & 721 GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >> 722 GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT; 723 724 switch (crystal_clock) { 725 case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ: 726 return f24_mhz; 727 case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ: 728 return f19_2_mhz; 729 case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ: 730 return f38_4_mhz; 731 case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ: 732 return f25_mhz; 733 default: 734 MISSING_CASE(crystal_clock); 735 return 0; 736 } 737 } 738 739 static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv) 740 { 741 u32 f12_5_mhz = 12500000; 742 u32 f19_2_mhz = 19200000; 743 u32 f24_mhz = 24000000; 744 745 if (INTEL_GEN(dev_priv) <= 4) { 746 /* PRMs say: 747 * 748 * "The value in this register increments once every 16 749 * hclks." (through the “Clocking Configuration” 750 * (“CLKCFG”) MCHBAR register) 751 */ 752 return RUNTIME_INFO(dev_priv)->rawclk_freq * 1000 / 16; 753 } else if (INTEL_GEN(dev_priv) <= 8) { 754 /* PRMs say: 755 * 756 * "The PCU TSC counts 10ns increments; this timestamp 757 * reflects bits 38:3 of the TSC (i.e. 80ns granularity, 758 * rolling over every 1.5 hours). 759 */ 760 return f12_5_mhz; 761 } else if (INTEL_GEN(dev_priv) <= 9) { 762 u32 ctc_reg = I915_READ(CTC_MODE); 763 u32 freq = 0; 764 765 if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) { 766 freq = read_reference_ts_freq(dev_priv); 767 } else { 768 freq = IS_GEN9_LP(dev_priv) ? f19_2_mhz : f24_mhz; 769 770 /* Now figure out how the command stream's timestamp 771 * register increments from this frequency (it might 772 * increment only every few clock cycle). 773 */ 774 freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >> 775 CTC_SHIFT_PARAMETER_SHIFT); 776 } 777 778 return freq; 779 } else if (INTEL_GEN(dev_priv) <= 12) { 780 u32 ctc_reg = I915_READ(CTC_MODE); 781 u32 freq = 0; 782 783 /* First figure out the reference frequency. There are 2 ways 784 * we can compute the frequency, either through the 785 * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE 786 * tells us which one we should use. 787 */ 788 if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) { 789 freq = read_reference_ts_freq(dev_priv); 790 } else { 791 u32 rpm_config_reg = I915_READ(RPM_CONFIG0); 792 793 if (INTEL_GEN(dev_priv) <= 10) 794 freq = gen10_get_crystal_clock_freq(dev_priv, 795 rpm_config_reg); 796 else 797 freq = gen11_get_crystal_clock_freq(dev_priv, 798 rpm_config_reg); 799 800 /* Now figure out how the command stream's timestamp 801 * register increments from this frequency (it might 802 * increment only every few clock cycle). 803 */ 804 freq >>= 3 - ((rpm_config_reg & 805 GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >> 806 GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT); 807 } 808 809 return freq; 810 } 811 812 MISSING_CASE("Unknown gen, unable to read command streamer timestamp frequency\n"); 813 return 0; 814 } 815 816 #undef INTEL_VGA_DEVICE 817 #define INTEL_VGA_DEVICE(id, info) (id) 818 819 static const u16 subplatform_ult_ids[] = { 820 INTEL_HSW_ULT_GT1_IDS(0), 821 INTEL_HSW_ULT_GT2_IDS(0), 822 INTEL_HSW_ULT_GT3_IDS(0), 823 INTEL_BDW_ULT_GT1_IDS(0), 824 INTEL_BDW_ULT_GT2_IDS(0), 825 INTEL_BDW_ULT_GT3_IDS(0), 826 INTEL_BDW_ULT_RSVD_IDS(0), 827 INTEL_SKL_ULT_GT1_IDS(0), 828 INTEL_SKL_ULT_GT2_IDS(0), 829 INTEL_SKL_ULT_GT3_IDS(0), 830 INTEL_KBL_ULT_GT1_IDS(0), 831 INTEL_KBL_ULT_GT2_IDS(0), 832 INTEL_KBL_ULT_GT3_IDS(0), 833 INTEL_CFL_U_GT2_IDS(0), 834 INTEL_CFL_U_GT3_IDS(0), 835 INTEL_WHL_U_GT1_IDS(0), 836 INTEL_WHL_U_GT2_IDS(0), 837 INTEL_WHL_U_GT3_IDS(0), 838 INTEL_CML_U_GT1_IDS(0), 839 INTEL_CML_U_GT2_IDS(0), 840 }; 841 842 static const u16 subplatform_ulx_ids[] = { 843 INTEL_HSW_ULX_GT1_IDS(0), 844 INTEL_HSW_ULX_GT2_IDS(0), 845 INTEL_BDW_ULX_GT1_IDS(0), 846 INTEL_BDW_ULX_GT2_IDS(0), 847 INTEL_BDW_ULX_GT3_IDS(0), 848 INTEL_BDW_ULX_RSVD_IDS(0), 849 INTEL_SKL_ULX_GT1_IDS(0), 850 INTEL_SKL_ULX_GT2_IDS(0), 851 INTEL_KBL_ULX_GT1_IDS(0), 852 INTEL_KBL_ULX_GT2_IDS(0), 853 INTEL_AML_KBL_GT2_IDS(0), 854 INTEL_AML_CFL_GT2_IDS(0), 855 }; 856 857 static const u16 subplatform_portf_ids[] = { 858 INTEL_CNL_PORT_F_IDS(0), 859 INTEL_ICL_PORT_F_IDS(0), 860 }; 861 862 static bool find_devid(u16 id, const u16 *p, unsigned int num) 863 { 864 for (; num; num--, p++) { 865 if (*p == id) 866 return true; 867 } 868 869 return false; 870 } 871 872 void intel_device_info_subplatform_init(struct drm_i915_private *i915) 873 { 874 const struct intel_device_info *info = INTEL_INFO(i915); 875 const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915); 876 const unsigned int pi = __platform_mask_index(rinfo, info->platform); 877 const unsigned int pb = __platform_mask_bit(rinfo, info->platform); 878 u16 devid = INTEL_DEVID(i915); 879 u32 mask = 0; 880 881 /* Make sure IS_<platform> checks are working. */ 882 RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb); 883 884 /* Find and mark subplatform bits based on the PCI device id. */ 885 if (find_devid(devid, subplatform_ult_ids, 886 ARRAY_SIZE(subplatform_ult_ids))) { 887 mask = BIT(INTEL_SUBPLATFORM_ULT); 888 } else if (find_devid(devid, subplatform_ulx_ids, 889 ARRAY_SIZE(subplatform_ulx_ids))) { 890 mask = BIT(INTEL_SUBPLATFORM_ULX); 891 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 892 /* ULX machines are also considered ULT. */ 893 mask |= BIT(INTEL_SUBPLATFORM_ULT); 894 } 895 } else if (find_devid(devid, subplatform_portf_ids, 896 ARRAY_SIZE(subplatform_portf_ids))) { 897 mask = BIT(INTEL_SUBPLATFORM_PORTF); 898 } 899 900 GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_BITS); 901 902 RUNTIME_INFO(i915)->platform_mask[pi] |= mask; 903 } 904 905 /** 906 * intel_device_info_runtime_init - initialize runtime info 907 * @dev_priv: the i915 device 908 * 909 * Determine various intel_device_info fields at runtime. 910 * 911 * Use it when either: 912 * - it's judged too laborious to fill n static structures with the limit 913 * when a simple if statement does the job, 914 * - run-time checks (eg read fuse/strap registers) are needed. 915 * 916 * This function needs to be called: 917 * - after the MMIO has been setup as we are reading registers, 918 * - after the PCH has been detected, 919 * - before the first usage of the fields it can tweak. 920 */ 921 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) 922 { 923 struct intel_device_info *info = mkwrite_device_info(dev_priv); 924 struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv); 925 enum pipe pipe; 926 927 if (INTEL_GEN(dev_priv) >= 10) { 928 for_each_pipe(dev_priv, pipe) 929 runtime->num_scalers[pipe] = 2; 930 } else if (IS_GEN(dev_priv, 9)) { 931 runtime->num_scalers[PIPE_A] = 2; 932 runtime->num_scalers[PIPE_B] = 2; 933 runtime->num_scalers[PIPE_C] = 1; 934 } 935 936 BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES); 937 938 if (IS_ROCKETLAKE(dev_priv)) 939 for_each_pipe(dev_priv, pipe) 940 runtime->num_sprites[pipe] = 4; 941 else if (INTEL_GEN(dev_priv) >= 11) 942 for_each_pipe(dev_priv, pipe) 943 runtime->num_sprites[pipe] = 6; 944 else if (IS_GEN(dev_priv, 10) || IS_GEMINILAKE(dev_priv)) 945 for_each_pipe(dev_priv, pipe) 946 runtime->num_sprites[pipe] = 3; 947 else if (IS_BROXTON(dev_priv)) { 948 /* 949 * Skylake and Broxton currently don't expose the topmost plane as its 950 * use is exclusive with the legacy cursor and we only want to expose 951 * one of those, not both. Until we can safely expose the topmost plane 952 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported, 953 * we don't expose the topmost plane at all to prevent ABI breakage 954 * down the line. 955 */ 956 957 runtime->num_sprites[PIPE_A] = 2; 958 runtime->num_sprites[PIPE_B] = 2; 959 runtime->num_sprites[PIPE_C] = 1; 960 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 961 for_each_pipe(dev_priv, pipe) 962 runtime->num_sprites[pipe] = 2; 963 } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) { 964 for_each_pipe(dev_priv, pipe) 965 runtime->num_sprites[pipe] = 1; 966 } 967 968 if (HAS_DISPLAY(dev_priv) && IS_GEN_RANGE(dev_priv, 7, 8) && 969 HAS_PCH_SPLIT(dev_priv)) { 970 u32 fuse_strap = I915_READ(FUSE_STRAP); 971 u32 sfuse_strap = I915_READ(SFUSE_STRAP); 972 973 /* 974 * SFUSE_STRAP is supposed to have a bit signalling the display 975 * is fused off. Unfortunately it seems that, at least in 976 * certain cases, fused off display means that PCH display 977 * reads don't land anywhere. In that case, we read 0s. 978 * 979 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK 980 * should be set when taking over after the firmware. 981 */ 982 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || 983 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || 984 (HAS_PCH_CPT(dev_priv) && 985 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { 986 drm_info(&dev_priv->drm, 987 "Display fused off, disabling\n"); 988 info->pipe_mask = 0; 989 info->cpu_transcoder_mask = 0; 990 } else if (fuse_strap & IVB_PIPE_C_DISABLE) { 991 drm_info(&dev_priv->drm, "PipeC fused off\n"); 992 info->pipe_mask &= ~BIT(PIPE_C); 993 info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); 994 } 995 } else if (HAS_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 9) { 996 u32 dfsm = I915_READ(SKL_DFSM); 997 998 if (dfsm & SKL_DFSM_PIPE_A_DISABLE) { 999 info->pipe_mask &= ~BIT(PIPE_A); 1000 info->cpu_transcoder_mask &= ~BIT(TRANSCODER_A); 1001 } 1002 if (dfsm & SKL_DFSM_PIPE_B_DISABLE) { 1003 info->pipe_mask &= ~BIT(PIPE_B); 1004 info->cpu_transcoder_mask &= ~BIT(TRANSCODER_B); 1005 } 1006 if (dfsm & SKL_DFSM_PIPE_C_DISABLE) { 1007 info->pipe_mask &= ~BIT(PIPE_C); 1008 info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); 1009 } 1010 if (INTEL_GEN(dev_priv) >= 12 && 1011 (dfsm & TGL_DFSM_PIPE_D_DISABLE)) { 1012 info->pipe_mask &= ~BIT(PIPE_D); 1013 info->cpu_transcoder_mask &= ~BIT(TRANSCODER_D); 1014 } 1015 1016 if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE) 1017 info->display.has_hdcp = 0; 1018 1019 if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE) 1020 info->display.has_fbc = 0; 1021 1022 if (INTEL_GEN(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) 1023 info->display.has_csr = 0; 1024 1025 if (INTEL_GEN(dev_priv) >= 10 && 1026 (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE)) 1027 info->display.has_dsc = 0; 1028 } 1029 1030 /* Initialize slice/subslice/EU info */ 1031 if (IS_HASWELL(dev_priv)) 1032 hsw_sseu_info_init(dev_priv); 1033 else if (IS_CHERRYVIEW(dev_priv)) 1034 cherryview_sseu_info_init(dev_priv); 1035 else if (IS_BROADWELL(dev_priv)) 1036 bdw_sseu_info_init(dev_priv); 1037 else if (IS_GEN(dev_priv, 9)) 1038 gen9_sseu_info_init(dev_priv); 1039 else if (IS_GEN(dev_priv, 10)) 1040 gen10_sseu_info_init(dev_priv); 1041 else if (IS_GEN(dev_priv, 11)) 1042 gen11_sseu_info_init(dev_priv); 1043 else if (INTEL_GEN(dev_priv) >= 12) 1044 gen12_sseu_info_init(dev_priv); 1045 1046 if (IS_GEN(dev_priv, 6) && intel_vtd_active()) { 1047 drm_info(&dev_priv->drm, 1048 "Disabling ppGTT for VT-d support\n"); 1049 info->ppgtt_type = INTEL_PPGTT_NONE; 1050 } 1051 1052 runtime->rawclk_freq = intel_read_rawclk(dev_priv); 1053 drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq); 1054 1055 /* Initialize command stream timestamp frequency */ 1056 runtime->cs_timestamp_frequency_hz = 1057 read_timestamp_frequency(dev_priv); 1058 if (runtime->cs_timestamp_frequency_hz) { 1059 runtime->cs_timestamp_period_ns = 1060 i915_cs_timestamp_ticks_to_ns(dev_priv, 1); 1061 drm_dbg(&dev_priv->drm, 1062 "CS timestamp wraparound in %lldms\n", 1063 div_u64(mul_u32_u32(runtime->cs_timestamp_period_ns, 1064 S32_MAX), 1065 USEC_PER_SEC)); 1066 } 1067 } 1068 1069 void intel_driver_caps_print(const struct intel_driver_caps *caps, 1070 struct drm_printer *p) 1071 { 1072 drm_printf(p, "Has logical contexts? %s\n", 1073 yesno(caps->has_logical_contexts)); 1074 drm_printf(p, "scheduler: %x\n", caps->scheduler); 1075 } 1076 1077 /* 1078 * Determine which engines are fused off in our particular hardware. Since the 1079 * fuse register is in the blitter powerwell, we need forcewake to be ready at 1080 * this point (but later we need to prune the forcewake domains for engines that 1081 * are indeed fused off). 1082 */ 1083 void intel_device_info_init_mmio(struct drm_i915_private *dev_priv) 1084 { 1085 struct intel_device_info *info = mkwrite_device_info(dev_priv); 1086 unsigned int logical_vdbox = 0; 1087 unsigned int i; 1088 u32 media_fuse; 1089 u16 vdbox_mask; 1090 u16 vebox_mask; 1091 1092 if (INTEL_GEN(dev_priv) < 11) 1093 return; 1094 1095 media_fuse = ~I915_READ(GEN11_GT_VEBOX_VDBOX_DISABLE); 1096 1097 vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK; 1098 vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >> 1099 GEN11_GT_VEBOX_DISABLE_SHIFT; 1100 1101 for (i = 0; i < I915_MAX_VCS; i++) { 1102 if (!HAS_ENGINE(dev_priv, _VCS(i))) { 1103 vdbox_mask &= ~BIT(i); 1104 continue; 1105 } 1106 1107 if (!(BIT(i) & vdbox_mask)) { 1108 info->engine_mask &= ~BIT(_VCS(i)); 1109 drm_dbg(&dev_priv->drm, "vcs%u fused off\n", i); 1110 continue; 1111 } 1112 1113 /* 1114 * In Gen11, only even numbered logical VDBOXes are 1115 * hooked up to an SFC (Scaler & Format Converter) unit. 1116 * In TGL each VDBOX has access to an SFC. 1117 */ 1118 if (INTEL_GEN(dev_priv) >= 12 || logical_vdbox++ % 2 == 0) 1119 RUNTIME_INFO(dev_priv)->vdbox_sfc_access |= BIT(i); 1120 } 1121 drm_dbg(&dev_priv->drm, "vdbox enable: %04x, instances: %04lx\n", 1122 vdbox_mask, VDBOX_MASK(dev_priv)); 1123 GEM_BUG_ON(vdbox_mask != VDBOX_MASK(dev_priv)); 1124 1125 for (i = 0; i < I915_MAX_VECS; i++) { 1126 if (!HAS_ENGINE(dev_priv, _VECS(i))) { 1127 vebox_mask &= ~BIT(i); 1128 continue; 1129 } 1130 1131 if (!(BIT(i) & vebox_mask)) { 1132 info->engine_mask &= ~BIT(_VECS(i)); 1133 drm_dbg(&dev_priv->drm, "vecs%u fused off\n", i); 1134 } 1135 } 1136 drm_dbg(&dev_priv->drm, "vebox enable: %04x, instances: %04lx\n", 1137 vebox_mask, VEBOX_MASK(dev_priv)); 1138 GEM_BUG_ON(vebox_mask != VEBOX_MASK(dev_priv)); 1139 } 1140