1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/string_helpers.h> 26 27 #include <drm/drm_print.h> 28 #include <drm/i915_pciids.h> 29 30 #include "display/intel_display_device.h" 31 #include "gt/intel_gt_regs.h" 32 #include "i915_drv.h" 33 #include "i915_reg.h" 34 #include "i915_utils.h" 35 #include "intel_device_info.h" 36 37 #define PLATFORM_NAME(x) [INTEL_##x] = #x 38 static const char * const platform_names[] = { 39 PLATFORM_NAME(I830), 40 PLATFORM_NAME(I845G), 41 PLATFORM_NAME(I85X), 42 PLATFORM_NAME(I865G), 43 PLATFORM_NAME(I915G), 44 PLATFORM_NAME(I915GM), 45 PLATFORM_NAME(I945G), 46 PLATFORM_NAME(I945GM), 47 PLATFORM_NAME(G33), 48 PLATFORM_NAME(PINEVIEW), 49 PLATFORM_NAME(I965G), 50 PLATFORM_NAME(I965GM), 51 PLATFORM_NAME(G45), 52 PLATFORM_NAME(GM45), 53 PLATFORM_NAME(IRONLAKE), 54 PLATFORM_NAME(SANDYBRIDGE), 55 PLATFORM_NAME(IVYBRIDGE), 56 PLATFORM_NAME(VALLEYVIEW), 57 PLATFORM_NAME(HASWELL), 58 PLATFORM_NAME(BROADWELL), 59 PLATFORM_NAME(CHERRYVIEW), 60 PLATFORM_NAME(SKYLAKE), 61 PLATFORM_NAME(BROXTON), 62 PLATFORM_NAME(KABYLAKE), 63 PLATFORM_NAME(GEMINILAKE), 64 PLATFORM_NAME(COFFEELAKE), 65 PLATFORM_NAME(COMETLAKE), 66 PLATFORM_NAME(ICELAKE), 67 PLATFORM_NAME(ELKHARTLAKE), 68 PLATFORM_NAME(JASPERLAKE), 69 PLATFORM_NAME(TIGERLAKE), 70 PLATFORM_NAME(ROCKETLAKE), 71 PLATFORM_NAME(DG1), 72 PLATFORM_NAME(ALDERLAKE_S), 73 PLATFORM_NAME(ALDERLAKE_P), 74 PLATFORM_NAME(XEHPSDV), 75 PLATFORM_NAME(DG2), 76 PLATFORM_NAME(PONTEVECCHIO), 77 PLATFORM_NAME(METEORLAKE), 78 }; 79 #undef PLATFORM_NAME 80 81 const char *intel_platform_name(enum intel_platform platform) 82 { 83 BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS); 84 85 if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) || 86 platform_names[platform] == NULL)) 87 return "<unknown>"; 88 89 return platform_names[platform]; 90 } 91 92 void intel_device_info_print(const struct intel_device_info *info, 93 const struct intel_runtime_info *runtime, 94 struct drm_printer *p) 95 { 96 if (runtime->graphics.ip.rel) 97 drm_printf(p, "graphics version: %u.%02u\n", 98 runtime->graphics.ip.ver, 99 runtime->graphics.ip.rel); 100 else 101 drm_printf(p, "graphics version: %u\n", 102 runtime->graphics.ip.ver); 103 104 if (runtime->media.ip.rel) 105 drm_printf(p, "media version: %u.%02u\n", 106 runtime->media.ip.ver, 107 runtime->media.ip.rel); 108 else 109 drm_printf(p, "media version: %u\n", 110 runtime->media.ip.ver); 111 112 drm_printf(p, "graphics stepping: %s\n", intel_step_name(runtime->step.graphics_step)); 113 drm_printf(p, "media stepping: %s\n", intel_step_name(runtime->step.media_step)); 114 drm_printf(p, "display stepping: %s\n", intel_step_name(runtime->step.display_step)); 115 drm_printf(p, "base die stepping: %s\n", intel_step_name(runtime->step.basedie_step)); 116 117 drm_printf(p, "gt: %d\n", info->gt); 118 drm_printf(p, "memory-regions: 0x%x\n", info->memory_regions); 119 drm_printf(p, "page-sizes: 0x%x\n", runtime->page_sizes); 120 drm_printf(p, "platform: %s\n", intel_platform_name(info->platform)); 121 drm_printf(p, "ppgtt-size: %d\n", runtime->ppgtt_size); 122 drm_printf(p, "ppgtt-type: %d\n", runtime->ppgtt_type); 123 drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size); 124 125 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->name)) 126 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); 127 #undef PRINT_FLAG 128 129 drm_printf(p, "has_pooled_eu: %s\n", str_yes_no(runtime->has_pooled_eu)); 130 drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq); 131 } 132 133 #undef INTEL_VGA_DEVICE 134 #define INTEL_VGA_DEVICE(id, info) (id) 135 136 static const u16 subplatform_ult_ids[] = { 137 INTEL_HSW_ULT_GT1_IDS(0), 138 INTEL_HSW_ULT_GT2_IDS(0), 139 INTEL_HSW_ULT_GT3_IDS(0), 140 INTEL_BDW_ULT_GT1_IDS(0), 141 INTEL_BDW_ULT_GT2_IDS(0), 142 INTEL_BDW_ULT_GT3_IDS(0), 143 INTEL_BDW_ULT_RSVD_IDS(0), 144 INTEL_SKL_ULT_GT1_IDS(0), 145 INTEL_SKL_ULT_GT2_IDS(0), 146 INTEL_SKL_ULT_GT3_IDS(0), 147 INTEL_KBL_ULT_GT1_IDS(0), 148 INTEL_KBL_ULT_GT2_IDS(0), 149 INTEL_KBL_ULT_GT3_IDS(0), 150 INTEL_CFL_U_GT2_IDS(0), 151 INTEL_CFL_U_GT3_IDS(0), 152 INTEL_WHL_U_GT1_IDS(0), 153 INTEL_WHL_U_GT2_IDS(0), 154 INTEL_WHL_U_GT3_IDS(0), 155 INTEL_CML_U_GT1_IDS(0), 156 INTEL_CML_U_GT2_IDS(0), 157 }; 158 159 static const u16 subplatform_ulx_ids[] = { 160 INTEL_HSW_ULX_GT1_IDS(0), 161 INTEL_HSW_ULX_GT2_IDS(0), 162 INTEL_BDW_ULX_GT1_IDS(0), 163 INTEL_BDW_ULX_GT2_IDS(0), 164 INTEL_BDW_ULX_GT3_IDS(0), 165 INTEL_BDW_ULX_RSVD_IDS(0), 166 INTEL_SKL_ULX_GT1_IDS(0), 167 INTEL_SKL_ULX_GT2_IDS(0), 168 INTEL_KBL_ULX_GT1_IDS(0), 169 INTEL_KBL_ULX_GT2_IDS(0), 170 INTEL_AML_KBL_GT2_IDS(0), 171 INTEL_AML_CFL_GT2_IDS(0), 172 }; 173 174 static const u16 subplatform_portf_ids[] = { 175 INTEL_ICL_PORT_F_IDS(0), 176 }; 177 178 static const u16 subplatform_uy_ids[] = { 179 INTEL_TGL_12_GT2_IDS(0), 180 }; 181 182 static const u16 subplatform_n_ids[] = { 183 INTEL_ADLN_IDS(0), 184 }; 185 186 static const u16 subplatform_rpl_ids[] = { 187 INTEL_RPLS_IDS(0), 188 INTEL_RPLP_IDS(0), 189 }; 190 191 static const u16 subplatform_rplu_ids[] = { 192 INTEL_RPLU_IDS(0), 193 }; 194 195 static const u16 subplatform_g10_ids[] = { 196 INTEL_DG2_G10_IDS(0), 197 INTEL_ATS_M150_IDS(0), 198 }; 199 200 static const u16 subplatform_g11_ids[] = { 201 INTEL_DG2_G11_IDS(0), 202 INTEL_ATS_M75_IDS(0), 203 }; 204 205 static const u16 subplatform_g12_ids[] = { 206 INTEL_DG2_G12_IDS(0), 207 }; 208 209 static const u16 subplatform_m_ids[] = { 210 INTEL_MTL_M_IDS(0), 211 }; 212 213 static const u16 subplatform_p_ids[] = { 214 INTEL_MTL_P_IDS(0), 215 }; 216 217 static bool find_devid(u16 id, const u16 *p, unsigned int num) 218 { 219 for (; num; num--, p++) { 220 if (*p == id) 221 return true; 222 } 223 224 return false; 225 } 226 227 static void intel_device_info_subplatform_init(struct drm_i915_private *i915) 228 { 229 const struct intel_device_info *info = INTEL_INFO(i915); 230 const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915); 231 const unsigned int pi = __platform_mask_index(rinfo, info->platform); 232 const unsigned int pb = __platform_mask_bit(rinfo, info->platform); 233 u16 devid = INTEL_DEVID(i915); 234 u32 mask = 0; 235 236 /* Make sure IS_<platform> checks are working. */ 237 RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb); 238 239 /* Find and mark subplatform bits based on the PCI device id. */ 240 if (find_devid(devid, subplatform_ult_ids, 241 ARRAY_SIZE(subplatform_ult_ids))) { 242 mask = BIT(INTEL_SUBPLATFORM_ULT); 243 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) 244 DISPLAY_RUNTIME_INFO(i915)->port_mask &= ~BIT(PORT_D); 245 } else if (find_devid(devid, subplatform_ulx_ids, 246 ARRAY_SIZE(subplatform_ulx_ids))) { 247 mask = BIT(INTEL_SUBPLATFORM_ULX); 248 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 249 /* ULX machines are also considered ULT. */ 250 mask |= BIT(INTEL_SUBPLATFORM_ULT); 251 DISPLAY_RUNTIME_INFO(i915)->port_mask &= ~BIT(PORT_D); 252 } 253 } else if (find_devid(devid, subplatform_portf_ids, 254 ARRAY_SIZE(subplatform_portf_ids))) { 255 DISPLAY_RUNTIME_INFO(i915)->port_mask |= BIT(PORT_F); 256 mask = BIT(INTEL_SUBPLATFORM_PORTF); 257 } else if (find_devid(devid, subplatform_uy_ids, 258 ARRAY_SIZE(subplatform_uy_ids))) { 259 mask = BIT(INTEL_SUBPLATFORM_UY); 260 } else if (find_devid(devid, subplatform_n_ids, 261 ARRAY_SIZE(subplatform_n_ids))) { 262 mask = BIT(INTEL_SUBPLATFORM_N); 263 } else if (find_devid(devid, subplatform_rpl_ids, 264 ARRAY_SIZE(subplatform_rpl_ids))) { 265 mask = BIT(INTEL_SUBPLATFORM_RPL); 266 if (find_devid(devid, subplatform_rplu_ids, 267 ARRAY_SIZE(subplatform_rplu_ids))) 268 mask |= BIT(INTEL_SUBPLATFORM_RPLU); 269 } else if (find_devid(devid, subplatform_g10_ids, 270 ARRAY_SIZE(subplatform_g10_ids))) { 271 mask = BIT(INTEL_SUBPLATFORM_G10); 272 } else if (find_devid(devid, subplatform_g11_ids, 273 ARRAY_SIZE(subplatform_g11_ids))) { 274 mask = BIT(INTEL_SUBPLATFORM_G11); 275 } else if (find_devid(devid, subplatform_g12_ids, 276 ARRAY_SIZE(subplatform_g12_ids))) { 277 mask = BIT(INTEL_SUBPLATFORM_G12); 278 } else if (find_devid(devid, subplatform_m_ids, 279 ARRAY_SIZE(subplatform_m_ids))) { 280 mask = BIT(INTEL_SUBPLATFORM_M); 281 } else if (find_devid(devid, subplatform_p_ids, 282 ARRAY_SIZE(subplatform_p_ids))) { 283 mask = BIT(INTEL_SUBPLATFORM_P); 284 } 285 286 GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK); 287 288 RUNTIME_INFO(i915)->platform_mask[pi] |= mask; 289 } 290 291 static void ip_ver_read(struct drm_i915_private *i915, u32 offset, struct intel_ip_version *ip) 292 { 293 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 294 void __iomem *addr; 295 u32 val; 296 u8 expected_ver = ip->ver; 297 u8 expected_rel = ip->rel; 298 299 addr = pci_iomap_range(pdev, 0, offset, sizeof(u32)); 300 if (drm_WARN_ON(&i915->drm, !addr)) 301 return; 302 303 val = ioread32(addr); 304 pci_iounmap(pdev, addr); 305 306 ip->ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val); 307 ip->rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val); 308 ip->step = REG_FIELD_GET(GMD_ID_STEP, val); 309 310 /* Sanity check against expected versions from device info */ 311 if (IP_VER(ip->ver, ip->rel) < IP_VER(expected_ver, expected_rel)) 312 drm_dbg(&i915->drm, 313 "Hardware reports GMD IP version %u.%u (REG[0x%x] = 0x%08x) but minimum expected is %u.%u\n", 314 ip->ver, ip->rel, offset, val, expected_ver, expected_rel); 315 } 316 317 /* 318 * Setup the graphics version for the current device. This must be done before 319 * any code that performs checks on GRAPHICS_VER or DISPLAY_VER, so this 320 * function should be called very early in the driver initialization sequence. 321 * 322 * Regular MMIO access is not yet setup at the point this function is called so 323 * we peek at the appropriate MMIO offset directly. The GMD_ID register is 324 * part of an 'always on' power well by design, so we don't need to worry about 325 * forcewake while reading it. 326 */ 327 static void intel_ipver_early_init(struct drm_i915_private *i915) 328 { 329 struct intel_runtime_info *runtime = RUNTIME_INFO(i915); 330 331 if (!HAS_GMD_ID(i915)) { 332 drm_WARN_ON(&i915->drm, RUNTIME_INFO(i915)->graphics.ip.ver > 12); 333 /* 334 * On older platforms, graphics and media share the same ip 335 * version and release. 336 */ 337 RUNTIME_INFO(i915)->media.ip = 338 RUNTIME_INFO(i915)->graphics.ip; 339 return; 340 } 341 342 ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_GRAPHICS), 343 &runtime->graphics.ip); 344 /* Wa_22012778468 */ 345 if (runtime->graphics.ip.ver == 0x0 && 346 INTEL_INFO(i915)->platform == INTEL_METEORLAKE) { 347 RUNTIME_INFO(i915)->graphics.ip.ver = 12; 348 RUNTIME_INFO(i915)->graphics.ip.rel = 70; 349 } 350 ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_MEDIA), 351 &runtime->media.ip); 352 } 353 354 /** 355 * intel_device_info_runtime_init_early - initialize early runtime info 356 * @i915: the i915 device 357 * 358 * Determine early intel_device_info fields at runtime. This function needs 359 * to be called before the MMIO has been setup. 360 */ 361 void intel_device_info_runtime_init_early(struct drm_i915_private *i915) 362 { 363 intel_ipver_early_init(i915); 364 intel_device_info_subplatform_init(i915); 365 } 366 367 static const struct intel_display_device_info no_display = {}; 368 369 /** 370 * intel_device_info_runtime_init - initialize runtime info 371 * @dev_priv: the i915 device 372 * 373 * Determine various intel_device_info fields at runtime. 374 * 375 * Use it when either: 376 * - it's judged too laborious to fill n static structures with the limit 377 * when a simple if statement does the job, 378 * - run-time checks (eg read fuse/strap registers) are needed. 379 * 380 * This function needs to be called: 381 * - after the MMIO has been setup as we are reading registers, 382 * - after the PCH has been detected, 383 * - before the first usage of the fields it can tweak. 384 */ 385 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) 386 { 387 struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv); 388 389 if (HAS_DISPLAY(dev_priv)) 390 intel_display_device_info_runtime_init(dev_priv); 391 392 /* Display may have been disabled by runtime init */ 393 if (!HAS_DISPLAY(dev_priv)) { 394 dev_priv->drm.driver_features &= ~(DRIVER_MODESET | 395 DRIVER_ATOMIC); 396 dev_priv->display.info.__device_info = &no_display; 397 } 398 399 /* Disable nuclear pageflip by default on pre-g4x */ 400 if (!dev_priv->params.nuclear_pageflip && 401 DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) 402 dev_priv->drm.driver_features &= ~DRIVER_ATOMIC; 403 404 BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES); 405 406 if (GRAPHICS_VER(dev_priv) == 6 && i915_vtd_active(dev_priv)) { 407 drm_info(&dev_priv->drm, 408 "Disabling ppGTT for VT-d support\n"); 409 runtime->ppgtt_type = INTEL_PPGTT_NONE; 410 } 411 412 runtime->rawclk_freq = intel_read_rawclk(dev_priv); 413 drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq); 414 415 } 416 417 /* 418 * Set up device info and initial runtime info at driver create. 419 * 420 * Note: i915 is only an allocated blob of memory at this point. 421 */ 422 void intel_device_info_driver_create(struct drm_i915_private *i915, 423 u16 device_id, 424 const struct intel_device_info *match_info) 425 { 426 struct intel_runtime_info *runtime; 427 u16 ver, rel, step; 428 429 /* Setup INTEL_INFO() */ 430 i915->__info = match_info; 431 432 /* Initialize initial runtime info from static const data and pdev. */ 433 runtime = RUNTIME_INFO(i915); 434 memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime)); 435 436 /* Probe display support */ 437 i915->display.info.__device_info = intel_display_device_probe(i915, HAS_GMD_ID(i915), 438 &ver, &rel, &step); 439 memcpy(DISPLAY_RUNTIME_INFO(i915), 440 &DISPLAY_INFO(i915)->__runtime_defaults, 441 sizeof(*DISPLAY_RUNTIME_INFO(i915))); 442 443 if (HAS_GMD_ID(i915)) { 444 DISPLAY_RUNTIME_INFO(i915)->ip.ver = ver; 445 DISPLAY_RUNTIME_INFO(i915)->ip.rel = rel; 446 DISPLAY_RUNTIME_INFO(i915)->ip.step = step; 447 } 448 449 runtime->device_id = device_id; 450 } 451 452 void intel_driver_caps_print(const struct intel_driver_caps *caps, 453 struct drm_printer *p) 454 { 455 drm_printf(p, "Has logical contexts? %s\n", 456 str_yes_no(caps->has_logical_contexts)); 457 drm_printf(p, "scheduler: 0x%x\n", caps->scheduler); 458 } 459