1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <drm/drm_print.h> 26 27 #include "display/intel_cdclk.h" 28 #include "intel_device_info.h" 29 #include "i915_drv.h" 30 31 #define PLATFORM_NAME(x) [INTEL_##x] = #x 32 static const char * const platform_names[] = { 33 PLATFORM_NAME(I830), 34 PLATFORM_NAME(I845G), 35 PLATFORM_NAME(I85X), 36 PLATFORM_NAME(I865G), 37 PLATFORM_NAME(I915G), 38 PLATFORM_NAME(I915GM), 39 PLATFORM_NAME(I945G), 40 PLATFORM_NAME(I945GM), 41 PLATFORM_NAME(G33), 42 PLATFORM_NAME(PINEVIEW), 43 PLATFORM_NAME(I965G), 44 PLATFORM_NAME(I965GM), 45 PLATFORM_NAME(G45), 46 PLATFORM_NAME(GM45), 47 PLATFORM_NAME(IRONLAKE), 48 PLATFORM_NAME(SANDYBRIDGE), 49 PLATFORM_NAME(IVYBRIDGE), 50 PLATFORM_NAME(VALLEYVIEW), 51 PLATFORM_NAME(HASWELL), 52 PLATFORM_NAME(BROADWELL), 53 PLATFORM_NAME(CHERRYVIEW), 54 PLATFORM_NAME(SKYLAKE), 55 PLATFORM_NAME(BROXTON), 56 PLATFORM_NAME(KABYLAKE), 57 PLATFORM_NAME(GEMINILAKE), 58 PLATFORM_NAME(COFFEELAKE), 59 PLATFORM_NAME(CANNONLAKE), 60 PLATFORM_NAME(ICELAKE), 61 PLATFORM_NAME(ELKHARTLAKE), 62 PLATFORM_NAME(TIGERLAKE), 63 }; 64 #undef PLATFORM_NAME 65 66 const char *intel_platform_name(enum intel_platform platform) 67 { 68 BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS); 69 70 if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) || 71 platform_names[platform] == NULL)) 72 return "<unknown>"; 73 74 return platform_names[platform]; 75 } 76 77 static const char *iommu_name(void) 78 { 79 const char *msg = "n/a"; 80 81 #ifdef CONFIG_INTEL_IOMMU 82 msg = enableddisabled(intel_iommu_gfx_mapped); 83 #endif 84 85 return msg; 86 } 87 88 void intel_device_info_print_static(const struct intel_device_info *info, 89 struct drm_printer *p) 90 { 91 drm_printf(p, "engines: %x\n", info->engine_mask); 92 drm_printf(p, "gen: %d\n", info->gen); 93 drm_printf(p, "gt: %d\n", info->gt); 94 drm_printf(p, "iommu: %s\n", iommu_name()); 95 drm_printf(p, "memory-regions: %x\n", info->memory_regions); 96 drm_printf(p, "page-sizes: %x\n", info->page_sizes); 97 drm_printf(p, "platform: %s\n", intel_platform_name(info->platform)); 98 drm_printf(p, "ppgtt-size: %d\n", info->ppgtt_size); 99 drm_printf(p, "ppgtt-type: %d\n", info->ppgtt_type); 100 101 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name)); 102 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); 103 #undef PRINT_FLAG 104 105 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->display.name)); 106 DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG); 107 #undef PRINT_FLAG 108 } 109 110 static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p) 111 { 112 int s; 113 114 drm_printf(p, "slice total: %u, mask=%04x\n", 115 hweight8(sseu->slice_mask), sseu->slice_mask); 116 drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu)); 117 for (s = 0; s < sseu->max_slices; s++) { 118 drm_printf(p, "slice%d: %u subslices, mask=%08x\n", 119 s, intel_sseu_subslices_per_slice(sseu, s), 120 intel_sseu_get_subslices(sseu, s)); 121 } 122 drm_printf(p, "EU total: %u\n", sseu->eu_total); 123 drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice); 124 drm_printf(p, "has slice power gating: %s\n", 125 yesno(sseu->has_slice_pg)); 126 drm_printf(p, "has subslice power gating: %s\n", 127 yesno(sseu->has_subslice_pg)); 128 drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg)); 129 } 130 131 void intel_device_info_print_runtime(const struct intel_runtime_info *info, 132 struct drm_printer *p) 133 { 134 sseu_dump(&info->sseu, p); 135 136 drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq); 137 drm_printf(p, "CS timestamp frequency: %u kHz\n", 138 info->cs_timestamp_frequency_khz); 139 } 140 141 static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice, 142 int subslice) 143 { 144 int slice_stride = sseu->max_subslices * sseu->eu_stride; 145 146 return slice * slice_stride + subslice * sseu->eu_stride; 147 } 148 149 static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice, 150 int subslice) 151 { 152 int i, offset = sseu_eu_idx(sseu, slice, subslice); 153 u16 eu_mask = 0; 154 155 for (i = 0; i < sseu->eu_stride; i++) { 156 eu_mask |= ((u16)sseu->eu_mask[offset + i]) << 157 (i * BITS_PER_BYTE); 158 } 159 160 return eu_mask; 161 } 162 163 static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice, 164 u16 eu_mask) 165 { 166 int i, offset = sseu_eu_idx(sseu, slice, subslice); 167 168 for (i = 0; i < sseu->eu_stride; i++) { 169 sseu->eu_mask[offset + i] = 170 (eu_mask >> (BITS_PER_BYTE * i)) & 0xff; 171 } 172 } 173 174 void intel_device_info_print_topology(const struct sseu_dev_info *sseu, 175 struct drm_printer *p) 176 { 177 int s, ss; 178 179 if (sseu->max_slices == 0) { 180 drm_printf(p, "Unavailable\n"); 181 return; 182 } 183 184 for (s = 0; s < sseu->max_slices; s++) { 185 drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n", 186 s, intel_sseu_subslices_per_slice(sseu, s), 187 intel_sseu_get_subslices(sseu, s)); 188 189 for (ss = 0; ss < sseu->max_subslices; ss++) { 190 u16 enabled_eus = sseu_get_eus(sseu, s, ss); 191 192 drm_printf(p, "\tsubslice%d: %u EUs (0x%hx)\n", 193 ss, hweight16(enabled_eus), enabled_eus); 194 } 195 } 196 } 197 198 static u16 compute_eu_total(const struct sseu_dev_info *sseu) 199 { 200 u16 i, total = 0; 201 202 for (i = 0; i < ARRAY_SIZE(sseu->eu_mask); i++) 203 total += hweight8(sseu->eu_mask[i]); 204 205 return total; 206 } 207 208 static void gen11_compute_sseu_info(struct sseu_dev_info *sseu, 209 u8 s_en, u32 ss_en, u16 eu_en) 210 { 211 int s, ss; 212 213 /* ss_en represents entire subslice mask across all slices */ 214 GEM_BUG_ON(sseu->max_slices * sseu->max_subslices > 215 sizeof(ss_en) * BITS_PER_BYTE); 216 217 for (s = 0; s < sseu->max_slices; s++) { 218 if ((s_en & BIT(s)) == 0) 219 continue; 220 221 sseu->slice_mask |= BIT(s); 222 223 intel_sseu_set_subslices(sseu, s, ss_en); 224 225 for (ss = 0; ss < sseu->max_subslices; ss++) 226 if (intel_sseu_has_subslice(sseu, s, ss)) 227 sseu_set_eus(sseu, s, ss, eu_en); 228 } 229 sseu->eu_per_subslice = hweight16(eu_en); 230 sseu->eu_total = compute_eu_total(sseu); 231 } 232 233 static void gen12_sseu_info_init(struct drm_i915_private *dev_priv) 234 { 235 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; 236 u8 s_en; 237 u32 dss_en; 238 u16 eu_en = 0; 239 u8 eu_en_fuse; 240 int eu; 241 242 /* 243 * Gen12 has Dual-Subslices, which behave similarly to 2 gen11 SS. 244 * Instead of splitting these, provide userspace with an array 245 * of DSS to more closely represent the hardware resource. 246 */ 247 intel_sseu_set_info(sseu, 1, 6, 16); 248 249 s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK; 250 251 dss_en = I915_READ(GEN12_GT_DSS_ENABLE); 252 253 /* one bit per pair of EUs */ 254 eu_en_fuse = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK); 255 for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++) 256 if (eu_en_fuse & BIT(eu)) 257 eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1); 258 259 gen11_compute_sseu_info(sseu, s_en, dss_en, eu_en); 260 261 /* TGL only supports slice-level power gating */ 262 sseu->has_slice_pg = 1; 263 } 264 265 static void gen11_sseu_info_init(struct drm_i915_private *dev_priv) 266 { 267 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; 268 u8 s_en; 269 u32 ss_en; 270 u8 eu_en; 271 272 if (IS_ELKHARTLAKE(dev_priv)) 273 intel_sseu_set_info(sseu, 1, 4, 8); 274 else 275 intel_sseu_set_info(sseu, 1, 8, 8); 276 277 s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK; 278 ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE); 279 eu_en = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK); 280 281 gen11_compute_sseu_info(sseu, s_en, ss_en, eu_en); 282 283 /* ICL has no power gating restrictions. */ 284 sseu->has_slice_pg = 1; 285 sseu->has_subslice_pg = 1; 286 sseu->has_eu_pg = 1; 287 } 288 289 static void gen10_sseu_info_init(struct drm_i915_private *dev_priv) 290 { 291 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; 292 const u32 fuse2 = I915_READ(GEN8_FUSE2); 293 int s, ss; 294 const int eu_mask = 0xff; 295 u32 subslice_mask, eu_en; 296 297 intel_sseu_set_info(sseu, 6, 4, 8); 298 299 sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >> 300 GEN10_F2_S_ENA_SHIFT; 301 302 /* Slice0 */ 303 eu_en = ~I915_READ(GEN8_EU_DISABLE0); 304 for (ss = 0; ss < sseu->max_subslices; ss++) 305 sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask); 306 /* Slice1 */ 307 sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask); 308 eu_en = ~I915_READ(GEN8_EU_DISABLE1); 309 sseu_set_eus(sseu, 1, 1, eu_en & eu_mask); 310 /* Slice2 */ 311 sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask); 312 sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask); 313 /* Slice3 */ 314 sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask); 315 eu_en = ~I915_READ(GEN8_EU_DISABLE2); 316 sseu_set_eus(sseu, 3, 1, eu_en & eu_mask); 317 /* Slice4 */ 318 sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask); 319 sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask); 320 /* Slice5 */ 321 sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask); 322 eu_en = ~I915_READ(GEN10_EU_DISABLE3); 323 sseu_set_eus(sseu, 5, 1, eu_en & eu_mask); 324 325 subslice_mask = (1 << 4) - 1; 326 subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >> 327 GEN10_F2_SS_DIS_SHIFT); 328 329 for (s = 0; s < sseu->max_slices; s++) { 330 u32 subslice_mask_with_eus = subslice_mask; 331 332 for (ss = 0; ss < sseu->max_subslices; ss++) { 333 if (sseu_get_eus(sseu, s, ss) == 0) 334 subslice_mask_with_eus &= ~BIT(ss); 335 } 336 337 /* 338 * Slice0 can have up to 3 subslices, but there are only 2 in 339 * slice1/2. 340 */ 341 intel_sseu_set_subslices(sseu, s, s == 0 ? 342 subslice_mask_with_eus : 343 subslice_mask_with_eus & 0x3); 344 } 345 346 sseu->eu_total = compute_eu_total(sseu); 347 348 /* 349 * CNL is expected to always have a uniform distribution 350 * of EU across subslices with the exception that any one 351 * EU in any one subslice may be fused off for die 352 * recovery. 353 */ 354 sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? 355 DIV_ROUND_UP(sseu->eu_total, 356 intel_sseu_subslice_total(sseu)) : 357 0; 358 359 /* No restrictions on Power Gating */ 360 sseu->has_slice_pg = 1; 361 sseu->has_subslice_pg = 1; 362 sseu->has_eu_pg = 1; 363 } 364 365 static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv) 366 { 367 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; 368 u32 fuse; 369 u8 subslice_mask = 0; 370 371 fuse = I915_READ(CHV_FUSE_GT); 372 373 sseu->slice_mask = BIT(0); 374 intel_sseu_set_info(sseu, 1, 2, 8); 375 376 if (!(fuse & CHV_FGT_DISABLE_SS0)) { 377 u8 disabled_mask = 378 ((fuse & CHV_FGT_EU_DIS_SS0_R0_MASK) >> 379 CHV_FGT_EU_DIS_SS0_R0_SHIFT) | 380 (((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >> 381 CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4); 382 383 subslice_mask |= BIT(0); 384 sseu_set_eus(sseu, 0, 0, ~disabled_mask); 385 } 386 387 if (!(fuse & CHV_FGT_DISABLE_SS1)) { 388 u8 disabled_mask = 389 ((fuse & CHV_FGT_EU_DIS_SS1_R0_MASK) >> 390 CHV_FGT_EU_DIS_SS1_R0_SHIFT) | 391 (((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >> 392 CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4); 393 394 subslice_mask |= BIT(1); 395 sseu_set_eus(sseu, 0, 1, ~disabled_mask); 396 } 397 398 intel_sseu_set_subslices(sseu, 0, subslice_mask); 399 400 sseu->eu_total = compute_eu_total(sseu); 401 402 /* 403 * CHV expected to always have a uniform distribution of EU 404 * across subslices. 405 */ 406 sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? 407 sseu->eu_total / 408 intel_sseu_subslice_total(sseu) : 409 0; 410 /* 411 * CHV supports subslice power gating on devices with more than 412 * one subslice, and supports EU power gating on devices with 413 * more than one EU pair per subslice. 414 */ 415 sseu->has_slice_pg = 0; 416 sseu->has_subslice_pg = intel_sseu_subslice_total(sseu) > 1; 417 sseu->has_eu_pg = (sseu->eu_per_subslice > 2); 418 } 419 420 static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) 421 { 422 struct intel_device_info *info = mkwrite_device_info(dev_priv); 423 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; 424 int s, ss; 425 u32 fuse2, eu_disable, subslice_mask; 426 const u8 eu_mask = 0xff; 427 428 fuse2 = I915_READ(GEN8_FUSE2); 429 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; 430 431 /* BXT has a single slice and at most 3 subslices. */ 432 intel_sseu_set_info(sseu, IS_GEN9_LP(dev_priv) ? 1 : 3, 433 IS_GEN9_LP(dev_priv) ? 3 : 4, 8); 434 435 /* 436 * The subslice disable field is global, i.e. it applies 437 * to each of the enabled slices. 438 */ 439 subslice_mask = (1 << sseu->max_subslices) - 1; 440 subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >> 441 GEN9_F2_SS_DIS_SHIFT); 442 443 /* 444 * Iterate through enabled slices and subslices to 445 * count the total enabled EU. 446 */ 447 for (s = 0; s < sseu->max_slices; s++) { 448 if (!(sseu->slice_mask & BIT(s))) 449 /* skip disabled slice */ 450 continue; 451 452 intel_sseu_set_subslices(sseu, s, subslice_mask); 453 454 eu_disable = I915_READ(GEN9_EU_DISABLE(s)); 455 for (ss = 0; ss < sseu->max_subslices; ss++) { 456 int eu_per_ss; 457 u8 eu_disabled_mask; 458 459 if (!intel_sseu_has_subslice(sseu, s, ss)) 460 /* skip disabled subslice */ 461 continue; 462 463 eu_disabled_mask = (eu_disable >> (ss * 8)) & eu_mask; 464 465 sseu_set_eus(sseu, s, ss, ~eu_disabled_mask); 466 467 eu_per_ss = sseu->max_eus_per_subslice - 468 hweight8(eu_disabled_mask); 469 470 /* 471 * Record which subslice(s) has(have) 7 EUs. we 472 * can tune the hash used to spread work among 473 * subslices if they are unbalanced. 474 */ 475 if (eu_per_ss == 7) 476 sseu->subslice_7eu[s] |= BIT(ss); 477 } 478 } 479 480 sseu->eu_total = compute_eu_total(sseu); 481 482 /* 483 * SKL is expected to always have a uniform distribution 484 * of EU across subslices with the exception that any one 485 * EU in any one subslice may be fused off for die 486 * recovery. BXT is expected to be perfectly uniform in EU 487 * distribution. 488 */ 489 sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? 490 DIV_ROUND_UP(sseu->eu_total, 491 intel_sseu_subslice_total(sseu)) : 492 0; 493 /* 494 * SKL+ supports slice power gating on devices with more than 495 * one slice, and supports EU power gating on devices with 496 * more than one EU pair per subslice. BXT+ supports subslice 497 * power gating on devices with more than one subslice, and 498 * supports EU power gating on devices with more than one EU 499 * pair per subslice. 500 */ 501 sseu->has_slice_pg = 502 !IS_GEN9_LP(dev_priv) && hweight8(sseu->slice_mask) > 1; 503 sseu->has_subslice_pg = 504 IS_GEN9_LP(dev_priv) && intel_sseu_subslice_total(sseu) > 1; 505 sseu->has_eu_pg = sseu->eu_per_subslice > 2; 506 507 if (IS_GEN9_LP(dev_priv)) { 508 #define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss))) 509 info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3; 510 511 sseu->min_eu_in_pool = 0; 512 if (info->has_pooled_eu) { 513 if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0)) 514 sseu->min_eu_in_pool = 3; 515 else if (IS_SS_DISABLED(1)) 516 sseu->min_eu_in_pool = 6; 517 else 518 sseu->min_eu_in_pool = 9; 519 } 520 #undef IS_SS_DISABLED 521 } 522 } 523 524 static void bdw_sseu_info_init(struct drm_i915_private *dev_priv) 525 { 526 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; 527 int s, ss; 528 u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */ 529 530 fuse2 = I915_READ(GEN8_FUSE2); 531 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; 532 intel_sseu_set_info(sseu, 3, 3, 8); 533 534 /* 535 * The subslice disable field is global, i.e. it applies 536 * to each of the enabled slices. 537 */ 538 subslice_mask = GENMASK(sseu->max_subslices - 1, 0); 539 subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >> 540 GEN8_F2_SS_DIS_SHIFT); 541 542 eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK; 543 eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) | 544 ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) << 545 (32 - GEN8_EU_DIS0_S1_SHIFT)); 546 eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) | 547 ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) << 548 (32 - GEN8_EU_DIS1_S2_SHIFT)); 549 550 /* 551 * Iterate through enabled slices and subslices to 552 * count the total enabled EU. 553 */ 554 for (s = 0; s < sseu->max_slices; s++) { 555 if (!(sseu->slice_mask & BIT(s))) 556 /* skip disabled slice */ 557 continue; 558 559 intel_sseu_set_subslices(sseu, s, subslice_mask); 560 561 for (ss = 0; ss < sseu->max_subslices; ss++) { 562 u8 eu_disabled_mask; 563 u32 n_disabled; 564 565 if (!intel_sseu_has_subslice(sseu, s, ss)) 566 /* skip disabled subslice */ 567 continue; 568 569 eu_disabled_mask = 570 eu_disable[s] >> (ss * sseu->max_eus_per_subslice); 571 572 sseu_set_eus(sseu, s, ss, ~eu_disabled_mask); 573 574 n_disabled = hweight8(eu_disabled_mask); 575 576 /* 577 * Record which subslices have 7 EUs. 578 */ 579 if (sseu->max_eus_per_subslice - n_disabled == 7) 580 sseu->subslice_7eu[s] |= 1 << ss; 581 } 582 } 583 584 sseu->eu_total = compute_eu_total(sseu); 585 586 /* 587 * BDW is expected to always have a uniform distribution of EU across 588 * subslices with the exception that any one EU in any one subslice may 589 * be fused off for die recovery. 590 */ 591 sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? 592 DIV_ROUND_UP(sseu->eu_total, 593 intel_sseu_subslice_total(sseu)) : 594 0; 595 596 /* 597 * BDW supports slice power gating on devices with more than 598 * one slice. 599 */ 600 sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1; 601 sseu->has_subslice_pg = 0; 602 sseu->has_eu_pg = 0; 603 } 604 605 static void hsw_sseu_info_init(struct drm_i915_private *dev_priv) 606 { 607 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; 608 u32 fuse1; 609 u8 subslice_mask = 0; 610 int s, ss; 611 612 /* 613 * There isn't a register to tell us how many slices/subslices. We 614 * work off the PCI-ids here. 615 */ 616 switch (INTEL_INFO(dev_priv)->gt) { 617 default: 618 MISSING_CASE(INTEL_INFO(dev_priv)->gt); 619 /* fall through */ 620 case 1: 621 sseu->slice_mask = BIT(0); 622 subslice_mask = BIT(0); 623 break; 624 case 2: 625 sseu->slice_mask = BIT(0); 626 subslice_mask = BIT(0) | BIT(1); 627 break; 628 case 3: 629 sseu->slice_mask = BIT(0) | BIT(1); 630 subslice_mask = BIT(0) | BIT(1); 631 break; 632 } 633 634 fuse1 = I915_READ(HSW_PAVP_FUSE1); 635 switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) { 636 default: 637 MISSING_CASE((fuse1 & HSW_F1_EU_DIS_MASK) >> 638 HSW_F1_EU_DIS_SHIFT); 639 /* fall through */ 640 case HSW_F1_EU_DIS_10EUS: 641 sseu->eu_per_subslice = 10; 642 break; 643 case HSW_F1_EU_DIS_8EUS: 644 sseu->eu_per_subslice = 8; 645 break; 646 case HSW_F1_EU_DIS_6EUS: 647 sseu->eu_per_subslice = 6; 648 break; 649 } 650 651 intel_sseu_set_info(sseu, hweight8(sseu->slice_mask), 652 hweight8(subslice_mask), 653 sseu->eu_per_subslice); 654 655 for (s = 0; s < sseu->max_slices; s++) { 656 intel_sseu_set_subslices(sseu, s, subslice_mask); 657 658 for (ss = 0; ss < sseu->max_subslices; ss++) { 659 sseu_set_eus(sseu, s, ss, 660 (1UL << sseu->eu_per_subslice) - 1); 661 } 662 } 663 664 sseu->eu_total = compute_eu_total(sseu); 665 666 /* No powergating for you. */ 667 sseu->has_slice_pg = 0; 668 sseu->has_subslice_pg = 0; 669 sseu->has_eu_pg = 0; 670 } 671 672 static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv) 673 { 674 u32 ts_override = I915_READ(GEN9_TIMESTAMP_OVERRIDE); 675 u32 base_freq, frac_freq; 676 677 base_freq = ((ts_override & GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >> 678 GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1; 679 base_freq *= 1000; 680 681 frac_freq = ((ts_override & 682 GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >> 683 GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT); 684 frac_freq = 1000 / (frac_freq + 1); 685 686 return base_freq + frac_freq; 687 } 688 689 static u32 gen10_get_crystal_clock_freq(struct drm_i915_private *dev_priv, 690 u32 rpm_config_reg) 691 { 692 u32 f19_2_mhz = 19200; 693 u32 f24_mhz = 24000; 694 u32 crystal_clock = (rpm_config_reg & 695 GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >> 696 GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT; 697 698 switch (crystal_clock) { 699 case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ: 700 return f19_2_mhz; 701 case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ: 702 return f24_mhz; 703 default: 704 MISSING_CASE(crystal_clock); 705 return 0; 706 } 707 } 708 709 static u32 gen11_get_crystal_clock_freq(struct drm_i915_private *dev_priv, 710 u32 rpm_config_reg) 711 { 712 u32 f19_2_mhz = 19200; 713 u32 f24_mhz = 24000; 714 u32 f25_mhz = 25000; 715 u32 f38_4_mhz = 38400; 716 u32 crystal_clock = (rpm_config_reg & 717 GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >> 718 GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT; 719 720 switch (crystal_clock) { 721 case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ: 722 return f24_mhz; 723 case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ: 724 return f19_2_mhz; 725 case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ: 726 return f38_4_mhz; 727 case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ: 728 return f25_mhz; 729 default: 730 MISSING_CASE(crystal_clock); 731 return 0; 732 } 733 } 734 735 static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv) 736 { 737 u32 f12_5_mhz = 12500; 738 u32 f19_2_mhz = 19200; 739 u32 f24_mhz = 24000; 740 741 if (INTEL_GEN(dev_priv) <= 4) { 742 /* PRMs say: 743 * 744 * "The value in this register increments once every 16 745 * hclks." (through the “Clocking Configuration” 746 * (“CLKCFG”) MCHBAR register) 747 */ 748 return RUNTIME_INFO(dev_priv)->rawclk_freq / 16; 749 } else if (INTEL_GEN(dev_priv) <= 8) { 750 /* PRMs say: 751 * 752 * "The PCU TSC counts 10ns increments; this timestamp 753 * reflects bits 38:3 of the TSC (i.e. 80ns granularity, 754 * rolling over every 1.5 hours). 755 */ 756 return f12_5_mhz; 757 } else if (INTEL_GEN(dev_priv) <= 9) { 758 u32 ctc_reg = I915_READ(CTC_MODE); 759 u32 freq = 0; 760 761 if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) { 762 freq = read_reference_ts_freq(dev_priv); 763 } else { 764 freq = IS_GEN9_LP(dev_priv) ? f19_2_mhz : f24_mhz; 765 766 /* Now figure out how the command stream's timestamp 767 * register increments from this frequency (it might 768 * increment only every few clock cycle). 769 */ 770 freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >> 771 CTC_SHIFT_PARAMETER_SHIFT); 772 } 773 774 return freq; 775 } else if (INTEL_GEN(dev_priv) <= 12) { 776 u32 ctc_reg = I915_READ(CTC_MODE); 777 u32 freq = 0; 778 779 /* First figure out the reference frequency. There are 2 ways 780 * we can compute the frequency, either through the 781 * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE 782 * tells us which one we should use. 783 */ 784 if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) { 785 freq = read_reference_ts_freq(dev_priv); 786 } else { 787 u32 rpm_config_reg = I915_READ(RPM_CONFIG0); 788 789 if (INTEL_GEN(dev_priv) <= 10) 790 freq = gen10_get_crystal_clock_freq(dev_priv, 791 rpm_config_reg); 792 else 793 freq = gen11_get_crystal_clock_freq(dev_priv, 794 rpm_config_reg); 795 796 /* Now figure out how the command stream's timestamp 797 * register increments from this frequency (it might 798 * increment only every few clock cycle). 799 */ 800 freq >>= 3 - ((rpm_config_reg & 801 GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >> 802 GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT); 803 } 804 805 return freq; 806 } 807 808 MISSING_CASE("Unknown gen, unable to read command streamer timestamp frequency\n"); 809 return 0; 810 } 811 812 #undef INTEL_VGA_DEVICE 813 #define INTEL_VGA_DEVICE(id, info) (id) 814 815 static const u16 subplatform_ult_ids[] = { 816 INTEL_HSW_ULT_GT1_IDS(0), 817 INTEL_HSW_ULT_GT2_IDS(0), 818 INTEL_HSW_ULT_GT3_IDS(0), 819 INTEL_BDW_ULT_GT1_IDS(0), 820 INTEL_BDW_ULT_GT2_IDS(0), 821 INTEL_BDW_ULT_GT3_IDS(0), 822 INTEL_BDW_ULT_RSVD_IDS(0), 823 INTEL_SKL_ULT_GT1_IDS(0), 824 INTEL_SKL_ULT_GT2_IDS(0), 825 INTEL_SKL_ULT_GT3_IDS(0), 826 INTEL_KBL_ULT_GT1_IDS(0), 827 INTEL_KBL_ULT_GT2_IDS(0), 828 INTEL_KBL_ULT_GT3_IDS(0), 829 INTEL_CFL_U_GT2_IDS(0), 830 INTEL_CFL_U_GT3_IDS(0), 831 INTEL_WHL_U_GT1_IDS(0), 832 INTEL_WHL_U_GT2_IDS(0), 833 INTEL_WHL_U_GT3_IDS(0), 834 INTEL_CML_U_GT1_IDS(0), 835 INTEL_CML_U_GT2_IDS(0), 836 }; 837 838 static const u16 subplatform_ulx_ids[] = { 839 INTEL_HSW_ULX_GT1_IDS(0), 840 INTEL_HSW_ULX_GT2_IDS(0), 841 INTEL_BDW_ULX_GT1_IDS(0), 842 INTEL_BDW_ULX_GT2_IDS(0), 843 INTEL_BDW_ULX_GT3_IDS(0), 844 INTEL_BDW_ULX_RSVD_IDS(0), 845 INTEL_SKL_ULX_GT1_IDS(0), 846 INTEL_SKL_ULX_GT2_IDS(0), 847 INTEL_KBL_ULX_GT1_IDS(0), 848 INTEL_KBL_ULX_GT2_IDS(0), 849 INTEL_AML_KBL_GT2_IDS(0), 850 INTEL_AML_CFL_GT2_IDS(0), 851 }; 852 853 static const u16 subplatform_portf_ids[] = { 854 INTEL_CNL_PORT_F_IDS(0), 855 INTEL_ICL_PORT_F_IDS(0), 856 }; 857 858 static bool find_devid(u16 id, const u16 *p, unsigned int num) 859 { 860 for (; num; num--, p++) { 861 if (*p == id) 862 return true; 863 } 864 865 return false; 866 } 867 868 void intel_device_info_subplatform_init(struct drm_i915_private *i915) 869 { 870 const struct intel_device_info *info = INTEL_INFO(i915); 871 const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915); 872 const unsigned int pi = __platform_mask_index(rinfo, info->platform); 873 const unsigned int pb = __platform_mask_bit(rinfo, info->platform); 874 u16 devid = INTEL_DEVID(i915); 875 u32 mask = 0; 876 877 /* Make sure IS_<platform> checks are working. */ 878 RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb); 879 880 /* Find and mark subplatform bits based on the PCI device id. */ 881 if (find_devid(devid, subplatform_ult_ids, 882 ARRAY_SIZE(subplatform_ult_ids))) { 883 mask = BIT(INTEL_SUBPLATFORM_ULT); 884 } else if (find_devid(devid, subplatform_ulx_ids, 885 ARRAY_SIZE(subplatform_ulx_ids))) { 886 mask = BIT(INTEL_SUBPLATFORM_ULX); 887 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 888 /* ULX machines are also considered ULT. */ 889 mask |= BIT(INTEL_SUBPLATFORM_ULT); 890 } 891 } else if (find_devid(devid, subplatform_portf_ids, 892 ARRAY_SIZE(subplatform_portf_ids))) { 893 mask = BIT(INTEL_SUBPLATFORM_PORTF); 894 } 895 896 GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_BITS); 897 898 RUNTIME_INFO(i915)->platform_mask[pi] |= mask; 899 } 900 901 /** 902 * intel_device_info_runtime_init - initialize runtime info 903 * @dev_priv: the i915 device 904 * 905 * Determine various intel_device_info fields at runtime. 906 * 907 * Use it when either: 908 * - it's judged too laborious to fill n static structures with the limit 909 * when a simple if statement does the job, 910 * - run-time checks (eg read fuse/strap registers) are needed. 911 * 912 * This function needs to be called: 913 * - after the MMIO has been setup as we are reading registers, 914 * - after the PCH has been detected, 915 * - before the first usage of the fields it can tweak. 916 */ 917 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) 918 { 919 struct intel_device_info *info = mkwrite_device_info(dev_priv); 920 struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv); 921 enum pipe pipe; 922 923 if (INTEL_GEN(dev_priv) >= 10) { 924 for_each_pipe(dev_priv, pipe) 925 runtime->num_scalers[pipe] = 2; 926 } else if (IS_GEN(dev_priv, 9)) { 927 runtime->num_scalers[PIPE_A] = 2; 928 runtime->num_scalers[PIPE_B] = 2; 929 runtime->num_scalers[PIPE_C] = 1; 930 } 931 932 BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES); 933 934 if (INTEL_GEN(dev_priv) >= 11) 935 for_each_pipe(dev_priv, pipe) 936 runtime->num_sprites[pipe] = 6; 937 else if (IS_GEN(dev_priv, 10) || IS_GEMINILAKE(dev_priv)) 938 for_each_pipe(dev_priv, pipe) 939 runtime->num_sprites[pipe] = 3; 940 else if (IS_BROXTON(dev_priv)) { 941 /* 942 * Skylake and Broxton currently don't expose the topmost plane as its 943 * use is exclusive with the legacy cursor and we only want to expose 944 * one of those, not both. Until we can safely expose the topmost plane 945 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported, 946 * we don't expose the topmost plane at all to prevent ABI breakage 947 * down the line. 948 */ 949 950 runtime->num_sprites[PIPE_A] = 2; 951 runtime->num_sprites[PIPE_B] = 2; 952 runtime->num_sprites[PIPE_C] = 1; 953 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 954 for_each_pipe(dev_priv, pipe) 955 runtime->num_sprites[pipe] = 2; 956 } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) { 957 for_each_pipe(dev_priv, pipe) 958 runtime->num_sprites[pipe] = 1; 959 } 960 961 if (HAS_DISPLAY(dev_priv) && IS_GEN_RANGE(dev_priv, 7, 8) && 962 HAS_PCH_SPLIT(dev_priv)) { 963 u32 fuse_strap = I915_READ(FUSE_STRAP); 964 u32 sfuse_strap = I915_READ(SFUSE_STRAP); 965 966 /* 967 * SFUSE_STRAP is supposed to have a bit signalling the display 968 * is fused off. Unfortunately it seems that, at least in 969 * certain cases, fused off display means that PCH display 970 * reads don't land anywhere. In that case, we read 0s. 971 * 972 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK 973 * should be set when taking over after the firmware. 974 */ 975 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || 976 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || 977 (HAS_PCH_CPT(dev_priv) && 978 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { 979 drm_info(&dev_priv->drm, 980 "Display fused off, disabling\n"); 981 info->pipe_mask = 0; 982 } else if (fuse_strap & IVB_PIPE_C_DISABLE) { 983 drm_info(&dev_priv->drm, "PipeC fused off\n"); 984 info->pipe_mask &= ~BIT(PIPE_C); 985 } 986 } else if (HAS_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 9) { 987 u32 dfsm = I915_READ(SKL_DFSM); 988 u8 enabled_mask = info->pipe_mask; 989 990 if (dfsm & SKL_DFSM_PIPE_A_DISABLE) 991 enabled_mask &= ~BIT(PIPE_A); 992 if (dfsm & SKL_DFSM_PIPE_B_DISABLE) 993 enabled_mask &= ~BIT(PIPE_B); 994 if (dfsm & SKL_DFSM_PIPE_C_DISABLE) 995 enabled_mask &= ~BIT(PIPE_C); 996 if (INTEL_GEN(dev_priv) >= 12 && 997 (dfsm & TGL_DFSM_PIPE_D_DISABLE)) 998 enabled_mask &= ~BIT(PIPE_D); 999 1000 /* 1001 * At least one pipe should be enabled and if there are 1002 * disabled pipes, they should be the last ones, with no holes 1003 * in the mask. 1004 */ 1005 if (enabled_mask == 0 || !is_power_of_2(enabled_mask + 1)) 1006 drm_err(&dev_priv->drm, 1007 "invalid pipe fuse configuration: enabled_mask=0x%x\n", 1008 enabled_mask); 1009 else 1010 info->pipe_mask = enabled_mask; 1011 1012 if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE) 1013 info->display.has_hdcp = 0; 1014 1015 if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE) 1016 info->display.has_fbc = 0; 1017 1018 if (INTEL_GEN(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) 1019 info->display.has_csr = 0; 1020 1021 if (INTEL_GEN(dev_priv) >= 10 && 1022 (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE)) 1023 info->display.has_dsc = 0; 1024 } 1025 1026 /* Initialize slice/subslice/EU info */ 1027 if (IS_HASWELL(dev_priv)) 1028 hsw_sseu_info_init(dev_priv); 1029 else if (IS_CHERRYVIEW(dev_priv)) 1030 cherryview_sseu_info_init(dev_priv); 1031 else if (IS_BROADWELL(dev_priv)) 1032 bdw_sseu_info_init(dev_priv); 1033 else if (IS_GEN(dev_priv, 9)) 1034 gen9_sseu_info_init(dev_priv); 1035 else if (IS_GEN(dev_priv, 10)) 1036 gen10_sseu_info_init(dev_priv); 1037 else if (IS_GEN(dev_priv, 11)) 1038 gen11_sseu_info_init(dev_priv); 1039 else if (INTEL_GEN(dev_priv) >= 12) 1040 gen12_sseu_info_init(dev_priv); 1041 1042 if (IS_GEN(dev_priv, 6) && intel_vtd_active()) { 1043 drm_info(&dev_priv->drm, 1044 "Disabling ppGTT for VT-d support\n"); 1045 info->ppgtt_type = INTEL_PPGTT_NONE; 1046 } 1047 1048 runtime->rawclk_freq = intel_read_rawclk(dev_priv); 1049 drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq); 1050 1051 /* Initialize command stream timestamp frequency */ 1052 runtime->cs_timestamp_frequency_khz = 1053 read_timestamp_frequency(dev_priv); 1054 if (runtime->cs_timestamp_frequency_khz) { 1055 runtime->cs_timestamp_period_ns = 1056 div_u64(1e6, runtime->cs_timestamp_frequency_khz); 1057 drm_dbg(&dev_priv->drm, 1058 "CS timestamp wraparound in %lldms\n", 1059 div_u64(mul_u32_u32(runtime->cs_timestamp_period_ns, 1060 S32_MAX), 1061 USEC_PER_SEC)); 1062 } 1063 } 1064 1065 void intel_driver_caps_print(const struct intel_driver_caps *caps, 1066 struct drm_printer *p) 1067 { 1068 drm_printf(p, "Has logical contexts? %s\n", 1069 yesno(caps->has_logical_contexts)); 1070 drm_printf(p, "scheduler: %x\n", caps->scheduler); 1071 } 1072 1073 /* 1074 * Determine which engines are fused off in our particular hardware. Since the 1075 * fuse register is in the blitter powerwell, we need forcewake to be ready at 1076 * this point (but later we need to prune the forcewake domains for engines that 1077 * are indeed fused off). 1078 */ 1079 void intel_device_info_init_mmio(struct drm_i915_private *dev_priv) 1080 { 1081 struct intel_device_info *info = mkwrite_device_info(dev_priv); 1082 unsigned int logical_vdbox = 0; 1083 unsigned int i; 1084 u32 media_fuse; 1085 u16 vdbox_mask; 1086 u16 vebox_mask; 1087 1088 if (INTEL_GEN(dev_priv) < 11) 1089 return; 1090 1091 media_fuse = ~I915_READ(GEN11_GT_VEBOX_VDBOX_DISABLE); 1092 1093 vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK; 1094 vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >> 1095 GEN11_GT_VEBOX_DISABLE_SHIFT; 1096 1097 for (i = 0; i < I915_MAX_VCS; i++) { 1098 if (!HAS_ENGINE(dev_priv, _VCS(i))) { 1099 vdbox_mask &= ~BIT(i); 1100 continue; 1101 } 1102 1103 if (!(BIT(i) & vdbox_mask)) { 1104 info->engine_mask &= ~BIT(_VCS(i)); 1105 drm_dbg(&dev_priv->drm, "vcs%u fused off\n", i); 1106 continue; 1107 } 1108 1109 /* 1110 * In Gen11, only even numbered logical VDBOXes are 1111 * hooked up to an SFC (Scaler & Format Converter) unit. 1112 * In TGL each VDBOX has access to an SFC. 1113 */ 1114 if (INTEL_GEN(dev_priv) >= 12 || logical_vdbox++ % 2 == 0) 1115 RUNTIME_INFO(dev_priv)->vdbox_sfc_access |= BIT(i); 1116 } 1117 drm_dbg(&dev_priv->drm, "vdbox enable: %04x, instances: %04lx\n", 1118 vdbox_mask, VDBOX_MASK(dev_priv)); 1119 GEM_BUG_ON(vdbox_mask != VDBOX_MASK(dev_priv)); 1120 1121 for (i = 0; i < I915_MAX_VECS; i++) { 1122 if (!HAS_ENGINE(dev_priv, _VECS(i))) { 1123 vebox_mask &= ~BIT(i); 1124 continue; 1125 } 1126 1127 if (!(BIT(i) & vebox_mask)) { 1128 info->engine_mask &= ~BIT(_VECS(i)); 1129 drm_dbg(&dev_priv->drm, "vecs%u fused off\n", i); 1130 } 1131 } 1132 drm_dbg(&dev_priv->drm, "vebox enable: %04x, instances: %04lx\n", 1133 vebox_mask, VEBOX_MASK(dev_priv)); 1134 GEM_BUG_ON(vebox_mask != VEBOX_MASK(dev_priv)); 1135 } 1136