1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <drm/drm_print.h> 29 #include <drm/intel/intel_gmd_misc_regs.h> 30 #include <drm/intel/intel_gmd_interrupt_regs.h> 31 32 #include "display/i9xx_plane_regs.h" 33 #include "display/intel_display.h" 34 #include "display/intel_display_core.h" 35 #include "display/intel_display_regs.h" 36 #include "display/intel_pch.h" 37 #include "gt/intel_engine_regs.h" 38 #include "gt/intel_gt.h" 39 #include "gt/intel_gt_mcr.h" 40 #include "gt/intel_gt_regs.h" 41 42 #include "i915_drv.h" 43 #include "i915_reg.h" 44 #include "intel_clock_gating.h" 45 #include "intel_mchbar_regs.h" 46 #include "vlv_iosf_sb.h" 47 48 struct drm_i915_clock_gating_funcs { 49 void (*init_clock_gating)(struct drm_i915_private *i915); 50 }; 51 52 static void gen9_init_clock_gating(struct drm_i915_private *i915) 53 { 54 if (HAS_LLC(i915)) { 55 /* 56 * WaCompressedResourceDisplayNewHashMode:skl,kbl 57 * Display WA #0390: skl,kbl 58 * 59 * Must match Sampler, Pixel Back End, and Media. See 60 * WaCompressedResourceSamplerPbeMediaNewHashMode. 61 */ 62 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE); 63 } 64 65 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */ 66 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_EDP_PSR_FIX_RDWRAP); 67 68 /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */ 69 intel_uncore_rmw(&i915->uncore, GEN8_CHICKEN_DCPR_1, 0, MASK_WAKEMEM); 70 71 /* 72 * WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl 73 * Display WA #0859: skl,bxt,kbl,glk,cfl 74 */ 75 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_MEMORY_WAKE); 76 } 77 78 static void bxt_init_clock_gating(struct drm_i915_private *i915) 79 { 80 gen9_init_clock_gating(i915); 81 82 /* WaDisableSDEUnitClockGating:bxt */ 83 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 84 85 /* 86 * FIXME: 87 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only. 88 */ 89 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ); 90 91 /* 92 * Wa: Backlight PWM may stop in the asserted state, causing backlight 93 * to stay fully on. 94 */ 95 intel_uncore_write(&i915->uncore, GEN9_CLKGATE_DIS_0, 96 intel_uncore_read(&i915->uncore, GEN9_CLKGATE_DIS_0) | 97 PWM1_GATING_DIS | PWM2_GATING_DIS); 98 99 /* 100 * Lower the display internal timeout. 101 * This is needed to avoid any hard hangs when DSI port PLL 102 * is off and a MMIO access is attempted by any privilege 103 * application, using batch buffers or any other means. 104 */ 105 intel_uncore_write(&i915->uncore, RM_TIMEOUT, MMIO_TIMEOUT_US(950)); 106 107 /* 108 * WaFbcTurnOffFbcWatermark:bxt 109 * Display WA #0562: bxt 110 */ 111 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); 112 } 113 114 static void glk_init_clock_gating(struct drm_i915_private *i915) 115 { 116 gen9_init_clock_gating(i915); 117 118 /* 119 * WaDisablePWMClockGating:glk 120 * Backlight PWM may stop in the asserted state, causing backlight 121 * to stay fully on. 122 */ 123 intel_uncore_write(&i915->uncore, GEN9_CLKGATE_DIS_0, 124 intel_uncore_read(&i915->uncore, GEN9_CLKGATE_DIS_0) | 125 PWM1_GATING_DIS | PWM2_GATING_DIS); 126 } 127 128 static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv) 129 { 130 struct intel_display *display = dev_priv->display; 131 enum pipe pipe; 132 133 for_each_pipe(display, pipe) { 134 intel_uncore_rmw(&dev_priv->uncore, DSPCNTR(display, pipe), 135 0, DISP_TRICKLE_FEED_DISABLE); 136 137 intel_uncore_rmw(&dev_priv->uncore, DSPSURF(display, pipe), 138 0, 0); 139 intel_uncore_posting_read(&dev_priv->uncore, 140 DSPSURF(display, pipe)); 141 } 142 } 143 144 static void ilk_init_clock_gating(struct drm_i915_private *i915) 145 { 146 u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; 147 148 /* 149 * Required for FBC 150 * WaFbcDisableDpfcClockGating:ilk 151 */ 152 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | 153 ILK_DPFCUNIT_CLOCK_GATE_DISABLE | 154 ILK_DPFDUNIT_CLOCK_GATE_ENABLE; 155 156 intel_uncore_write(&i915->uncore, PCH_3DCGDIS0, 157 MARIUNIT_CLOCK_GATE_DISABLE | 158 SVSMUNIT_CLOCK_GATE_DISABLE); 159 intel_uncore_write(&i915->uncore, PCH_3DCGDIS1, 160 VFMUNIT_CLOCK_GATE_DISABLE); 161 162 /* 163 * According to the spec the following bits should be set in 164 * order to enable memory self-refresh 165 * The bit 22/21 of 0x42004 166 * The bit 5 of 0x42020 167 * The bit 15 of 0x45000 168 */ 169 intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN2, 170 (intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) | 171 ILK_DPARB_GATE | ILK_VSDPFD_FULL)); 172 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; 173 intel_uncore_write(&i915->uncore, DISP_ARB_CTL, 174 (intel_uncore_read(&i915->uncore, DISP_ARB_CTL) | 175 DISP_FBC_WM_DIS)); 176 177 /* 178 * Based on the document from hardware guys the following bits 179 * should be set unconditionally in order to enable FBC. 180 * The bit 22 of 0x42000 181 * The bit 22 of 0x42004 182 * The bit 7,8,9 of 0x42020. 183 */ 184 if (IS_IRONLAKE_M(i915)) { 185 /* WaFbcAsynchFlipDisableFbcQueue:ilk */ 186 intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS); 187 intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_DPARB_GATE); 188 } 189 190 intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, dspclk_gate); 191 192 intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT); 193 194 g4x_disable_trickle_feed(i915); 195 196 intel_pch_init_clock_gating(i915->display); 197 } 198 199 static void gen6_check_mch_setup(struct drm_i915_private *i915) 200 { 201 u32 tmp; 202 203 tmp = intel_uncore_read(&i915->uncore, MCH_SSKPD); 204 if (REG_FIELD_GET(SSKPD_WM0_MASK_SNB, tmp) != 12) 205 drm_dbg_kms(&i915->drm, 206 "Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n", 207 tmp); 208 } 209 210 static void gen6_init_clock_gating(struct drm_i915_private *i915) 211 { 212 u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; 213 214 intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, dspclk_gate); 215 216 intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT); 217 218 intel_uncore_write(&i915->uncore, GEN6_UCGCTL1, 219 intel_uncore_read(&i915->uncore, GEN6_UCGCTL1) | 220 GEN6_BLBUNIT_CLOCK_GATE_DISABLE | 221 GEN6_CSUNIT_CLOCK_GATE_DISABLE); 222 223 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock 224 * gating disable must be set. Failure to set it results in 225 * flickering pixels due to Z write ordering failures after 226 * some amount of runtime in the Mesa "fire" demo, and Unigine 227 * Sanctuary and Tropics, and apparently anything else with 228 * alpha test or pixel discard. 229 * 230 * According to the spec, bit 11 (RCCUNIT) must also be set, 231 * but we didn't debug actual testcases to find it out. 232 * 233 * WaDisableRCCUnitClockGating:snb 234 * WaDisableRCPBUnitClockGating:snb 235 */ 236 intel_uncore_write(&i915->uncore, GEN6_UCGCTL2, 237 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | 238 GEN6_RCCUNIT_CLOCK_GATE_DISABLE); 239 240 /* 241 * According to the spec the following bits should be 242 * set in order to enable memory self-refresh and fbc: 243 * The bit21 and bit22 of 0x42000 244 * The bit21 and bit22 of 0x42004 245 * The bit5 and bit7 of 0x42020 246 * The bit14 of 0x70180 247 * The bit14 of 0x71180 248 * 249 * WaFbcAsynchFlipDisableFbcQueue:snb 250 */ 251 intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN1, 252 intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN1) | 253 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); 254 intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN2, 255 intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) | 256 ILK_DPARB_GATE | ILK_VSDPFD_FULL); 257 intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, 258 intel_uncore_read(&i915->uncore, ILK_DSPCLK_GATE_D) | 259 ILK_DPARBUNIT_CLOCK_GATE_ENABLE | 260 ILK_DPFDUNIT_CLOCK_GATE_ENABLE); 261 262 g4x_disable_trickle_feed(i915); 263 264 intel_pch_init_clock_gating(i915->display); 265 266 gen6_check_mch_setup(i915); 267 } 268 269 static void gen8_set_l3sqc_credits(struct drm_i915_private *i915, 270 int general_prio_credits, 271 int high_prio_credits) 272 { 273 u32 misccpctl; 274 u32 val; 275 276 /* WaTempDisableDOPClkGating:bdw */ 277 misccpctl = intel_uncore_rmw(&i915->uncore, GEN7_MISCCPCTL, 278 GEN7_DOP_CLOCK_GATE_ENABLE, 0); 279 280 val = intel_gt_mcr_read_any(to_gt(i915), GEN8_L3SQCREG1); 281 val &= ~L3_PRIO_CREDITS_MASK; 282 val |= L3_GENERAL_PRIO_CREDITS(general_prio_credits); 283 val |= L3_HIGH_PRIO_CREDITS(high_prio_credits); 284 intel_gt_mcr_multicast_write(to_gt(i915), GEN8_L3SQCREG1, val); 285 286 /* 287 * Wait at least 100 clocks before re-enabling clock gating. 288 * See the definition of L3SQCREG1 in BSpec. 289 */ 290 intel_gt_mcr_read_any(to_gt(i915), GEN8_L3SQCREG1); 291 udelay(1); 292 intel_uncore_write(&i915->uncore, GEN7_MISCCPCTL, misccpctl); 293 } 294 295 static void dg2_init_clock_gating(struct drm_i915_private *i915) 296 { 297 /* Wa_22010954014:dg2 */ 298 intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0, 299 SGSI_SIDECLK_DIS); 300 } 301 302 static void cfl_init_clock_gating(struct drm_i915_private *i915) 303 { 304 intel_pch_init_clock_gating(i915->display); 305 gen9_init_clock_gating(i915); 306 307 /* WAC6entrylatency:cfl */ 308 intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN); 309 310 /* 311 * WaFbcTurnOffFbcWatermark:cfl 312 * Display WA #0562: cfl 313 */ 314 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); 315 } 316 317 static void kbl_init_clock_gating(struct drm_i915_private *i915) 318 { 319 gen9_init_clock_gating(i915); 320 321 /* WAC6entrylatency:kbl */ 322 intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN); 323 324 /* WaDisableSDEUnitClockGating:kbl */ 325 if (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, 0, STEP_C0)) 326 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 327 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 328 329 /* WaDisableGamClockGating:kbl */ 330 if (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, 0, STEP_C0)) 331 intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1, 332 0, GEN6_GAMUNIT_CLOCK_GATE_DISABLE); 333 334 /* 335 * WaFbcTurnOffFbcWatermark:kbl 336 * Display WA #0562: kbl 337 */ 338 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); 339 } 340 341 static void skl_init_clock_gating(struct drm_i915_private *i915) 342 { 343 gen9_init_clock_gating(i915); 344 345 /* WaDisableDopClockGating:skl */ 346 intel_uncore_rmw(&i915->uncore, GEN7_MISCCPCTL, 347 GEN7_DOP_CLOCK_GATE_ENABLE, 0); 348 349 /* WAC6entrylatency:skl */ 350 intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN); 351 352 /* 353 * WaFbcTurnOffFbcWatermark:skl 354 * Display WA #0562: skl 355 */ 356 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); 357 } 358 359 static void bdw_init_clock_gating(struct drm_i915_private *i915) 360 { 361 struct intel_display *display = i915->display; 362 enum pipe pipe; 363 364 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ 365 intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS); 366 367 /* WaSwitchSolVfFArbitrationPriority:bdw */ 368 intel_uncore_rmw(&i915->uncore, GAM_ECOCHK, 0, HSW_ECOCHK_ARB_PRIO_SOL); 369 370 /* WaPsrDPAMaskVBlankInSRD:bdw */ 371 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD); 372 373 for_each_pipe(display, pipe) { 374 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ 375 intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe), 376 0, BDW_UNMASK_VBL_TO_REGS_IN_SRD); 377 } 378 379 /* WaVSRefCountFullforceMissDisable:bdw */ 380 /* WaDSRefCountFullforceMissDisable:bdw */ 381 intel_uncore_rmw(&i915->uncore, GEN7_FF_THREAD_MODE, 382 GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME, 0); 383 384 intel_uncore_write(&i915->uncore, RING_PSMI_CTL(RENDER_RING_BASE), 385 REG_MASKED_FIELD_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); 386 387 /* WaDisableSDEUnitClockGating:bdw */ 388 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 389 390 /* WaProgramL3SqcReg1Default:bdw */ 391 gen8_set_l3sqc_credits(i915, 30, 2); 392 393 /* WaKVMNotificationOnConfigChange:bdw */ 394 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR2_1, 395 0, KVM_CONFIG_CHANGE_NOTIFICATION_SELECT); 396 397 intel_pch_init_clock_gating(i915->display); 398 399 /* WaDisableDopClockGating:bdw 400 * 401 * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP 402 * clock gating. 403 */ 404 intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1, 0, GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE); 405 } 406 407 static void hsw_init_clock_gating(struct drm_i915_private *i915) 408 { 409 struct intel_display *display = i915->display; 410 enum pipe pipe; 411 412 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ 413 intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS); 414 415 /* WaPsrDPAMaskVBlankInSRD:hsw */ 416 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD); 417 418 for_each_pipe(display, pipe) { 419 /* WaPsrDPRSUnmaskVBlankInSRD:hsw */ 420 intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe), 421 0, HSW_UNMASK_VBL_TO_REGS_IN_SRD); 422 } 423 424 /* This is required by WaCatErrorRejectionIssue:hsw */ 425 intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 426 0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 427 428 /* WaSwitchSolVfFArbitrationPriority:hsw */ 429 intel_uncore_rmw(&i915->uncore, GAM_ECOCHK, 0, HSW_ECOCHK_ARB_PRIO_SOL); 430 431 intel_pch_init_clock_gating(i915->display); 432 } 433 434 static void ivb_init_clock_gating(struct drm_i915_private *i915) 435 { 436 struct intel_display *display = i915->display; 437 438 intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); 439 440 /* WaFbcAsynchFlipDisableFbcQueue:ivb */ 441 intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS); 442 443 /* WaDisableBackToBackFlipFix:ivb */ 444 intel_uncore_write(&i915->uncore, IVB_CHICKEN3, 445 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | 446 CHICKEN3_DGMG_DONE_FIX_DISABLE); 447 448 if (INTEL_INFO(i915)->gt == 1) 449 intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2, 450 REG_MASKED_FIELD_ENABLE(DOP_CLOCK_GATING_DISABLE)); 451 else { 452 /* must write both registers */ 453 intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2, 454 REG_MASKED_FIELD_ENABLE(DOP_CLOCK_GATING_DISABLE)); 455 intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2_GT2, 456 REG_MASKED_FIELD_ENABLE(DOP_CLOCK_GATING_DISABLE)); 457 } 458 459 /* 460 * According to the spec, bit 13 (RCZUNIT) must be set on IVB. 461 * This implements the WaDisableRCZUnitClockGating:ivb workaround. 462 */ 463 intel_uncore_write(&i915->uncore, GEN6_UCGCTL2, 464 GEN6_RCZUNIT_CLOCK_GATE_DISABLE); 465 466 /* This is required by WaCatErrorRejectionIssue:ivb */ 467 intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 468 0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 469 470 g4x_disable_trickle_feed(i915); 471 472 intel_uncore_rmw(&i915->uncore, GEN6_MBCUNIT_SNPCR, GEN6_MBC_SNPCR_MASK, 473 GEN6_MBC_SNPCR_MED); 474 475 if (!HAS_PCH_NOP(display)) 476 intel_pch_init_clock_gating(display); 477 478 gen6_check_mch_setup(i915); 479 } 480 481 static void vlv_init_clock_gating(struct drm_i915_private *i915) 482 { 483 /* WaDisableBackToBackFlipFix:vlv */ 484 intel_uncore_write(&i915->uncore, IVB_CHICKEN3, 485 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | 486 CHICKEN3_DGMG_DONE_FIX_DISABLE); 487 488 /* WaDisableDopClockGating:vlv */ 489 intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2, 490 REG_MASKED_FIELD_ENABLE(DOP_CLOCK_GATING_DISABLE)); 491 492 /* This is required by WaCatErrorRejectionIssue:vlv */ 493 intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 494 0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 495 496 /* 497 * According to the spec, bit 13 (RCZUNIT) must be set on IVB. 498 * This implements the WaDisableRCZUnitClockGating:vlv workaround. 499 */ 500 intel_uncore_write(&i915->uncore, GEN6_UCGCTL2, 501 GEN6_RCZUNIT_CLOCK_GATE_DISABLE); 502 503 /* WaDisableL3Bank2xClockGate:vlv 504 * Disabling L3 clock gating- MMIO 940c[25] = 1 505 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */ 506 intel_uncore_rmw(&i915->uncore, GEN7_UCGCTL4, 0, GEN7_L3BANK2X_CLOCK_GATE_DISABLE); 507 508 /* 509 * WaDisableVLVClockGating_VBIIssue:vlv 510 * Disable clock gating on th GCFG unit to prevent a delay 511 * in the reporting of vblank events. 512 */ 513 intel_uncore_write(&i915->uncore, VLV_GUNIT_CLOCK_GATE, GCFG_DIS); 514 } 515 516 static void chv_init_clock_gating(struct drm_i915_private *i915) 517 { 518 /* WaVSRefCountFullforceMissDisable:chv */ 519 /* WaDSRefCountFullforceMissDisable:chv */ 520 intel_uncore_rmw(&i915->uncore, GEN7_FF_THREAD_MODE, 521 GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME, 0); 522 523 /* WaDisableSemaphoreAndSyncFlipWait:chv */ 524 intel_uncore_write(&i915->uncore, RING_PSMI_CTL(RENDER_RING_BASE), 525 REG_MASKED_FIELD_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); 526 527 /* WaDisableCSUnitClockGating:chv */ 528 intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1, 0, GEN6_CSUNIT_CLOCK_GATE_DISABLE); 529 530 /* WaDisableSDEUnitClockGating:chv */ 531 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 532 533 /* 534 * WaProgramL3SqcReg1Default:chv 535 * See gfxspecs/Related Documents/Performance Guide/ 536 * LSQC Setting Recommendations. 537 */ 538 gen8_set_l3sqc_credits(i915, 38, 2); 539 } 540 541 static void g4x_init_clock_gating(struct drm_i915_private *i915) 542 { 543 u32 dspclk_gate; 544 545 intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, 0); 546 intel_uncore_write(&i915->uncore, RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | 547 GS_UNIT_CLOCK_GATE_DISABLE | 548 CL_UNIT_CLOCK_GATE_DISABLE); 549 intel_uncore_write(&i915->uncore, RAMCLK_GATE_D, 0); 550 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | 551 OVRUNIT_CLOCK_GATE_DISABLE | 552 OVCUNIT_CLOCK_GATE_DISABLE; 553 if (IS_GM45(i915)) 554 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; 555 intel_uncore_write(&i915->uncore, DSPCLK_GATE_D, dspclk_gate); 556 557 g4x_disable_trickle_feed(i915); 558 } 559 560 static void i965gm_init_clock_gating(struct drm_i915_private *i915) 561 { 562 struct intel_uncore *uncore = &i915->uncore; 563 564 intel_uncore_write(uncore, RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); 565 intel_uncore_write(uncore, RENCLK_GATE_D2, 0); 566 intel_uncore_write(uncore, DSPCLK_GATE_D, 0); 567 intel_uncore_write(uncore, RAMCLK_GATE_D, 0); 568 intel_uncore_write16(uncore, DEUC, 0); 569 intel_uncore_write(uncore, 570 MI_ARB_STATE, 571 REG_MASKED_FIELD_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); 572 } 573 574 static void i965g_init_clock_gating(struct drm_i915_private *i915) 575 { 576 intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | 577 I965_RCC_CLOCK_GATE_DISABLE | 578 I965_RCPB_CLOCK_GATE_DISABLE | 579 I965_ISC_CLOCK_GATE_DISABLE | 580 I965_FBC_CLOCK_GATE_DISABLE); 581 intel_uncore_write(&i915->uncore, RENCLK_GATE_D2, 0); 582 intel_uncore_write(&i915->uncore, MI_ARB_STATE, 583 REG_MASKED_FIELD_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); 584 } 585 586 static void gen3_init_clock_gating(struct drm_i915_private *i915) 587 { 588 u32 dstate = intel_uncore_read(&i915->uncore, D_STATE); 589 590 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | 591 DSTATE_DOT_CLOCK_GATING; 592 intel_uncore_write(&i915->uncore, D_STATE, dstate); 593 594 if (IS_PINEVIEW(i915)) 595 intel_uncore_write(&i915->uncore, ECOSKPD(RENDER_RING_BASE), 596 REG_MASKED_FIELD_ENABLE(ECO_GATING_CX_ONLY)); 597 598 /* IIR "flip pending" means done if this bit is set */ 599 intel_uncore_write(&i915->uncore, ECOSKPD(RENDER_RING_BASE), 600 REG_MASKED_FIELD_DISABLE(ECO_FLIP_DONE)); 601 602 /* interrupts should cause a wake up from C3 */ 603 intel_uncore_write(&i915->uncore, INSTPM, REG_MASKED_FIELD_ENABLE(INSTPM_AGPBUSY_INT_EN)); 604 605 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ 606 intel_uncore_write(&i915->uncore, MI_ARB_STATE, 607 REG_MASKED_FIELD_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); 608 609 intel_uncore_write(&i915->uncore, MI_ARB_STATE, 610 REG_MASKED_FIELD_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); 611 } 612 613 static void i85x_init_clock_gating(struct drm_i915_private *i915) 614 { 615 intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); 616 617 /* interrupts should cause a wake up from C3 */ 618 intel_uncore_write(&i915->uncore, MI_STATE, REG_MASKED_FIELD_ENABLE(MI_AGPBUSY_INT_EN) | 619 REG_MASKED_FIELD_DISABLE(MI_AGPBUSY_830_MODE)); 620 621 intel_uncore_write(&i915->uncore, MEM_MODE, 622 REG_MASKED_FIELD_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE)); 623 624 /* 625 * Have FBC ignore 3D activity since we use software 626 * render tracking, and otherwise a pure 3D workload 627 * (even if it just renders a single frame and then does 628 * absolutely nothing) would not allow FBC to recompress 629 * until a 2D blit occurs. 630 */ 631 intel_uncore_write(&i915->uncore, SCPD0, 632 REG_MASKED_FIELD_ENABLE(SCPD_FBC_IGNORE_3D)); 633 } 634 635 static void i830_init_clock_gating(struct drm_i915_private *i915) 636 { 637 intel_uncore_write(&i915->uncore, MEM_MODE, 638 REG_MASKED_FIELD_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) | 639 REG_MASKED_FIELD_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE)); 640 } 641 642 void intel_clock_gating_init(struct drm_device *drm) 643 { 644 struct drm_i915_private *i915 = to_i915(drm); 645 646 i915->clock_gating_funcs->init_clock_gating(i915); 647 } 648 649 static void nop_init_clock_gating(struct drm_i915_private *i915) 650 { 651 drm_dbg_kms(&i915->drm, 652 "No clock gating settings or workarounds applied.\n"); 653 } 654 655 #define CG_FUNCS(platform) \ 656 static const struct drm_i915_clock_gating_funcs platform##_clock_gating_funcs = { \ 657 .init_clock_gating = platform##_init_clock_gating, \ 658 } 659 660 CG_FUNCS(dg2); 661 CG_FUNCS(cfl); 662 CG_FUNCS(skl); 663 CG_FUNCS(kbl); 664 CG_FUNCS(bxt); 665 CG_FUNCS(glk); 666 CG_FUNCS(bdw); 667 CG_FUNCS(chv); 668 CG_FUNCS(hsw); 669 CG_FUNCS(ivb); 670 CG_FUNCS(vlv); 671 CG_FUNCS(gen6); 672 CG_FUNCS(ilk); 673 CG_FUNCS(g4x); 674 CG_FUNCS(i965gm); 675 CG_FUNCS(i965g); 676 CG_FUNCS(gen3); 677 CG_FUNCS(i85x); 678 CG_FUNCS(i830); 679 CG_FUNCS(nop); 680 #undef CG_FUNCS 681 682 /** 683 * intel_clock_gating_hooks_init - setup the clock gating hooks 684 * @drm: drm device 685 * 686 * Setup the hooks that configure which clocks of a given platform can be 687 * gated and also apply various GT and display specific workarounds for these 688 * platforms. Note that some GT specific workarounds are applied separately 689 * when GPU contexts or batchbuffers start their execution. 690 */ 691 void intel_clock_gating_hooks_init(struct drm_device *drm) 692 { 693 struct drm_i915_private *i915 = to_i915(drm); 694 695 if (IS_DG2(i915)) 696 i915->clock_gating_funcs = &dg2_clock_gating_funcs; 697 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 698 i915->clock_gating_funcs = &cfl_clock_gating_funcs; 699 else if (IS_SKYLAKE(i915)) 700 i915->clock_gating_funcs = &skl_clock_gating_funcs; 701 else if (IS_KABYLAKE(i915)) 702 i915->clock_gating_funcs = &kbl_clock_gating_funcs; 703 else if (IS_BROXTON(i915)) 704 i915->clock_gating_funcs = &bxt_clock_gating_funcs; 705 else if (IS_GEMINILAKE(i915)) 706 i915->clock_gating_funcs = &glk_clock_gating_funcs; 707 else if (IS_BROADWELL(i915)) 708 i915->clock_gating_funcs = &bdw_clock_gating_funcs; 709 else if (IS_CHERRYVIEW(i915)) 710 i915->clock_gating_funcs = &chv_clock_gating_funcs; 711 else if (IS_HASWELL(i915)) 712 i915->clock_gating_funcs = &hsw_clock_gating_funcs; 713 else if (IS_IVYBRIDGE(i915)) 714 i915->clock_gating_funcs = &ivb_clock_gating_funcs; 715 else if (IS_VALLEYVIEW(i915)) 716 i915->clock_gating_funcs = &vlv_clock_gating_funcs; 717 else if (GRAPHICS_VER(i915) == 6) 718 i915->clock_gating_funcs = &gen6_clock_gating_funcs; 719 else if (GRAPHICS_VER(i915) == 5) 720 i915->clock_gating_funcs = &ilk_clock_gating_funcs; 721 else if (IS_G4X(i915)) 722 i915->clock_gating_funcs = &g4x_clock_gating_funcs; 723 else if (IS_I965GM(i915)) 724 i915->clock_gating_funcs = &i965gm_clock_gating_funcs; 725 else if (IS_I965G(i915)) 726 i915->clock_gating_funcs = &i965g_clock_gating_funcs; 727 else if (GRAPHICS_VER(i915) == 3) 728 i915->clock_gating_funcs = &gen3_clock_gating_funcs; 729 else if (IS_I85X(i915) || IS_I865G(i915)) 730 i915->clock_gating_funcs = &i85x_clock_gating_funcs; 731 else if (GRAPHICS_VER(i915) == 2) 732 i915->clock_gating_funcs = &i830_clock_gating_funcs; 733 else 734 i915->clock_gating_funcs = &nop_clock_gating_funcs; 735 } 736