1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <drm/drm_print.h> 29 #include <drm/intel/intel_gmd_misc_regs.h> 30 #include <drm/intel/intel_gmd_interrupt_regs.h> 31 32 #include "display/i9xx_plane_regs.h" 33 #include "display/intel_display.h" 34 #include "display/intel_display_core.h" 35 #include "display/intel_display_regs.h" 36 #include "gt/intel_engine_regs.h" 37 #include "gt/intel_gt.h" 38 #include "gt/intel_gt_mcr.h" 39 #include "gt/intel_gt_regs.h" 40 41 #include "i915_drv.h" 42 #include "i915_reg.h" 43 #include "intel_clock_gating.h" 44 #include "intel_mchbar_regs.h" 45 #include "vlv_iosf_sb.h" 46 47 struct drm_i915_clock_gating_funcs { 48 void (*init_clock_gating)(struct drm_i915_private *i915); 49 }; 50 51 static void gen9_init_clock_gating(struct drm_i915_private *i915) 52 { 53 if (HAS_LLC(i915)) { 54 /* 55 * WaCompressedResourceDisplayNewHashMode:skl,kbl 56 * Display WA #0390: skl,kbl 57 * 58 * Must match Sampler, Pixel Back End, and Media. See 59 * WaCompressedResourceSamplerPbeMediaNewHashMode. 60 */ 61 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE); 62 } 63 64 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */ 65 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_EDP_PSR_FIX_RDWRAP); 66 67 /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */ 68 intel_uncore_rmw(&i915->uncore, GEN8_CHICKEN_DCPR_1, 0, MASK_WAKEMEM); 69 70 /* 71 * WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl 72 * Display WA #0859: skl,bxt,kbl,glk,cfl 73 */ 74 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_MEMORY_WAKE); 75 } 76 77 static void bxt_init_clock_gating(struct drm_i915_private *i915) 78 { 79 gen9_init_clock_gating(i915); 80 81 /* WaDisableSDEUnitClockGating:bxt */ 82 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 83 84 /* 85 * FIXME: 86 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only. 87 */ 88 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ); 89 90 /* 91 * Wa: Backlight PWM may stop in the asserted state, causing backlight 92 * to stay fully on. 93 */ 94 intel_uncore_write(&i915->uncore, GEN9_CLKGATE_DIS_0, 95 intel_uncore_read(&i915->uncore, GEN9_CLKGATE_DIS_0) | 96 PWM1_GATING_DIS | PWM2_GATING_DIS); 97 98 /* 99 * Lower the display internal timeout. 100 * This is needed to avoid any hard hangs when DSI port PLL 101 * is off and a MMIO access is attempted by any privilege 102 * application, using batch buffers or any other means. 103 */ 104 intel_uncore_write(&i915->uncore, RM_TIMEOUT, MMIO_TIMEOUT_US(950)); 105 106 /* 107 * WaFbcTurnOffFbcWatermark:bxt 108 * Display WA #0562: bxt 109 */ 110 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); 111 } 112 113 static void glk_init_clock_gating(struct drm_i915_private *i915) 114 { 115 gen9_init_clock_gating(i915); 116 117 /* 118 * WaDisablePWMClockGating:glk 119 * Backlight PWM may stop in the asserted state, causing backlight 120 * to stay fully on. 121 */ 122 intel_uncore_write(&i915->uncore, GEN9_CLKGATE_DIS_0, 123 intel_uncore_read(&i915->uncore, GEN9_CLKGATE_DIS_0) | 124 PWM1_GATING_DIS | PWM2_GATING_DIS); 125 } 126 127 static void ibx_init_clock_gating(struct drm_i915_private *i915) 128 { 129 /* 130 * On Ibex Peak and Cougar Point, we need to disable clock 131 * gating for the panel power sequencer or it will fail to 132 * start up when no ports are active. 133 */ 134 intel_uncore_write(&i915->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); 135 } 136 137 static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv) 138 { 139 struct intel_display *display = dev_priv->display; 140 enum pipe pipe; 141 142 for_each_pipe(display, pipe) { 143 intel_uncore_rmw(&dev_priv->uncore, DSPCNTR(display, pipe), 144 0, DISP_TRICKLE_FEED_DISABLE); 145 146 intel_uncore_rmw(&dev_priv->uncore, DSPSURF(display, pipe), 147 0, 0); 148 intel_uncore_posting_read(&dev_priv->uncore, 149 DSPSURF(display, pipe)); 150 } 151 } 152 153 static void ilk_init_clock_gating(struct drm_i915_private *i915) 154 { 155 u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; 156 157 /* 158 * Required for FBC 159 * WaFbcDisableDpfcClockGating:ilk 160 */ 161 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | 162 ILK_DPFCUNIT_CLOCK_GATE_DISABLE | 163 ILK_DPFDUNIT_CLOCK_GATE_ENABLE; 164 165 intel_uncore_write(&i915->uncore, PCH_3DCGDIS0, 166 MARIUNIT_CLOCK_GATE_DISABLE | 167 SVSMUNIT_CLOCK_GATE_DISABLE); 168 intel_uncore_write(&i915->uncore, PCH_3DCGDIS1, 169 VFMUNIT_CLOCK_GATE_DISABLE); 170 171 /* 172 * According to the spec the following bits should be set in 173 * order to enable memory self-refresh 174 * The bit 22/21 of 0x42004 175 * The bit 5 of 0x42020 176 * The bit 15 of 0x45000 177 */ 178 intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN2, 179 (intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) | 180 ILK_DPARB_GATE | ILK_VSDPFD_FULL)); 181 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; 182 intel_uncore_write(&i915->uncore, DISP_ARB_CTL, 183 (intel_uncore_read(&i915->uncore, DISP_ARB_CTL) | 184 DISP_FBC_WM_DIS)); 185 186 /* 187 * Based on the document from hardware guys the following bits 188 * should be set unconditionally in order to enable FBC. 189 * The bit 22 of 0x42000 190 * The bit 22 of 0x42004 191 * The bit 7,8,9 of 0x42020. 192 */ 193 if (IS_IRONLAKE_M(i915)) { 194 /* WaFbcAsynchFlipDisableFbcQueue:ilk */ 195 intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS); 196 intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_DPARB_GATE); 197 } 198 199 intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, dspclk_gate); 200 201 intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT); 202 203 g4x_disable_trickle_feed(i915); 204 205 ibx_init_clock_gating(i915); 206 } 207 208 static void cpt_init_clock_gating(struct drm_i915_private *i915) 209 { 210 struct intel_display *display = i915->display; 211 enum pipe pipe; 212 u32 val; 213 214 /* 215 * On Ibex Peak and Cougar Point, we need to disable clock 216 * gating for the panel power sequencer or it will fail to 217 * start up when no ports are active. 218 */ 219 intel_uncore_write(&i915->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | 220 PCH_DPLUNIT_CLOCK_GATE_DISABLE | 221 PCH_CPUNIT_CLOCK_GATE_DISABLE); 222 intel_uncore_rmw(&i915->uncore, SOUTH_CHICKEN2, 0, DPLS_EDP_PPS_FIX_DIS); 223 /* The below fixes the weird display corruption, a few pixels shifted 224 * downward, on (only) LVDS of some HP laptops with IVY. 225 */ 226 for_each_pipe(display, pipe) { 227 val = intel_uncore_read(&i915->uncore, TRANS_CHICKEN2(pipe)); 228 val |= TRANS_CHICKEN2_TIMING_OVERRIDE; 229 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED; 230 if (display->vbt.fdi_rx_polarity_inverted) 231 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; 232 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER; 233 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH; 234 intel_uncore_write(&i915->uncore, TRANS_CHICKEN2(pipe), val); 235 } 236 /* WADP0ClockGatingDisable */ 237 for_each_pipe(display, pipe) { 238 intel_uncore_write(&i915->uncore, TRANS_CHICKEN1(pipe), 239 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); 240 } 241 } 242 243 static void gen6_check_mch_setup(struct drm_i915_private *i915) 244 { 245 u32 tmp; 246 247 tmp = intel_uncore_read(&i915->uncore, MCH_SSKPD); 248 if (REG_FIELD_GET(SSKPD_WM0_MASK_SNB, tmp) != 12) 249 drm_dbg_kms(&i915->drm, 250 "Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n", 251 tmp); 252 } 253 254 static void gen6_init_clock_gating(struct drm_i915_private *i915) 255 { 256 u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; 257 258 intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, dspclk_gate); 259 260 intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT); 261 262 intel_uncore_write(&i915->uncore, GEN6_UCGCTL1, 263 intel_uncore_read(&i915->uncore, GEN6_UCGCTL1) | 264 GEN6_BLBUNIT_CLOCK_GATE_DISABLE | 265 GEN6_CSUNIT_CLOCK_GATE_DISABLE); 266 267 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock 268 * gating disable must be set. Failure to set it results in 269 * flickering pixels due to Z write ordering failures after 270 * some amount of runtime in the Mesa "fire" demo, and Unigine 271 * Sanctuary and Tropics, and apparently anything else with 272 * alpha test or pixel discard. 273 * 274 * According to the spec, bit 11 (RCCUNIT) must also be set, 275 * but we didn't debug actual testcases to find it out. 276 * 277 * WaDisableRCCUnitClockGating:snb 278 * WaDisableRCPBUnitClockGating:snb 279 */ 280 intel_uncore_write(&i915->uncore, GEN6_UCGCTL2, 281 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | 282 GEN6_RCCUNIT_CLOCK_GATE_DISABLE); 283 284 /* 285 * According to the spec the following bits should be 286 * set in order to enable memory self-refresh and fbc: 287 * The bit21 and bit22 of 0x42000 288 * The bit21 and bit22 of 0x42004 289 * The bit5 and bit7 of 0x42020 290 * The bit14 of 0x70180 291 * The bit14 of 0x71180 292 * 293 * WaFbcAsynchFlipDisableFbcQueue:snb 294 */ 295 intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN1, 296 intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN1) | 297 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); 298 intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN2, 299 intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) | 300 ILK_DPARB_GATE | ILK_VSDPFD_FULL); 301 intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, 302 intel_uncore_read(&i915->uncore, ILK_DSPCLK_GATE_D) | 303 ILK_DPARBUNIT_CLOCK_GATE_ENABLE | 304 ILK_DPFDUNIT_CLOCK_GATE_ENABLE); 305 306 g4x_disable_trickle_feed(i915); 307 308 cpt_init_clock_gating(i915); 309 310 gen6_check_mch_setup(i915); 311 } 312 313 static void lpt_init_clock_gating(struct drm_i915_private *i915) 314 { 315 struct intel_display *display = i915->display; 316 317 /* 318 * TODO: this bit should only be enabled when really needed, then 319 * disabled when not needed anymore in order to save power. 320 */ 321 if (HAS_PCH_LPT_LP(display)) 322 intel_uncore_rmw(&i915->uncore, SOUTH_DSPCLK_GATE_D, 323 0, PCH_LP_PARTITION_LEVEL_DISABLE); 324 325 /* WADPOClockGatingDisable:hsw */ 326 intel_uncore_rmw(&i915->uncore, TRANS_CHICKEN1(PIPE_A), 327 0, TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); 328 } 329 330 static void gen8_set_l3sqc_credits(struct drm_i915_private *i915, 331 int general_prio_credits, 332 int high_prio_credits) 333 { 334 u32 misccpctl; 335 u32 val; 336 337 /* WaTempDisableDOPClkGating:bdw */ 338 misccpctl = intel_uncore_rmw(&i915->uncore, GEN7_MISCCPCTL, 339 GEN7_DOP_CLOCK_GATE_ENABLE, 0); 340 341 val = intel_gt_mcr_read_any(to_gt(i915), GEN8_L3SQCREG1); 342 val &= ~L3_PRIO_CREDITS_MASK; 343 val |= L3_GENERAL_PRIO_CREDITS(general_prio_credits); 344 val |= L3_HIGH_PRIO_CREDITS(high_prio_credits); 345 intel_gt_mcr_multicast_write(to_gt(i915), GEN8_L3SQCREG1, val); 346 347 /* 348 * Wait at least 100 clocks before re-enabling clock gating. 349 * See the definition of L3SQCREG1 in BSpec. 350 */ 351 intel_gt_mcr_read_any(to_gt(i915), GEN8_L3SQCREG1); 352 udelay(1); 353 intel_uncore_write(&i915->uncore, GEN7_MISCCPCTL, misccpctl); 354 } 355 356 static void dg2_init_clock_gating(struct drm_i915_private *i915) 357 { 358 /* Wa_22010954014:dg2 */ 359 intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0, 360 SGSI_SIDECLK_DIS); 361 } 362 363 static void cnp_init_clock_gating(struct drm_i915_private *i915) 364 { 365 struct intel_display *display = i915->display; 366 367 if (!HAS_PCH_CNP(display)) 368 return; 369 370 /* Display WA #1181 WaSouthDisplayDisablePWMCGEGating: cnp */ 371 intel_uncore_rmw(&i915->uncore, SOUTH_DSPCLK_GATE_D, 0, CNP_PWM_CGE_GATING_DISABLE); 372 } 373 374 static void cfl_init_clock_gating(struct drm_i915_private *i915) 375 { 376 cnp_init_clock_gating(i915); 377 gen9_init_clock_gating(i915); 378 379 /* WAC6entrylatency:cfl */ 380 intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN); 381 382 /* 383 * WaFbcTurnOffFbcWatermark:cfl 384 * Display WA #0562: cfl 385 */ 386 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); 387 } 388 389 static void kbl_init_clock_gating(struct drm_i915_private *i915) 390 { 391 gen9_init_clock_gating(i915); 392 393 /* WAC6entrylatency:kbl */ 394 intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN); 395 396 /* WaDisableSDEUnitClockGating:kbl */ 397 if (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, 0, STEP_C0)) 398 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 399 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 400 401 /* WaDisableGamClockGating:kbl */ 402 if (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, 0, STEP_C0)) 403 intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1, 404 0, GEN6_GAMUNIT_CLOCK_GATE_DISABLE); 405 406 /* 407 * WaFbcTurnOffFbcWatermark:kbl 408 * Display WA #0562: kbl 409 */ 410 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); 411 } 412 413 static void skl_init_clock_gating(struct drm_i915_private *i915) 414 { 415 gen9_init_clock_gating(i915); 416 417 /* WaDisableDopClockGating:skl */ 418 intel_uncore_rmw(&i915->uncore, GEN7_MISCCPCTL, 419 GEN7_DOP_CLOCK_GATE_ENABLE, 0); 420 421 /* WAC6entrylatency:skl */ 422 intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN); 423 424 /* 425 * WaFbcTurnOffFbcWatermark:skl 426 * Display WA #0562: skl 427 */ 428 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); 429 } 430 431 static void bdw_init_clock_gating(struct drm_i915_private *i915) 432 { 433 struct intel_display *display = i915->display; 434 enum pipe pipe; 435 436 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ 437 intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS); 438 439 /* WaSwitchSolVfFArbitrationPriority:bdw */ 440 intel_uncore_rmw(&i915->uncore, GAM_ECOCHK, 0, HSW_ECOCHK_ARB_PRIO_SOL); 441 442 /* WaPsrDPAMaskVBlankInSRD:bdw */ 443 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD); 444 445 for_each_pipe(display, pipe) { 446 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ 447 intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe), 448 0, BDW_UNMASK_VBL_TO_REGS_IN_SRD); 449 } 450 451 /* WaVSRefCountFullforceMissDisable:bdw */ 452 /* WaDSRefCountFullforceMissDisable:bdw */ 453 intel_uncore_rmw(&i915->uncore, GEN7_FF_THREAD_MODE, 454 GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME, 0); 455 456 intel_uncore_write(&i915->uncore, RING_PSMI_CTL(RENDER_RING_BASE), 457 REG_MASKED_FIELD_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); 458 459 /* WaDisableSDEUnitClockGating:bdw */ 460 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 461 462 /* WaProgramL3SqcReg1Default:bdw */ 463 gen8_set_l3sqc_credits(i915, 30, 2); 464 465 /* WaKVMNotificationOnConfigChange:bdw */ 466 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR2_1, 467 0, KVM_CONFIG_CHANGE_NOTIFICATION_SELECT); 468 469 lpt_init_clock_gating(i915); 470 471 /* WaDisableDopClockGating:bdw 472 * 473 * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP 474 * clock gating. 475 */ 476 intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1, 0, GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE); 477 } 478 479 static void hsw_init_clock_gating(struct drm_i915_private *i915) 480 { 481 struct intel_display *display = i915->display; 482 enum pipe pipe; 483 484 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ 485 intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS); 486 487 /* WaPsrDPAMaskVBlankInSRD:hsw */ 488 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD); 489 490 for_each_pipe(display, pipe) { 491 /* WaPsrDPRSUnmaskVBlankInSRD:hsw */ 492 intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe), 493 0, HSW_UNMASK_VBL_TO_REGS_IN_SRD); 494 } 495 496 /* This is required by WaCatErrorRejectionIssue:hsw */ 497 intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 498 0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 499 500 /* WaSwitchSolVfFArbitrationPriority:hsw */ 501 intel_uncore_rmw(&i915->uncore, GAM_ECOCHK, 0, HSW_ECOCHK_ARB_PRIO_SOL); 502 503 lpt_init_clock_gating(i915); 504 } 505 506 static void ivb_init_clock_gating(struct drm_i915_private *i915) 507 { 508 struct intel_display *display = i915->display; 509 510 intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); 511 512 /* WaFbcAsynchFlipDisableFbcQueue:ivb */ 513 intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS); 514 515 /* WaDisableBackToBackFlipFix:ivb */ 516 intel_uncore_write(&i915->uncore, IVB_CHICKEN3, 517 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | 518 CHICKEN3_DGMG_DONE_FIX_DISABLE); 519 520 if (INTEL_INFO(i915)->gt == 1) 521 intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2, 522 REG_MASKED_FIELD_ENABLE(DOP_CLOCK_GATING_DISABLE)); 523 else { 524 /* must write both registers */ 525 intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2, 526 REG_MASKED_FIELD_ENABLE(DOP_CLOCK_GATING_DISABLE)); 527 intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2_GT2, 528 REG_MASKED_FIELD_ENABLE(DOP_CLOCK_GATING_DISABLE)); 529 } 530 531 /* 532 * According to the spec, bit 13 (RCZUNIT) must be set on IVB. 533 * This implements the WaDisableRCZUnitClockGating:ivb workaround. 534 */ 535 intel_uncore_write(&i915->uncore, GEN6_UCGCTL2, 536 GEN6_RCZUNIT_CLOCK_GATE_DISABLE); 537 538 /* This is required by WaCatErrorRejectionIssue:ivb */ 539 intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 540 0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 541 542 g4x_disable_trickle_feed(i915); 543 544 intel_uncore_rmw(&i915->uncore, GEN6_MBCUNIT_SNPCR, GEN6_MBC_SNPCR_MASK, 545 GEN6_MBC_SNPCR_MED); 546 547 if (!HAS_PCH_NOP(display)) 548 cpt_init_clock_gating(i915); 549 550 gen6_check_mch_setup(i915); 551 } 552 553 static void vlv_init_clock_gating(struct drm_i915_private *i915) 554 { 555 /* WaDisableBackToBackFlipFix:vlv */ 556 intel_uncore_write(&i915->uncore, IVB_CHICKEN3, 557 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | 558 CHICKEN3_DGMG_DONE_FIX_DISABLE); 559 560 /* WaDisableDopClockGating:vlv */ 561 intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2, 562 REG_MASKED_FIELD_ENABLE(DOP_CLOCK_GATING_DISABLE)); 563 564 /* This is required by WaCatErrorRejectionIssue:vlv */ 565 intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 566 0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 567 568 /* 569 * According to the spec, bit 13 (RCZUNIT) must be set on IVB. 570 * This implements the WaDisableRCZUnitClockGating:vlv workaround. 571 */ 572 intel_uncore_write(&i915->uncore, GEN6_UCGCTL2, 573 GEN6_RCZUNIT_CLOCK_GATE_DISABLE); 574 575 /* WaDisableL3Bank2xClockGate:vlv 576 * Disabling L3 clock gating- MMIO 940c[25] = 1 577 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */ 578 intel_uncore_rmw(&i915->uncore, GEN7_UCGCTL4, 0, GEN7_L3BANK2X_CLOCK_GATE_DISABLE); 579 580 /* 581 * WaDisableVLVClockGating_VBIIssue:vlv 582 * Disable clock gating on th GCFG unit to prevent a delay 583 * in the reporting of vblank events. 584 */ 585 intel_uncore_write(&i915->uncore, VLV_GUNIT_CLOCK_GATE, GCFG_DIS); 586 } 587 588 static void chv_init_clock_gating(struct drm_i915_private *i915) 589 { 590 /* WaVSRefCountFullforceMissDisable:chv */ 591 /* WaDSRefCountFullforceMissDisable:chv */ 592 intel_uncore_rmw(&i915->uncore, GEN7_FF_THREAD_MODE, 593 GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME, 0); 594 595 /* WaDisableSemaphoreAndSyncFlipWait:chv */ 596 intel_uncore_write(&i915->uncore, RING_PSMI_CTL(RENDER_RING_BASE), 597 REG_MASKED_FIELD_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); 598 599 /* WaDisableCSUnitClockGating:chv */ 600 intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1, 0, GEN6_CSUNIT_CLOCK_GATE_DISABLE); 601 602 /* WaDisableSDEUnitClockGating:chv */ 603 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 604 605 /* 606 * WaProgramL3SqcReg1Default:chv 607 * See gfxspecs/Related Documents/Performance Guide/ 608 * LSQC Setting Recommendations. 609 */ 610 gen8_set_l3sqc_credits(i915, 38, 2); 611 } 612 613 static void g4x_init_clock_gating(struct drm_i915_private *i915) 614 { 615 u32 dspclk_gate; 616 617 intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, 0); 618 intel_uncore_write(&i915->uncore, RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | 619 GS_UNIT_CLOCK_GATE_DISABLE | 620 CL_UNIT_CLOCK_GATE_DISABLE); 621 intel_uncore_write(&i915->uncore, RAMCLK_GATE_D, 0); 622 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | 623 OVRUNIT_CLOCK_GATE_DISABLE | 624 OVCUNIT_CLOCK_GATE_DISABLE; 625 if (IS_GM45(i915)) 626 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; 627 intel_uncore_write(&i915->uncore, DSPCLK_GATE_D, dspclk_gate); 628 629 g4x_disable_trickle_feed(i915); 630 } 631 632 static void i965gm_init_clock_gating(struct drm_i915_private *i915) 633 { 634 struct intel_uncore *uncore = &i915->uncore; 635 636 intel_uncore_write(uncore, RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); 637 intel_uncore_write(uncore, RENCLK_GATE_D2, 0); 638 intel_uncore_write(uncore, DSPCLK_GATE_D, 0); 639 intel_uncore_write(uncore, RAMCLK_GATE_D, 0); 640 intel_uncore_write16(uncore, DEUC, 0); 641 intel_uncore_write(uncore, 642 MI_ARB_STATE, 643 REG_MASKED_FIELD_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); 644 } 645 646 static void i965g_init_clock_gating(struct drm_i915_private *i915) 647 { 648 intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | 649 I965_RCC_CLOCK_GATE_DISABLE | 650 I965_RCPB_CLOCK_GATE_DISABLE | 651 I965_ISC_CLOCK_GATE_DISABLE | 652 I965_FBC_CLOCK_GATE_DISABLE); 653 intel_uncore_write(&i915->uncore, RENCLK_GATE_D2, 0); 654 intel_uncore_write(&i915->uncore, MI_ARB_STATE, 655 REG_MASKED_FIELD_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); 656 } 657 658 static void gen3_init_clock_gating(struct drm_i915_private *i915) 659 { 660 u32 dstate = intel_uncore_read(&i915->uncore, D_STATE); 661 662 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | 663 DSTATE_DOT_CLOCK_GATING; 664 intel_uncore_write(&i915->uncore, D_STATE, dstate); 665 666 if (IS_PINEVIEW(i915)) 667 intel_uncore_write(&i915->uncore, ECOSKPD(RENDER_RING_BASE), 668 REG_MASKED_FIELD_ENABLE(ECO_GATING_CX_ONLY)); 669 670 /* IIR "flip pending" means done if this bit is set */ 671 intel_uncore_write(&i915->uncore, ECOSKPD(RENDER_RING_BASE), 672 REG_MASKED_FIELD_DISABLE(ECO_FLIP_DONE)); 673 674 /* interrupts should cause a wake up from C3 */ 675 intel_uncore_write(&i915->uncore, INSTPM, REG_MASKED_FIELD_ENABLE(INSTPM_AGPBUSY_INT_EN)); 676 677 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ 678 intel_uncore_write(&i915->uncore, MI_ARB_STATE, 679 REG_MASKED_FIELD_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); 680 681 intel_uncore_write(&i915->uncore, MI_ARB_STATE, 682 REG_MASKED_FIELD_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); 683 } 684 685 static void i85x_init_clock_gating(struct drm_i915_private *i915) 686 { 687 intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); 688 689 /* interrupts should cause a wake up from C3 */ 690 intel_uncore_write(&i915->uncore, MI_STATE, REG_MASKED_FIELD_ENABLE(MI_AGPBUSY_INT_EN) | 691 REG_MASKED_FIELD_DISABLE(MI_AGPBUSY_830_MODE)); 692 693 intel_uncore_write(&i915->uncore, MEM_MODE, 694 REG_MASKED_FIELD_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE)); 695 696 /* 697 * Have FBC ignore 3D activity since we use software 698 * render tracking, and otherwise a pure 3D workload 699 * (even if it just renders a single frame and then does 700 * absolutely nothing) would not allow FBC to recompress 701 * until a 2D blit occurs. 702 */ 703 intel_uncore_write(&i915->uncore, SCPD0, 704 REG_MASKED_FIELD_ENABLE(SCPD_FBC_IGNORE_3D)); 705 } 706 707 static void i830_init_clock_gating(struct drm_i915_private *i915) 708 { 709 intel_uncore_write(&i915->uncore, MEM_MODE, 710 REG_MASKED_FIELD_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) | 711 REG_MASKED_FIELD_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE)); 712 } 713 714 void intel_clock_gating_init(struct drm_device *drm) 715 { 716 struct drm_i915_private *i915 = to_i915(drm); 717 718 i915->clock_gating_funcs->init_clock_gating(i915); 719 } 720 721 static void nop_init_clock_gating(struct drm_i915_private *i915) 722 { 723 drm_dbg_kms(&i915->drm, 724 "No clock gating settings or workarounds applied.\n"); 725 } 726 727 #define CG_FUNCS(platform) \ 728 static const struct drm_i915_clock_gating_funcs platform##_clock_gating_funcs = { \ 729 .init_clock_gating = platform##_init_clock_gating, \ 730 } 731 732 CG_FUNCS(dg2); 733 CG_FUNCS(cfl); 734 CG_FUNCS(skl); 735 CG_FUNCS(kbl); 736 CG_FUNCS(bxt); 737 CG_FUNCS(glk); 738 CG_FUNCS(bdw); 739 CG_FUNCS(chv); 740 CG_FUNCS(hsw); 741 CG_FUNCS(ivb); 742 CG_FUNCS(vlv); 743 CG_FUNCS(gen6); 744 CG_FUNCS(ilk); 745 CG_FUNCS(g4x); 746 CG_FUNCS(i965gm); 747 CG_FUNCS(i965g); 748 CG_FUNCS(gen3); 749 CG_FUNCS(i85x); 750 CG_FUNCS(i830); 751 CG_FUNCS(nop); 752 #undef CG_FUNCS 753 754 /** 755 * intel_clock_gating_hooks_init - setup the clock gating hooks 756 * @drm: drm device 757 * 758 * Setup the hooks that configure which clocks of a given platform can be 759 * gated and also apply various GT and display specific workarounds for these 760 * platforms. Note that some GT specific workarounds are applied separately 761 * when GPU contexts or batchbuffers start their execution. 762 */ 763 void intel_clock_gating_hooks_init(struct drm_device *drm) 764 { 765 struct drm_i915_private *i915 = to_i915(drm); 766 767 if (IS_DG2(i915)) 768 i915->clock_gating_funcs = &dg2_clock_gating_funcs; 769 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 770 i915->clock_gating_funcs = &cfl_clock_gating_funcs; 771 else if (IS_SKYLAKE(i915)) 772 i915->clock_gating_funcs = &skl_clock_gating_funcs; 773 else if (IS_KABYLAKE(i915)) 774 i915->clock_gating_funcs = &kbl_clock_gating_funcs; 775 else if (IS_BROXTON(i915)) 776 i915->clock_gating_funcs = &bxt_clock_gating_funcs; 777 else if (IS_GEMINILAKE(i915)) 778 i915->clock_gating_funcs = &glk_clock_gating_funcs; 779 else if (IS_BROADWELL(i915)) 780 i915->clock_gating_funcs = &bdw_clock_gating_funcs; 781 else if (IS_CHERRYVIEW(i915)) 782 i915->clock_gating_funcs = &chv_clock_gating_funcs; 783 else if (IS_HASWELL(i915)) 784 i915->clock_gating_funcs = &hsw_clock_gating_funcs; 785 else if (IS_IVYBRIDGE(i915)) 786 i915->clock_gating_funcs = &ivb_clock_gating_funcs; 787 else if (IS_VALLEYVIEW(i915)) 788 i915->clock_gating_funcs = &vlv_clock_gating_funcs; 789 else if (GRAPHICS_VER(i915) == 6) 790 i915->clock_gating_funcs = &gen6_clock_gating_funcs; 791 else if (GRAPHICS_VER(i915) == 5) 792 i915->clock_gating_funcs = &ilk_clock_gating_funcs; 793 else if (IS_G4X(i915)) 794 i915->clock_gating_funcs = &g4x_clock_gating_funcs; 795 else if (IS_I965GM(i915)) 796 i915->clock_gating_funcs = &i965gm_clock_gating_funcs; 797 else if (IS_I965G(i915)) 798 i915->clock_gating_funcs = &i965g_clock_gating_funcs; 799 else if (GRAPHICS_VER(i915) == 3) 800 i915->clock_gating_funcs = &gen3_clock_gating_funcs; 801 else if (IS_I85X(i915) || IS_I865G(i915)) 802 i915->clock_gating_funcs = &i85x_clock_gating_funcs; 803 else if (GRAPHICS_VER(i915) == 2) 804 i915->clock_gating_funcs = &i830_clock_gating_funcs; 805 else 806 i915->clock_gating_funcs = &nop_clock_gating_funcs; 807 } 808