xref: /linux/drivers/gpu/drm/i915/i915_sysfs.c (revision d003d772e64df08af04ee63609d47169ee82ae0e)
1 /*
2  * Copyright © 2012 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Authors:
24  *    Ben Widawsky <ben@bwidawsk.net>
25  *
26  */
27 
28 #include <linux/device.h>
29 #include <linux/module.h>
30 #include <linux/stat.h>
31 #include <linux/sysfs.h>
32 #include "intel_drv.h"
33 #include "i915_drv.h"
34 
35 static inline struct drm_i915_private *kdev_minor_to_i915(struct device *kdev)
36 {
37 	struct drm_minor *minor = dev_get_drvdata(kdev);
38 	return to_i915(minor->dev);
39 }
40 
41 #ifdef CONFIG_PM
42 static u32 calc_residency(struct drm_i915_private *dev_priv,
43 			  i915_reg_t reg)
44 {
45 	intel_wakeref_t wakeref;
46 	u64 res = 0;
47 
48 	with_intel_runtime_pm(dev_priv, wakeref)
49 		res = intel_rc6_residency_us(dev_priv, reg);
50 
51 	return DIV_ROUND_CLOSEST_ULL(res, 1000);
52 }
53 
54 static ssize_t
55 show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf)
56 {
57 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
58 	unsigned int mask;
59 
60 	mask = 0;
61 	if (HAS_RC6(dev_priv))
62 		mask |= BIT(0);
63 	if (HAS_RC6p(dev_priv))
64 		mask |= BIT(1);
65 	if (HAS_RC6pp(dev_priv))
66 		mask |= BIT(2);
67 
68 	return snprintf(buf, PAGE_SIZE, "%x\n", mask);
69 }
70 
71 static ssize_t
72 show_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
73 {
74 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
75 	u32 rc6_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6);
76 	return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
77 }
78 
79 static ssize_t
80 show_rc6p_ms(struct device *kdev, struct device_attribute *attr, char *buf)
81 {
82 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
83 	u32 rc6p_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6p);
84 	return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency);
85 }
86 
87 static ssize_t
88 show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf)
89 {
90 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
91 	u32 rc6pp_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6pp);
92 	return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency);
93 }
94 
95 static ssize_t
96 show_media_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
97 {
98 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
99 	u32 rc6_residency = calc_residency(dev_priv, VLV_GT_MEDIA_RC6);
100 	return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
101 }
102 
103 static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL);
104 static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL);
105 static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL);
106 static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL);
107 static DEVICE_ATTR(media_rc6_residency_ms, S_IRUGO, show_media_rc6_ms, NULL);
108 
109 static struct attribute *rc6_attrs[] = {
110 	&dev_attr_rc6_enable.attr,
111 	&dev_attr_rc6_residency_ms.attr,
112 	NULL
113 };
114 
115 static const struct attribute_group rc6_attr_group = {
116 	.name = power_group_name,
117 	.attrs =  rc6_attrs
118 };
119 
120 static struct attribute *rc6p_attrs[] = {
121 	&dev_attr_rc6p_residency_ms.attr,
122 	&dev_attr_rc6pp_residency_ms.attr,
123 	NULL
124 };
125 
126 static const struct attribute_group rc6p_attr_group = {
127 	.name = power_group_name,
128 	.attrs =  rc6p_attrs
129 };
130 
131 static struct attribute *media_rc6_attrs[] = {
132 	&dev_attr_media_rc6_residency_ms.attr,
133 	NULL
134 };
135 
136 static const struct attribute_group media_rc6_attr_group = {
137 	.name = power_group_name,
138 	.attrs =  media_rc6_attrs
139 };
140 #endif
141 
142 static int l3_access_valid(struct drm_i915_private *dev_priv, loff_t offset)
143 {
144 	if (!HAS_L3_DPF(dev_priv))
145 		return -EPERM;
146 
147 	if (offset % 4 != 0)
148 		return -EINVAL;
149 
150 	if (offset >= GEN7_L3LOG_SIZE)
151 		return -ENXIO;
152 
153 	return 0;
154 }
155 
156 static ssize_t
157 i915_l3_read(struct file *filp, struct kobject *kobj,
158 	     struct bin_attribute *attr, char *buf,
159 	     loff_t offset, size_t count)
160 {
161 	struct device *kdev = kobj_to_dev(kobj);
162 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
163 	struct drm_device *dev = &dev_priv->drm;
164 	int slice = (int)(uintptr_t)attr->private;
165 	int ret;
166 
167 	count = round_down(count, 4);
168 
169 	ret = l3_access_valid(dev_priv, offset);
170 	if (ret)
171 		return ret;
172 
173 	count = min_t(size_t, GEN7_L3LOG_SIZE - offset, count);
174 
175 	ret = i915_mutex_lock_interruptible(dev);
176 	if (ret)
177 		return ret;
178 
179 	if (dev_priv->l3_parity.remap_info[slice])
180 		memcpy(buf,
181 		       dev_priv->l3_parity.remap_info[slice] + (offset/4),
182 		       count);
183 	else
184 		memset(buf, 0, count);
185 
186 	mutex_unlock(&dev->struct_mutex);
187 
188 	return count;
189 }
190 
191 static ssize_t
192 i915_l3_write(struct file *filp, struct kobject *kobj,
193 	      struct bin_attribute *attr, char *buf,
194 	      loff_t offset, size_t count)
195 {
196 	struct device *kdev = kobj_to_dev(kobj);
197 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
198 	struct drm_device *dev = &dev_priv->drm;
199 	struct i915_gem_context *ctx;
200 	int slice = (int)(uintptr_t)attr->private;
201 	u32 **remap_info;
202 	int ret;
203 
204 	ret = l3_access_valid(dev_priv, offset);
205 	if (ret)
206 		return ret;
207 
208 	ret = i915_mutex_lock_interruptible(dev);
209 	if (ret)
210 		return ret;
211 
212 	remap_info = &dev_priv->l3_parity.remap_info[slice];
213 	if (!*remap_info) {
214 		*remap_info = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL);
215 		if (!*remap_info) {
216 			ret = -ENOMEM;
217 			goto out;
218 		}
219 	}
220 
221 	/* TODO: Ideally we really want a GPU reset here to make sure errors
222 	 * aren't propagated. Since I cannot find a stable way to reset the GPU
223 	 * at this point it is left as a TODO.
224 	*/
225 	memcpy(*remap_info + (offset/4), buf, count);
226 
227 	/* NB: We defer the remapping until we switch to the context */
228 	list_for_each_entry(ctx, &dev_priv->contexts.list, link)
229 		ctx->remap_slice |= (1<<slice);
230 
231 	ret = count;
232 
233 out:
234 	mutex_unlock(&dev->struct_mutex);
235 
236 	return ret;
237 }
238 
239 static const struct bin_attribute dpf_attrs = {
240 	.attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)},
241 	.size = GEN7_L3LOG_SIZE,
242 	.read = i915_l3_read,
243 	.write = i915_l3_write,
244 	.mmap = NULL,
245 	.private = (void *)0
246 };
247 
248 static const struct bin_attribute dpf_attrs_1 = {
249 	.attr = {.name = "l3_parity_slice_1", .mode = (S_IRUSR | S_IWUSR)},
250 	.size = GEN7_L3LOG_SIZE,
251 	.read = i915_l3_read,
252 	.write = i915_l3_write,
253 	.mmap = NULL,
254 	.private = (void *)1
255 };
256 
257 static ssize_t gt_act_freq_mhz_show(struct device *kdev,
258 				    struct device_attribute *attr, char *buf)
259 {
260 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
261 	intel_wakeref_t wakeref;
262 	int ret;
263 
264 	wakeref = intel_runtime_pm_get(dev_priv);
265 
266 	mutex_lock(&dev_priv->pcu_lock);
267 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
268 		u32 freq;
269 		freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
270 		ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
271 	} else {
272 		ret = intel_gpu_freq(dev_priv,
273 				     intel_get_cagf(dev_priv,
274 						    I915_READ(GEN6_RPSTAT1)));
275 	}
276 	mutex_unlock(&dev_priv->pcu_lock);
277 
278 	intel_runtime_pm_put(dev_priv, wakeref);
279 
280 	return snprintf(buf, PAGE_SIZE, "%d\n", ret);
281 }
282 
283 static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
284 				    struct device_attribute *attr, char *buf)
285 {
286 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
287 
288 	return snprintf(buf, PAGE_SIZE, "%d\n",
289 			intel_gpu_freq(dev_priv,
290 				       dev_priv->gt_pm.rps.cur_freq));
291 }
292 
293 static ssize_t gt_boost_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
294 {
295 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
296 
297 	return snprintf(buf, PAGE_SIZE, "%d\n",
298 			intel_gpu_freq(dev_priv,
299 				       dev_priv->gt_pm.rps.boost_freq));
300 }
301 
302 static ssize_t gt_boost_freq_mhz_store(struct device *kdev,
303 				       struct device_attribute *attr,
304 				       const char *buf, size_t count)
305 {
306 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
307 	struct intel_rps *rps = &dev_priv->gt_pm.rps;
308 	bool boost = false;
309 	ssize_t ret;
310 	u32 val;
311 
312 	ret = kstrtou32(buf, 0, &val);
313 	if (ret)
314 		return ret;
315 
316 	/* Validate against (static) hardware limits */
317 	val = intel_freq_opcode(dev_priv, val);
318 	if (val < rps->min_freq || val > rps->max_freq)
319 		return -EINVAL;
320 
321 	mutex_lock(&dev_priv->pcu_lock);
322 	if (val != rps->boost_freq) {
323 		rps->boost_freq = val;
324 		boost = atomic_read(&rps->num_waiters);
325 	}
326 	mutex_unlock(&dev_priv->pcu_lock);
327 	if (boost)
328 		schedule_work(&rps->work);
329 
330 	return count;
331 }
332 
333 static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
334 				     struct device_attribute *attr, char *buf)
335 {
336 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
337 
338 	return snprintf(buf, PAGE_SIZE, "%d\n",
339 			intel_gpu_freq(dev_priv,
340 				       dev_priv->gt_pm.rps.efficient_freq));
341 }
342 
343 static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
344 {
345 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
346 
347 	return snprintf(buf, PAGE_SIZE, "%d\n",
348 			intel_gpu_freq(dev_priv,
349 				       dev_priv->gt_pm.rps.max_freq_softlimit));
350 }
351 
352 static ssize_t gt_max_freq_mhz_store(struct device *kdev,
353 				     struct device_attribute *attr,
354 				     const char *buf, size_t count)
355 {
356 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
357 	struct intel_rps *rps = &dev_priv->gt_pm.rps;
358 	intel_wakeref_t wakeref;
359 	u32 val;
360 	ssize_t ret;
361 
362 	ret = kstrtou32(buf, 0, &val);
363 	if (ret)
364 		return ret;
365 
366 	wakeref = intel_runtime_pm_get(dev_priv);
367 
368 	mutex_lock(&dev_priv->pcu_lock);
369 
370 	val = intel_freq_opcode(dev_priv, val);
371 
372 	if (val < rps->min_freq ||
373 	    val > rps->max_freq ||
374 	    val < rps->min_freq_softlimit) {
375 		mutex_unlock(&dev_priv->pcu_lock);
376 		intel_runtime_pm_put(dev_priv, wakeref);
377 		return -EINVAL;
378 	}
379 
380 	if (val > rps->rp0_freq)
381 		DRM_DEBUG("User requested overclocking to %d\n",
382 			  intel_gpu_freq(dev_priv, val));
383 
384 	rps->max_freq_softlimit = val;
385 
386 	val = clamp_t(int, rps->cur_freq,
387 		      rps->min_freq_softlimit,
388 		      rps->max_freq_softlimit);
389 
390 	/* We still need *_set_rps to process the new max_delay and
391 	 * update the interrupt limits and PMINTRMSK even though
392 	 * frequency request may be unchanged. */
393 	ret = intel_set_rps(dev_priv, val);
394 
395 	mutex_unlock(&dev_priv->pcu_lock);
396 
397 	intel_runtime_pm_put(dev_priv, wakeref);
398 
399 	return ret ?: count;
400 }
401 
402 static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
403 {
404 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
405 
406 	return snprintf(buf, PAGE_SIZE, "%d\n",
407 			intel_gpu_freq(dev_priv,
408 				       dev_priv->gt_pm.rps.min_freq_softlimit));
409 }
410 
411 static ssize_t gt_min_freq_mhz_store(struct device *kdev,
412 				     struct device_attribute *attr,
413 				     const char *buf, size_t count)
414 {
415 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
416 	struct intel_rps *rps = &dev_priv->gt_pm.rps;
417 	intel_wakeref_t wakeref;
418 	u32 val;
419 	ssize_t ret;
420 
421 	ret = kstrtou32(buf, 0, &val);
422 	if (ret)
423 		return ret;
424 
425 	wakeref = intel_runtime_pm_get(dev_priv);
426 
427 	mutex_lock(&dev_priv->pcu_lock);
428 
429 	val = intel_freq_opcode(dev_priv, val);
430 
431 	if (val < rps->min_freq ||
432 	    val > rps->max_freq ||
433 	    val > rps->max_freq_softlimit) {
434 		mutex_unlock(&dev_priv->pcu_lock);
435 		intel_runtime_pm_put(dev_priv, wakeref);
436 		return -EINVAL;
437 	}
438 
439 	rps->min_freq_softlimit = val;
440 
441 	val = clamp_t(int, rps->cur_freq,
442 		      rps->min_freq_softlimit,
443 		      rps->max_freq_softlimit);
444 
445 	/* We still need *_set_rps to process the new min_delay and
446 	 * update the interrupt limits and PMINTRMSK even though
447 	 * frequency request may be unchanged. */
448 	ret = intel_set_rps(dev_priv, val);
449 
450 	mutex_unlock(&dev_priv->pcu_lock);
451 
452 	intel_runtime_pm_put(dev_priv, wakeref);
453 
454 	return ret ?: count;
455 }
456 
457 static DEVICE_ATTR_RO(gt_act_freq_mhz);
458 static DEVICE_ATTR_RO(gt_cur_freq_mhz);
459 static DEVICE_ATTR_RW(gt_boost_freq_mhz);
460 static DEVICE_ATTR_RW(gt_max_freq_mhz);
461 static DEVICE_ATTR_RW(gt_min_freq_mhz);
462 
463 static DEVICE_ATTR_RO(vlv_rpe_freq_mhz);
464 
465 static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf);
466 static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
467 static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
468 static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
469 
470 /* For now we have a static number of RP states */
471 static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
472 {
473 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
474 	struct intel_rps *rps = &dev_priv->gt_pm.rps;
475 	u32 val;
476 
477 	if (attr == &dev_attr_gt_RP0_freq_mhz)
478 		val = intel_gpu_freq(dev_priv, rps->rp0_freq);
479 	else if (attr == &dev_attr_gt_RP1_freq_mhz)
480 		val = intel_gpu_freq(dev_priv, rps->rp1_freq);
481 	else if (attr == &dev_attr_gt_RPn_freq_mhz)
482 		val = intel_gpu_freq(dev_priv, rps->min_freq);
483 	else
484 		BUG();
485 
486 	return snprintf(buf, PAGE_SIZE, "%d\n", val);
487 }
488 
489 static const struct attribute * const gen6_attrs[] = {
490 	&dev_attr_gt_act_freq_mhz.attr,
491 	&dev_attr_gt_cur_freq_mhz.attr,
492 	&dev_attr_gt_boost_freq_mhz.attr,
493 	&dev_attr_gt_max_freq_mhz.attr,
494 	&dev_attr_gt_min_freq_mhz.attr,
495 	&dev_attr_gt_RP0_freq_mhz.attr,
496 	&dev_attr_gt_RP1_freq_mhz.attr,
497 	&dev_attr_gt_RPn_freq_mhz.attr,
498 	NULL,
499 };
500 
501 static const struct attribute * const vlv_attrs[] = {
502 	&dev_attr_gt_act_freq_mhz.attr,
503 	&dev_attr_gt_cur_freq_mhz.attr,
504 	&dev_attr_gt_boost_freq_mhz.attr,
505 	&dev_attr_gt_max_freq_mhz.attr,
506 	&dev_attr_gt_min_freq_mhz.attr,
507 	&dev_attr_gt_RP0_freq_mhz.attr,
508 	&dev_attr_gt_RP1_freq_mhz.attr,
509 	&dev_attr_gt_RPn_freq_mhz.attr,
510 	&dev_attr_vlv_rpe_freq_mhz.attr,
511 	NULL,
512 };
513 
514 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
515 
516 static ssize_t error_state_read(struct file *filp, struct kobject *kobj,
517 				struct bin_attribute *attr, char *buf,
518 				loff_t off, size_t count)
519 {
520 
521 	struct device *kdev = kobj_to_dev(kobj);
522 	struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
523 	struct i915_gpu_state *gpu;
524 	ssize_t ret;
525 
526 	gpu = i915_first_error_state(i915);
527 	if (IS_ERR(gpu)) {
528 		ret = PTR_ERR(gpu);
529 	} else if (gpu) {
530 		ret = i915_gpu_state_copy_to_buffer(gpu, buf, off, count);
531 		i915_gpu_state_put(gpu);
532 	} else {
533 		const char *str = "No error state collected\n";
534 		size_t len = strlen(str);
535 
536 		ret = min_t(size_t, count, len - off);
537 		memcpy(buf, str + off, ret);
538 	}
539 
540 	return ret;
541 }
542 
543 static ssize_t error_state_write(struct file *file, struct kobject *kobj,
544 				 struct bin_attribute *attr, char *buf,
545 				 loff_t off, size_t count)
546 {
547 	struct device *kdev = kobj_to_dev(kobj);
548 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
549 
550 	DRM_DEBUG_DRIVER("Resetting error state\n");
551 	i915_reset_error_state(dev_priv);
552 
553 	return count;
554 }
555 
556 static const struct bin_attribute error_state_attr = {
557 	.attr.name = "error",
558 	.attr.mode = S_IRUSR | S_IWUSR,
559 	.size = 0,
560 	.read = error_state_read,
561 	.write = error_state_write,
562 };
563 
564 static void i915_setup_error_capture(struct device *kdev)
565 {
566 	if (sysfs_create_bin_file(&kdev->kobj, &error_state_attr))
567 		DRM_ERROR("error_state sysfs setup failed\n");
568 }
569 
570 static void i915_teardown_error_capture(struct device *kdev)
571 {
572 	sysfs_remove_bin_file(&kdev->kobj, &error_state_attr);
573 }
574 #else
575 static void i915_setup_error_capture(struct device *kdev) {}
576 static void i915_teardown_error_capture(struct device *kdev) {}
577 #endif
578 
579 void i915_setup_sysfs(struct drm_i915_private *dev_priv)
580 {
581 	struct device *kdev = dev_priv->drm.primary->kdev;
582 	int ret;
583 
584 #ifdef CONFIG_PM
585 	if (HAS_RC6(dev_priv)) {
586 		ret = sysfs_merge_group(&kdev->kobj,
587 					&rc6_attr_group);
588 		if (ret)
589 			DRM_ERROR("RC6 residency sysfs setup failed\n");
590 	}
591 	if (HAS_RC6p(dev_priv)) {
592 		ret = sysfs_merge_group(&kdev->kobj,
593 					&rc6p_attr_group);
594 		if (ret)
595 			DRM_ERROR("RC6p residency sysfs setup failed\n");
596 	}
597 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
598 		ret = sysfs_merge_group(&kdev->kobj,
599 					&media_rc6_attr_group);
600 		if (ret)
601 			DRM_ERROR("Media RC6 residency sysfs setup failed\n");
602 	}
603 #endif
604 	if (HAS_L3_DPF(dev_priv)) {
605 		ret = device_create_bin_file(kdev, &dpf_attrs);
606 		if (ret)
607 			DRM_ERROR("l3 parity sysfs setup failed\n");
608 
609 		if (NUM_L3_SLICES(dev_priv) > 1) {
610 			ret = device_create_bin_file(kdev,
611 						     &dpf_attrs_1);
612 			if (ret)
613 				DRM_ERROR("l3 parity slice 1 setup failed\n");
614 		}
615 	}
616 
617 	ret = 0;
618 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
619 		ret = sysfs_create_files(&kdev->kobj, vlv_attrs);
620 	else if (INTEL_GEN(dev_priv) >= 6)
621 		ret = sysfs_create_files(&kdev->kobj, gen6_attrs);
622 	if (ret)
623 		DRM_ERROR("RPS sysfs setup failed\n");
624 
625 	i915_setup_error_capture(kdev);
626 }
627 
628 void i915_teardown_sysfs(struct drm_i915_private *dev_priv)
629 {
630 	struct device *kdev = dev_priv->drm.primary->kdev;
631 
632 	i915_teardown_error_capture(kdev);
633 
634 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
635 		sysfs_remove_files(&kdev->kobj, vlv_attrs);
636 	else
637 		sysfs_remove_files(&kdev->kobj, gen6_attrs);
638 	device_remove_bin_file(kdev,  &dpf_attrs_1);
639 	device_remove_bin_file(kdev,  &dpf_attrs);
640 #ifdef CONFIG_PM
641 	sysfs_unmerge_group(&kdev->kobj, &rc6_attr_group);
642 	sysfs_unmerge_group(&kdev->kobj, &rc6p_attr_group);
643 #endif
644 }
645