1 /* 2 * Copyright © 2008-2015 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/prefetch.h> 26 #include <linux/dma-fence-array.h> 27 #include <linux/sched.h> 28 #include <linux/sched/clock.h> 29 #include <linux/sched/signal.h> 30 31 #include "i915_drv.h" 32 33 static const char *i915_fence_get_driver_name(struct dma_fence *fence) 34 { 35 return "i915"; 36 } 37 38 static const char *i915_fence_get_timeline_name(struct dma_fence *fence) 39 { 40 /* 41 * The timeline struct (as part of the ppgtt underneath a context) 42 * may be freed when the request is no longer in use by the GPU. 43 * We could extend the life of a context to beyond that of all 44 * fences, possibly keeping the hw resource around indefinitely, 45 * or we just give them a false name. Since 46 * dma_fence_ops.get_timeline_name is a debug feature, the occasional 47 * lie seems justifiable. 48 */ 49 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) 50 return "signaled"; 51 52 return to_request(fence)->timeline->name; 53 } 54 55 static bool i915_fence_signaled(struct dma_fence *fence) 56 { 57 return i915_request_completed(to_request(fence)); 58 } 59 60 static bool i915_fence_enable_signaling(struct dma_fence *fence) 61 { 62 return intel_engine_enable_signaling(to_request(fence), true); 63 } 64 65 static signed long i915_fence_wait(struct dma_fence *fence, 66 bool interruptible, 67 signed long timeout) 68 { 69 return i915_request_wait(to_request(fence), interruptible, timeout); 70 } 71 72 static void i915_fence_release(struct dma_fence *fence) 73 { 74 struct i915_request *rq = to_request(fence); 75 76 /* 77 * The request is put onto a RCU freelist (i.e. the address 78 * is immediately reused), mark the fences as being freed now. 79 * Otherwise the debugobjects for the fences are only marked as 80 * freed when the slab cache itself is freed, and so we would get 81 * caught trying to reuse dead objects. 82 */ 83 i915_sw_fence_fini(&rq->submit); 84 85 kmem_cache_free(rq->i915->requests, rq); 86 } 87 88 const struct dma_fence_ops i915_fence_ops = { 89 .get_driver_name = i915_fence_get_driver_name, 90 .get_timeline_name = i915_fence_get_timeline_name, 91 .enable_signaling = i915_fence_enable_signaling, 92 .signaled = i915_fence_signaled, 93 .wait = i915_fence_wait, 94 .release = i915_fence_release, 95 }; 96 97 static inline void 98 i915_request_remove_from_client(struct i915_request *request) 99 { 100 struct drm_i915_file_private *file_priv; 101 102 file_priv = request->file_priv; 103 if (!file_priv) 104 return; 105 106 spin_lock(&file_priv->mm.lock); 107 if (request->file_priv) { 108 list_del(&request->client_link); 109 request->file_priv = NULL; 110 } 111 spin_unlock(&file_priv->mm.lock); 112 } 113 114 static struct i915_dependency * 115 i915_dependency_alloc(struct drm_i915_private *i915) 116 { 117 return kmem_cache_alloc(i915->dependencies, GFP_KERNEL); 118 } 119 120 static void 121 i915_dependency_free(struct drm_i915_private *i915, 122 struct i915_dependency *dep) 123 { 124 kmem_cache_free(i915->dependencies, dep); 125 } 126 127 static void 128 __i915_sched_node_add_dependency(struct i915_sched_node *node, 129 struct i915_sched_node *signal, 130 struct i915_dependency *dep, 131 unsigned long flags) 132 { 133 INIT_LIST_HEAD(&dep->dfs_link); 134 list_add(&dep->wait_link, &signal->waiters_list); 135 list_add(&dep->signal_link, &node->signalers_list); 136 dep->signaler = signal; 137 dep->flags = flags; 138 } 139 140 static int 141 i915_sched_node_add_dependency(struct drm_i915_private *i915, 142 struct i915_sched_node *node, 143 struct i915_sched_node *signal) 144 { 145 struct i915_dependency *dep; 146 147 dep = i915_dependency_alloc(i915); 148 if (!dep) 149 return -ENOMEM; 150 151 __i915_sched_node_add_dependency(node, signal, dep, 152 I915_DEPENDENCY_ALLOC); 153 return 0; 154 } 155 156 static void 157 i915_sched_node_fini(struct drm_i915_private *i915, 158 struct i915_sched_node *node) 159 { 160 struct i915_dependency *dep, *tmp; 161 162 GEM_BUG_ON(!list_empty(&node->link)); 163 164 /* 165 * Everyone we depended upon (the fences we wait to be signaled) 166 * should retire before us and remove themselves from our list. 167 * However, retirement is run independently on each timeline and 168 * so we may be called out-of-order. 169 */ 170 list_for_each_entry_safe(dep, tmp, &node->signalers_list, signal_link) { 171 GEM_BUG_ON(!i915_sched_node_signaled(dep->signaler)); 172 GEM_BUG_ON(!list_empty(&dep->dfs_link)); 173 174 list_del(&dep->wait_link); 175 if (dep->flags & I915_DEPENDENCY_ALLOC) 176 i915_dependency_free(i915, dep); 177 } 178 179 /* Remove ourselves from everyone who depends upon us */ 180 list_for_each_entry_safe(dep, tmp, &node->waiters_list, wait_link) { 181 GEM_BUG_ON(dep->signaler != node); 182 GEM_BUG_ON(!list_empty(&dep->dfs_link)); 183 184 list_del(&dep->signal_link); 185 if (dep->flags & I915_DEPENDENCY_ALLOC) 186 i915_dependency_free(i915, dep); 187 } 188 } 189 190 static void 191 i915_sched_node_init(struct i915_sched_node *node) 192 { 193 INIT_LIST_HEAD(&node->signalers_list); 194 INIT_LIST_HEAD(&node->waiters_list); 195 INIT_LIST_HEAD(&node->link); 196 node->attr.priority = I915_PRIORITY_INVALID; 197 } 198 199 static int reset_all_global_seqno(struct drm_i915_private *i915, u32 seqno) 200 { 201 struct intel_engine_cs *engine; 202 struct i915_timeline *timeline; 203 enum intel_engine_id id; 204 int ret; 205 206 /* Carefully retire all requests without writing to the rings */ 207 ret = i915_gem_wait_for_idle(i915, 208 I915_WAIT_INTERRUPTIBLE | 209 I915_WAIT_LOCKED); 210 if (ret) 211 return ret; 212 213 GEM_BUG_ON(i915->gt.active_requests); 214 215 /* If the seqno wraps around, we need to clear the breadcrumb rbtree */ 216 for_each_engine(engine, i915, id) { 217 GEM_TRACE("%s seqno %d (current %d) -> %d\n", 218 engine->name, 219 engine->timeline.seqno, 220 intel_engine_get_seqno(engine), 221 seqno); 222 223 if (!i915_seqno_passed(seqno, engine->timeline.seqno)) { 224 /* Flush any waiters before we reuse the seqno */ 225 intel_engine_disarm_breadcrumbs(engine); 226 intel_engine_init_hangcheck(engine); 227 GEM_BUG_ON(!list_empty(&engine->breadcrumbs.signals)); 228 } 229 230 /* Check we are idle before we fiddle with hw state! */ 231 GEM_BUG_ON(!intel_engine_is_idle(engine)); 232 GEM_BUG_ON(i915_gem_active_isset(&engine->timeline.last_request)); 233 234 /* Finally reset hw state */ 235 intel_engine_init_global_seqno(engine, seqno); 236 engine->timeline.seqno = seqno; 237 } 238 239 list_for_each_entry(timeline, &i915->gt.timelines, link) 240 memset(timeline->global_sync, 0, sizeof(timeline->global_sync)); 241 242 i915->gt.request_serial = seqno; 243 244 return 0; 245 } 246 247 int i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno) 248 { 249 struct drm_i915_private *i915 = to_i915(dev); 250 251 lockdep_assert_held(&i915->drm.struct_mutex); 252 253 if (seqno == 0) 254 return -EINVAL; 255 256 /* HWS page needs to be set less than what we will inject to ring */ 257 return reset_all_global_seqno(i915, seqno - 1); 258 } 259 260 static int reserve_gt(struct drm_i915_private *i915) 261 { 262 int ret; 263 264 /* 265 * Reservation is fine until we may need to wrap around 266 * 267 * By incrementing the serial for every request, we know that no 268 * individual engine may exceed that serial (as each is reset to 0 269 * on any wrap). This protects even the most pessimistic of migrations 270 * of every request from all engines onto just one. 271 */ 272 while (unlikely(++i915->gt.request_serial == 0)) { 273 ret = reset_all_global_seqno(i915, 0); 274 if (ret) { 275 i915->gt.request_serial--; 276 return ret; 277 } 278 } 279 280 if (!i915->gt.active_requests++) 281 i915_gem_unpark(i915); 282 283 return 0; 284 } 285 286 static void unreserve_gt(struct drm_i915_private *i915) 287 { 288 GEM_BUG_ON(!i915->gt.active_requests); 289 if (!--i915->gt.active_requests) 290 i915_gem_park(i915); 291 } 292 293 void i915_gem_retire_noop(struct i915_gem_active *active, 294 struct i915_request *request) 295 { 296 /* Space left intentionally blank */ 297 } 298 299 static void advance_ring(struct i915_request *request) 300 { 301 struct intel_ring *ring = request->ring; 302 unsigned int tail; 303 304 /* 305 * We know the GPU must have read the request to have 306 * sent us the seqno + interrupt, so use the position 307 * of tail of the request to update the last known position 308 * of the GPU head. 309 * 310 * Note this requires that we are always called in request 311 * completion order. 312 */ 313 GEM_BUG_ON(!list_is_first(&request->ring_link, &ring->request_list)); 314 if (list_is_last(&request->ring_link, &ring->request_list)) { 315 /* 316 * We may race here with execlists resubmitting this request 317 * as we retire it. The resubmission will move the ring->tail 318 * forwards (to request->wa_tail). We either read the 319 * current value that was written to hw, or the value that 320 * is just about to be. Either works, if we miss the last two 321 * noops - they are safe to be replayed on a reset. 322 */ 323 tail = READ_ONCE(request->tail); 324 list_del(&ring->active_link); 325 } else { 326 tail = request->postfix; 327 } 328 list_del_init(&request->ring_link); 329 330 ring->head = tail; 331 } 332 333 static void free_capture_list(struct i915_request *request) 334 { 335 struct i915_capture_list *capture; 336 337 capture = request->capture_list; 338 while (capture) { 339 struct i915_capture_list *next = capture->next; 340 341 kfree(capture); 342 capture = next; 343 } 344 } 345 346 static void __retire_engine_request(struct intel_engine_cs *engine, 347 struct i915_request *rq) 348 { 349 GEM_TRACE("%s(%s) fence %llx:%d, global=%d, current %d\n", 350 __func__, engine->name, 351 rq->fence.context, rq->fence.seqno, 352 rq->global_seqno, 353 intel_engine_get_seqno(engine)); 354 355 GEM_BUG_ON(!i915_request_completed(rq)); 356 357 local_irq_disable(); 358 359 spin_lock(&engine->timeline.lock); 360 GEM_BUG_ON(!list_is_first(&rq->link, &engine->timeline.requests)); 361 list_del_init(&rq->link); 362 spin_unlock(&engine->timeline.lock); 363 364 spin_lock(&rq->lock); 365 if (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags)) 366 dma_fence_signal_locked(&rq->fence); 367 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &rq->fence.flags)) 368 intel_engine_cancel_signaling(rq); 369 if (rq->waitboost) { 370 GEM_BUG_ON(!atomic_read(&rq->i915->gt_pm.rps.num_waiters)); 371 atomic_dec(&rq->i915->gt_pm.rps.num_waiters); 372 } 373 spin_unlock(&rq->lock); 374 375 local_irq_enable(); 376 377 /* 378 * The backing object for the context is done after switching to the 379 * *next* context. Therefore we cannot retire the previous context until 380 * the next context has already started running. However, since we 381 * cannot take the required locks at i915_request_submit() we 382 * defer the unpinning of the active context to now, retirement of 383 * the subsequent request. 384 */ 385 if (engine->last_retired_context) 386 intel_context_unpin(engine->last_retired_context, engine); 387 engine->last_retired_context = rq->ctx; 388 } 389 390 static void __retire_engine_upto(struct intel_engine_cs *engine, 391 struct i915_request *rq) 392 { 393 struct i915_request *tmp; 394 395 if (list_empty(&rq->link)) 396 return; 397 398 do { 399 tmp = list_first_entry(&engine->timeline.requests, 400 typeof(*tmp), link); 401 402 GEM_BUG_ON(tmp->engine != engine); 403 __retire_engine_request(engine, tmp); 404 } while (tmp != rq); 405 } 406 407 static void i915_request_retire(struct i915_request *request) 408 { 409 struct i915_gem_active *active, *next; 410 411 GEM_TRACE("%s fence %llx:%d, global=%d, current %d\n", 412 request->engine->name, 413 request->fence.context, request->fence.seqno, 414 request->global_seqno, 415 intel_engine_get_seqno(request->engine)); 416 417 lockdep_assert_held(&request->i915->drm.struct_mutex); 418 GEM_BUG_ON(!i915_sw_fence_signaled(&request->submit)); 419 GEM_BUG_ON(!i915_request_completed(request)); 420 421 trace_i915_request_retire(request); 422 423 advance_ring(request); 424 free_capture_list(request); 425 426 /* 427 * Walk through the active list, calling retire on each. This allows 428 * objects to track their GPU activity and mark themselves as idle 429 * when their *last* active request is completed (updating state 430 * tracking lists for eviction, active references for GEM, etc). 431 * 432 * As the ->retire() may free the node, we decouple it first and 433 * pass along the auxiliary information (to avoid dereferencing 434 * the node after the callback). 435 */ 436 list_for_each_entry_safe(active, next, &request->active_list, link) { 437 /* 438 * In microbenchmarks or focusing upon time inside the kernel, 439 * we may spend an inordinate amount of time simply handling 440 * the retirement of requests and processing their callbacks. 441 * Of which, this loop itself is particularly hot due to the 442 * cache misses when jumping around the list of i915_gem_active. 443 * So we try to keep this loop as streamlined as possible and 444 * also prefetch the next i915_gem_active to try and hide 445 * the likely cache miss. 446 */ 447 prefetchw(next); 448 449 INIT_LIST_HEAD(&active->link); 450 RCU_INIT_POINTER(active->request, NULL); 451 452 active->retire(active, request); 453 } 454 455 i915_request_remove_from_client(request); 456 457 /* Retirement decays the ban score as it is a sign of ctx progress */ 458 atomic_dec_if_positive(&request->ctx->ban_score); 459 intel_context_unpin(request->ctx, request->engine); 460 461 __retire_engine_upto(request->engine, request); 462 463 unreserve_gt(request->i915); 464 465 i915_sched_node_fini(request->i915, &request->sched); 466 i915_request_put(request); 467 } 468 469 void i915_request_retire_upto(struct i915_request *rq) 470 { 471 struct intel_ring *ring = rq->ring; 472 struct i915_request *tmp; 473 474 GEM_TRACE("%s fence %llx:%d, global=%d, current %d\n", 475 rq->engine->name, 476 rq->fence.context, rq->fence.seqno, 477 rq->global_seqno, 478 intel_engine_get_seqno(rq->engine)); 479 480 lockdep_assert_held(&rq->i915->drm.struct_mutex); 481 GEM_BUG_ON(!i915_request_completed(rq)); 482 483 if (list_empty(&rq->ring_link)) 484 return; 485 486 do { 487 tmp = list_first_entry(&ring->request_list, 488 typeof(*tmp), ring_link); 489 490 i915_request_retire(tmp); 491 } while (tmp != rq); 492 } 493 494 static u32 timeline_get_seqno(struct i915_timeline *tl) 495 { 496 return ++tl->seqno; 497 } 498 499 static void move_to_timeline(struct i915_request *request, 500 struct i915_timeline *timeline) 501 { 502 GEM_BUG_ON(request->timeline == &request->engine->timeline); 503 lockdep_assert_held(&request->engine->timeline.lock); 504 505 spin_lock_nested(&request->timeline->lock, SINGLE_DEPTH_NESTING); 506 list_move_tail(&request->link, &timeline->requests); 507 spin_unlock(&request->timeline->lock); 508 } 509 510 void __i915_request_submit(struct i915_request *request) 511 { 512 struct intel_engine_cs *engine = request->engine; 513 u32 seqno; 514 515 GEM_TRACE("%s fence %llx:%d -> global=%d, current %d\n", 516 engine->name, 517 request->fence.context, request->fence.seqno, 518 engine->timeline.seqno + 1, 519 intel_engine_get_seqno(engine)); 520 521 GEM_BUG_ON(!irqs_disabled()); 522 lockdep_assert_held(&engine->timeline.lock); 523 524 GEM_BUG_ON(request->global_seqno); 525 526 seqno = timeline_get_seqno(&engine->timeline); 527 GEM_BUG_ON(!seqno); 528 GEM_BUG_ON(i915_seqno_passed(intel_engine_get_seqno(engine), seqno)); 529 530 /* We may be recursing from the signal callback of another i915 fence */ 531 spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING); 532 request->global_seqno = seqno; 533 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags)) 534 intel_engine_enable_signaling(request, false); 535 spin_unlock(&request->lock); 536 537 engine->emit_breadcrumb(request, 538 request->ring->vaddr + request->postfix); 539 540 /* Transfer from per-context onto the global per-engine timeline */ 541 move_to_timeline(request, &engine->timeline); 542 543 trace_i915_request_execute(request); 544 545 wake_up_all(&request->execute); 546 } 547 548 void i915_request_submit(struct i915_request *request) 549 { 550 struct intel_engine_cs *engine = request->engine; 551 unsigned long flags; 552 553 /* Will be called from irq-context when using foreign fences. */ 554 spin_lock_irqsave(&engine->timeline.lock, flags); 555 556 __i915_request_submit(request); 557 558 spin_unlock_irqrestore(&engine->timeline.lock, flags); 559 } 560 561 void __i915_request_unsubmit(struct i915_request *request) 562 { 563 struct intel_engine_cs *engine = request->engine; 564 565 GEM_TRACE("%s fence %llx:%d <- global=%d, current %d\n", 566 engine->name, 567 request->fence.context, request->fence.seqno, 568 request->global_seqno, 569 intel_engine_get_seqno(engine)); 570 571 GEM_BUG_ON(!irqs_disabled()); 572 lockdep_assert_held(&engine->timeline.lock); 573 574 /* 575 * Only unwind in reverse order, required so that the per-context list 576 * is kept in seqno/ring order. 577 */ 578 GEM_BUG_ON(!request->global_seqno); 579 GEM_BUG_ON(request->global_seqno != engine->timeline.seqno); 580 GEM_BUG_ON(i915_seqno_passed(intel_engine_get_seqno(engine), 581 request->global_seqno)); 582 engine->timeline.seqno--; 583 584 /* We may be recursing from the signal callback of another i915 fence */ 585 spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING); 586 request->global_seqno = 0; 587 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags)) 588 intel_engine_cancel_signaling(request); 589 spin_unlock(&request->lock); 590 591 /* Transfer back from the global per-engine timeline to per-context */ 592 move_to_timeline(request, request->timeline); 593 594 /* 595 * We don't need to wake_up any waiters on request->execute, they 596 * will get woken by any other event or us re-adding this request 597 * to the engine timeline (__i915_request_submit()). The waiters 598 * should be quite adapt at finding that the request now has a new 599 * global_seqno to the one they went to sleep on. 600 */ 601 } 602 603 void i915_request_unsubmit(struct i915_request *request) 604 { 605 struct intel_engine_cs *engine = request->engine; 606 unsigned long flags; 607 608 /* Will be called from irq-context when using foreign fences. */ 609 spin_lock_irqsave(&engine->timeline.lock, flags); 610 611 __i915_request_unsubmit(request); 612 613 spin_unlock_irqrestore(&engine->timeline.lock, flags); 614 } 615 616 static int __i915_sw_fence_call 617 submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) 618 { 619 struct i915_request *request = 620 container_of(fence, typeof(*request), submit); 621 622 switch (state) { 623 case FENCE_COMPLETE: 624 trace_i915_request_submit(request); 625 /* 626 * We need to serialize use of the submit_request() callback 627 * with its hotplugging performed during an emergency 628 * i915_gem_set_wedged(). We use the RCU mechanism to mark the 629 * critical section in order to force i915_gem_set_wedged() to 630 * wait until the submit_request() is completed before 631 * proceeding. 632 */ 633 rcu_read_lock(); 634 request->engine->submit_request(request); 635 rcu_read_unlock(); 636 break; 637 638 case FENCE_FREE: 639 i915_request_put(request); 640 break; 641 } 642 643 return NOTIFY_DONE; 644 } 645 646 /** 647 * i915_request_alloc - allocate a request structure 648 * 649 * @engine: engine that we wish to issue the request on. 650 * @ctx: context that the request will be associated with. 651 * 652 * Returns a pointer to the allocated request if successful, 653 * or an error code if not. 654 */ 655 struct i915_request * 656 i915_request_alloc(struct intel_engine_cs *engine, struct i915_gem_context *ctx) 657 { 658 struct drm_i915_private *i915 = engine->i915; 659 struct i915_request *rq; 660 struct intel_ring *ring; 661 int ret; 662 663 lockdep_assert_held(&i915->drm.struct_mutex); 664 665 /* 666 * Preempt contexts are reserved for exclusive use to inject a 667 * preemption context switch. They are never to be used for any trivial 668 * request! 669 */ 670 GEM_BUG_ON(ctx == i915->preempt_context); 671 672 /* 673 * ABI: Before userspace accesses the GPU (e.g. execbuffer), report 674 * EIO if the GPU is already wedged. 675 */ 676 if (i915_terminally_wedged(&i915->gpu_error)) 677 return ERR_PTR(-EIO); 678 679 /* 680 * Pinning the contexts may generate requests in order to acquire 681 * GGTT space, so do this first before we reserve a seqno for 682 * ourselves. 683 */ 684 ring = intel_context_pin(ctx, engine); 685 if (IS_ERR(ring)) 686 return ERR_CAST(ring); 687 GEM_BUG_ON(!ring); 688 689 ret = reserve_gt(i915); 690 if (ret) 691 goto err_unpin; 692 693 ret = intel_ring_wait_for_space(ring, MIN_SPACE_FOR_ADD_REQUEST); 694 if (ret) 695 goto err_unreserve; 696 697 /* Move our oldest request to the slab-cache (if not in use!) */ 698 rq = list_first_entry(&ring->request_list, typeof(*rq), ring_link); 699 if (!list_is_last(&rq->ring_link, &ring->request_list) && 700 i915_request_completed(rq)) 701 i915_request_retire(rq); 702 703 /* 704 * Beware: Dragons be flying overhead. 705 * 706 * We use RCU to look up requests in flight. The lookups may 707 * race with the request being allocated from the slab freelist. 708 * That is the request we are writing to here, may be in the process 709 * of being read by __i915_gem_active_get_rcu(). As such, 710 * we have to be very careful when overwriting the contents. During 711 * the RCU lookup, we change chase the request->engine pointer, 712 * read the request->global_seqno and increment the reference count. 713 * 714 * The reference count is incremented atomically. If it is zero, 715 * the lookup knows the request is unallocated and complete. Otherwise, 716 * it is either still in use, or has been reallocated and reset 717 * with dma_fence_init(). This increment is safe for release as we 718 * check that the request we have a reference to and matches the active 719 * request. 720 * 721 * Before we increment the refcount, we chase the request->engine 722 * pointer. We must not call kmem_cache_zalloc() or else we set 723 * that pointer to NULL and cause a crash during the lookup. If 724 * we see the request is completed (based on the value of the 725 * old engine and seqno), the lookup is complete and reports NULL. 726 * If we decide the request is not completed (new engine or seqno), 727 * then we grab a reference and double check that it is still the 728 * active request - which it won't be and restart the lookup. 729 * 730 * Do not use kmem_cache_zalloc() here! 731 */ 732 rq = kmem_cache_alloc(i915->requests, 733 GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN); 734 if (unlikely(!rq)) { 735 /* Ratelimit ourselves to prevent oom from malicious clients */ 736 ret = i915_gem_wait_for_idle(i915, 737 I915_WAIT_LOCKED | 738 I915_WAIT_INTERRUPTIBLE); 739 if (ret) 740 goto err_unreserve; 741 742 /* 743 * We've forced the client to stall and catch up with whatever 744 * backlog there might have been. As we are assuming that we 745 * caused the mempressure, now is an opportune time to 746 * recover as much memory from the request pool as is possible. 747 * Having already penalized the client to stall, we spend 748 * a little extra time to re-optimise page allocation. 749 */ 750 kmem_cache_shrink(i915->requests); 751 rcu_barrier(); /* Recover the TYPESAFE_BY_RCU pages */ 752 753 rq = kmem_cache_alloc(i915->requests, GFP_KERNEL); 754 if (!rq) { 755 ret = -ENOMEM; 756 goto err_unreserve; 757 } 758 } 759 760 INIT_LIST_HEAD(&rq->active_list); 761 rq->i915 = i915; 762 rq->engine = engine; 763 rq->ctx = ctx; 764 rq->ring = ring; 765 rq->timeline = ring->timeline; 766 GEM_BUG_ON(rq->timeline == &engine->timeline); 767 768 spin_lock_init(&rq->lock); 769 dma_fence_init(&rq->fence, 770 &i915_fence_ops, 771 &rq->lock, 772 rq->timeline->fence_context, 773 timeline_get_seqno(rq->timeline)); 774 775 /* We bump the ref for the fence chain */ 776 i915_sw_fence_init(&i915_request_get(rq)->submit, submit_notify); 777 init_waitqueue_head(&rq->execute); 778 779 i915_sched_node_init(&rq->sched); 780 781 /* No zalloc, must clear what we need by hand */ 782 rq->global_seqno = 0; 783 rq->signaling.wait.seqno = 0; 784 rq->file_priv = NULL; 785 rq->batch = NULL; 786 rq->capture_list = NULL; 787 rq->waitboost = false; 788 789 /* 790 * Reserve space in the ring buffer for all the commands required to 791 * eventually emit this request. This is to guarantee that the 792 * i915_request_add() call can't fail. Note that the reserve may need 793 * to be redone if the request is not actually submitted straight 794 * away, e.g. because a GPU scheduler has deferred it. 795 */ 796 rq->reserved_space = MIN_SPACE_FOR_ADD_REQUEST; 797 GEM_BUG_ON(rq->reserved_space < engine->emit_breadcrumb_sz); 798 799 /* 800 * Record the position of the start of the request so that 801 * should we detect the updated seqno part-way through the 802 * GPU processing the request, we never over-estimate the 803 * position of the head. 804 */ 805 rq->head = rq->ring->emit; 806 807 /* Unconditionally invalidate GPU caches and TLBs. */ 808 ret = engine->emit_flush(rq, EMIT_INVALIDATE); 809 if (ret) 810 goto err_unwind; 811 812 ret = engine->request_alloc(rq); 813 if (ret) 814 goto err_unwind; 815 816 /* Keep a second pin for the dual retirement along engine and ring */ 817 __intel_context_pin(rq->ctx, engine); 818 819 /* Check that we didn't interrupt ourselves with a new request */ 820 GEM_BUG_ON(rq->timeline->seqno != rq->fence.seqno); 821 return rq; 822 823 err_unwind: 824 rq->ring->emit = rq->head; 825 826 /* Make sure we didn't add ourselves to external state before freeing */ 827 GEM_BUG_ON(!list_empty(&rq->active_list)); 828 GEM_BUG_ON(!list_empty(&rq->sched.signalers_list)); 829 GEM_BUG_ON(!list_empty(&rq->sched.waiters_list)); 830 831 kmem_cache_free(i915->requests, rq); 832 err_unreserve: 833 unreserve_gt(i915); 834 err_unpin: 835 intel_context_unpin(ctx, engine); 836 return ERR_PTR(ret); 837 } 838 839 static int 840 i915_request_await_request(struct i915_request *to, struct i915_request *from) 841 { 842 int ret; 843 844 GEM_BUG_ON(to == from); 845 GEM_BUG_ON(to->timeline == from->timeline); 846 847 if (i915_request_completed(from)) 848 return 0; 849 850 if (to->engine->schedule) { 851 ret = i915_sched_node_add_dependency(to->i915, 852 &to->sched, 853 &from->sched); 854 if (ret < 0) 855 return ret; 856 } 857 858 if (to->engine == from->engine) { 859 ret = i915_sw_fence_await_sw_fence_gfp(&to->submit, 860 &from->submit, 861 I915_FENCE_GFP); 862 return ret < 0 ? ret : 0; 863 } 864 865 if (to->engine->semaphore.sync_to) { 866 u32 seqno; 867 868 GEM_BUG_ON(!from->engine->semaphore.signal); 869 870 seqno = i915_request_global_seqno(from); 871 if (!seqno) 872 goto await_dma_fence; 873 874 if (seqno <= to->timeline->global_sync[from->engine->id]) 875 return 0; 876 877 trace_i915_gem_ring_sync_to(to, from); 878 ret = to->engine->semaphore.sync_to(to, from); 879 if (ret) 880 return ret; 881 882 to->timeline->global_sync[from->engine->id] = seqno; 883 return 0; 884 } 885 886 await_dma_fence: 887 ret = i915_sw_fence_await_dma_fence(&to->submit, 888 &from->fence, 0, 889 I915_FENCE_GFP); 890 return ret < 0 ? ret : 0; 891 } 892 893 int 894 i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence) 895 { 896 struct dma_fence **child = &fence; 897 unsigned int nchild = 1; 898 int ret; 899 900 /* 901 * Note that if the fence-array was created in signal-on-any mode, 902 * we should *not* decompose it into its individual fences. However, 903 * we don't currently store which mode the fence-array is operating 904 * in. Fortunately, the only user of signal-on-any is private to 905 * amdgpu and we should not see any incoming fence-array from 906 * sync-file being in signal-on-any mode. 907 */ 908 if (dma_fence_is_array(fence)) { 909 struct dma_fence_array *array = to_dma_fence_array(fence); 910 911 child = array->fences; 912 nchild = array->num_fences; 913 GEM_BUG_ON(!nchild); 914 } 915 916 do { 917 fence = *child++; 918 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) 919 continue; 920 921 /* 922 * Requests on the same timeline are explicitly ordered, along 923 * with their dependencies, by i915_request_add() which ensures 924 * that requests are submitted in-order through each ring. 925 */ 926 if (fence->context == rq->fence.context) 927 continue; 928 929 /* Squash repeated waits to the same timelines */ 930 if (fence->context != rq->i915->mm.unordered_timeline && 931 i915_timeline_sync_is_later(rq->timeline, fence)) 932 continue; 933 934 if (dma_fence_is_i915(fence)) 935 ret = i915_request_await_request(rq, to_request(fence)); 936 else 937 ret = i915_sw_fence_await_dma_fence(&rq->submit, fence, 938 I915_FENCE_TIMEOUT, 939 I915_FENCE_GFP); 940 if (ret < 0) 941 return ret; 942 943 /* Record the latest fence used against each timeline */ 944 if (fence->context != rq->i915->mm.unordered_timeline) 945 i915_timeline_sync_set(rq->timeline, fence); 946 } while (--nchild); 947 948 return 0; 949 } 950 951 /** 952 * i915_request_await_object - set this request to (async) wait upon a bo 953 * @to: request we are wishing to use 954 * @obj: object which may be in use on another ring. 955 * @write: whether the wait is on behalf of a writer 956 * 957 * This code is meant to abstract object synchronization with the GPU. 958 * Conceptually we serialise writes between engines inside the GPU. 959 * We only allow one engine to write into a buffer at any time, but 960 * multiple readers. To ensure each has a coherent view of memory, we must: 961 * 962 * - If there is an outstanding write request to the object, the new 963 * request must wait for it to complete (either CPU or in hw, requests 964 * on the same ring will be naturally ordered). 965 * 966 * - If we are a write request (pending_write_domain is set), the new 967 * request must wait for outstanding read requests to complete. 968 * 969 * Returns 0 if successful, else propagates up the lower layer error. 970 */ 971 int 972 i915_request_await_object(struct i915_request *to, 973 struct drm_i915_gem_object *obj, 974 bool write) 975 { 976 struct dma_fence *excl; 977 int ret = 0; 978 979 if (write) { 980 struct dma_fence **shared; 981 unsigned int count, i; 982 983 ret = reservation_object_get_fences_rcu(obj->resv, 984 &excl, &count, &shared); 985 if (ret) 986 return ret; 987 988 for (i = 0; i < count; i++) { 989 ret = i915_request_await_dma_fence(to, shared[i]); 990 if (ret) 991 break; 992 993 dma_fence_put(shared[i]); 994 } 995 996 for (; i < count; i++) 997 dma_fence_put(shared[i]); 998 kfree(shared); 999 } else { 1000 excl = reservation_object_get_excl_rcu(obj->resv); 1001 } 1002 1003 if (excl) { 1004 if (ret == 0) 1005 ret = i915_request_await_dma_fence(to, excl); 1006 1007 dma_fence_put(excl); 1008 } 1009 1010 return ret; 1011 } 1012 1013 /* 1014 * NB: This function is not allowed to fail. Doing so would mean the the 1015 * request is not being tracked for completion but the work itself is 1016 * going to happen on the hardware. This would be a Bad Thing(tm). 1017 */ 1018 void __i915_request_add(struct i915_request *request, bool flush_caches) 1019 { 1020 struct intel_engine_cs *engine = request->engine; 1021 struct intel_ring *ring = request->ring; 1022 struct i915_timeline *timeline = request->timeline; 1023 struct i915_request *prev; 1024 u32 *cs; 1025 int err; 1026 1027 GEM_TRACE("%s fence %llx:%d\n", 1028 engine->name, request->fence.context, request->fence.seqno); 1029 1030 lockdep_assert_held(&request->i915->drm.struct_mutex); 1031 trace_i915_request_add(request); 1032 1033 /* 1034 * Make sure that no request gazumped us - if it was allocated after 1035 * our i915_request_alloc() and called __i915_request_add() before 1036 * us, the timeline will hold its seqno which is later than ours. 1037 */ 1038 GEM_BUG_ON(timeline->seqno != request->fence.seqno); 1039 1040 /* 1041 * To ensure that this call will not fail, space for its emissions 1042 * should already have been reserved in the ring buffer. Let the ring 1043 * know that it is time to use that space up. 1044 */ 1045 request->reserved_space = 0; 1046 1047 /* 1048 * Emit any outstanding flushes - execbuf can fail to emit the flush 1049 * after having emitted the batchbuffer command. Hence we need to fix 1050 * things up similar to emitting the lazy request. The difference here 1051 * is that the flush _must_ happen before the next request, no matter 1052 * what. 1053 */ 1054 if (flush_caches) { 1055 err = engine->emit_flush(request, EMIT_FLUSH); 1056 1057 /* Not allowed to fail! */ 1058 WARN(err, "engine->emit_flush() failed: %d!\n", err); 1059 } 1060 1061 /* 1062 * Record the position of the start of the breadcrumb so that 1063 * should we detect the updated seqno part-way through the 1064 * GPU processing the request, we never over-estimate the 1065 * position of the ring's HEAD. 1066 */ 1067 cs = intel_ring_begin(request, engine->emit_breadcrumb_sz); 1068 GEM_BUG_ON(IS_ERR(cs)); 1069 request->postfix = intel_ring_offset(request, cs); 1070 1071 /* 1072 * Seal the request and mark it as pending execution. Note that 1073 * we may inspect this state, without holding any locks, during 1074 * hangcheck. Hence we apply the barrier to ensure that we do not 1075 * see a more recent value in the hws than we are tracking. 1076 */ 1077 1078 prev = i915_gem_active_raw(&timeline->last_request, 1079 &request->i915->drm.struct_mutex); 1080 if (prev && !i915_request_completed(prev)) { 1081 i915_sw_fence_await_sw_fence(&request->submit, &prev->submit, 1082 &request->submitq); 1083 if (engine->schedule) 1084 __i915_sched_node_add_dependency(&request->sched, 1085 &prev->sched, 1086 &request->dep, 1087 0); 1088 } 1089 1090 spin_lock_irq(&timeline->lock); 1091 list_add_tail(&request->link, &timeline->requests); 1092 spin_unlock_irq(&timeline->lock); 1093 1094 GEM_BUG_ON(timeline->seqno != request->fence.seqno); 1095 i915_gem_active_set(&timeline->last_request, request); 1096 1097 list_add_tail(&request->ring_link, &ring->request_list); 1098 if (list_is_first(&request->ring_link, &ring->request_list)) 1099 list_add(&ring->active_link, &request->i915->gt.active_rings); 1100 request->emitted_jiffies = jiffies; 1101 1102 /* 1103 * Let the backend know a new request has arrived that may need 1104 * to adjust the existing execution schedule due to a high priority 1105 * request - i.e. we may want to preempt the current request in order 1106 * to run a high priority dependency chain *before* we can execute this 1107 * request. 1108 * 1109 * This is called before the request is ready to run so that we can 1110 * decide whether to preempt the entire chain so that it is ready to 1111 * run at the earliest possible convenience. 1112 */ 1113 local_bh_disable(); 1114 rcu_read_lock(); /* RCU serialisation for set-wedged protection */ 1115 if (engine->schedule) 1116 engine->schedule(request, &request->ctx->sched); 1117 rcu_read_unlock(); 1118 i915_sw_fence_commit(&request->submit); 1119 local_bh_enable(); /* Kick the execlists tasklet if just scheduled */ 1120 1121 /* 1122 * In typical scenarios, we do not expect the previous request on 1123 * the timeline to be still tracked by timeline->last_request if it 1124 * has been completed. If the completed request is still here, that 1125 * implies that request retirement is a long way behind submission, 1126 * suggesting that we haven't been retiring frequently enough from 1127 * the combination of retire-before-alloc, waiters and the background 1128 * retirement worker. So if the last request on this timeline was 1129 * already completed, do a catch up pass, flushing the retirement queue 1130 * up to this client. Since we have now moved the heaviest operations 1131 * during retirement onto secondary workers, such as freeing objects 1132 * or contexts, retiring a bunch of requests is mostly list management 1133 * (and cache misses), and so we should not be overly penalizing this 1134 * client by performing excess work, though we may still performing 1135 * work on behalf of others -- but instead we should benefit from 1136 * improved resource management. (Well, that's the theory at least.) 1137 */ 1138 if (prev && i915_request_completed(prev)) 1139 i915_request_retire_upto(prev); 1140 } 1141 1142 static unsigned long local_clock_us(unsigned int *cpu) 1143 { 1144 unsigned long t; 1145 1146 /* 1147 * Cheaply and approximately convert from nanoseconds to microseconds. 1148 * The result and subsequent calculations are also defined in the same 1149 * approximate microseconds units. The principal source of timing 1150 * error here is from the simple truncation. 1151 * 1152 * Note that local_clock() is only defined wrt to the current CPU; 1153 * the comparisons are no longer valid if we switch CPUs. Instead of 1154 * blocking preemption for the entire busywait, we can detect the CPU 1155 * switch and use that as indicator of system load and a reason to 1156 * stop busywaiting, see busywait_stop(). 1157 */ 1158 *cpu = get_cpu(); 1159 t = local_clock() >> 10; 1160 put_cpu(); 1161 1162 return t; 1163 } 1164 1165 static bool busywait_stop(unsigned long timeout, unsigned int cpu) 1166 { 1167 unsigned int this_cpu; 1168 1169 if (time_after(local_clock_us(&this_cpu), timeout)) 1170 return true; 1171 1172 return this_cpu != cpu; 1173 } 1174 1175 static bool __i915_spin_request(const struct i915_request *rq, 1176 u32 seqno, int state, unsigned long timeout_us) 1177 { 1178 struct intel_engine_cs *engine = rq->engine; 1179 unsigned int irq, cpu; 1180 1181 GEM_BUG_ON(!seqno); 1182 1183 /* 1184 * Only wait for the request if we know it is likely to complete. 1185 * 1186 * We don't track the timestamps around requests, nor the average 1187 * request length, so we do not have a good indicator that this 1188 * request will complete within the timeout. What we do know is the 1189 * order in which requests are executed by the engine and so we can 1190 * tell if the request has started. If the request hasn't started yet, 1191 * it is a fair assumption that it will not complete within our 1192 * relatively short timeout. 1193 */ 1194 if (!i915_seqno_passed(intel_engine_get_seqno(engine), seqno - 1)) 1195 return false; 1196 1197 /* 1198 * When waiting for high frequency requests, e.g. during synchronous 1199 * rendering split between the CPU and GPU, the finite amount of time 1200 * required to set up the irq and wait upon it limits the response 1201 * rate. By busywaiting on the request completion for a short while we 1202 * can service the high frequency waits as quick as possible. However, 1203 * if it is a slow request, we want to sleep as quickly as possible. 1204 * The tradeoff between waiting and sleeping is roughly the time it 1205 * takes to sleep on a request, on the order of a microsecond. 1206 */ 1207 1208 irq = atomic_read(&engine->irq_count); 1209 timeout_us += local_clock_us(&cpu); 1210 do { 1211 if (i915_seqno_passed(intel_engine_get_seqno(engine), seqno)) 1212 return seqno == i915_request_global_seqno(rq); 1213 1214 /* 1215 * Seqno are meant to be ordered *before* the interrupt. If 1216 * we see an interrupt without a corresponding seqno advance, 1217 * assume we won't see one in the near future but require 1218 * the engine->seqno_barrier() to fixup coherency. 1219 */ 1220 if (atomic_read(&engine->irq_count) != irq) 1221 break; 1222 1223 if (signal_pending_state(state, current)) 1224 break; 1225 1226 if (busywait_stop(timeout_us, cpu)) 1227 break; 1228 1229 cpu_relax(); 1230 } while (!need_resched()); 1231 1232 return false; 1233 } 1234 1235 static bool __i915_wait_request_check_and_reset(struct i915_request *request) 1236 { 1237 struct i915_gpu_error *error = &request->i915->gpu_error; 1238 1239 if (likely(!i915_reset_handoff(error))) 1240 return false; 1241 1242 __set_current_state(TASK_RUNNING); 1243 i915_reset(request->i915, error->stalled_mask, error->reason); 1244 return true; 1245 } 1246 1247 /** 1248 * i915_request_wait - wait until execution of request has finished 1249 * @rq: the request to wait upon 1250 * @flags: how to wait 1251 * @timeout: how long to wait in jiffies 1252 * 1253 * i915_request_wait() waits for the request to be completed, for a 1254 * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an 1255 * unbounded wait). 1256 * 1257 * If the caller holds the struct_mutex, the caller must pass I915_WAIT_LOCKED 1258 * in via the flags, and vice versa if the struct_mutex is not held, the caller 1259 * must not specify that the wait is locked. 1260 * 1261 * Returns the remaining time (in jiffies) if the request completed, which may 1262 * be zero or -ETIME if the request is unfinished after the timeout expires. 1263 * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is 1264 * pending before the request completes. 1265 */ 1266 long i915_request_wait(struct i915_request *rq, 1267 unsigned int flags, 1268 long timeout) 1269 { 1270 const int state = flags & I915_WAIT_INTERRUPTIBLE ? 1271 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE; 1272 wait_queue_head_t *errq = &rq->i915->gpu_error.wait_queue; 1273 DEFINE_WAIT_FUNC(reset, default_wake_function); 1274 DEFINE_WAIT_FUNC(exec, default_wake_function); 1275 struct intel_wait wait; 1276 1277 might_sleep(); 1278 #if IS_ENABLED(CONFIG_LOCKDEP) 1279 GEM_BUG_ON(debug_locks && 1280 !!lockdep_is_held(&rq->i915->drm.struct_mutex) != 1281 !!(flags & I915_WAIT_LOCKED)); 1282 #endif 1283 GEM_BUG_ON(timeout < 0); 1284 1285 if (i915_request_completed(rq)) 1286 return timeout; 1287 1288 if (!timeout) 1289 return -ETIME; 1290 1291 trace_i915_request_wait_begin(rq, flags); 1292 1293 add_wait_queue(&rq->execute, &exec); 1294 if (flags & I915_WAIT_LOCKED) 1295 add_wait_queue(errq, &reset); 1296 1297 intel_wait_init(&wait, rq); 1298 1299 restart: 1300 do { 1301 set_current_state(state); 1302 if (intel_wait_update_request(&wait, rq)) 1303 break; 1304 1305 if (flags & I915_WAIT_LOCKED && 1306 __i915_wait_request_check_and_reset(rq)) 1307 continue; 1308 1309 if (signal_pending_state(state, current)) { 1310 timeout = -ERESTARTSYS; 1311 goto complete; 1312 } 1313 1314 if (!timeout) { 1315 timeout = -ETIME; 1316 goto complete; 1317 } 1318 1319 timeout = io_schedule_timeout(timeout); 1320 } while (1); 1321 1322 GEM_BUG_ON(!intel_wait_has_seqno(&wait)); 1323 GEM_BUG_ON(!i915_sw_fence_signaled(&rq->submit)); 1324 1325 /* Optimistic short spin before touching IRQs */ 1326 if (__i915_spin_request(rq, wait.seqno, state, 5)) 1327 goto complete; 1328 1329 set_current_state(state); 1330 if (intel_engine_add_wait(rq->engine, &wait)) 1331 /* 1332 * In order to check that we haven't missed the interrupt 1333 * as we enabled it, we need to kick ourselves to do a 1334 * coherent check on the seqno before we sleep. 1335 */ 1336 goto wakeup; 1337 1338 if (flags & I915_WAIT_LOCKED) 1339 __i915_wait_request_check_and_reset(rq); 1340 1341 for (;;) { 1342 if (signal_pending_state(state, current)) { 1343 timeout = -ERESTARTSYS; 1344 break; 1345 } 1346 1347 if (!timeout) { 1348 timeout = -ETIME; 1349 break; 1350 } 1351 1352 timeout = io_schedule_timeout(timeout); 1353 1354 if (intel_wait_complete(&wait) && 1355 intel_wait_check_request(&wait, rq)) 1356 break; 1357 1358 set_current_state(state); 1359 1360 wakeup: 1361 /* 1362 * Carefully check if the request is complete, giving time 1363 * for the seqno to be visible following the interrupt. 1364 * We also have to check in case we are kicked by the GPU 1365 * reset in order to drop the struct_mutex. 1366 */ 1367 if (__i915_request_irq_complete(rq)) 1368 break; 1369 1370 /* 1371 * If the GPU is hung, and we hold the lock, reset the GPU 1372 * and then check for completion. On a full reset, the engine's 1373 * HW seqno will be advanced passed us and we are complete. 1374 * If we do a partial reset, we have to wait for the GPU to 1375 * resume and update the breadcrumb. 1376 * 1377 * If we don't hold the mutex, we can just wait for the worker 1378 * to come along and update the breadcrumb (either directly 1379 * itself, or indirectly by recovering the GPU). 1380 */ 1381 if (flags & I915_WAIT_LOCKED && 1382 __i915_wait_request_check_and_reset(rq)) 1383 continue; 1384 1385 /* Only spin if we know the GPU is processing this request */ 1386 if (__i915_spin_request(rq, wait.seqno, state, 2)) 1387 break; 1388 1389 if (!intel_wait_check_request(&wait, rq)) { 1390 intel_engine_remove_wait(rq->engine, &wait); 1391 goto restart; 1392 } 1393 } 1394 1395 intel_engine_remove_wait(rq->engine, &wait); 1396 complete: 1397 __set_current_state(TASK_RUNNING); 1398 if (flags & I915_WAIT_LOCKED) 1399 remove_wait_queue(errq, &reset); 1400 remove_wait_queue(&rq->execute, &exec); 1401 trace_i915_request_wait_end(rq); 1402 1403 return timeout; 1404 } 1405 1406 static void ring_retire_requests(struct intel_ring *ring) 1407 { 1408 struct i915_request *request, *next; 1409 1410 list_for_each_entry_safe(request, next, 1411 &ring->request_list, ring_link) { 1412 if (!i915_request_completed(request)) 1413 break; 1414 1415 i915_request_retire(request); 1416 } 1417 } 1418 1419 void i915_retire_requests(struct drm_i915_private *i915) 1420 { 1421 struct intel_ring *ring, *tmp; 1422 1423 lockdep_assert_held(&i915->drm.struct_mutex); 1424 1425 if (!i915->gt.active_requests) 1426 return; 1427 1428 list_for_each_entry_safe(ring, tmp, &i915->gt.active_rings, active_link) 1429 ring_retire_requests(ring); 1430 } 1431 1432 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 1433 #include "selftests/mock_request.c" 1434 #include "selftests/i915_request.c" 1435 #endif 1436