1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef __I915_REG_DEFS__ 7 #define __I915_REG_DEFS__ 8 9 #include <drm/intel/pick.h> 10 #include <drm/intel/reg_bits.h> 11 12 typedef struct { 13 u32 reg; 14 } i915_reg_t; 15 16 #define _MMIO(r) ((const i915_reg_t){ .reg = (r) }) 17 18 typedef struct { 19 u32 reg; 20 } i915_mcr_reg_t; 21 22 #define MCR_REG(offset) ((const i915_mcr_reg_t){ .reg = (offset) }) 23 24 #define INVALID_MMIO_REG _MMIO(0) 25 26 /* 27 * These macros can be used on either i915_reg_t or i915_mcr_reg_t since they're 28 * simply operations on the register's offset and don't care about the MCR vs 29 * non-MCR nature of the register. 30 */ 31 #define i915_mmio_reg_offset(r) \ 32 _Generic((r), i915_reg_t: (r).reg, i915_mcr_reg_t: (r).reg) 33 #define i915_mmio_reg_equal(a, b) (i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b)) 34 #define i915_mmio_reg_valid(r) (!i915_mmio_reg_equal(r, INVALID_MMIO_REG)) 35 36 /* A triplet for IMR/IER/IIR registers. */ 37 struct i915_irq_regs { 38 i915_reg_t imr; 39 i915_reg_t ier; 40 i915_reg_t iir; 41 }; 42 43 #define I915_IRQ_REGS(_imr, _ier, _iir) \ 44 ((const struct i915_irq_regs){ .imr = (_imr), .ier = (_ier), .iir = (_iir) }) 45 46 struct i915_error_regs { 47 i915_reg_t emr; 48 i915_reg_t eir; 49 }; 50 51 #define I915_ERROR_REGS(_emr, _eir) \ 52 ((const struct i915_error_regs){ .emr = (_emr), .eir = (_eir) }) 53 54 #endif /* __I915_REG_DEFS__ */ 55