1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 2 * All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef _I915_REG_H_ 26 #define _I915_REG_H_ 27 28 #include "i915_reg_defs.h" 29 #include "display/intel_display_reg_defs.h" 30 31 /** 32 * DOC: The i915 register macro definition style guide 33 * 34 * Follow the style described here for new macros, and while changing existing 35 * macros. Do **not** mass change existing definitions just to update the style. 36 * 37 * File Layout 38 * ~~~~~~~~~~~ 39 * 40 * Keep helper macros near the top. For example, _PIPE() and friends. 41 * 42 * Prefix macros that generally should not be used outside of this file with 43 * underscore '_'. For example, _PIPE() and friends, single instances of 44 * registers that are defined solely for the use by function-like macros. 45 * 46 * Avoid using the underscore prefixed macros outside of this file. There are 47 * exceptions, but keep them to a minimum. 48 * 49 * There are two basic types of register definitions: Single registers and 50 * register groups. Register groups are registers which have two or more 51 * instances, for example one per pipe, port, transcoder, etc. Register groups 52 * should be defined using function-like macros. 53 * 54 * For single registers, define the register offset first, followed by register 55 * contents. 56 * 57 * For register groups, define the register instance offsets first, prefixed 58 * with underscore, followed by a function-like macro choosing the right 59 * instance based on the parameter, followed by register contents. 60 * 61 * Define the register contents (i.e. bit and bit field macros) from most 62 * significant to least significant bit. Indent the register content macros 63 * using two extra spaces between ``#define`` and the macro name. 64 * 65 * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents 66 * using ``REG_FIELD_PREP(mask, value)``. This will define the values already 67 * shifted in place, so they can be directly OR'd together. For convenience, 68 * function-like macros may be used to define bit fields, but do note that the 69 * macros may be needed to read as well as write the register contents. 70 * 71 * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name. 72 * 73 * Group the register and its contents together without blank lines, separate 74 * from other registers and their contents with one blank line. 75 * 76 * Indent macro values from macro names using TABs. Align values vertically. Use 77 * braces in macro values as needed to avoid unintended precedence after macro 78 * substitution. Use spaces in macro values according to kernel coding 79 * style. Use lower case in hexadecimal values. 80 * 81 * Naming 82 * ~~~~~~ 83 * 84 * Try to name registers according to the specs. If the register name changes in 85 * the specs from platform to another, stick to the original name. 86 * 87 * Try to re-use existing register macro definitions. Only add new macros for 88 * new register offsets, or when the register contents have changed enough to 89 * warrant a full redefinition. 90 * 91 * When a register macro changes for a new platform, prefix the new macro using 92 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The 93 * prefix signifies the start platform/generation using the register. 94 * 95 * When a bit (field) macro changes or gets added for a new platform, while 96 * retaining the existing register macro, add a platform acronym or generation 97 * suffix to the name. For example, ``_SKL`` or ``_GEN8``. 98 * 99 * Examples 100 * ~~~~~~~~ 101 * 102 * (Note that the values in the example are indented using spaces instead of 103 * TABs to avoid misalignment in generated documentation. Use TABs in the 104 * definitions.):: 105 * 106 * #define _FOO_A 0xf000 107 * #define _FOO_B 0xf001 108 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B) 109 * #define FOO_ENABLE REG_BIT(31) 110 * #define FOO_MODE_MASK REG_GENMASK(19, 16) 111 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0) 112 * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1) 113 * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2) 114 * 115 * #define BAR _MMIO(0xb000) 116 * #define GEN8_BAR _MMIO(0xb888) 117 */ 118 119 #define GU_CNTL_PROTECTED _MMIO(0x10100C) 120 #define DEPRESENT REG_BIT(9) 121 122 #define GU_CNTL _MMIO(0x101010) 123 #define LMEM_INIT REG_BIT(7) 124 #define DRIVERFLR REG_BIT(31) 125 #define GU_DEBUG _MMIO(0x101018) 126 #define DRIVERFLR_STATUS REG_BIT(31) 127 128 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0) 129 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20) 130 #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18) 131 #define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4) 132 #define GEN6_STOLEN_RESERVED_1M (0 << 4) 133 #define GEN6_STOLEN_RESERVED_512K (1 << 4) 134 #define GEN6_STOLEN_RESERVED_256K (2 << 4) 135 #define GEN6_STOLEN_RESERVED_128K (3 << 4) 136 #define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5) 137 #define GEN7_STOLEN_RESERVED_1M (0 << 5) 138 #define GEN7_STOLEN_RESERVED_256K (1 << 5) 139 #define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7) 140 #define GEN8_STOLEN_RESERVED_1M (0 << 7) 141 #define GEN8_STOLEN_RESERVED_2M (1 << 7) 142 #define GEN8_STOLEN_RESERVED_4M (2 << 7) 143 #define GEN8_STOLEN_RESERVED_8M (3 << 7) 144 #define GEN6_STOLEN_RESERVED_ENABLE (1 << 0) 145 #define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20) 146 147 #define _VGA_MSR_WRITE _MMIO(0x3c2) 148 149 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 150 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 151 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL) 152 153 /* 154 * Reset registers 155 */ 156 #define DEBUG_RESET_I830 _MMIO(0x6070) 157 #define DEBUG_RESET_FULL (1 << 7) 158 #define DEBUG_RESET_RENDER (1 << 8) 159 #define DEBUG_RESET_DISPLAY (1 << 9) 160 161 /* 162 * IOSF sideband 163 */ 164 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100) 165 #define IOSF_DEVFN_SHIFT 24 166 #define IOSF_OPCODE_SHIFT 16 167 #define IOSF_PORT_SHIFT 8 168 #define IOSF_BYTE_ENABLES_SHIFT 4 169 #define IOSF_BAR_SHIFT 1 170 #define IOSF_SB_BUSY (1 << 0) 171 #define IOSF_PORT_BUNIT 0x03 172 #define IOSF_PORT_PUNIT 0x04 173 #define IOSF_PORT_NC 0x11 174 #define IOSF_PORT_DPIO 0x12 175 #define IOSF_PORT_GPIO_NC 0x13 176 #define IOSF_PORT_CCK 0x14 177 #define IOSF_PORT_DPIO_2 0x1a 178 #define IOSF_PORT_FLISDSI 0x1b 179 #define IOSF_PORT_GPIO_SC 0x48 180 #define IOSF_PORT_GPIO_SUS 0xa8 181 #define IOSF_PORT_CCU 0xa9 182 #define CHV_IOSF_PORT_GPIO_N 0x13 183 #define CHV_IOSF_PORT_GPIO_SE 0x48 184 #define CHV_IOSF_PORT_GPIO_E 0xa8 185 #define CHV_IOSF_PORT_GPIO_SW 0xb2 186 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104) 187 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108) 188 189 /* DPIO registers */ 190 #define DPIO_DEVFN 0 191 192 #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110) 193 #define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */ 194 #define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */ 195 #define DPIO_SFR_BYPASS (1 << 1) 196 #define DPIO_CMNRST (1 << 0) 197 198 #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090) 199 #define MIPIO_RST_CTRL (1 << 2) 200 201 #define _BXT_PHY_CTL_DDI_A 0x64C00 202 #define _BXT_PHY_CTL_DDI_B 0x64C10 203 #define _BXT_PHY_CTL_DDI_C 0x64C20 204 #define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10) 205 #define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9) 206 #define BXT_PHY_LANE_ENABLED (1 << 8) 207 #define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \ 208 _BXT_PHY_CTL_DDI_B) 209 210 #define _PHY_CTL_FAMILY_DDI 0x64C90 211 #define _PHY_CTL_FAMILY_EDP 0x64C80 212 #define _PHY_CTL_FAMILY_DDI_C 0x64CA0 213 #define COMMON_RESET_DIS (1 << 31) 214 #define BXT_PHY_CTL_FAMILY(phy) \ 215 _MMIO(_PICK_EVEN_2RANGES(phy, 1, \ 216 _PHY_CTL_FAMILY_DDI, _PHY_CTL_FAMILY_DDI, \ 217 _PHY_CTL_FAMILY_EDP, _PHY_CTL_FAMILY_DDI_C)) 218 219 /* UAIMI scratch pad register 1 */ 220 #define UAIMI_SPR1 _MMIO(0x4F074) 221 /* SKL VccIO mask */ 222 #define SKL_VCCIO_MASK 0x1 223 /* SKL balance leg register */ 224 #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C) 225 /* I_boost values */ 226 #define BALANCE_LEG_SHIFT(port) (8 + 3 * (port)) 227 #define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port))) 228 /* Balance leg disable bits */ 229 #define BALANCE_LEG_DISABLE_SHIFT 23 230 #define BALANCE_LEG_DISABLE(port) (1 << (23 + (port))) 231 232 /* 233 * Fence registers 234 * [0-7] @ 0x2000 gen2,gen3 235 * [8-15] @ 0x3000 945,g33,pnv 236 * 237 * [0-15] @ 0x3000 gen4,gen5 238 * 239 * [0-15] @ 0x100000 gen6,vlv,chv 240 * [0-31] @ 0x100000 gen7+ 241 */ 242 #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4) 243 #define I830_FENCE_START_MASK 0x07f80000 244 #define I830_FENCE_TILING_Y_SHIFT 12 245 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 246 #define I830_FENCE_PITCH_SHIFT 4 247 #define I830_FENCE_REG_VALID (1 << 0) 248 #define I915_FENCE_MAX_PITCH_VAL 4 249 #define I830_FENCE_MAX_PITCH_VAL 6 250 #define I830_FENCE_MAX_SIZE_VAL (1 << 8) 251 252 #define I915_FENCE_START_MASK 0x0ff00000 253 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) 254 255 #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8) 256 #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4) 257 #define I965_FENCE_PITCH_SHIFT 2 258 #define I965_FENCE_TILING_Y_SHIFT 1 259 #define I965_FENCE_REG_VALID (1 << 0) 260 #define I965_FENCE_MAX_PITCH_VAL 0x0400 261 262 #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8) 263 #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4) 264 #define GEN6_FENCE_PITCH_SHIFT 32 265 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 266 267 268 /* control register for cpu gtt access */ 269 #define TILECTL _MMIO(0x101000) 270 #define TILECTL_SWZCTL (1 << 0) 271 #define TILECTL_TLBPF (1 << 1) 272 #define TILECTL_TLB_PREFETCH_DIS (1 << 2) 273 #define TILECTL_BACKSNOOP_DIS (1 << 3) 274 275 /* 276 * Instruction and interrupt control regs 277 */ 278 #define PGTBL_CTL _MMIO(0x02020) 279 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ 280 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ 281 #define PGTBL_ER _MMIO(0x02024) 282 #define PRB0_BASE (0x2030 - 0x30) 283 #define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */ 284 #define PRB2_BASE (0x2050 - 0x30) /* gen3 */ 285 #define SRB0_BASE (0x2100 - 0x30) /* gen2 */ 286 #define SRB1_BASE (0x2110 - 0x30) /* gen2 */ 287 #define SRB2_BASE (0x2120 - 0x30) /* 830 */ 288 #define SRB3_BASE (0x2130 - 0x30) /* 830 */ 289 #define RENDER_RING_BASE 0x02000 290 #define BSD_RING_BASE 0x04000 291 #define GEN6_BSD_RING_BASE 0x12000 292 #define GEN8_BSD2_RING_BASE 0x1c000 293 #define GEN11_BSD_RING_BASE 0x1c0000 294 #define GEN11_BSD2_RING_BASE 0x1c4000 295 #define GEN11_BSD3_RING_BASE 0x1d0000 296 #define GEN11_BSD4_RING_BASE 0x1d4000 297 #define XEHP_BSD5_RING_BASE 0x1e0000 298 #define XEHP_BSD6_RING_BASE 0x1e4000 299 #define XEHP_BSD7_RING_BASE 0x1f0000 300 #define XEHP_BSD8_RING_BASE 0x1f4000 301 #define VEBOX_RING_BASE 0x1a000 302 #define GEN11_VEBOX_RING_BASE 0x1c8000 303 #define GEN11_VEBOX2_RING_BASE 0x1d8000 304 #define XEHP_VEBOX3_RING_BASE 0x1e8000 305 #define XEHP_VEBOX4_RING_BASE 0x1f8000 306 #define MTL_GSC_RING_BASE 0x11a000 307 #define GEN12_COMPUTE0_RING_BASE 0x1a000 308 #define GEN12_COMPUTE1_RING_BASE 0x1c000 309 #define GEN12_COMPUTE2_RING_BASE 0x1e000 310 #define GEN12_COMPUTE3_RING_BASE 0x26000 311 #define BLT_RING_BASE 0x22000 312 #define XEHPC_BCS1_RING_BASE 0x3e0000 313 #define XEHPC_BCS2_RING_BASE 0x3e2000 314 #define XEHPC_BCS3_RING_BASE 0x3e4000 315 #define XEHPC_BCS4_RING_BASE 0x3e6000 316 #define XEHPC_BCS5_RING_BASE 0x3e8000 317 #define XEHPC_BCS6_RING_BASE 0x3ea000 318 #define XEHPC_BCS7_RING_BASE 0x3ec000 319 #define XEHPC_BCS8_RING_BASE 0x3ee000 320 #define DG1_GSC_HECI1_BASE 0x00258000 321 #define DG1_GSC_HECI2_BASE 0x00259000 322 #define DG2_GSC_HECI1_BASE 0x00373000 323 #define DG2_GSC_HECI2_BASE 0x00374000 324 #define MTL_GSC_HECI1_BASE 0x00116000 325 #define MTL_GSC_HECI2_BASE 0x00117000 326 327 #define HECI_H_CSR(base) _MMIO((base) + 0x4) 328 #define HECI_H_CSR_IE REG_BIT(0) 329 #define HECI_H_CSR_IS REG_BIT(1) 330 #define HECI_H_CSR_IG REG_BIT(2) 331 #define HECI_H_CSR_RDY REG_BIT(3) 332 #define HECI_H_CSR_RST REG_BIT(4) 333 334 #define HECI_H_GS1(base) _MMIO((base) + 0xc4c) 335 #define HECI_H_GS1_ER_PREP REG_BIT(0) 336 337 /* 338 * The FWSTS register values are FW defined and can be different between 339 * HECI1 and HECI2 340 */ 341 #define HECI_FWSTS1 0xc40 342 #define HECI1_FWSTS1_CURRENT_STATE REG_GENMASK(3, 0) 343 #define HECI1_FWSTS1_CURRENT_STATE_RESET 0 344 #define HECI1_FWSTS1_PROXY_STATE_NORMAL 5 345 #define HECI1_FWSTS1_INIT_COMPLETE REG_BIT(9) 346 #define HECI_FWSTS2 0xc48 347 #define HECI_FWSTS3 0xc60 348 #define HECI_FWSTS4 0xc64 349 #define HECI_FWSTS5 0xc68 350 #define HECI1_FWSTS5_HUC_AUTH_DONE (1 << 19) 351 #define HECI_FWSTS6 0xc6c 352 353 /* the FWSTS regs are 1-based, so we use -base for index 0 to get an invalid reg */ 354 #define HECI_FWSTS(base, x) _MMIO((base) + _PICK(x, -(base), \ 355 HECI_FWSTS1, \ 356 HECI_FWSTS2, \ 357 HECI_FWSTS3, \ 358 HECI_FWSTS4, \ 359 HECI_FWSTS5, \ 360 HECI_FWSTS6)) 361 362 #define HSW_GTT_CACHE_EN _MMIO(0x4024) 363 #define GTT_CACHE_EN_ALL 0xF0007FFF 364 #define GEN7_WR_WATERMARK _MMIO(0x4028) 365 #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C) 366 #define ARB_MODE _MMIO(0x4030) 367 #define ARB_MODE_SWIZZLE_SNB (1 << 4) 368 #define ARB_MODE_SWIZZLE_IVB (1 << 5) 369 #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034) 370 #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038) 371 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ 372 #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4) 373 #define GEN7_LRA_LIMITS_REG_NUM 13 374 #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070) 375 #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074) 376 377 #define GEN7_ERR_INT _MMIO(0x44040) 378 #define ERR_INT_POISON (1 << 31) 379 #define ERR_INT_MMIO_UNCLAIMED (1 << 13) 380 #define ERR_INT_PIPE_CRC_DONE_C (1 << 8) 381 #define ERR_INT_FIFO_UNDERRUN_C (1 << 6) 382 #define ERR_INT_PIPE_CRC_DONE_B (1 << 5) 383 #define ERR_INT_FIFO_UNDERRUN_B (1 << 3) 384 #define ERR_INT_PIPE_CRC_DONE_A (1 << 2) 385 #define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3)) 386 #define ERR_INT_FIFO_UNDERRUN_A (1 << 0) 387 #define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) 388 389 #define FPGA_DBG _MMIO(0x42300) 390 #define FPGA_DBG_RM_NOCLAIM REG_BIT(31) 391 392 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028) 393 #define CLAIM_ER_CLR REG_BIT(31) 394 #define CLAIM_ER_OVERFLOW REG_BIT(16) 395 #define CLAIM_ER_CTR_MASK REG_GENMASK(15, 0) 396 397 #define DERRMR _MMIO(0x44050) 398 /* Note that HBLANK events are reserved on bdw+ */ 399 #define DERRMR_PIPEA_SCANLINE (1 << 0) 400 #define DERRMR_PIPEA_PRI_FLIP_DONE (1 << 1) 401 #define DERRMR_PIPEA_SPR_FLIP_DONE (1 << 2) 402 #define DERRMR_PIPEA_VBLANK (1 << 3) 403 #define DERRMR_PIPEA_HBLANK (1 << 5) 404 #define DERRMR_PIPEB_SCANLINE (1 << 8) 405 #define DERRMR_PIPEB_PRI_FLIP_DONE (1 << 9) 406 #define DERRMR_PIPEB_SPR_FLIP_DONE (1 << 10) 407 #define DERRMR_PIPEB_VBLANK (1 << 11) 408 #define DERRMR_PIPEB_HBLANK (1 << 13) 409 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */ 410 #define DERRMR_PIPEC_SCANLINE (1 << 14) 411 #define DERRMR_PIPEC_PRI_FLIP_DONE (1 << 15) 412 #define DERRMR_PIPEC_SPR_FLIP_DONE (1 << 20) 413 #define DERRMR_PIPEC_VBLANK (1 << 21) 414 #define DERRMR_PIPEC_HBLANK (1 << 22) 415 416 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030) 417 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034) 418 #define SCPD0 _MMIO(0x209c) /* 915+ only */ 419 #define SCPD_FBC_IGNORE_3D (1 << 6) 420 #define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5) 421 #define GEN2_IER _MMIO(0x20a0) 422 #define GEN2_IIR _MMIO(0x20a4) 423 #define GEN2_IMR _MMIO(0x20a8) 424 #define GEN2_ISR _MMIO(0x20ac) 425 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060) 426 #define GINT_DIS (1 << 22) 427 #define GCFG_DIS (1 << 8) 428 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064) 429 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084) 430 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0) 431 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4) 432 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8) 433 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac) 434 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120) 435 #define VLV_PCBR_ADDR_SHIFT 12 436 437 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */ 438 #define EIR _MMIO(0x20b0) 439 #define EMR _MMIO(0x20b4) 440 #define ESR _MMIO(0x20b8) 441 #define GM45_ERROR_PAGE_TABLE (1 << 5) 442 #define GM45_ERROR_MEM_PRIV (1 << 4) 443 #define I915_ERROR_PAGE_TABLE (1 << 4) 444 #define GM45_ERROR_CP_PRIV (1 << 3) 445 #define I915_ERROR_MEMORY_REFRESH (1 << 1) 446 #define I915_ERROR_INSTRUCTION (1 << 0) 447 #define INSTPM _MMIO(0x20c0) 448 #define INSTPM_SELF_EN (1 << 12) /* 915GM only */ 449 #define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts 450 will not assert AGPBUSY# and will only 451 be delivered when out of C3. */ 452 #define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */ 453 #define INSTPM_TLB_INVALIDATE (1 << 9) 454 #define INSTPM_SYNC_FLUSH (1 << 5) 455 #define MEM_MODE _MMIO(0x20cc) 456 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */ 457 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */ 458 #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */ 459 #define FW_BLC _MMIO(0x20d8) 460 #define FW_BLC2 _MMIO(0x20dc) 461 #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */ 462 #define FW_BLC_SELF_EN_MASK (1 << 31) 463 #define FW_BLC_SELF_FIFO_MASK (1 << 16) /* 945 only */ 464 #define FW_BLC_SELF_EN (1 << 15) /* 945 only */ 465 #define MM_BURST_LENGTH 0x00700000 466 #define MM_FIFO_WATERMARK 0x0001F000 467 #define LM_BURST_LENGTH 0x00000700 468 #define LM_FIFO_WATERMARK 0x0000001F 469 #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */ 470 471 #define _MBUS_ABOX0_CTL 0x45038 472 #define _MBUS_ABOX1_CTL 0x45048 473 #define _MBUS_ABOX2_CTL 0x4504C 474 #define MBUS_ABOX_CTL(x) \ 475 _MMIO(_PICK_EVEN_2RANGES(x, 2, \ 476 _MBUS_ABOX0_CTL, _MBUS_ABOX1_CTL, \ 477 _MBUS_ABOX2_CTL, _MBUS_ABOX2_CTL)) 478 479 #define MBUS_ABOX_BW_CREDIT_MASK (3 << 20) 480 #define MBUS_ABOX_BW_CREDIT(x) ((x) << 20) 481 #define MBUS_ABOX_B_CREDIT_MASK (0xF << 16) 482 #define MBUS_ABOX_B_CREDIT(x) ((x) << 16) 483 #define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8) 484 #define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8) 485 #define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0) 486 #define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0) 487 488 /* Make render/texture TLB fetches lower priorty than associated data 489 * fetches. This is not turned on by default 490 */ 491 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) 492 493 /* Isoch request wait on GTT enable (Display A/B/C streams). 494 * Make isoch requests stall on the TLB update. May cause 495 * display underruns (test mode only) 496 */ 497 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) 498 499 /* Block grant count for isoch requests when block count is 500 * set to a finite value. 501 */ 502 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) 503 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ 504 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ 505 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ 506 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ 507 508 /* Enable render writes to complete in C2/C3/C4 power states. 509 * If this isn't enabled, render writes are prevented in low 510 * power states. That seems bad to me. 511 */ 512 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) 513 514 /* This acknowledges an async flip immediately instead 515 * of waiting for 2TLB fetches. 516 */ 517 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) 518 519 /* Enables non-sequential data reads through arbiter 520 */ 521 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) 522 523 /* Disable FSB snooping of cacheable write cycles from binner/render 524 * command stream 525 */ 526 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) 527 528 /* Arbiter time slice for non-isoch streams */ 529 #define MI_ARB_TIME_SLICE_MASK (7 << 5) 530 #define MI_ARB_TIME_SLICE_1 (0 << 5) 531 #define MI_ARB_TIME_SLICE_2 (1 << 5) 532 #define MI_ARB_TIME_SLICE_4 (2 << 5) 533 #define MI_ARB_TIME_SLICE_6 (3 << 5) 534 #define MI_ARB_TIME_SLICE_8 (4 << 5) 535 #define MI_ARB_TIME_SLICE_10 (5 << 5) 536 #define MI_ARB_TIME_SLICE_14 (6 << 5) 537 #define MI_ARB_TIME_SLICE_16 (7 << 5) 538 539 /* Low priority grace period page size */ 540 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ 541 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) 542 543 /* Disable display A/B trickle feed */ 544 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) 545 546 /* Set display plane priority */ 547 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ 548 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ 549 550 #define MI_STATE _MMIO(0x20e4) /* gen2 only */ 551 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */ 552 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */ 553 554 /* On modern GEN architectures interrupt control consists of two sets 555 * of registers. The first set pertains to the ring generating the 556 * interrupt. The second control is for the functional block generating the 557 * interrupt. These are PM, GT, DE, etc. 558 * 559 * Luckily *knocks on wood* all the ring interrupt bits match up with the 560 * GT interrupt bits, so we don't need to duplicate the defines. 561 * 562 * These defines should cover us well from SNB->HSW with minor exceptions 563 * it can also work on ILK. 564 */ 565 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) 566 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25) 567 #define GT_BLT_USER_INTERRUPT (1 << 22) 568 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15) 569 #define GT_BSD_USER_INTERRUPT (1 << 12) 570 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */ 571 #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) /* bdw+ */ 572 #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8) 573 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */ 574 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) 575 #define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3) 576 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2) 577 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1) 578 #define GT_RENDER_USER_INTERRUPT (1 << 0) 579 580 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */ 581 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */ 582 583 #define GT_PARITY_ERROR(dev_priv) \ 584 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \ 585 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0)) 586 587 /* These are all the "old" interrupts */ 588 #define ILK_BSD_USER_INTERRUPT (1 << 5) 589 590 #define I915_PM_INTERRUPT (1 << 31) 591 #define I915_ISP_INTERRUPT (1 << 22) 592 #define I915_LPE_PIPE_B_INTERRUPT (1 << 21) 593 #define I915_LPE_PIPE_A_INTERRUPT (1 << 20) 594 #define I915_MIPIC_INTERRUPT (1 << 19) 595 #define I915_MIPIA_INTERRUPT (1 << 18) 596 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18) 597 #define I915_DISPLAY_PORT_INTERRUPT (1 << 17) 598 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16) 599 #define I915_MASTER_ERROR_INTERRUPT (1 << 15) 600 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14) 601 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */ 602 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13) 603 #define I915_HWB_OOM_INTERRUPT (1 << 13) 604 #define I915_LPE_PIPE_C_INTERRUPT (1 << 12) 605 #define I915_SYNC_STATUS_INTERRUPT (1 << 12) 606 #define I915_MISC_INTERRUPT (1 << 11) 607 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11) 608 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10) 609 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10) 610 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9) 611 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9) 612 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8) 613 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8) 614 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7) 615 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6) 616 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5) 617 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4) 618 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3) 619 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2) 620 #define I915_DEBUG_INTERRUPT (1 << 2) 621 #define I915_WINVALID_INTERRUPT (1 << 1) 622 #define I915_USER_INTERRUPT (1 << 1) 623 #define I915_ASLE_INTERRUPT (1 << 0) 624 #define I915_BSD_USER_INTERRUPT (1 << 25) 625 626 #define GEN6_BSD_RNCID _MMIO(0x12198) 627 628 #define GEN7_FF_THREAD_MODE _MMIO(0x20a0) 629 #define GEN7_FF_SCHED_MASK 0x0077070 630 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19) 631 #define GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19) 632 #define GEN7_FF_TS_SCHED_HS1 (0x5 << 16) 633 #define GEN7_FF_TS_SCHED_HS0 (0x3 << 16) 634 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16) 635 #define GEN7_FF_TS_SCHED_HW (0x0 << 16) /* Default */ 636 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15) 637 #define GEN7_FF_VS_SCHED_HS1 (0x5 << 12) 638 #define GEN7_FF_VS_SCHED_HS0 (0x3 << 12) 639 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */ 640 #define GEN7_FF_VS_SCHED_HW (0x0 << 12) 641 #define GEN7_FF_DS_SCHED_HS1 (0x5 << 4) 642 #define GEN7_FF_DS_SCHED_HS0 (0x3 << 4) 643 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */ 644 #define GEN7_FF_DS_SCHED_HW (0x0 << 4) 645 646 #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000) 647 #define ILK_FBCQ_DIS REG_BIT(22) 648 #define ILK_PABSTRETCH_DIS REG_BIT(21) 649 #define ILK_SABSTRETCH_DIS REG_BIT(20) 650 #define IVB_PRI_STRETCH_MAX_MASK REG_GENMASK(21, 20) 651 #define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0) 652 #define IVB_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1) 653 #define IVB_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2) 654 #define IVB_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3) 655 #define IVB_SPR_STRETCH_MAX_MASK REG_GENMASK(19, 18) 656 #define IVB_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0) 657 #define IVB_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1) 658 #define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2) 659 #define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3) 660 661 #define IPS_CTL _MMIO(0x43408) 662 #define IPS_ENABLE REG_BIT(31) 663 #define IPS_FALSE_COLOR REG_BIT(4) 664 665 /* 666 * Clock control & power management 667 */ 668 #define _DPLL_A 0x6014 669 #define _DPLL_B 0x6018 670 #define _CHV_DPLL_C 0x6030 671 #define DPLL(pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \ 672 (pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) 673 674 #define VGA0 _MMIO(0x6000) 675 #define VGA1 _MMIO(0x6004) 676 #define VGA_PD _MMIO(0x6010) 677 #define VGA0_PD_P2_DIV_4 (1 << 7) 678 #define VGA0_PD_P1_DIV_2 (1 << 5) 679 #define VGA0_PD_P1_SHIFT 0 680 #define VGA0_PD_P1_MASK (0x1f << 0) 681 #define VGA1_PD_P2_DIV_4 (1 << 15) 682 #define VGA1_PD_P1_DIV_2 (1 << 13) 683 #define VGA1_PD_P1_SHIFT 8 684 #define VGA1_PD_P1_MASK (0x1f << 8) 685 #define DPLL_VCO_ENABLE (1 << 31) 686 #define DPLL_SDVO_HIGH_SPEED (1 << 30) 687 #define DPLL_DVO_2X_MODE (1 << 30) 688 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) 689 #define DPLL_SYNCLOCK_ENABLE (1 << 29) 690 #define DPLL_REF_CLK_ENABLE_VLV (1 << 29) 691 #define DPLL_VGA_MODE_DIS (1 << 28) 692 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 693 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 694 #define DPLL_MODE_MASK (3 << 26) 695 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 696 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 697 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 698 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 699 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 700 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 701 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ 702 #define DPLL_LOCK_VLV (1 << 15) 703 #define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14) 704 #define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13) 705 #define DPLL_SSC_REF_CLK_CHV (1 << 13) 706 #define DPLL_PORTC_READY_MASK (0xf << 4) 707 #define DPLL_PORTB_READY_MASK (0xf) 708 709 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 710 711 /* Additional CHV pll/phy registers */ 712 #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240) 713 #define DPLL_PORTD_READY_MASK (0xf) 714 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100) 715 #define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27)) 716 #define PHY_LDO_DELAY_0NS 0x0 717 #define PHY_LDO_DELAY_200NS 0x1 718 #define PHY_LDO_DELAY_600NS 0x2 719 #define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23)) 720 #define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11)) 721 #define PHY_CH_SU_PSR 0x1 722 #define PHY_CH_DEEP_PSR 0x7 723 #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2)) 724 #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy)) 725 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104) 726 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30)) 727 #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch)))) 728 #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline)))) 729 730 /* 731 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 732 * this field (only one bit may be set). 733 */ 734 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 735 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 736 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 737 /* i830, required in DVO non-gang */ 738 #define PLL_P2_DIVIDE_BY_4 (1 << 23) 739 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 740 #define PLL_REF_INPUT_DREFCLK (0 << 13) 741 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 742 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 743 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 744 #define PLL_REF_INPUT_MASK (3 << 13) 745 #define PLL_LOAD_PULSE_PHASE_SHIFT 9 746 /* Ironlake */ 747 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 748 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) 749 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9) 750 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 751 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff 752 753 /* 754 * Parallel to Serial Load Pulse phase selection. 755 * Selects the phase for the 10X DPLL clock for the PCIe 756 * digital display port. The range is 4 to 13; 10 or more 757 * is just a flip delay. The default is 6 758 */ 759 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 760 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 761 /* 762 * SDVO multiplier for 945G/GM. Not used on 965. 763 */ 764 #define SDVO_MULTIPLIER_MASK 0x000000ff 765 #define SDVO_MULTIPLIER_SHIFT_HIRES 4 766 #define SDVO_MULTIPLIER_SHIFT_VGA 0 767 768 #define _DPLL_A_MD 0x601c 769 #define _DPLL_B_MD 0x6020 770 #define _CHV_DPLL_C_MD 0x603c 771 #define DPLL_MD(pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \ 772 (pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) 773 774 /* 775 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 776 * 777 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 778 */ 779 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 780 #define DPLL_MD_UDI_DIVIDER_SHIFT 24 781 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 782 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 783 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 784 /* 785 * SDVO/UDI pixel multiplier. 786 * 787 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 788 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 789 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 790 * dummy bytes in the datastream at an increased clock rate, with both sides of 791 * the link knowing how many bytes are fill. 792 * 793 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 794 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 795 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 796 * through an SDVO command. 797 * 798 * This register field has values of multiplication factor minus 1, with 799 * a maximum multiplier of 5 for SDVO. 800 */ 801 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 802 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 803 /* 804 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 805 * This best be set to the default value (3) or the CRT won't work. No, 806 * I don't entirely understand what this does... 807 */ 808 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 809 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 810 811 #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024) 812 813 #define _FPA0 0x6040 814 #define _FPA1 0x6044 815 #define _FPB0 0x6048 816 #define _FPB1 0x604c 817 #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0) 818 #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1) 819 #define FP_N_DIV_MASK 0x003f0000 820 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 821 #define FP_N_DIV_SHIFT 16 822 #define FP_M1_DIV_MASK 0x00003f00 823 #define FP_M1_DIV_SHIFT 8 824 #define FP_M2_DIV_MASK 0x0000003f 825 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff 826 #define FP_M2_DIV_SHIFT 0 827 #define DPLL_TEST _MMIO(0x606c) 828 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 829 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 830 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 831 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 832 #define DPLLB_TEST_N_BYPASS (1 << 19) 833 #define DPLLB_TEST_M_BYPASS (1 << 18) 834 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 835 #define DPLLA_TEST_N_BYPASS (1 << 3) 836 #define DPLLA_TEST_M_BYPASS (1 << 2) 837 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 838 #define D_STATE _MMIO(0x6104) 839 #define DSTATE_GFX_RESET_I830 (1 << 6) 840 #define DSTATE_PLL_D3_OFF (1 << 3) 841 #define DSTATE_GFX_CLOCK_GATING (1 << 1) 842 #define DSTATE_DOT_CLOCK_GATING (1 << 0) 843 #define DSPCLK_GATE_D(__i915) _MMIO(DISPLAY_MMIO_BASE(__i915) + 0x6200) 844 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 845 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 846 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 847 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ 848 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ 849 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ 850 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ 851 # define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */ 852 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ 853 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ 854 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ 855 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ 856 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ 857 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ 858 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ 859 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ 860 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ 861 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ 862 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ 863 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ 864 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 865 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) 866 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) 867 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) 868 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ 869 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ 870 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ 871 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) 872 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) 873 /* 874 * This bit must be set on the 830 to prevent hangs when turning off the 875 * overlay scaler. 876 */ 877 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 878 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) 879 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) 880 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ 881 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ 882 883 #define RENCLK_GATE_D1 _MMIO(0x6204) 884 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ 885 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ 886 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) 887 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) 888 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) 889 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) 890 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) 891 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) 892 # define MAG_CLOCK_GATE_DISABLE (1 << 5) 893 /* This bit must be unset on 855,865 */ 894 # define MECI_CLOCK_GATE_DISABLE (1 << 4) 895 # define DCMP_CLOCK_GATE_DISABLE (1 << 3) 896 # define MEC_CLOCK_GATE_DISABLE (1 << 2) 897 # define MECO_CLOCK_GATE_DISABLE (1 << 1) 898 /* This bit must be set on 855,865. */ 899 # define SV_CLOCK_GATE_DISABLE (1 << 0) 900 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) 901 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) 902 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) 903 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) 904 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) 905 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) 906 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) 907 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) 908 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) 909 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) 910 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) 911 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) 912 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) 913 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) 914 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) 915 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) 916 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) 917 918 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) 919 /* This bit must always be set on 965G/965GM */ 920 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) 921 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) 922 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) 923 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) 924 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) 925 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) 926 /* This bit must always be set on 965G */ 927 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) 928 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) 929 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) 930 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) 931 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) 932 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) 933 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) 934 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) 935 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) 936 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) 937 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) 938 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) 939 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) 940 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) 941 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) 942 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) 943 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) 944 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) 945 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) 946 947 #define RENCLK_GATE_D2 _MMIO(0x6208) 948 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) 949 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) 950 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) 951 952 #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */ 953 #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4) 954 955 #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */ 956 #define DEUC _MMIO(0x6214) /* CRL only */ 957 958 #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500) 959 #define FW_CSPWRDWNEN (1 << 15) 960 961 #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504) 962 963 #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508) 964 #define CDCLK_FREQ_SHIFT 4 965 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT) 966 #define CZCLK_FREQ_MASK 0xf 967 968 #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C) 969 #define PFI_CREDIT_63 (9 << 28) /* chv only */ 970 #define PFI_CREDIT_31 (8 << 28) /* chv only */ 971 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */ 972 #define PFI_CREDIT_RESEND (1 << 27) 973 #define VGA_FAST_MODE_DISABLE (1 << 14) 974 975 #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510) 976 977 #define PEG_BAND_GAP_DATA _MMIO(0x14d68) 978 979 #define BXT_RP_STATE_CAP _MMIO(0x138170) 980 #define GEN9_RP_STATE_LIMITS _MMIO(0x138148) 981 982 #define MTL_RP_STATE_CAP _MMIO(0x138000) 983 #define MTL_MEDIAP_STATE_CAP _MMIO(0x138020) 984 #define MTL_RP0_CAP_MASK REG_GENMASK(8, 0) 985 #define MTL_RPN_CAP_MASK REG_GENMASK(24, 16) 986 987 #define MTL_GT_RPE_FREQUENCY _MMIO(0x13800c) 988 #define MTL_MPE_FREQUENCY _MMIO(0x13802c) 989 #define MTL_RPE_MASK REG_GENMASK(8, 0) 990 991 #define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8) 992 #define GT0_PERF_LIMIT_REASONS_MASK 0xde3 993 #define PROCHOT_MASK REG_BIT(0) 994 #define THERMAL_LIMIT_MASK REG_BIT(1) 995 #define RATL_MASK REG_BIT(5) 996 #define VR_THERMALERT_MASK REG_BIT(6) 997 #define VR_TDC_MASK REG_BIT(7) 998 #define POWER_LIMIT_4_MASK REG_BIT(8) 999 #define POWER_LIMIT_1_MASK REG_BIT(10) 1000 #define POWER_LIMIT_2_MASK REG_BIT(11) 1001 #define GT0_PERF_LIMIT_REASONS_LOG_MASK REG_GENMASK(31, 16) 1002 #define MTL_MEDIA_PERF_LIMIT_REASONS _MMIO(0x138030) 1003 1004 #define CHV_CLK_CTL1 _MMIO(0x101100) 1005 #define VLV_CLK_CTL2 _MMIO(0x101104) 1006 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28 1007 1008 /* 1009 * Overlay regs 1010 */ 1011 1012 #define OVADD _MMIO(0x30000) 1013 #define DOVSTA _MMIO(0x30008) 1014 #define OC_BUF (0x3 << 20) 1015 #define OGAMC5 _MMIO(0x30010) 1016 #define OGAMC4 _MMIO(0x30014) 1017 #define OGAMC3 _MMIO(0x30018) 1018 #define OGAMC2 _MMIO(0x3001c) 1019 #define OGAMC1 _MMIO(0x30020) 1020 #define OGAMC0 _MMIO(0x30024) 1021 1022 /* 1023 * GEN9 clock gating regs 1024 */ 1025 #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530) 1026 #define DARBF_GATING_DIS REG_BIT(27) 1027 #define MTL_PIPEDMC_GATING_DIS_A REG_BIT(15) 1028 #define MTL_PIPEDMC_GATING_DIS_B REG_BIT(14) 1029 #define PWM2_GATING_DIS REG_BIT(14) 1030 #define PWM1_GATING_DIS REG_BIT(13) 1031 1032 #define GEN9_CLKGATE_DIS_3 _MMIO(0x46538) 1033 #define TGL_VRH_GATING_DIS REG_BIT(31) 1034 #define DPT_GATING_DIS REG_BIT(22) 1035 1036 #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C) 1037 #define BXT_GMBUS_GATING_DIS (1 << 14) 1038 1039 #define GEN9_CLKGATE_DIS_5 _MMIO(0x46540) 1040 #define DPCE_GATING_DIS REG_BIT(17) 1041 1042 #define _CLKGATE_DIS_PSL_A 0x46520 1043 #define _CLKGATE_DIS_PSL_B 0x46524 1044 #define _CLKGATE_DIS_PSL_C 0x46528 1045 #define DUPS1_GATING_DIS (1 << 15) 1046 #define DUPS2_GATING_DIS (1 << 19) 1047 #define DUPS3_GATING_DIS (1 << 23) 1048 #define CURSOR_GATING_DIS REG_BIT(28) 1049 #define DPF_GATING_DIS (1 << 10) 1050 #define DPF_RAM_GATING_DIS (1 << 9) 1051 #define DPFR_GATING_DIS (1 << 8) 1052 1053 #define CLKGATE_DIS_PSL(pipe) \ 1054 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B) 1055 1056 #define _CLKGATE_DIS_PSL_EXT_A 0x4654C 1057 #define _CLKGATE_DIS_PSL_EXT_B 0x46550 1058 #define PIPEDMC_GATING_DIS REG_BIT(12) 1059 1060 #define CLKGATE_DIS_PSL_EXT(pipe) \ 1061 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_EXT_A, _CLKGATE_DIS_PSL_EXT_B) 1062 1063 /* DDI Buffer Control */ 1064 #define _DDI_CLK_VALFREQ_A 0x64030 1065 #define _DDI_CLK_VALFREQ_B 0x64130 1066 #define DDI_CLK_VALFREQ(port) _MMIO_PORT(port, _DDI_CLK_VALFREQ_A, _DDI_CLK_VALFREQ_B) 1067 1068 /* 1069 * Display engine regs 1070 */ 1071 1072 /* Pipe A CRC regs */ 1073 #define _PIPE_CRC_CTL_A 0x60050 1074 #define PIPE_CRC_ENABLE REG_BIT(31) 1075 /* skl+ source selection */ 1076 #define PIPE_CRC_SOURCE_MASK_SKL REG_GENMASK(30, 28) 1077 #define PIPE_CRC_SOURCE_PLANE_1_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 0) 1078 #define PIPE_CRC_SOURCE_PLANE_2_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 2) 1079 #define PIPE_CRC_SOURCE_DMUX_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 4) 1080 #define PIPE_CRC_SOURCE_PLANE_3_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 6) 1081 #define PIPE_CRC_SOURCE_PLANE_4_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 7) 1082 #define PIPE_CRC_SOURCE_PLANE_5_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 5) 1083 #define PIPE_CRC_SOURCE_PLANE_6_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 3) 1084 #define PIPE_CRC_SOURCE_PLANE_7_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 1) 1085 /* ivb+ source selection */ 1086 #define PIPE_CRC_SOURCE_MASK_IVB REG_GENMASK(30, 29) 1087 #define PIPE_CRC_SOURCE_PRIMARY_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 0) 1088 #define PIPE_CRC_SOURCE_SPRITE_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 1) 1089 #define PIPE_CRC_SOURCE_PF_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 2) 1090 /* ilk+ source selection */ 1091 #define PIPE_CRC_SOURCE_MASK_ILK REG_GENMASK(30, 28) 1092 #define PIPE_CRC_SOURCE_PRIMARY_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 0) 1093 #define PIPE_CRC_SOURCE_SPRITE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 1) 1094 #define PIPE_CRC_SOURCE_PIPE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 2) 1095 /* embedded DP port on the north display block */ 1096 #define PIPE_CRC_SOURCE_PORT_A_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 4) 1097 #define PIPE_CRC_SOURCE_FDI_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 5) 1098 /* vlv source selection */ 1099 #define PIPE_CRC_SOURCE_MASK_VLV REG_GENMASK(30, 27) 1100 #define PIPE_CRC_SOURCE_PIPE_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 0) 1101 #define PIPE_CRC_SOURCE_HDMIB_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 1) 1102 #define PIPE_CRC_SOURCE_HDMIC_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 2) 1103 /* with DP port the pipe source is invalid */ 1104 #define PIPE_CRC_SOURCE_DP_D_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 3) 1105 #define PIPE_CRC_SOURCE_DP_B_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 6) 1106 #define PIPE_CRC_SOURCE_DP_C_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 7) 1107 /* gen3+ source selection */ 1108 #define PIPE_CRC_SOURCE_MASK_I9XX REG_GENMASK(30, 28) 1109 #define PIPE_CRC_SOURCE_PIPE_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 0) 1110 #define PIPE_CRC_SOURCE_SDVOB_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 1) 1111 #define PIPE_CRC_SOURCE_SDVOC_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 2) 1112 /* with DP/TV port the pipe source is invalid */ 1113 #define PIPE_CRC_SOURCE_DP_D_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 3) 1114 #define PIPE_CRC_SOURCE_TV_PRE REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 4) 1115 #define PIPE_CRC_SOURCE_TV_POST REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 5) 1116 #define PIPE_CRC_SOURCE_DP_B_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 6) 1117 #define PIPE_CRC_SOURCE_DP_C_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 7) 1118 /* gen2 doesn't have source selection bits */ 1119 #define PIPE_CRC_INCLUDE_BORDER_I8XX REG_BIT(30) 1120 1121 #define _PIPE_CRC_RES_1_A_IVB 0x60064 1122 #define _PIPE_CRC_RES_2_A_IVB 0x60068 1123 #define _PIPE_CRC_RES_3_A_IVB 0x6006c 1124 #define _PIPE_CRC_RES_4_A_IVB 0x60070 1125 #define _PIPE_CRC_RES_5_A_IVB 0x60074 1126 1127 #define _PIPE_CRC_RES_RED_A 0x60060 1128 #define _PIPE_CRC_RES_GREEN_A 0x60064 1129 #define _PIPE_CRC_RES_BLUE_A 0x60068 1130 #define _PIPE_CRC_RES_RES1_A_I915 0x6006c 1131 #define _PIPE_CRC_RES_RES2_A_G4X 0x60080 1132 1133 /* Pipe B CRC regs */ 1134 #define _PIPE_CRC_RES_1_B_IVB 0x61064 1135 #define _PIPE_CRC_RES_2_B_IVB 0x61068 1136 #define _PIPE_CRC_RES_3_B_IVB 0x6106c 1137 #define _PIPE_CRC_RES_4_B_IVB 0x61070 1138 #define _PIPE_CRC_RES_5_B_IVB 0x61074 1139 1140 #define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_CTL_A) 1141 #define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_1_A_IVB) 1142 #define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_2_A_IVB) 1143 #define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_3_A_IVB) 1144 #define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_4_A_IVB) 1145 #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_5_A_IVB) 1146 1147 #define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A) 1148 #define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A) 1149 #define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_BLUE_A) 1150 #define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915) 1151 #define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X) 1152 1153 /* Pipe/transcoder A timing regs */ 1154 #define _TRANS_HTOTAL_A 0x60000 1155 #define HTOTAL_MASK REG_GENMASK(31, 16) 1156 #define HTOTAL(htotal) REG_FIELD_PREP(HTOTAL_MASK, (htotal)) 1157 #define HACTIVE_MASK REG_GENMASK(15, 0) 1158 #define HACTIVE(hdisplay) REG_FIELD_PREP(HACTIVE_MASK, (hdisplay)) 1159 #define _TRANS_HBLANK_A 0x60004 1160 #define HBLANK_END_MASK REG_GENMASK(31, 16) 1161 #define HBLANK_END(hblank_end) REG_FIELD_PREP(HBLANK_END_MASK, (hblank_end)) 1162 #define HBLANK_START_MASK REG_GENMASK(15, 0) 1163 #define HBLANK_START(hblank_start) REG_FIELD_PREP(HBLANK_START_MASK, (hblank_start)) 1164 #define _TRANS_HSYNC_A 0x60008 1165 #define HSYNC_END_MASK REG_GENMASK(31, 16) 1166 #define HSYNC_END(hsync_end) REG_FIELD_PREP(HSYNC_END_MASK, (hsync_end)) 1167 #define HSYNC_START_MASK REG_GENMASK(15, 0) 1168 #define HSYNC_START(hsync_start) REG_FIELD_PREP(HSYNC_START_MASK, (hsync_start)) 1169 #define _TRANS_VTOTAL_A 0x6000c 1170 #define VTOTAL_MASK REG_GENMASK(31, 16) 1171 #define VTOTAL(vtotal) REG_FIELD_PREP(VTOTAL_MASK, (vtotal)) 1172 #define VACTIVE_MASK REG_GENMASK(15, 0) 1173 #define VACTIVE(vdisplay) REG_FIELD_PREP(VACTIVE_MASK, (vdisplay)) 1174 #define _TRANS_VBLANK_A 0x60010 1175 #define VBLANK_END_MASK REG_GENMASK(31, 16) 1176 #define VBLANK_END(vblank_end) REG_FIELD_PREP(VBLANK_END_MASK, (vblank_end)) 1177 #define VBLANK_START_MASK REG_GENMASK(15, 0) 1178 #define VBLANK_START(vblank_start) REG_FIELD_PREP(VBLANK_START_MASK, (vblank_start)) 1179 #define _TRANS_VSYNC_A 0x60014 1180 #define VSYNC_END_MASK REG_GENMASK(31, 16) 1181 #define VSYNC_END(vsync_end) REG_FIELD_PREP(VSYNC_END_MASK, (vsync_end)) 1182 #define VSYNC_START_MASK REG_GENMASK(15, 0) 1183 #define VSYNC_START(vsync_start) REG_FIELD_PREP(VSYNC_START_MASK, (vsync_start)) 1184 #define _TRANS_EXITLINE_A 0x60018 1185 #define _PIPEASRC 0x6001c 1186 #define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16) 1187 #define PIPESRC_WIDTH(w) REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w)) 1188 #define PIPESRC_HEIGHT_MASK REG_GENMASK(15, 0) 1189 #define PIPESRC_HEIGHT(h) REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h)) 1190 #define _BCLRPAT_A 0x60020 1191 #define _TRANS_VSYNCSHIFT_A 0x60028 1192 #define _TRANS_MULT_A 0x6002c 1193 1194 /* Pipe/transcoder B timing regs */ 1195 #define _TRANS_HTOTAL_B 0x61000 1196 #define _TRANS_HBLANK_B 0x61004 1197 #define _TRANS_HSYNC_B 0x61008 1198 #define _TRANS_VTOTAL_B 0x6100c 1199 #define _TRANS_VBLANK_B 0x61010 1200 #define _TRANS_VSYNC_B 0x61014 1201 #define _PIPEBSRC 0x6101c 1202 #define _BCLRPAT_B 0x61020 1203 #define _TRANS_VSYNCSHIFT_B 0x61028 1204 #define _TRANS_MULT_B 0x6102c 1205 1206 /* DSI 0 timing regs */ 1207 #define _TRANS_HTOTAL_DSI0 0x6b000 1208 #define _TRANS_HSYNC_DSI0 0x6b008 1209 #define _TRANS_VTOTAL_DSI0 0x6b00c 1210 #define _TRANS_VSYNC_DSI0 0x6b014 1211 #define _TRANS_VSYNCSHIFT_DSI0 0x6b028 1212 1213 /* DSI 1 timing regs */ 1214 #define _TRANS_HTOTAL_DSI1 0x6b800 1215 #define _TRANS_HSYNC_DSI1 0x6b808 1216 #define _TRANS_VTOTAL_DSI1 0x6b80c 1217 #define _TRANS_VSYNC_DSI1 0x6b814 1218 #define _TRANS_VSYNCSHIFT_DSI1 0x6b828 1219 1220 #define TRANS_HTOTAL(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HTOTAL_A) 1221 #define TRANS_HBLANK(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A) 1222 #define TRANS_HSYNC(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A) 1223 #define TRANS_VTOTAL(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A) 1224 #define TRANS_VBLANK(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A) 1225 #define TRANS_VSYNC(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A) 1226 #define BCLRPAT(trans) _MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A) 1227 #define TRANS_VSYNCSHIFT(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A) 1228 #define PIPESRC(pipe) _MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC) 1229 #define TRANS_MULT(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A) 1230 1231 /* VRR registers */ 1232 #define _TRANS_VRR_CTL_A 0x60420 1233 #define _TRANS_VRR_CTL_B 0x61420 1234 #define _TRANS_VRR_CTL_C 0x62420 1235 #define _TRANS_VRR_CTL_D 0x63420 1236 #define TRANS_VRR_CTL(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A) 1237 #define VRR_CTL_VRR_ENABLE REG_BIT(31) 1238 #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) 1239 #define VRR_CTL_FLIP_LINE_EN REG_BIT(29) 1240 #define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3) 1241 #define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x)) 1242 #define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0) 1243 #define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0) 1244 #define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x)) 1245 1246 #define _TRANS_VRR_VMAX_A 0x60424 1247 #define _TRANS_VRR_VMAX_B 0x61424 1248 #define _TRANS_VRR_VMAX_C 0x62424 1249 #define _TRANS_VRR_VMAX_D 0x63424 1250 #define TRANS_VRR_VMAX(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMAX_A) 1251 #define VRR_VMAX_MASK REG_GENMASK(19, 0) 1252 1253 #define _TRANS_VRR_VMIN_A 0x60434 1254 #define _TRANS_VRR_VMIN_B 0x61434 1255 #define _TRANS_VRR_VMIN_C 0x62434 1256 #define _TRANS_VRR_VMIN_D 0x63434 1257 #define TRANS_VRR_VMIN(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMIN_A) 1258 #define VRR_VMIN_MASK REG_GENMASK(15, 0) 1259 1260 #define _TRANS_VRR_VMAXSHIFT_A 0x60428 1261 #define _TRANS_VRR_VMAXSHIFT_B 0x61428 1262 #define _TRANS_VRR_VMAXSHIFT_C 0x62428 1263 #define _TRANS_VRR_VMAXSHIFT_D 0x63428 1264 #define TRANS_VRR_VMAXSHIFT(trans) _MMIO_TRANS2(dev_priv, trans, \ 1265 _TRANS_VRR_VMAXSHIFT_A) 1266 #define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16) 1267 #define VRR_VMAXSHIFT_DEC REG_BIT(16) 1268 #define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0) 1269 1270 #define _TRANS_VRR_STATUS_A 0x6042C 1271 #define _TRANS_VRR_STATUS_B 0x6142C 1272 #define _TRANS_VRR_STATUS_C 0x6242C 1273 #define _TRANS_VRR_STATUS_D 0x6342C 1274 #define TRANS_VRR_STATUS(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A) 1275 #define VRR_STATUS_VMAX_REACHED REG_BIT(31) 1276 #define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30) 1277 #define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29) 1278 #define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28) 1279 #define VRR_STATUS_VRR_EN_LIVE REG_BIT(27) 1280 #define VRR_STATUS_FLIPS_SERVICED REG_BIT(26) 1281 #define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20) 1282 #define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0) 1283 #define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1) 1284 #define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2) 1285 #define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3) 1286 #define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4) 1287 #define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5) 1288 #define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6) 1289 1290 #define _TRANS_VRR_VTOTAL_PREV_A 0x60480 1291 #define _TRANS_VRR_VTOTAL_PREV_B 0x61480 1292 #define _TRANS_VRR_VTOTAL_PREV_C 0x62480 1293 #define _TRANS_VRR_VTOTAL_PREV_D 0x63480 1294 #define TRANS_VRR_VTOTAL_PREV(trans) _MMIO_TRANS2(dev_priv, trans, \ 1295 _TRANS_VRR_VTOTAL_PREV_A) 1296 #define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31) 1297 #define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30) 1298 #define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29) 1299 #define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0) 1300 1301 #define _TRANS_VRR_FLIPLINE_A 0x60438 1302 #define _TRANS_VRR_FLIPLINE_B 0x61438 1303 #define _TRANS_VRR_FLIPLINE_C 0x62438 1304 #define _TRANS_VRR_FLIPLINE_D 0x63438 1305 #define TRANS_VRR_FLIPLINE(trans) _MMIO_TRANS2(dev_priv, trans, \ 1306 _TRANS_VRR_FLIPLINE_A) 1307 #define VRR_FLIPLINE_MASK REG_GENMASK(19, 0) 1308 1309 #define _TRANS_VRR_STATUS2_A 0x6043C 1310 #define _TRANS_VRR_STATUS2_B 0x6143C 1311 #define _TRANS_VRR_STATUS2_C 0x6243C 1312 #define _TRANS_VRR_STATUS2_D 0x6343C 1313 #define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS2_A) 1314 #define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0) 1315 1316 #define _TRANS_PUSH_A 0x60A70 1317 #define _TRANS_PUSH_B 0x61A70 1318 #define _TRANS_PUSH_C 0x62A70 1319 #define _TRANS_PUSH_D 0x63A70 1320 #define TRANS_PUSH(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_PUSH_A) 1321 #define TRANS_PUSH_EN REG_BIT(31) 1322 #define TRANS_PUSH_SEND REG_BIT(30) 1323 1324 #define _TRANS_VRR_VSYNC_A 0x60078 1325 #define TRANS_VRR_VSYNC(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A) 1326 #define VRR_VSYNC_END_MASK REG_GENMASK(28, 16) 1327 #define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end)) 1328 #define VRR_VSYNC_START_MASK REG_GENMASK(12, 0) 1329 #define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start)) 1330 1331 /* VGA port control */ 1332 #define ADPA _MMIO(0x61100) 1333 #define PCH_ADPA _MMIO(0xe1100) 1334 #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100) 1335 1336 #define ADPA_DAC_ENABLE (1 << 31) 1337 #define ADPA_DAC_DISABLE 0 1338 #define ADPA_PIPE_SEL_SHIFT 30 1339 #define ADPA_PIPE_SEL_MASK (1 << 30) 1340 #define ADPA_PIPE_SEL(pipe) ((pipe) << 30) 1341 #define ADPA_PIPE_SEL_SHIFT_CPT 29 1342 #define ADPA_PIPE_SEL_MASK_CPT (3 << 29) 1343 #define ADPA_PIPE_SEL_CPT(pipe) ((pipe) << 29) 1344 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ 1345 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0 << 24) 1346 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3 << 24) 1347 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24) 1348 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2 << 24) 1349 #define ADPA_CRT_HOTPLUG_ENABLE (1 << 23) 1350 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0 << 22) 1351 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1 << 22) 1352 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0 << 21) 1353 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1 << 21) 1354 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0 << 20) 1355 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1 << 20) 1356 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0 << 18) 1357 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1 << 18) 1358 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2 << 18) 1359 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3 << 18) 1360 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0 << 17) 1361 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1 << 17) 1362 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16) 1363 #define ADPA_USE_VGA_HVPOLARITY (1 << 15) 1364 #define ADPA_SETS_HVPOLARITY 0 1365 #define ADPA_VSYNC_CNTL_DISABLE (1 << 10) 1366 #define ADPA_VSYNC_CNTL_ENABLE 0 1367 #define ADPA_HSYNC_CNTL_DISABLE (1 << 11) 1368 #define ADPA_HSYNC_CNTL_ENABLE 0 1369 #define ADPA_VSYNC_ACTIVE_HIGH (1 << 4) 1370 #define ADPA_VSYNC_ACTIVE_LOW 0 1371 #define ADPA_HSYNC_ACTIVE_HIGH (1 << 3) 1372 #define ADPA_HSYNC_ACTIVE_LOW 0 1373 #define ADPA_DPMS_MASK (~(3 << 10)) 1374 #define ADPA_DPMS_ON (0 << 10) 1375 #define ADPA_DPMS_SUSPEND (1 << 10) 1376 #define ADPA_DPMS_STANDBY (2 << 10) 1377 #define ADPA_DPMS_OFF (3 << 10) 1378 1379 1380 /* Hotplug control (945+ only) */ 1381 #define PORT_HOTPLUG_EN _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110) 1382 #define PORTB_HOTPLUG_INT_EN (1 << 29) 1383 #define PORTC_HOTPLUG_INT_EN (1 << 28) 1384 #define PORTD_HOTPLUG_INT_EN (1 << 27) 1385 #define SDVOB_HOTPLUG_INT_EN (1 << 26) 1386 #define SDVOC_HOTPLUG_INT_EN (1 << 25) 1387 #define TV_HOTPLUG_INT_EN (1 << 18) 1388 #define CRT_HOTPLUG_INT_EN (1 << 9) 1389 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \ 1390 PORTC_HOTPLUG_INT_EN | \ 1391 PORTD_HOTPLUG_INT_EN | \ 1392 SDVOC_HOTPLUG_INT_EN | \ 1393 SDVOB_HOTPLUG_INT_EN | \ 1394 CRT_HOTPLUG_INT_EN) 1395 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 1396 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 1397 /* must use period 64 on GM45 according to docs */ 1398 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 1399 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 1400 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 1401 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 1402 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 1403 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 1404 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 1405 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 1406 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 1407 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 1408 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 1409 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 1410 1411 #define PORT_HOTPLUG_STAT _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114) 1412 /* HDMI/DP bits are g4x+ */ 1413 #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27) 1414 #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) 1415 #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29) 1416 #define PORTD_HOTPLUG_INT_STATUS (3 << 21) 1417 #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21) 1418 #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21) 1419 #define PORTC_HOTPLUG_INT_STATUS (3 << 19) 1420 #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19) 1421 #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19) 1422 #define PORTB_HOTPLUG_INT_STATUS (3 << 17) 1423 #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17) 1424 #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17) 1425 /* CRT/TV common between gen3+ */ 1426 #define CRT_HOTPLUG_INT_STATUS (1 << 11) 1427 #define TV_HOTPLUG_INT_STATUS (1 << 10) 1428 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 1429 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 1430 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 1431 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 1432 #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6) 1433 #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5) 1434 #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4) 1435 #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4) 1436 1437 /* SDVO is different across gen3/4 */ 1438 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) 1439 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) 1440 /* 1441 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, 1442 * since reality corrobates that they're the same as on gen3. But keep these 1443 * bits here (and the comment!) to help any other lost wanderers back onto the 1444 * right tracks. 1445 */ 1446 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) 1447 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) 1448 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) 1449 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) 1450 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \ 1451 SDVOB_HOTPLUG_INT_STATUS_G4X | \ 1452 SDVOC_HOTPLUG_INT_STATUS_G4X | \ 1453 PORTB_HOTPLUG_INT_STATUS | \ 1454 PORTC_HOTPLUG_INT_STATUS | \ 1455 PORTD_HOTPLUG_INT_STATUS) 1456 1457 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \ 1458 SDVOB_HOTPLUG_INT_STATUS_I915 | \ 1459 SDVOC_HOTPLUG_INT_STATUS_I915 | \ 1460 PORTB_HOTPLUG_INT_STATUS | \ 1461 PORTC_HOTPLUG_INT_STATUS | \ 1462 PORTD_HOTPLUG_INT_STATUS) 1463 1464 /* SDVO and HDMI port control. 1465 * The same register may be used for SDVO or HDMI */ 1466 #define _GEN3_SDVOB 0x61140 1467 #define _GEN3_SDVOC 0x61160 1468 #define GEN3_SDVOB _MMIO(_GEN3_SDVOB) 1469 #define GEN3_SDVOC _MMIO(_GEN3_SDVOC) 1470 #define GEN4_HDMIB GEN3_SDVOB 1471 #define GEN4_HDMIC GEN3_SDVOC 1472 #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140) 1473 #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160) 1474 #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C) 1475 #define PCH_SDVOB _MMIO(0xe1140) 1476 #define PCH_HDMIB PCH_SDVOB 1477 #define PCH_HDMIC _MMIO(0xe1150) 1478 #define PCH_HDMID _MMIO(0xe1160) 1479 1480 #define PORT_DFT_I9XX _MMIO(0x61150) 1481 #define DC_BALANCE_RESET (1 << 25) 1482 #define PORT_DFT2_G4X _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154) 1483 #define DC_BALANCE_RESET_VLV (1 << 31) 1484 #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0)) 1485 #define PIPE_C_SCRAMBLE_RESET REG_BIT(14) /* chv */ 1486 #define PIPE_B_SCRAMBLE_RESET REG_BIT(1) 1487 #define PIPE_A_SCRAMBLE_RESET REG_BIT(0) 1488 1489 /* Gen 3 SDVO bits: */ 1490 #define SDVO_ENABLE (1 << 31) 1491 #define SDVO_PIPE_SEL_SHIFT 30 1492 #define SDVO_PIPE_SEL_MASK (1 << 30) 1493 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30) 1494 #define SDVO_STALL_SELECT (1 << 29) 1495 #define SDVO_INTERRUPT_ENABLE (1 << 26) 1496 /* 1497 * 915G/GM SDVO pixel multiplier. 1498 * Programmed value is multiplier - 1, up to 5x. 1499 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 1500 */ 1501 #define SDVO_PORT_MULTIPLY_MASK (7 << 23) 1502 #define SDVO_PORT_MULTIPLY_SHIFT 23 1503 #define SDVO_PHASE_SELECT_MASK (15 << 19) 1504 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 1505 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 1506 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */ 1507 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */ 1508 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */ 1509 #define SDVO_DETECTED (1 << 2) 1510 /* Bits to be preserved when writing */ 1511 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \ 1512 SDVO_INTERRUPT_ENABLE) 1513 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE) 1514 1515 /* Gen 4 SDVO/HDMI bits: */ 1516 #define SDVO_COLOR_FORMAT_8bpc (0 << 26) 1517 #define SDVO_COLOR_FORMAT_MASK (7 << 26) 1518 #define SDVO_ENCODING_SDVO (0 << 10) 1519 #define SDVO_ENCODING_HDMI (2 << 10) 1520 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */ 1521 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */ 1522 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */ 1523 #define HDMI_AUDIO_ENABLE (1 << 6) /* HDMI only */ 1524 /* VSYNC/HSYNC bits new with 965, default is to be set */ 1525 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) 1526 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) 1527 1528 /* Gen 5 (IBX) SDVO/HDMI bits: */ 1529 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */ 1530 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */ 1531 1532 /* Gen 6 (CPT) SDVO/HDMI bits: */ 1533 #define SDVO_PIPE_SEL_SHIFT_CPT 29 1534 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29) 1535 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29) 1536 1537 /* CHV SDVO/HDMI bits: */ 1538 #define SDVO_PIPE_SEL_SHIFT_CHV 24 1539 #define SDVO_PIPE_SEL_MASK_CHV (3 << 24) 1540 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24) 1541 1542 /* Video Data Island Packet control */ 1543 #define VIDEO_DIP_DATA _MMIO(0x61178) 1544 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC 1545 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte 1546 * of the infoframe structure specified by CEA-861. */ 1547 #define VIDEO_DIP_DATA_SIZE 32 1548 #define VIDEO_DIP_ASYNC_DATA_SIZE 36 1549 #define VIDEO_DIP_GMP_DATA_SIZE 36 1550 #define VIDEO_DIP_VSC_DATA_SIZE 36 1551 #define VIDEO_DIP_PPS_DATA_SIZE 132 1552 #define VIDEO_DIP_CTL _MMIO(0x61170) 1553 /* Pre HSW: */ 1554 #define VIDEO_DIP_ENABLE (1 << 31) 1555 #define VIDEO_DIP_PORT(port) ((port) << 29) 1556 #define VIDEO_DIP_PORT_MASK (3 << 29) 1557 #define VIDEO_DIP_ENABLE_GCP (1 << 25) /* ilk+ */ 1558 #define VIDEO_DIP_ENABLE_AVI (1 << 21) 1559 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) 1560 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) /* ilk+ */ 1561 #define VIDEO_DIP_ENABLE_SPD (8 << 21) 1562 #define VIDEO_DIP_SELECT_AVI (0 << 19) 1563 #define VIDEO_DIP_SELECT_VENDOR (1 << 19) 1564 #define VIDEO_DIP_SELECT_GAMUT (2 << 19) 1565 #define VIDEO_DIP_SELECT_SPD (3 << 19) 1566 #define VIDEO_DIP_SELECT_MASK (3 << 19) 1567 #define VIDEO_DIP_FREQ_ONCE (0 << 16) 1568 #define VIDEO_DIP_FREQ_VSYNC (1 << 16) 1569 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) 1570 #define VIDEO_DIP_FREQ_MASK (3 << 16) 1571 /* HSW and later: */ 1572 #define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28) 1573 #define PSR_VSC_BIT_7_SET (1 << 27) 1574 #define VSC_SELECT_MASK (0x3 << 25) 1575 #define VSC_SELECT_SHIFT 25 1576 #define VSC_DIP_HW_HEA_DATA (0 << 25) 1577 #define VSC_DIP_HW_HEA_SW_DATA (1 << 25) 1578 #define VSC_DIP_HW_DATA_SW_HEA (2 << 25) 1579 #define VSC_DIP_SW_HEA_DATA (3 << 25) 1580 #define VDIP_ENABLE_PPS (1 << 24) 1581 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) 1582 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) 1583 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) 1584 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) 1585 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) 1586 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) 1587 /* ADL and later: */ 1588 #define VIDEO_DIP_ENABLE_AS_ADL REG_BIT(23) 1589 1590 /* Panel fitting */ 1591 #define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230) 1592 #define PFIT_ENABLE REG_BIT(31) 1593 #define PFIT_PIPE_MASK REG_GENMASK(30, 29) /* 965+ */ 1594 #define PFIT_PIPE(pipe) REG_FIELD_PREP(PFIT_PIPE_MASK, (pipe)) 1595 #define PFIT_SCALING_MASK REG_GENMASK(28, 26) /* 965+ */ 1596 #define PFIT_SCALING_AUTO REG_FIELD_PREP(PFIT_SCALING_MASK, 0) 1597 #define PFIT_SCALING_PROGRAMMED REG_FIELD_PREP(PFIT_SCALING_MASK, 1) 1598 #define PFIT_SCALING_PILLAR REG_FIELD_PREP(PFIT_SCALING_MASK, 2) 1599 #define PFIT_SCALING_LETTER REG_FIELD_PREP(PFIT_SCALING_MASK, 3) 1600 #define PFIT_FILTER_MASK REG_GENMASK(25, 24) /* 965+ */ 1601 #define PFIT_FILTER_FUZZY REG_FIELD_PREP(PFIT_FILTER_MASK, 0) 1602 #define PFIT_FILTER_CRISP REG_FIELD_PREP(PFIT_FILTER_MASK, 1) 1603 #define PFIT_FILTER_MEDIAN REG_FIELD_PREP(PFIT_FILTER_MASK, 2) 1604 #define PFIT_VERT_INTERP_MASK REG_GENMASK(11, 10) /* pre-965 */ 1605 #define PFIT_VERT_INTERP_BILINEAR REG_FIELD_PREP(PFIT_VERT_INTERP_MASK, 1) 1606 #define PFIT_VERT_AUTO_SCALE REG_BIT(9) /* pre-965 */ 1607 #define PFIT_HORIZ_INTERP_MASK REG_GENMASK(7, 6) /* pre-965 */ 1608 #define PFIT_HORIZ_INTERP_BILINEAR REG_FIELD_PREP(PFIT_HORIZ_INTERP_MASK, 1) 1609 #define PFIT_HORIZ_AUTO_SCALE REG_BIT(5) /* pre-965 */ 1610 #define PFIT_PANEL_8TO6_DITHER_ENABLE REG_BIT(3) /* pre-965 */ 1611 1612 #define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234) 1613 #define PFIT_VERT_SCALE_MASK REG_GENMASK(31, 20) /* pre-965 */ 1614 #define PFIT_VERT_SCALE(x) REG_FIELD_PREP(PFIT_VERT_SCALE_MASK, (x)) 1615 #define PFIT_HORIZ_SCALE_MASK REG_GENMASK(15, 4) /* pre-965 */ 1616 #define PFIT_HORIZ_SCALE(x) REG_FIELD_PREP(PFIT_HORIZ_SCALE_MASK, (x)) 1617 #define PFIT_VERT_SCALE_MASK_965 REG_GENMASK(28, 16) /* 965+ */ 1618 #define PFIT_HORIZ_SCALE_MASK_965 REG_GENMASK(12, 0) /* 965+ */ 1619 1620 #define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238) 1621 1622 #define PCH_GTC_CTL _MMIO(0xe7000) 1623 #define PCH_GTC_ENABLE (1 << 31) 1624 1625 /* Display Port */ 1626 #define DP_A _MMIO(0x64000) /* eDP */ 1627 #define DP_B _MMIO(0x64100) 1628 #define DP_C _MMIO(0x64200) 1629 #define DP_D _MMIO(0x64300) 1630 1631 #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100) 1632 #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200) 1633 #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300) 1634 1635 #define DP_PORT_EN (1 << 31) 1636 #define DP_PIPE_SEL_SHIFT 30 1637 #define DP_PIPE_SEL_MASK (1 << 30) 1638 #define DP_PIPE_SEL(pipe) ((pipe) << 30) 1639 #define DP_PIPE_SEL_SHIFT_IVB 29 1640 #define DP_PIPE_SEL_MASK_IVB (3 << 29) 1641 #define DP_PIPE_SEL_IVB(pipe) ((pipe) << 29) 1642 #define DP_PIPE_SEL_SHIFT_CHV 16 1643 #define DP_PIPE_SEL_MASK_CHV (3 << 16) 1644 #define DP_PIPE_SEL_CHV(pipe) ((pipe) << 16) 1645 1646 /* Link training mode - select a suitable mode for each stage */ 1647 #define DP_LINK_TRAIN_PAT_1 (0 << 28) 1648 #define DP_LINK_TRAIN_PAT_2 (1 << 28) 1649 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) 1650 #define DP_LINK_TRAIN_OFF (3 << 28) 1651 #define DP_LINK_TRAIN_MASK (3 << 28) 1652 #define DP_LINK_TRAIN_SHIFT 28 1653 1654 /* CPT Link training mode */ 1655 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) 1656 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) 1657 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) 1658 #define DP_LINK_TRAIN_OFF_CPT (3 << 8) 1659 #define DP_LINK_TRAIN_MASK_CPT (7 << 8) 1660 #define DP_LINK_TRAIN_SHIFT_CPT 8 1661 1662 /* Signal voltages. These are mostly controlled by the other end */ 1663 #define DP_VOLTAGE_0_4 (0 << 25) 1664 #define DP_VOLTAGE_0_6 (1 << 25) 1665 #define DP_VOLTAGE_0_8 (2 << 25) 1666 #define DP_VOLTAGE_1_2 (3 << 25) 1667 #define DP_VOLTAGE_MASK (7 << 25) 1668 #define DP_VOLTAGE_SHIFT 25 1669 1670 /* Signal pre-emphasis levels, like voltages, the other end tells us what 1671 * they want 1672 */ 1673 #define DP_PRE_EMPHASIS_0 (0 << 22) 1674 #define DP_PRE_EMPHASIS_3_5 (1 << 22) 1675 #define DP_PRE_EMPHASIS_6 (2 << 22) 1676 #define DP_PRE_EMPHASIS_9_5 (3 << 22) 1677 #define DP_PRE_EMPHASIS_MASK (7 << 22) 1678 #define DP_PRE_EMPHASIS_SHIFT 22 1679 1680 /* How many wires to use. I guess 3 was too hard */ 1681 #define DP_PORT_WIDTH(width) (((width) - 1) << 19) 1682 #define DP_PORT_WIDTH_MASK (7 << 19) 1683 #define DP_PORT_WIDTH_SHIFT 19 1684 1685 /* Mystic DPCD version 1.1 special mode */ 1686 #define DP_ENHANCED_FRAMING (1 << 18) 1687 1688 /* eDP */ 1689 #define DP_PLL_FREQ_270MHZ (0 << 16) 1690 #define DP_PLL_FREQ_162MHZ (1 << 16) 1691 #define DP_PLL_FREQ_MASK (3 << 16) 1692 1693 /* locked once port is enabled */ 1694 #define DP_PORT_REVERSAL (1 << 15) 1695 1696 /* eDP */ 1697 #define DP_PLL_ENABLE (1 << 14) 1698 1699 /* sends the clock on lane 15 of the PEG for debug */ 1700 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 1701 1702 #define DP_SCRAMBLING_DISABLE (1 << 12) 1703 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) 1704 1705 /* limit RGB values to avoid confusing TVs */ 1706 #define DP_COLOR_RANGE_16_235 (1 << 8) 1707 1708 /* Turn on the audio link */ 1709 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) 1710 1711 /* vs and hs sync polarity */ 1712 #define DP_SYNC_VS_HIGH (1 << 4) 1713 #define DP_SYNC_HS_HIGH (1 << 3) 1714 1715 /* A fantasy */ 1716 #define DP_DETECTED (1 << 2) 1717 1718 /* 1719 * Computing GMCH M and N values for the Display Port link 1720 * 1721 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes 1722 * 1723 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) 1724 * 1725 * The GMCH value is used internally 1726 * 1727 * bytes_per_pixel is the number of bytes coming out of the plane, 1728 * which is after the LUTs, so we want the bytes for our color format. 1729 * For our current usage, this is always 3, one byte for R, G and B. 1730 */ 1731 #define _PIPEA_DATA_M_G4X 0x70050 1732 #define _PIPEB_DATA_M_G4X 0x71050 1733 1734 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 1735 #define TU_SIZE_MASK REG_GENMASK(30, 25) 1736 #define TU_SIZE(x) REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */ 1737 1738 #define DATA_LINK_M_N_MASK REG_GENMASK(23, 0) 1739 #define DATA_LINK_N_MAX (0x800000) 1740 1741 #define _PIPEA_DATA_N_G4X 0x70054 1742 #define _PIPEB_DATA_N_G4X 0x71054 1743 1744 /* 1745 * Computing Link M and N values for the Display Port link 1746 * 1747 * Link M / N = pixel_clock / ls_clk 1748 * 1749 * (the DP spec calls pixel_clock the 'strm_clk') 1750 * 1751 * The Link value is transmitted in the Main Stream 1752 * Attributes and VB-ID. 1753 */ 1754 1755 #define _PIPEA_LINK_M_G4X 0x70060 1756 #define _PIPEB_LINK_M_G4X 0x71060 1757 #define _PIPEA_LINK_N_G4X 0x70064 1758 #define _PIPEB_LINK_N_G4X 0x71064 1759 1760 #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X) 1761 #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X) 1762 #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X) 1763 #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X) 1764 1765 /* Display & cursor control */ 1766 1767 /* Pipe A */ 1768 #define _PIPEADSL 0x70000 1769 #define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */ 1770 #define PIPEDSL_LINE_MASK REG_GENMASK(19, 0) 1771 #define _TRANSACONF 0x70008 1772 #define TRANSCONF_ENABLE REG_BIT(31) 1773 #define TRANSCONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */ 1774 #define TRANSCONF_STATE_ENABLE REG_BIT(30) /* i965+ */ 1775 #define TRANSCONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv & pipe A only */ 1776 #define TRANSCONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */ 1777 #define TRANSCONF_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANSCONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */ 1778 #define TRANSCONF_PIPE_LOCKED REG_BIT(25) 1779 #define TRANSCONF_FORCE_BORDER REG_BIT(25) 1780 #define TRANSCONF_GAMMA_MODE_MASK_I9XX REG_BIT(24) /* gmch */ 1781 #define TRANSCONF_GAMMA_MODE_MASK_ILK REG_GENMASK(25, 24) /* ilk-ivb */ 1782 #define TRANSCONF_GAMMA_MODE_8BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 0) 1783 #define TRANSCONF_GAMMA_MODE_10BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 1) 1784 #define TRANSCONF_GAMMA_MODE_12BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */ 1785 #define TRANSCONF_GAMMA_MODE_SPLIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */ 1786 #define TRANSCONF_GAMMA_MODE(x) REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */ 1787 #define TRANSCONF_INTERLACE_MASK REG_GENMASK(23, 21) /* gen3+ */ 1788 #define TRANSCONF_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 0) 1789 #define TRANSCONF_INTERLACE_W_SYNC_SHIFT_PANEL REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 4) /* gen4 only */ 1790 #define TRANSCONF_INTERLACE_W_SYNC_SHIFT REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 5) /* gen4 only */ 1791 #define TRANSCONF_INTERLACE_W_FIELD_INDICATION REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 6) 1792 #define TRANSCONF_INTERLACE_FIELD_0_ONLY REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 7) /* gen3 only */ 1793 /* 1794 * ilk+: PF/D=progressive fetch/display, IF/D=interlaced fetch/display, 1795 * DBL=power saving pixel doubling, PF-ID* requires panel fitter 1796 */ 1797 #define TRANSCONF_INTERLACE_MASK_ILK REG_GENMASK(23, 21) /* ilk+ */ 1798 #define TRANSCONF_INTERLACE_MASK_HSW REG_GENMASK(22, 21) /* hsw+ */ 1799 #define TRANSCONF_INTERLACE_PF_PD_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 0) 1800 #define TRANSCONF_INTERLACE_PF_ID_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 1) 1801 #define TRANSCONF_INTERLACE_IF_ID_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 3) 1802 #define TRANSCONF_INTERLACE_IF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */ 1803 #define TRANSCONF_INTERLACE_PF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */ 1804 #define TRANSCONF_REFRESH_RATE_ALT_ILK REG_BIT(20) 1805 #define TRANSCONF_MSA_TIMING_DELAY_MASK REG_GENMASK(19, 18) /* ilk/snb/ivb */ 1806 #define TRANSCONF_MSA_TIMING_DELAY(x) REG_FIELD_PREP(TRANSCONF_MSA_TIMING_DELAY_MASK, (x)) 1807 #define TRANSCONF_CXSR_DOWNCLOCK REG_BIT(16) 1808 #define TRANSCONF_WGC_ENABLE REG_BIT(15) /* vlv/chv only */ 1809 #define TRANSCONF_REFRESH_RATE_ALT_VLV REG_BIT(14) 1810 #define TRANSCONF_COLOR_RANGE_SELECT REG_BIT(13) 1811 #define TRANSCONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */ 1812 #define TRANSCONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */ 1813 #define TRANSCONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */ 1814 #define TRANSCONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */ 1815 #define TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11) /* hsw only */ 1816 #define TRANSCONF_BPC_MASK REG_GENMASK(7, 5) /* ctg-ivb */ 1817 #define TRANSCONF_BPC_8 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 0) 1818 #define TRANSCONF_BPC_10 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 1) 1819 #define TRANSCONF_BPC_6 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 2) 1820 #define TRANSCONF_BPC_12 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 3) 1821 #define TRANSCONF_DITHER_EN REG_BIT(4) 1822 #define TRANSCONF_DITHER_TYPE_MASK REG_GENMASK(3, 2) 1823 #define TRANSCONF_DITHER_TYPE_SP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 0) 1824 #define TRANSCONF_DITHER_TYPE_ST1 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 1) 1825 #define TRANSCONF_DITHER_TYPE_ST2 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 2) 1826 #define TRANSCONF_DITHER_TYPE_TEMP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 3) 1827 #define TRANSCONF_PIXEL_COUNT_SCALING_MASK REG_GENMASK(1, 0) 1828 #define TRANSCONF_PIXEL_COUNT_SCALING_X4 1 1829 1830 #define _PIPEASTAT 0x70024 1831 #define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31) 1832 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30) 1833 #define PIPE_CRC_ERROR_ENABLE (1UL << 29) 1834 #define PIPE_CRC_DONE_ENABLE (1UL << 28) 1835 #define PERF_COUNTER2_INTERRUPT_EN (1UL << 27) 1836 #define PIPE_GMBUS_EVENT_ENABLE (1UL << 27) 1837 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26) 1838 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26) 1839 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25) 1840 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24) 1841 #define PIPE_DPST_EVENT_ENABLE (1UL << 23) 1842 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22) 1843 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22) 1844 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21) 1845 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20) 1846 #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL << 19) 1847 #define PERF_COUNTER_INTERRUPT_EN (1UL << 19) 1848 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */ 1849 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) /* 965 or later */ 1850 #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL << 17) 1851 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17) 1852 #define PIPEA_HBLANK_INT_EN_VLV (1UL << 16) 1853 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16) 1854 #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL << 15) 1855 #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL << 14) 1856 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13) 1857 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12) 1858 #define PERF_COUNTER2_INTERRUPT_STATUS (1UL << 11) 1859 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11) 1860 #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL << 10) 1861 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10) 1862 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9) 1863 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8) 1864 #define PIPE_DPST_EVENT_STATUS (1UL << 7) 1865 #define PIPE_A_PSR_STATUS_VLV (1UL << 6) 1866 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6) 1867 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5) 1868 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4) 1869 #define PIPE_B_PSR_STATUS_VLV (1UL << 3) 1870 #define PERF_COUNTER_INTERRUPT_STATUS (1UL << 3) 1871 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */ 1872 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) /* 965 or later */ 1873 #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL << 1) 1874 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1) 1875 #define PIPE_HBLANK_INT_STATUS (1UL << 0) 1876 #define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0) 1877 1878 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 1879 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff 1880 1881 #define TRANSCONF(trans) _MMIO_PIPE2(dev_priv, (trans), _TRANSACONF) 1882 #define PIPEDSL(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEADSL) 1883 #define PIPEFRAME(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEHIGH) 1884 #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL) 1885 #define PIPESTAT(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT) 1886 1887 #define _PIPEAGCMAX 0x70010 1888 #define _PIPEBGCMAX 0x71010 1889 #define PIPEGCMAX(pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + (i) * 4) /* u1.16 */ 1890 1891 #define _PIPE_ARB_CTL_A 0x70028 /* icl+ */ 1892 #define PIPE_ARB_CTL(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPE_ARB_CTL_A) 1893 #define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13) 1894 1895 #define _PIPE_MISC_A 0x70030 1896 #define _PIPE_MISC_B 0x71030 1897 #define PIPE_MISC_YUV420_ENABLE REG_BIT(27) /* glk+ */ 1898 #define PIPE_MISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */ 1899 #define PIPE_MISC_HDR_MODE_PRECISION REG_BIT(23) /* icl+ */ 1900 #define PIPE_MISC_PSR_MASK_PRIMARY_FLIP REG_BIT(23) /* bdw */ 1901 #define PIPE_MISC_PSR_MASK_SPRITE_ENABLE REG_BIT(22) /* bdw */ 1902 #define PIPE_MISC_PSR_MASK_PIPE_REG_WRITE REG_BIT(21) /* skl+ */ 1903 #define PIPE_MISC_PSR_MASK_CURSOR_MOVE REG_BIT(21) /* bdw */ 1904 #define PIPE_MISC_PSR_MASK_VBLANK_VSYNC_INT REG_BIT(20) 1905 #define PIPE_MISC_OUTPUT_COLORSPACE_YUV REG_BIT(11) 1906 #define PIPE_MISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */ 1907 /* 1908 * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with 1909 * valid values of: 6, 8, 10 BPC. 1910 * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of: 1911 * 6, 8, 10, 12 BPC. 1912 */ 1913 #define PIPE_MISC_BPC_MASK REG_GENMASK(7, 5) 1914 #define PIPE_MISC_BPC_8 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 0) 1915 #define PIPE_MISC_BPC_10 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 1) 1916 #define PIPE_MISC_BPC_6 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 2) 1917 #define PIPE_MISC_BPC_12_ADLP REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 4) /* adlp+ */ 1918 #define PIPE_MISC_DITHER_ENABLE REG_BIT(4) 1919 #define PIPE_MISC_DITHER_TYPE_MASK REG_GENMASK(3, 2) 1920 #define PIPE_MISC_DITHER_TYPE_SP REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 0) 1921 #define PIPE_MISC_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 1) 1922 #define PIPE_MISC_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 2) 1923 #define PIPE_MISC_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 3) 1924 #define PIPE_MISC(pipe) _MMIO_PIPE(pipe, _PIPE_MISC_A, _PIPE_MISC_B) 1925 1926 #define _PIPE_MISC2_A 0x7002C 1927 #define _PIPE_MISC2_B 0x7102C 1928 #define PIPE_MISC2_BUBBLE_COUNTER_MASK REG_GENMASK(31, 24) 1929 #define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80) 1930 #define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20) 1931 #define PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK REG_GENMASK(2, 0) /* tgl+ */ 1932 #define PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id) REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id)) 1933 #define PIPE_MISC2(pipe) _MMIO_PIPE(pipe, _PIPE_MISC2_A, _PIPE_MISC2_B) 1934 1935 #define _ICL_PIPE_A_STATUS 0x70058 1936 #define ICL_PIPESTATUS(pipe) _MMIO_PIPE2(dev_priv, pipe, _ICL_PIPE_A_STATUS) 1937 #define PIPE_STATUS_UNDERRUN REG_BIT(31) 1938 #define PIPE_STATUS_SOFT_UNDERRUN_XELPD REG_BIT(28) 1939 #define PIPE_STATUS_HARD_UNDERRUN_XELPD REG_BIT(27) 1940 #define PIPE_STATUS_PORT_UNDERRUN_XELPD REG_BIT(26) 1941 1942 #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028) 1943 #define PIPEB_LINE_COMPARE_INT_EN REG_BIT(29) 1944 #define PIPEB_HLINE_INT_EN REG_BIT(28) 1945 #define PIPEB_VBLANK_INT_EN REG_BIT(27) 1946 #define SPRITED_FLIP_DONE_INT_EN REG_BIT(26) 1947 #define SPRITEC_FLIP_DONE_INT_EN REG_BIT(25) 1948 #define PLANEB_FLIP_DONE_INT_EN REG_BIT(24) 1949 #define PIPE_PSR_INT_EN REG_BIT(22) 1950 #define PIPEA_LINE_COMPARE_INT_EN REG_BIT(21) 1951 #define PIPEA_HLINE_INT_EN REG_BIT(20) 1952 #define PIPEA_VBLANK_INT_EN REG_BIT(19) 1953 #define SPRITEB_FLIP_DONE_INT_EN REG_BIT(18) 1954 #define SPRITEA_FLIP_DONE_INT_EN REG_BIT(17) 1955 #define PLANEA_FLIPDONE_INT_EN REG_BIT(16) 1956 #define PIPEC_LINE_COMPARE_INT_EN REG_BIT(13) 1957 #define PIPEC_HLINE_INT_EN REG_BIT(12) 1958 #define PIPEC_VBLANK_INT_EN REG_BIT(11) 1959 #define SPRITEF_FLIPDONE_INT_EN REG_BIT(10) 1960 #define SPRITEE_FLIPDONE_INT_EN REG_BIT(9) 1961 #define PLANEC_FLIPDONE_INT_EN REG_BIT(8) 1962 1963 #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ 1964 #define DPINVGTT_EN_MASK_CHV REG_GENMASK(27, 16) 1965 #define DPINVGTT_EN_MASK_VLV REG_GENMASK(23, 16) 1966 #define SPRITEF_INVALID_GTT_INT_EN REG_BIT(27) 1967 #define SPRITEE_INVALID_GTT_INT_EN REG_BIT(26) 1968 #define PLANEC_INVALID_GTT_INT_EN REG_BIT(25) 1969 #define CURSORC_INVALID_GTT_INT_EN REG_BIT(24) 1970 #define CURSORB_INVALID_GTT_INT_EN REG_BIT(23) 1971 #define CURSORA_INVALID_GTT_INT_EN REG_BIT(22) 1972 #define SPRITED_INVALID_GTT_INT_EN REG_BIT(21) 1973 #define SPRITEC_INVALID_GTT_INT_EN REG_BIT(20) 1974 #define PLANEB_INVALID_GTT_INT_EN REG_BIT(19) 1975 #define SPRITEB_INVALID_GTT_INT_EN REG_BIT(18) 1976 #define SPRITEA_INVALID_GTT_INT_EN REG_BIT(17) 1977 #define PLANEA_INVALID_GTT_INT_EN REG_BIT(16) 1978 #define DPINVGTT_STATUS_MASK_CHV REG_GENMASK(11, 0) 1979 #define DPINVGTT_STATUS_MASK_VLV REG_GENMASK(7, 0) 1980 #define SPRITEF_INVALID_GTT_STATUS REG_BIT(11) 1981 #define SPRITEE_INVALID_GTT_STATUS REG_BIT(10) 1982 #define PLANEC_INVALID_GTT_STATUS REG_BIT(9) 1983 #define CURSORC_INVALID_GTT_STATUS REG_BIT(8) 1984 #define CURSORB_INVALID_GTT_STATUS REG_BIT(7) 1985 #define CURSORA_INVALID_GTT_STATUS REG_BIT(6) 1986 #define SPRITED_INVALID_GTT_STATUS REG_BIT(5) 1987 #define SPRITEC_INVALID_GTT_STATUS REG_BIT(4) 1988 #define PLANEB_INVALID_GTT_STATUS REG_BIT(3) 1989 #define SPRITEB_INVALID_GTT_STATUS REG_BIT(2) 1990 #define SPRITEA_INVALID_GTT_STATUS REG_BIT(1) 1991 #define PLANEA_INVALID_GTT_STATUS REG_BIT(0) 1992 1993 #define DSPARB _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030) 1994 #define DSPARB_CSTART_MASK (0x7f << 7) 1995 #define DSPARB_CSTART_SHIFT 7 1996 #define DSPARB_BSTART_MASK (0x7f) 1997 #define DSPARB_BSTART_SHIFT 0 1998 #define DSPARB_BEND_SHIFT 9 /* on 855 */ 1999 #define DSPARB_AEND_SHIFT 0 2000 #define DSPARB_SPRITEA_SHIFT_VLV 0 2001 #define DSPARB_SPRITEA_MASK_VLV (0xff << 0) 2002 #define DSPARB_SPRITEB_SHIFT_VLV 8 2003 #define DSPARB_SPRITEB_MASK_VLV (0xff << 8) 2004 #define DSPARB_SPRITEC_SHIFT_VLV 16 2005 #define DSPARB_SPRITEC_MASK_VLV (0xff << 16) 2006 #define DSPARB_SPRITED_SHIFT_VLV 24 2007 #define DSPARB_SPRITED_MASK_VLV (0xff << 24) 2008 #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */ 2009 #define DSPARB_SPRITEA_HI_SHIFT_VLV 0 2010 #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0) 2011 #define DSPARB_SPRITEB_HI_SHIFT_VLV 4 2012 #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4) 2013 #define DSPARB_SPRITEC_HI_SHIFT_VLV 8 2014 #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8) 2015 #define DSPARB_SPRITED_HI_SHIFT_VLV 12 2016 #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12) 2017 #define DSPARB_SPRITEE_HI_SHIFT_VLV 16 2018 #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16) 2019 #define DSPARB_SPRITEF_HI_SHIFT_VLV 20 2020 #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20) 2021 #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */ 2022 #define DSPARB_SPRITEE_SHIFT_VLV 0 2023 #define DSPARB_SPRITEE_MASK_VLV (0xff << 0) 2024 #define DSPARB_SPRITEF_SHIFT_VLV 8 2025 #define DSPARB_SPRITEF_MASK_VLV (0xff << 8) 2026 2027 /* pnv/gen4/g4x/vlv/chv */ 2028 #define DSPFW1 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034) 2029 #define DSPFW_SR_SHIFT 23 2030 #define DSPFW_SR_MASK (0x1ff << 23) 2031 #define DSPFW_CURSORB_SHIFT 16 2032 #define DSPFW_CURSORB_MASK (0x3f << 16) 2033 #define DSPFW_PLANEB_SHIFT 8 2034 #define DSPFW_PLANEB_MASK (0x7f << 8) 2035 #define DSPFW_PLANEB_MASK_VLV (0xff << 8) /* vlv/chv */ 2036 #define DSPFW_PLANEA_SHIFT 0 2037 #define DSPFW_PLANEA_MASK (0x7f << 0) 2038 #define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */ 2039 #define DSPFW2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038) 2040 #define DSPFW_FBC_SR_EN (1 << 31) /* g4x */ 2041 #define DSPFW_FBC_SR_SHIFT 28 2042 #define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */ 2043 #define DSPFW_FBC_HPLL_SR_SHIFT 24 2044 #define DSPFW_FBC_HPLL_SR_MASK (0xf << 24) /* g4x */ 2045 #define DSPFW_SPRITEB_SHIFT (16) 2046 #define DSPFW_SPRITEB_MASK (0x7f << 16) /* g4x */ 2047 #define DSPFW_SPRITEB_MASK_VLV (0xff << 16) /* vlv/chv */ 2048 #define DSPFW_CURSORA_SHIFT 8 2049 #define DSPFW_CURSORA_MASK (0x3f << 8) 2050 #define DSPFW_PLANEC_OLD_SHIFT 0 2051 #define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */ 2052 #define DSPFW_SPRITEA_SHIFT 0 2053 #define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */ 2054 #define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */ 2055 #define DSPFW3 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c) 2056 #define DSPFW_HPLL_SR_EN (1 << 31) 2057 #define PINEVIEW_SELF_REFRESH_EN (1 << 30) 2058 #define DSPFW_CURSOR_SR_SHIFT 24 2059 #define DSPFW_CURSOR_SR_MASK (0x3f << 24) 2060 #define DSPFW_HPLL_CURSOR_SHIFT 16 2061 #define DSPFW_HPLL_CURSOR_MASK (0x3f << 16) 2062 #define DSPFW_HPLL_SR_SHIFT 0 2063 #define DSPFW_HPLL_SR_MASK (0x1ff << 0) 2064 2065 /* vlv/chv */ 2066 #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070) 2067 #define DSPFW_SPRITEB_WM1_SHIFT 16 2068 #define DSPFW_SPRITEB_WM1_MASK (0xff << 16) 2069 #define DSPFW_CURSORA_WM1_SHIFT 8 2070 #define DSPFW_CURSORA_WM1_MASK (0x3f << 8) 2071 #define DSPFW_SPRITEA_WM1_SHIFT 0 2072 #define DSPFW_SPRITEA_WM1_MASK (0xff << 0) 2073 #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074) 2074 #define DSPFW_PLANEB_WM1_SHIFT 24 2075 #define DSPFW_PLANEB_WM1_MASK (0xff << 24) 2076 #define DSPFW_PLANEA_WM1_SHIFT 16 2077 #define DSPFW_PLANEA_WM1_MASK (0xff << 16) 2078 #define DSPFW_CURSORB_WM1_SHIFT 8 2079 #define DSPFW_CURSORB_WM1_MASK (0x3f << 8) 2080 #define DSPFW_CURSOR_SR_WM1_SHIFT 0 2081 #define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0) 2082 #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078) 2083 #define DSPFW_SR_WM1_SHIFT 0 2084 #define DSPFW_SR_WM1_MASK (0x1ff << 0) 2085 #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c) 2086 #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */ 2087 #define DSPFW_SPRITED_WM1_SHIFT 24 2088 #define DSPFW_SPRITED_WM1_MASK (0xff << 24) 2089 #define DSPFW_SPRITED_SHIFT 16 2090 #define DSPFW_SPRITED_MASK_VLV (0xff << 16) 2091 #define DSPFW_SPRITEC_WM1_SHIFT 8 2092 #define DSPFW_SPRITEC_WM1_MASK (0xff << 8) 2093 #define DSPFW_SPRITEC_SHIFT 0 2094 #define DSPFW_SPRITEC_MASK_VLV (0xff << 0) 2095 #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8) 2096 #define DSPFW_SPRITEF_WM1_SHIFT 24 2097 #define DSPFW_SPRITEF_WM1_MASK (0xff << 24) 2098 #define DSPFW_SPRITEF_SHIFT 16 2099 #define DSPFW_SPRITEF_MASK_VLV (0xff << 16) 2100 #define DSPFW_SPRITEE_WM1_SHIFT 8 2101 #define DSPFW_SPRITEE_WM1_MASK (0xff << 8) 2102 #define DSPFW_SPRITEE_SHIFT 0 2103 #define DSPFW_SPRITEE_MASK_VLV (0xff << 0) 2104 #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */ 2105 #define DSPFW_PLANEC_WM1_SHIFT 24 2106 #define DSPFW_PLANEC_WM1_MASK (0xff << 24) 2107 #define DSPFW_PLANEC_SHIFT 16 2108 #define DSPFW_PLANEC_MASK_VLV (0xff << 16) 2109 #define DSPFW_CURSORC_WM1_SHIFT 8 2110 #define DSPFW_CURSORC_WM1_MASK (0x3f << 16) 2111 #define DSPFW_CURSORC_SHIFT 0 2112 #define DSPFW_CURSORC_MASK (0x3f << 0) 2113 2114 /* vlv/chv high order bits */ 2115 #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064) 2116 #define DSPFW_SR_HI_SHIFT 24 2117 #define DSPFW_SR_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */ 2118 #define DSPFW_SPRITEF_HI_SHIFT 23 2119 #define DSPFW_SPRITEF_HI_MASK (1 << 23) 2120 #define DSPFW_SPRITEE_HI_SHIFT 22 2121 #define DSPFW_SPRITEE_HI_MASK (1 << 22) 2122 #define DSPFW_PLANEC_HI_SHIFT 21 2123 #define DSPFW_PLANEC_HI_MASK (1 << 21) 2124 #define DSPFW_SPRITED_HI_SHIFT 20 2125 #define DSPFW_SPRITED_HI_MASK (1 << 20) 2126 #define DSPFW_SPRITEC_HI_SHIFT 16 2127 #define DSPFW_SPRITEC_HI_MASK (1 << 16) 2128 #define DSPFW_PLANEB_HI_SHIFT 12 2129 #define DSPFW_PLANEB_HI_MASK (1 << 12) 2130 #define DSPFW_SPRITEB_HI_SHIFT 8 2131 #define DSPFW_SPRITEB_HI_MASK (1 << 8) 2132 #define DSPFW_SPRITEA_HI_SHIFT 4 2133 #define DSPFW_SPRITEA_HI_MASK (1 << 4) 2134 #define DSPFW_PLANEA_HI_SHIFT 0 2135 #define DSPFW_PLANEA_HI_MASK (1 << 0) 2136 #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068) 2137 #define DSPFW_SR_WM1_HI_SHIFT 24 2138 #define DSPFW_SR_WM1_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */ 2139 #define DSPFW_SPRITEF_WM1_HI_SHIFT 23 2140 #define DSPFW_SPRITEF_WM1_HI_MASK (1 << 23) 2141 #define DSPFW_SPRITEE_WM1_HI_SHIFT 22 2142 #define DSPFW_SPRITEE_WM1_HI_MASK (1 << 22) 2143 #define DSPFW_PLANEC_WM1_HI_SHIFT 21 2144 #define DSPFW_PLANEC_WM1_HI_MASK (1 << 21) 2145 #define DSPFW_SPRITED_WM1_HI_SHIFT 20 2146 #define DSPFW_SPRITED_WM1_HI_MASK (1 << 20) 2147 #define DSPFW_SPRITEC_WM1_HI_SHIFT 16 2148 #define DSPFW_SPRITEC_WM1_HI_MASK (1 << 16) 2149 #define DSPFW_PLANEB_WM1_HI_SHIFT 12 2150 #define DSPFW_PLANEB_WM1_HI_MASK (1 << 12) 2151 #define DSPFW_SPRITEB_WM1_HI_SHIFT 8 2152 #define DSPFW_SPRITEB_WM1_HI_MASK (1 << 8) 2153 #define DSPFW_SPRITEA_WM1_HI_SHIFT 4 2154 #define DSPFW_SPRITEA_WM1_HI_MASK (1 << 4) 2155 #define DSPFW_PLANEA_WM1_HI_SHIFT 0 2156 #define DSPFW_PLANEA_WM1_HI_MASK (1 << 0) 2157 2158 /* drain latency register values*/ 2159 #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe)) 2160 #define DDL_CURSOR_SHIFT 24 2161 #define DDL_SPRITE_SHIFT(sprite) (8 + 8 * (sprite)) 2162 #define DDL_PLANE_SHIFT 0 2163 #define DDL_PRECISION_HIGH (1 << 7) 2164 #define DDL_PRECISION_LOW (0 << 7) 2165 #define DRAIN_LATENCY_MASK 0x7f 2166 2167 #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400) 2168 #define CBR_PND_DEADLINE_DISABLE (1 << 31) 2169 #define CBR_PWM_CLOCK_MUX_SELECT (1 << 30) 2170 2171 #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450) 2172 #define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */ 2173 2174 /* FIFO watermark sizes etc */ 2175 #define G4X_FIFO_LINE_SIZE 64 2176 #define I915_FIFO_LINE_SIZE 64 2177 #define I830_FIFO_LINE_SIZE 32 2178 2179 #define VALLEYVIEW_FIFO_SIZE 255 2180 #define G4X_FIFO_SIZE 127 2181 #define I965_FIFO_SIZE 512 2182 #define I945_FIFO_SIZE 127 2183 #define I915_FIFO_SIZE 95 2184 #define I855GM_FIFO_SIZE 127 /* In cachelines */ 2185 #define I830_FIFO_SIZE 95 2186 2187 #define VALLEYVIEW_MAX_WM 0xff 2188 #define G4X_MAX_WM 0x3f 2189 #define I915_MAX_WM 0x3f 2190 2191 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ 2192 #define PINEVIEW_FIFO_LINE_SIZE 64 2193 #define PINEVIEW_MAX_WM 0x1ff 2194 #define PINEVIEW_DFT_WM 0x3f 2195 #define PINEVIEW_DFT_HPLLOFF_WM 0 2196 #define PINEVIEW_GUARD_WM 10 2197 #define PINEVIEW_CURSOR_FIFO 64 2198 #define PINEVIEW_CURSOR_MAX_WM 0x3f 2199 #define PINEVIEW_CURSOR_DFT_WM 0 2200 #define PINEVIEW_CURSOR_GUARD_WM 5 2201 2202 #define VALLEYVIEW_CURSOR_MAX_WM 64 2203 #define I965_CURSOR_FIFO 64 2204 #define I965_CURSOR_MAX_WM 32 2205 #define I965_CURSOR_DFT_WM 8 2206 2207 /* define the Watermark register on Ironlake */ 2208 #define _WM0_PIPEA_ILK 0x45100 2209 #define _WM0_PIPEB_ILK 0x45104 2210 #define _WM0_PIPEC_IVB 0x45200 2211 #define WM0_PIPE_ILK(pipe) _MMIO_BASE_PIPE3(0, (pipe), _WM0_PIPEA_ILK, \ 2212 _WM0_PIPEB_ILK, _WM0_PIPEC_IVB) 2213 #define WM0_PIPE_PRIMARY_MASK REG_GENMASK(31, 16) 2214 #define WM0_PIPE_SPRITE_MASK REG_GENMASK(15, 8) 2215 #define WM0_PIPE_CURSOR_MASK REG_GENMASK(7, 0) 2216 #define WM0_PIPE_PRIMARY(x) REG_FIELD_PREP(WM0_PIPE_PRIMARY_MASK, (x)) 2217 #define WM0_PIPE_SPRITE(x) REG_FIELD_PREP(WM0_PIPE_SPRITE_MASK, (x)) 2218 #define WM0_PIPE_CURSOR(x) REG_FIELD_PREP(WM0_PIPE_CURSOR_MASK, (x)) 2219 #define WM1_LP_ILK _MMIO(0x45108) 2220 #define WM2_LP_ILK _MMIO(0x4510c) 2221 #define WM3_LP_ILK _MMIO(0x45110) 2222 #define WM_LP_ENABLE REG_BIT(31) 2223 #define WM_LP_LATENCY_MASK REG_GENMASK(30, 24) 2224 #define WM_LP_FBC_MASK_BDW REG_GENMASK(23, 19) 2225 #define WM_LP_FBC_MASK_ILK REG_GENMASK(23, 20) 2226 #define WM_LP_PRIMARY_MASK REG_GENMASK(18, 8) 2227 #define WM_LP_CURSOR_MASK REG_GENMASK(7, 0) 2228 #define WM_LP_LATENCY(x) REG_FIELD_PREP(WM_LP_LATENCY_MASK, (x)) 2229 #define WM_LP_FBC_BDW(x) REG_FIELD_PREP(WM_LP_FBC_MASK_BDW, (x)) 2230 #define WM_LP_FBC_ILK(x) REG_FIELD_PREP(WM_LP_FBC_MASK_ILK, (x)) 2231 #define WM_LP_PRIMARY(x) REG_FIELD_PREP(WM_LP_PRIMARY_MASK, (x)) 2232 #define WM_LP_CURSOR(x) REG_FIELD_PREP(WM_LP_CURSOR_MASK, (x)) 2233 #define WM1S_LP_ILK _MMIO(0x45120) 2234 #define WM2S_LP_IVB _MMIO(0x45124) 2235 #define WM3S_LP_IVB _MMIO(0x45128) 2236 #define WM_LP_SPRITE_ENABLE REG_BIT(31) /* ilk/snb WM1S only */ 2237 #define WM_LP_SPRITE_MASK REG_GENMASK(10, 0) 2238 #define WM_LP_SPRITE(x) REG_FIELD_PREP(WM_LP_SPRITE_MASK, (x)) 2239 2240 /* 2241 * The two pipe frame counter registers are not synchronized, so 2242 * reading a stable value is somewhat tricky. The following code 2243 * should work: 2244 * 2245 * do { 2246 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 2247 * PIPE_FRAME_HIGH_SHIFT; 2248 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 2249 * PIPE_FRAME_LOW_SHIFT); 2250 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 2251 * PIPE_FRAME_HIGH_SHIFT); 2252 * } while (high1 != high2); 2253 * frame = (high1 << 8) | low1; 2254 */ 2255 #define _PIPEAFRAMEHIGH 0x70040 2256 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 2257 #define PIPE_FRAME_HIGH_SHIFT 0 2258 #define _PIPEAFRAMEPIXEL 0x70044 2259 #define PIPE_FRAME_LOW_MASK 0xff000000 2260 #define PIPE_FRAME_LOW_SHIFT 24 2261 #define PIPE_PIXEL_MASK 0x00ffffff 2262 #define PIPE_PIXEL_SHIFT 0 2263 /* GM45+ just has to be different */ 2264 #define _PIPEA_FRMCOUNT_G4X 0x70040 2265 #define _PIPEA_FLIPCOUNT_G4X 0x70044 2266 #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FRMCOUNT_G4X) 2267 #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FLIPCOUNT_G4X) 2268 2269 /* Cursor A & B regs */ 2270 #define _CURACNTR 0x70080 2271 /* Old style CUR*CNTR flags (desktop 8xx) */ 2272 #define CURSOR_ENABLE REG_BIT(31) 2273 #define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30) 2274 #define CURSOR_STRIDE_MASK REG_GENMASK(29, 28) 2275 #define CURSOR_STRIDE(stride) REG_FIELD_PREP(CURSOR_STRIDE_MASK, ffs(stride) - 9) /* 256,512,1k,2k */ 2276 #define CURSOR_FORMAT_MASK REG_GENMASK(26, 24) 2277 #define CURSOR_FORMAT_2C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 0) 2278 #define CURSOR_FORMAT_3C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 1) 2279 #define CURSOR_FORMAT_4C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 2) 2280 #define CURSOR_FORMAT_ARGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 4) 2281 #define CURSOR_FORMAT_XRGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 5) 2282 /* New style CUR*CNTR flags */ 2283 #define MCURSOR_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ 2284 #define MCURSOR_ARB_SLOTS(x) REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */ 2285 #define MCURSOR_PIPE_SEL_MASK REG_GENMASK(29, 28) 2286 #define MCURSOR_PIPE_SEL(pipe) REG_FIELD_PREP(MCURSOR_PIPE_SEL_MASK, (pipe)) 2287 #define MCURSOR_PIPE_GAMMA_ENABLE REG_BIT(26) 2288 #define MCURSOR_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ 2289 #define MCURSOR_ROTATE_180 REG_BIT(15) 2290 #define MCURSOR_TRICKLE_FEED_DISABLE REG_BIT(14) 2291 #define MCURSOR_MODE_MASK 0x27 2292 #define MCURSOR_MODE_DISABLE 0x00 2293 #define MCURSOR_MODE_128_32B_AX 0x02 2294 #define MCURSOR_MODE_256_32B_AX 0x03 2295 #define MCURSOR_MODE_64_2B 0x04 2296 #define MCURSOR_MODE_64_32B_AX 0x07 2297 #define MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX) 2298 #define MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX) 2299 #define MCURSOR_MODE_64_ARGB_AX (0x20 | MCURSOR_MODE_64_32B_AX) 2300 #define _CURABASE 0x70084 2301 #define _CURAPOS 0x70088 2302 #define _CURAPOS_ERLY_TPT 0x7008c 2303 #define CURSOR_POS_Y_SIGN REG_BIT(31) 2304 #define CURSOR_POS_Y_MASK REG_GENMASK(30, 16) 2305 #define CURSOR_POS_Y(y) REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y)) 2306 #define CURSOR_POS_X_SIGN REG_BIT(15) 2307 #define CURSOR_POS_X_MASK REG_GENMASK(14, 0) 2308 #define CURSOR_POS_X(x) REG_FIELD_PREP(CURSOR_POS_X_MASK, (x)) 2309 #define _CURASIZE 0x700a0 /* 845/865 */ 2310 #define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12) 2311 #define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h)) 2312 #define CURSOR_WIDTH_MASK REG_GENMASK(9, 0) 2313 #define CURSOR_WIDTH(w) REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w)) 2314 #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */ 2315 #define CUR_FBC_EN REG_BIT(31) 2316 #define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0) 2317 #define CUR_FBC_HEIGHT(h) REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h)) 2318 #define _CUR_CHICKEN_A 0x700a4 /* mtl+ */ 2319 #define _CURASURFLIVE 0x700ac /* g4x+ */ 2320 #define _CURBCNTR 0x700c0 2321 #define _CURBBASE 0x700c4 2322 #define _CURBPOS 0x700c8 2323 2324 #define _CURBCNTR_IVB 0x71080 2325 #define _CURBBASE_IVB 0x71084 2326 #define _CURBPOS_IVB 0x71088 2327 2328 #define CURCNTR(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURACNTR) 2329 #define CURBASE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURABASE) 2330 #define CURPOS(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS) 2331 #define CURPOS_ERLY_TPT(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS_ERLY_TPT) 2332 #define CURSIZE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE) 2333 #define CUR_FBC_CTL(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_FBC_CTL_A) 2334 #define CUR_CHICKEN(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_CHICKEN_A) 2335 #define CURSURFLIVE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASURFLIVE) 2336 2337 /* Display A control */ 2338 #define _DSPAADDR_VLV 0x7017C /* vlv/chv */ 2339 #define _DSPACNTR 0x70180 2340 #define DISP_ENABLE REG_BIT(31) 2341 #define DISP_PIPE_GAMMA_ENABLE REG_BIT(30) 2342 #define DISP_FORMAT_MASK REG_GENMASK(29, 26) 2343 #define DISP_FORMAT_8BPP REG_FIELD_PREP(DISP_FORMAT_MASK, 2) 2344 #define DISP_FORMAT_BGRA555 REG_FIELD_PREP(DISP_FORMAT_MASK, 3) 2345 #define DISP_FORMAT_BGRX555 REG_FIELD_PREP(DISP_FORMAT_MASK, 4) 2346 #define DISP_FORMAT_BGRX565 REG_FIELD_PREP(DISP_FORMAT_MASK, 5) 2347 #define DISP_FORMAT_BGRX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 6) 2348 #define DISP_FORMAT_BGRA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 7) 2349 #define DISP_FORMAT_RGBX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 8) 2350 #define DISP_FORMAT_RGBA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 9) 2351 #define DISP_FORMAT_BGRX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 10) 2352 #define DISP_FORMAT_BGRA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 11) 2353 #define DISP_FORMAT_RGBX161616 REG_FIELD_PREP(DISP_FORMAT_MASK, 12) 2354 #define DISP_FORMAT_RGBX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 14) 2355 #define DISP_FORMAT_RGBA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 15) 2356 #define DISP_STEREO_ENABLE REG_BIT(25) 2357 #define DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ 2358 #define DISP_PIPE_SEL_MASK REG_GENMASK(25, 24) 2359 #define DISP_PIPE_SEL(pipe) REG_FIELD_PREP(DISP_PIPE_SEL_MASK, (pipe)) 2360 #define DISP_SRC_KEY_ENABLE REG_BIT(22) 2361 #define DISP_LINE_DOUBLE REG_BIT(20) 2362 #define DISP_STEREO_POLARITY_SECOND REG_BIT(18) 2363 #define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */ 2364 #define DISP_ROTATE_180 REG_BIT(15) 2365 #define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */ 2366 #define DISP_TILED REG_BIT(10) 2367 #define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */ 2368 #define DISP_MIRROR REG_BIT(8) /* CHV pipe B */ 2369 #define _DSPAADDR 0x70184 2370 #define _DSPASTRIDE 0x70188 2371 #define _DSPAPOS 0x7018C /* reserved */ 2372 #define DISP_POS_Y_MASK REG_GENMASK(31, 16) 2373 #define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y)) 2374 #define DISP_POS_X_MASK REG_GENMASK(15, 0) 2375 #define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x)) 2376 #define _DSPASIZE 0x70190 2377 #define DISP_HEIGHT_MASK REG_GENMASK(31, 16) 2378 #define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h)) 2379 #define DISP_WIDTH_MASK REG_GENMASK(15, 0) 2380 #define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w)) 2381 #define _DSPASURF 0x7019C /* 965+ only */ 2382 #define DISP_ADDR_MASK REG_GENMASK(31, 12) 2383 #define _DSPATILEOFF 0x701A4 /* 965+ only */ 2384 #define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16) 2385 #define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y)) 2386 #define DISP_OFFSET_X_MASK REG_GENMASK(15, 0) 2387 #define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x)) 2388 #define _DSPAOFFSET 0x701A4 /* HSW */ 2389 #define _DSPASURFLIVE 0x701AC 2390 #define _DSPAGAMC 0x701E0 2391 2392 #define DSPADDR_VLV(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV) 2393 #define DSPCNTR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR) 2394 #define DSPADDR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR) 2395 #define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE) 2396 #define DSPPOS(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS) 2397 #define DSPSIZE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE) 2398 #define DSPSURF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF) 2399 #define DSPTILEOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF) 2400 #define DSPLINOFF(plane) DSPADDR(plane) 2401 #define DSPOFFSET(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET) 2402 #define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE) 2403 #define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ 2404 2405 /* CHV pipe B blender and primary plane */ 2406 #define _CHV_BLEND_A 0x60a00 2407 #define CHV_BLEND_MASK REG_GENMASK(31, 30) 2408 #define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0) 2409 #define CHV_BLEND_ANDROID REG_FIELD_PREP(CHV_BLEND_MASK, 1) 2410 #define CHV_BLEND_MPO REG_FIELD_PREP(CHV_BLEND_MASK, 2) 2411 #define _CHV_CANVAS_A 0x60a04 2412 #define CHV_CANVAS_RED_MASK REG_GENMASK(29, 20) 2413 #define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10) 2414 #define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0) 2415 #define _PRIMPOS_A 0x60a08 2416 #define PRIM_POS_Y_MASK REG_GENMASK(31, 16) 2417 #define PRIM_POS_Y(y) REG_FIELD_PREP(PRIM_POS_Y_MASK, (y)) 2418 #define PRIM_POS_X_MASK REG_GENMASK(15, 0) 2419 #define PRIM_POS_X(x) REG_FIELD_PREP(PRIM_POS_X_MASK, (x)) 2420 #define _PRIMSIZE_A 0x60a0c 2421 #define PRIM_HEIGHT_MASK REG_GENMASK(31, 16) 2422 #define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h)) 2423 #define PRIM_WIDTH_MASK REG_GENMASK(15, 0) 2424 #define PRIM_WIDTH(w) REG_FIELD_PREP(PRIM_WIDTH_MASK, (w)) 2425 #define _PRIMCNSTALPHA_A 0x60a10 2426 #define PRIM_CONST_ALPHA_ENABLE REG_BIT(31) 2427 #define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0) 2428 #define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha)) 2429 2430 #define CHV_BLEND(pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_BLEND_A) 2431 #define CHV_CANVAS(pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_CANVAS_A) 2432 #define PRIMPOS(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMPOS_A) 2433 #define PRIMSIZE(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMSIZE_A) 2434 #define PRIMCNSTALPHA(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMCNSTALPHA_A) 2435 2436 /* Display/Sprite base address macros */ 2437 #define DISP_BASEADDR_MASK (0xfffff000) 2438 #define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK) 2439 #define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK) 2440 2441 /* 2442 * VBIOS flags 2443 * gen2: 2444 * [00:06] alm,mgm 2445 * [10:16] all 2446 * [30:32] alm,mgm 2447 * gen3+: 2448 * [00:0f] all 2449 * [10:1f] all 2450 * [30:32] all 2451 */ 2452 #define SWF0(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4) 2453 #define SWF1(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4) 2454 #define SWF3(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4) 2455 #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) 2456 2457 /* Pipe B */ 2458 #define _PIPEBDSL (DISPLAY_MMIO_BASE(dev_priv) + 0x71000) 2459 #define _TRANSBCONF (DISPLAY_MMIO_BASE(dev_priv) + 0x71008) 2460 #define _PIPEBSTAT (DISPLAY_MMIO_BASE(dev_priv) + 0x71024) 2461 #define _PIPEBFRAMEHIGH 0x71040 2462 #define _PIPEBFRAMEPIXEL 0x71044 2463 #define _PIPEB_FRMCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71040) 2464 #define _PIPEB_FLIPCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71044) 2465 2466 2467 /* Display B control */ 2468 #define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180) 2469 #define DISP_ALPHA_TRANS_ENABLE REG_BIT(15) 2470 #define DISP_SPRITE_ABOVE_OVERLAY REG_BIT(0) 2471 #define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184) 2472 #define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188) 2473 #define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C) 2474 #define _DSPBSIZE (DISPLAY_MMIO_BASE(dev_priv) + 0x71190) 2475 #define _DSPBSURF (DISPLAY_MMIO_BASE(dev_priv) + 0x7119C) 2476 #define _DSPBTILEOFF (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) 2477 #define _DSPBOFFSET (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) 2478 #define _DSPBSURFLIVE (DISPLAY_MMIO_BASE(dev_priv) + 0x711AC) 2479 2480 /* ICL DSI 0 and 1 */ 2481 #define _PIPEDSI0CONF 0x7b008 2482 #define _PIPEDSI1CONF 0x7b808 2483 2484 /* Skylake plane registers */ 2485 2486 #define _PLANE_CTL_1_A 0x70180 2487 #define _PLANE_CTL_2_A 0x70280 2488 #define _PLANE_CTL_3_A 0x70380 2489 #define PLANE_CTL_ENABLE REG_BIT(31) 2490 #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ 2491 #define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */ 2492 #define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */ 2493 #define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) 2494 /* 2495 * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition 2496 * expanded to include bit 23 as well. However, the shift-24 based values 2497 * correctly map to the same formats in ICL, as long as bit 23 is set to 0 2498 */ 2499 #define PLANE_CTL_FORMAT_MASK_SKL REG_GENMASK(27, 24) /* pre-icl */ 2500 #define PLANE_CTL_FORMAT_MASK_ICL REG_GENMASK(27, 23) /* icl+ */ 2501 #define PLANE_CTL_FORMAT_YUV422 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0) 2502 #define PLANE_CTL_FORMAT_NV12 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 1) 2503 #define PLANE_CTL_FORMAT_XRGB_2101010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 2) 2504 #define PLANE_CTL_FORMAT_P010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 3) 2505 #define PLANE_CTL_FORMAT_XRGB_8888 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 4) 2506 #define PLANE_CTL_FORMAT_P012 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 5) 2507 #define PLANE_CTL_FORMAT_XRGB_16161616F REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 6) 2508 #define PLANE_CTL_FORMAT_P016 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 7) 2509 #define PLANE_CTL_FORMAT_XYUV REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 8) 2510 #define PLANE_CTL_FORMAT_INDEXED REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 12) 2511 #define PLANE_CTL_FORMAT_RGB_565 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 14) 2512 #define PLANE_CTL_FORMAT_Y210 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 1) 2513 #define PLANE_CTL_FORMAT_Y212 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 3) 2514 #define PLANE_CTL_FORMAT_Y216 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 5) 2515 #define PLANE_CTL_FORMAT_Y410 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 7) 2516 #define PLANE_CTL_FORMAT_Y412 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 9) 2517 #define PLANE_CTL_FORMAT_Y416 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 11) 2518 #define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */ 2519 #define PLANE_CTL_KEY_ENABLE_MASK REG_GENMASK(22, 21) 2520 #define PLANE_CTL_KEY_ENABLE_SOURCE REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 1) 2521 #define PLANE_CTL_KEY_ENABLE_DESTINATION REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 2) 2522 #define PLANE_CTL_ORDER_RGBX REG_BIT(20) 2523 #define PLANE_CTL_YUV420_Y_PLANE REG_BIT(19) 2524 #define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) 2525 #define PLANE_CTL_YUV422_ORDER_MASK REG_GENMASK(17, 16) 2526 #define PLANE_CTL_YUV422_ORDER_YUYV REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0) 2527 #define PLANE_CTL_YUV422_ORDER_UYVY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 1) 2528 #define PLANE_CTL_YUV422_ORDER_YVYU REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 2) 2529 #define PLANE_CTL_YUV422_ORDER_VYUY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 3) 2530 #define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE REG_BIT(15) 2531 #define PLANE_CTL_TRICKLE_FEED_DISABLE REG_BIT(14) 2532 #define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */ 2533 #define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */ 2534 #define PLANE_CTL_TILED_MASK REG_GENMASK(12, 10) 2535 #define PLANE_CTL_TILED_LINEAR REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 0) 2536 #define PLANE_CTL_TILED_X REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 1) 2537 #define PLANE_CTL_TILED_Y REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 4) 2538 #define PLANE_CTL_TILED_YF REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5) 2539 #define PLANE_CTL_TILED_4 REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5) 2540 #define PLANE_CTL_ASYNC_FLIP REG_BIT(9) 2541 #define PLANE_CTL_FLIP_HORIZONTAL REG_BIT(8) 2542 #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */ 2543 #define PLANE_CTL_ALPHA_MASK REG_GENMASK(5, 4) /* Pre-GLK */ 2544 #define PLANE_CTL_ALPHA_DISABLE REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 0) 2545 #define PLANE_CTL_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 2) 2546 #define PLANE_CTL_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 3) 2547 #define PLANE_CTL_ROTATE_MASK REG_GENMASK(1, 0) 2548 #define PLANE_CTL_ROTATE_0 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 0) 2549 #define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1) 2550 #define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2) 2551 #define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3) 2552 #define _PLANE_STRIDE_1_A 0x70188 2553 #define _PLANE_STRIDE_2_A 0x70288 2554 #define _PLANE_STRIDE_3_A 0x70388 2555 #define PLANE_STRIDE__MASK REG_GENMASK(11, 0) 2556 #define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride)) 2557 #define _PLANE_POS_1_A 0x7018c 2558 #define _PLANE_POS_2_A 0x7028c 2559 #define _PLANE_POS_3_A 0x7038c 2560 #define PLANE_POS_Y_MASK REG_GENMASK(31, 16) 2561 #define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y)) 2562 #define PLANE_POS_X_MASK REG_GENMASK(15, 0) 2563 #define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x)) 2564 #define _PLANE_SIZE_1_A 0x70190 2565 #define _PLANE_SIZE_2_A 0x70290 2566 #define _PLANE_SIZE_3_A 0x70390 2567 #define PLANE_HEIGHT_MASK REG_GENMASK(31, 16) 2568 #define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h)) 2569 #define PLANE_WIDTH_MASK REG_GENMASK(15, 0) 2570 #define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w)) 2571 #define _PLANE_SURF_1_A 0x7019c 2572 #define _PLANE_SURF_2_A 0x7029c 2573 #define _PLANE_SURF_3_A 0x7039c 2574 #define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12) 2575 #define PLANE_SURF_DECRYPT REG_BIT(2) 2576 #define _PLANE_OFFSET_1_A 0x701a4 2577 #define _PLANE_OFFSET_2_A 0x702a4 2578 #define _PLANE_OFFSET_3_A 0x703a4 2579 #define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16) 2580 #define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y)) 2581 #define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0) 2582 #define PLANE_OFFSET_X(x) REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x)) 2583 #define _PLANE_KEYVAL_1_A 0x70194 2584 #define _PLANE_KEYVAL_2_A 0x70294 2585 #define _PLANE_KEYMSK_1_A 0x70198 2586 #define _PLANE_KEYMSK_2_A 0x70298 2587 #define PLANE_KEYMSK_ALPHA_ENABLE REG_BIT(31) 2588 #define _PLANE_KEYMAX_1_A 0x701a0 2589 #define _PLANE_KEYMAX_2_A 0x702a0 2590 #define PLANE_KEYMAX_ALPHA_MASK REG_GENMASK(31, 24) 2591 #define PLANE_KEYMAX_ALPHA(a) REG_FIELD_PREP(PLANE_KEYMAX_ALPHA_MASK, (a)) 2592 #define _PLANE_SURFLIVE_1_A 0x701ac 2593 #define _PLANE_SURFLIVE_2_A 0x702ac 2594 #define _PLANE_CC_VAL_1_A 0x701b4 2595 #define _PLANE_CC_VAL_2_A 0x702b4 2596 #define _PLANE_AUX_DIST_1_A 0x701c0 2597 #define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12) 2598 #define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0) 2599 #define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride)) 2600 #define _PLANE_AUX_DIST_2_A 0x702c0 2601 #define _PLANE_AUX_OFFSET_1_A 0x701c4 2602 #define _PLANE_AUX_OFFSET_2_A 0x702c4 2603 #define _PLANE_CUS_CTL_1_A 0x701c8 2604 #define _PLANE_CUS_CTL_2_A 0x702c8 2605 #define PLANE_CUS_ENABLE REG_BIT(31) 2606 #define PLANE_CUS_Y_PLANE_MASK REG_BIT(30) 2607 #define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) 2608 #define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) 2609 #define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) 2610 #define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) 2611 #define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19) 2612 #define PLANE_CUS_HPHASE_MASK REG_GENMASK(17, 16) 2613 #define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0) 2614 #define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1) 2615 #define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2) 2616 #define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15) 2617 #define PLANE_CUS_VPHASE_MASK REG_GENMASK(13, 12) 2618 #define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0) 2619 #define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1) 2620 #define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2) 2621 #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */ 2622 #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */ 2623 #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */ 2624 #define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */ 2625 #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) 2626 #define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */ 2627 #define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */ 2628 #define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */ 2629 #define PLANE_COLOR_CSC_MODE_MASK REG_GENMASK(19, 17) 2630 #define PLANE_COLOR_CSC_MODE_BYPASS REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0) 2631 #define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 1) 2632 #define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 2) 2633 #define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 3) 2634 #define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 4) 2635 #define PLANE_COLOR_PLANE_GAMMA_DISABLE REG_BIT(13) 2636 #define PLANE_COLOR_ALPHA_MASK REG_GENMASK(5, 4) 2637 #define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0) 2638 #define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2) 2639 #define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3) 2640 #define _PLANE_CHICKEN_1_A 0x7026C /* tgl+ */ 2641 #define _PLANE_CHICKEN_2_A 0x7036C /* tgl+ */ 2642 #define PLANE_CHICKEN_DISABLE_DPT REG_BIT(19) /* mtl+ */ 2643 #define _PLANE_BUF_CFG_1_A 0x7027c 2644 #define _PLANE_BUF_CFG_2_A 0x7037c 2645 /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */ 2646 #define PLANE_BUF_END_MASK REG_GENMASK(27, 16) 2647 #define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end)) 2648 #define PLANE_BUF_START_MASK REG_GENMASK(11, 0) 2649 #define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start)) 2650 #define _PLANE_NV12_BUF_CFG_1_A 0x70278 2651 #define _PLANE_NV12_BUF_CFG_2_A 0x70378 2652 2653 #define _PLANE_CC_VAL_1_B 0x711b4 2654 #define _PLANE_CC_VAL_2_B 0x712b4 2655 #define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4) 2656 #define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4) 2657 #define PLANE_CC_VAL(pipe, plane, dw) \ 2658 _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw))) 2659 2660 /* Input CSC Register Definitions */ 2661 #define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0 2662 #define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0 2663 2664 #define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0 2665 #define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0 2666 2667 #define _PLANE_INPUT_CSC_RY_GY_1(pipe) \ 2668 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \ 2669 _PLANE_INPUT_CSC_RY_GY_1_B) 2670 #define _PLANE_INPUT_CSC_RY_GY_2(pipe) \ 2671 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \ 2672 _PLANE_INPUT_CSC_RY_GY_2_B) 2673 2674 #define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \ 2675 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \ 2676 _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4) 2677 2678 #define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8 2679 #define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8 2680 2681 #define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8 2682 #define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8 2683 2684 #define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \ 2685 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \ 2686 _PLANE_INPUT_CSC_PREOFF_HI_1_B) 2687 #define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \ 2688 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \ 2689 _PLANE_INPUT_CSC_PREOFF_HI_2_B) 2690 #define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \ 2691 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \ 2692 _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4) 2693 2694 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204 2695 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304 2696 2697 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204 2698 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304 2699 2700 #define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \ 2701 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \ 2702 _PLANE_INPUT_CSC_POSTOFF_HI_1_B) 2703 #define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \ 2704 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \ 2705 _PLANE_INPUT_CSC_POSTOFF_HI_2_B) 2706 #define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \ 2707 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \ 2708 _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4) 2709 2710 #define _PLANE_CTL_1_B 0x71180 2711 #define _PLANE_CTL_2_B 0x71280 2712 #define _PLANE_CTL_3_B 0x71380 2713 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) 2714 #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) 2715 #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B) 2716 #define PLANE_CTL(pipe, plane) \ 2717 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) 2718 2719 #define _PLANE_STRIDE_1_B 0x71188 2720 #define _PLANE_STRIDE_2_B 0x71288 2721 #define _PLANE_STRIDE_3_B 0x71388 2722 #define _PLANE_STRIDE_1(pipe) \ 2723 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) 2724 #define _PLANE_STRIDE_2(pipe) \ 2725 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) 2726 #define _PLANE_STRIDE_3(pipe) \ 2727 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B) 2728 #define PLANE_STRIDE(pipe, plane) \ 2729 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) 2730 2731 #define _PLANE_POS_1_B 0x7118c 2732 #define _PLANE_POS_2_B 0x7128c 2733 #define _PLANE_POS_3_B 0x7138c 2734 #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) 2735 #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) 2736 #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B) 2737 #define PLANE_POS(pipe, plane) \ 2738 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) 2739 2740 #define _PLANE_SIZE_1_B 0x71190 2741 #define _PLANE_SIZE_2_B 0x71290 2742 #define _PLANE_SIZE_3_B 0x71390 2743 #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) 2744 #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) 2745 #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B) 2746 #define PLANE_SIZE(pipe, plane) \ 2747 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) 2748 2749 #define _PLANE_SURF_1_B 0x7119c 2750 #define _PLANE_SURF_2_B 0x7129c 2751 #define _PLANE_SURF_3_B 0x7139c 2752 #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B) 2753 #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B) 2754 #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) 2755 #define PLANE_SURF(pipe, plane) \ 2756 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) 2757 2758 #define _PLANE_OFFSET_1_B 0x711a4 2759 #define _PLANE_OFFSET_2_B 0x712a4 2760 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B) 2761 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B) 2762 #define PLANE_OFFSET(pipe, plane) \ 2763 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe)) 2764 2765 #define _PLANE_KEYVAL_1_B 0x71194 2766 #define _PLANE_KEYVAL_2_B 0x71294 2767 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B) 2768 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) 2769 #define PLANE_KEYVAL(pipe, plane) \ 2770 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe)) 2771 2772 #define _PLANE_KEYMSK_1_B 0x71198 2773 #define _PLANE_KEYMSK_2_B 0x71298 2774 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B) 2775 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B) 2776 #define PLANE_KEYMSK(pipe, plane) \ 2777 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe)) 2778 2779 #define _PLANE_KEYMAX_1_B 0x711a0 2780 #define _PLANE_KEYMAX_2_B 0x712a0 2781 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B) 2782 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B) 2783 #define PLANE_KEYMAX(pipe, plane) \ 2784 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe)) 2785 2786 #define _PLANE_SURFLIVE_1_B 0x711ac 2787 #define _PLANE_SURFLIVE_2_B 0x712ac 2788 #define _PLANE_SURFLIVE_1(pipe) _PIPE(pipe, _PLANE_SURFLIVE_1_A, _PLANE_SURFLIVE_1_B) 2789 #define _PLANE_SURFLIVE_2(pipe) _PIPE(pipe, _PLANE_SURFLIVE_2_A, _PLANE_SURFLIVE_2_B) 2790 #define PLANE_SURFLIVE(pipe, plane) \ 2791 _MMIO_PLANE(plane, _PLANE_SURFLIVE_1(pipe), _PLANE_SURFLIVE_2(pipe)) 2792 2793 #define _PLANE_CHICKEN_1_B 0x7126c 2794 #define _PLANE_CHICKEN_2_B 0x7136c 2795 #define _PLANE_CHICKEN_1(pipe) _PIPE(pipe, _PLANE_CHICKEN_1_A, _PLANE_CHICKEN_1_B) 2796 #define _PLANE_CHICKEN_2(pipe) _PIPE(pipe, _PLANE_CHICKEN_2_A, _PLANE_CHICKEN_2_B) 2797 #define PLANE_CHICKEN(pipe, plane) \ 2798 _MMIO_PLANE(plane, _PLANE_CHICKEN_1(pipe), _PLANE_CHICKEN_2(pipe)) 2799 2800 #define _PLANE_AUX_DIST_1_B 0x711c0 2801 #define _PLANE_AUX_DIST_2_B 0x712c0 2802 #define _PLANE_AUX_DIST_1(pipe) \ 2803 _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B) 2804 #define _PLANE_AUX_DIST_2(pipe) \ 2805 _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B) 2806 #define PLANE_AUX_DIST(pipe, plane) \ 2807 _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe)) 2808 2809 #define _PLANE_AUX_OFFSET_1_B 0x711c4 2810 #define _PLANE_AUX_OFFSET_2_B 0x712c4 2811 #define _PLANE_AUX_OFFSET_1(pipe) \ 2812 _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B) 2813 #define _PLANE_AUX_OFFSET_2(pipe) \ 2814 _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B) 2815 #define PLANE_AUX_OFFSET(pipe, plane) \ 2816 _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe)) 2817 2818 #define _PLANE_CUS_CTL_1_B 0x711c8 2819 #define _PLANE_CUS_CTL_2_B 0x712c8 2820 #define _PLANE_CUS_CTL_1(pipe) \ 2821 _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B) 2822 #define _PLANE_CUS_CTL_2(pipe) \ 2823 _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B) 2824 #define PLANE_CUS_CTL(pipe, plane) \ 2825 _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe)) 2826 2827 #define _PLANE_COLOR_CTL_1_B 0x711CC 2828 #define _PLANE_COLOR_CTL_2_B 0x712CC 2829 #define _PLANE_COLOR_CTL_3_B 0x713CC 2830 #define _PLANE_COLOR_CTL_1(pipe) \ 2831 _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B) 2832 #define _PLANE_COLOR_CTL_2(pipe) \ 2833 _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B) 2834 #define PLANE_COLOR_CTL(pipe, plane) \ 2835 _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe)) 2836 2837 /* VBIOS regs */ 2838 #define VGACNTRL _MMIO(0x71400) 2839 # define VGA_DISP_DISABLE (1 << 31) 2840 # define VGA_2X_MODE (1 << 30) 2841 # define VGA_PIPE_B_SELECT (1 << 29) 2842 2843 #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400) 2844 2845 /* Ironlake */ 2846 2847 #define CPU_VGACNTRL _MMIO(0x41000) 2848 2849 #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030) 2850 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 2851 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */ 2852 #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */ 2853 #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */ 2854 #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */ 2855 #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */ 2856 #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0) 2857 #define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0) 2858 #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0) 2859 #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0) 2860 2861 /* refresh rate hardware control */ 2862 #define RR_HW_CTL _MMIO(0x45300) 2863 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff 2864 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 2865 2866 #define PCH_3DCGDIS0 _MMIO(0x46020) 2867 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) 2868 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) 2869 2870 #define PCH_3DCGDIS1 _MMIO(0x46024) 2871 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) 2872 2873 #define _PIPEA_DATA_M1 0x60030 2874 #define _PIPEA_DATA_N1 0x60034 2875 #define _PIPEA_DATA_M2 0x60038 2876 #define _PIPEA_DATA_N2 0x6003c 2877 #define _PIPEA_LINK_M1 0x60040 2878 #define _PIPEA_LINK_N1 0x60044 2879 #define _PIPEA_LINK_M2 0x60048 2880 #define _PIPEA_LINK_N2 0x6004c 2881 2882 /* PIPEB timing regs are same start from 0x61000 */ 2883 2884 #define _PIPEB_DATA_M1 0x61030 2885 #define _PIPEB_DATA_N1 0x61034 2886 #define _PIPEB_DATA_M2 0x61038 2887 #define _PIPEB_DATA_N2 0x6103c 2888 #define _PIPEB_LINK_M1 0x61040 2889 #define _PIPEB_LINK_N1 0x61044 2890 #define _PIPEB_LINK_M2 0x61048 2891 #define _PIPEB_LINK_N2 0x6104c 2892 2893 #define PIPE_DATA_M1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M1) 2894 #define PIPE_DATA_N1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1) 2895 #define PIPE_DATA_M2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2) 2896 #define PIPE_DATA_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2) 2897 #define PIPE_LINK_M1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1) 2898 #define PIPE_LINK_N1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1) 2899 #define PIPE_LINK_M2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2) 2900 #define PIPE_LINK_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2) 2901 2902 /* CPU panel fitter */ 2903 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ 2904 #define _PFA_CTL_1 0x68080 2905 #define _PFB_CTL_1 0x68880 2906 #define PF_ENABLE REG_BIT(31) 2907 #define PF_PIPE_SEL_MASK_IVB REG_GENMASK(30, 29) /* ivb/hsw */ 2908 #define PF_PIPE_SEL_IVB(pipe) REG_FIELD_PREP(PF_PIPE_SEL_MASK_IVB, (pipe)) 2909 #define PF_FILTER_MASK REG_GENMASK(24, 23) 2910 #define PF_FILTER_PROGRAMMED REG_FIELD_PREP(PF_FILTER_MASK, 0) 2911 #define PF_FILTER_MED_3x3 REG_FIELD_PREP(PF_FILTER_MASK, 1) 2912 #define PF_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 2) 2913 #define PF_FILTER_EDGE_SOFTEN REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 3) 2914 #define _PFA_WIN_SZ 0x68074 2915 #define _PFB_WIN_SZ 0x68874 2916 #define PF_WIN_XSIZE_MASK REG_GENMASK(31, 16) 2917 #define PF_WIN_XSIZE(w) REG_FIELD_PREP(PF_WIN_XSIZE_MASK, (w)) 2918 #define PF_WIN_YSIZE_MASK REG_GENMASK(15, 0) 2919 #define PF_WIN_YSIZE(h) REG_FIELD_PREP(PF_WIN_YSIZE_MASK, (h)) 2920 #define _PFA_WIN_POS 0x68070 2921 #define _PFB_WIN_POS 0x68870 2922 #define PF_WIN_XPOS_MASK REG_GENMASK(31, 16) 2923 #define PF_WIN_XPOS(x) REG_FIELD_PREP(PF_WIN_XPOS_MASK, (x)) 2924 #define PF_WIN_YPOS_MASK REG_GENMASK(15, 0) 2925 #define PF_WIN_YPOS(y) REG_FIELD_PREP(PF_WIN_YPOS_MASK, (y)) 2926 #define _PFA_VSCALE 0x68084 2927 #define _PFB_VSCALE 0x68884 2928 #define _PFA_HSCALE 0x68090 2929 #define _PFB_HSCALE 0x68890 2930 2931 #define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) 2932 #define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) 2933 #define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) 2934 #define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) 2935 #define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) 2936 2937 /* 2938 * Skylake scalers 2939 */ 2940 #define _PS_1A_CTRL 0x68180 2941 #define _PS_2A_CTRL 0x68280 2942 #define _PS_1B_CTRL 0x68980 2943 #define _PS_2B_CTRL 0x68A80 2944 #define _PS_1C_CTRL 0x69180 2945 #define PS_SCALER_EN REG_BIT(31) 2946 #define PS_SCALER_TYPE_MASK REG_BIT(30) /* icl+ */ 2947 #define PS_SCALER_TYPE_NON_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 0) 2948 #define PS_SCALER_TYPE_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 1) 2949 #define SKL_PS_SCALER_MODE_MASK REG_GENMASK(29, 28) /* skl/bxt */ 2950 #define SKL_PS_SCALER_MODE_DYN REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 0) 2951 #define SKL_PS_SCALER_MODE_HQ REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 1) 2952 #define SKL_PS_SCALER_MODE_NV12 REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 2) 2953 #define PS_SCALER_MODE_MASK REG_BIT(29) /* glk-tgl */ 2954 #define PS_SCALER_MODE_NORMAL REG_FIELD_PREP(PS_SCALER_MODE_MASK, 0) 2955 #define PS_SCALER_MODE_PLANAR REG_FIELD_PREP(PS_SCALER_MODE_MASK, 1) 2956 #define PS_ADAPTIVE_FILTERING_EN REG_BIT(28) /* icl+ */ 2957 #define PS_BINDING_MASK REG_GENMASK(27, 25) 2958 #define PS_BINDING_PIPE REG_FIELD_PREP(PS_BINDING_MASK, 0) 2959 #define PS_BINDING_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_MASK, (plane_id) + 1) 2960 #define PS_FILTER_MASK REG_GENMASK(24, 23) 2961 #define PS_FILTER_MEDIUM REG_FIELD_PREP(PS_FILTER_MASK, 0) 2962 #define PS_FILTER_PROGRAMMED REG_FIELD_PREP(PS_FILTER_MASK, 1) 2963 #define PS_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_FILTER_MASK, 2) 2964 #define PS_FILTER_BILINEAR REG_FIELD_PREP(PS_FILTER_MASK, 3) 2965 #define PS_ADAPTIVE_FILTER_MASK REG_BIT(22) /* icl+ */ 2966 #define PS_ADAPTIVE_FILTER_MEDIUM REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 0) 2967 #define PS_ADAPTIVE_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 1) 2968 #define PS_PIPE_SCALER_LOC_MASK REG_BIT(21) /* icl+ */ 2969 #define PS_PIPE_SCALER_LOC_AFTER_OUTPUT_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 0) /* non-linear */ 2970 #define PS_PIPE_SCALER_LOC_AFTER_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 1) /* linear */ 2971 #define PS_VERT3TAP REG_BIT(21) /* skl/bxt */ 2972 #define PS_VERT_INT_INVERT_FIELD REG_BIT(20) 2973 #define PS_PROG_SCALE_FACTOR REG_BIT(19) /* tgl+ */ 2974 #define PS_PWRUP_PROGRESS REG_BIT(17) 2975 #define PS_V_FILTER_BYPASS REG_BIT(8) 2976 #define PS_VADAPT_EN REG_BIT(7) /* skl/bxt */ 2977 #define PS_VADAPT_MODE_MASK REG_GENMASK(6, 5) /* skl/bxt */ 2978 #define PS_VADAPT_MODE_LEAST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 0) 2979 #define PS_VADAPT_MODE_MOD_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 1) 2980 #define PS_VADAPT_MODE_MOST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 3) 2981 #define PS_BINDING_Y_MASK REG_GENMASK(7, 5) /* icl-tgl */ 2982 #define PS_BINDING_Y_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_Y_MASK, (plane_id) + 1) 2983 #define PS_Y_VERT_FILTER_SELECT_MASK REG_BIT(4) /* glk+ */ 2984 #define PS_Y_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_VERT_FILTER_SELECT_MASK, (set)) 2985 #define PS_Y_HORZ_FILTER_SELECT_MASK REG_BIT(3) /* glk+ */ 2986 #define PS_Y_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_HORZ_FILTER_SELECT_MASK, (set)) 2987 #define PS_UV_VERT_FILTER_SELECT_MASK REG_BIT(2) /* glk+ */ 2988 #define PS_UV_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_VERT_FILTER_SELECT_MASK, (set)) 2989 #define PS_UV_HORZ_FILTER_SELECT_MASK REG_BIT(1) /* glk+ */ 2990 #define PS_UV_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_HORZ_FILTER_SELECT_MASK, (set)) 2991 2992 #define _PS_PWR_GATE_1A 0x68160 2993 #define _PS_PWR_GATE_2A 0x68260 2994 #define _PS_PWR_GATE_1B 0x68960 2995 #define _PS_PWR_GATE_2B 0x68A60 2996 #define _PS_PWR_GATE_1C 0x69160 2997 #define PS_PWR_GATE_DIS_OVERRIDE REG_BIT(31) 2998 #define PS_PWR_GATE_SETTLING_TIME_MASK REG_GENMASK(4, 3) 2999 #define PS_PWR_GATE_SETTLING_TIME_32 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 0) 3000 #define PS_PWR_GATE_SETTLING_TIME_64 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 1) 3001 #define PS_PWR_GATE_SETTLING_TIME_96 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 2) 3002 #define PS_PWR_GATE_SETTLING_TIME_128 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 3) 3003 #define PS_PWR_GATE_SLPEN_MASK REG_GENMASK(1, 0) 3004 #define PS_PWR_GATE_SLPEN_8 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 0) 3005 #define PS_PWR_GATE_SLPEN_16 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 1) 3006 #define PS_PWR_GATE_SLPEN_24 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 2) 3007 #define PS_PWR_GATE_SLPEN_32 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 3) 3008 3009 #define _PS_WIN_POS_1A 0x68170 3010 #define _PS_WIN_POS_2A 0x68270 3011 #define _PS_WIN_POS_1B 0x68970 3012 #define _PS_WIN_POS_2B 0x68A70 3013 #define _PS_WIN_POS_1C 0x69170 3014 #define PS_WIN_XPOS_MASK REG_GENMASK(31, 16) 3015 #define PS_WIN_XPOS(x) REG_FIELD_PREP(PS_WIN_XPOS_MASK, (x)) 3016 #define PS_WIN_YPOS_MASK REG_GENMASK(15, 0) 3017 #define PS_WIN_YPOS(y) REG_FIELD_PREP(PS_WIN_YPOS_MASK, (y)) 3018 3019 #define _PS_WIN_SZ_1A 0x68174 3020 #define _PS_WIN_SZ_2A 0x68274 3021 #define _PS_WIN_SZ_1B 0x68974 3022 #define _PS_WIN_SZ_2B 0x68A74 3023 #define _PS_WIN_SZ_1C 0x69174 3024 #define PS_WIN_XSIZE_MASK REG_GENMASK(31, 16) 3025 #define PS_WIN_XSIZE(w) REG_FIELD_PREP(PS_WIN_XSIZE_MASK, (w)) 3026 #define PS_WIN_YSIZE_MASK REG_GENMASK(15, 0) 3027 #define PS_WIN_YSIZE(h) REG_FIELD_PREP(PS_WIN_YSIZE_MASK, (h)) 3028 3029 #define _PS_VSCALE_1A 0x68184 3030 #define _PS_VSCALE_2A 0x68284 3031 #define _PS_VSCALE_1B 0x68984 3032 #define _PS_VSCALE_2B 0x68A84 3033 #define _PS_VSCALE_1C 0x69184 3034 3035 #define _PS_HSCALE_1A 0x68190 3036 #define _PS_HSCALE_2A 0x68290 3037 #define _PS_HSCALE_1B 0x68990 3038 #define _PS_HSCALE_2B 0x68A90 3039 #define _PS_HSCALE_1C 0x69190 3040 3041 #define _PS_VPHASE_1A 0x68188 3042 #define _PS_VPHASE_2A 0x68288 3043 #define _PS_VPHASE_1B 0x68988 3044 #define _PS_VPHASE_2B 0x68A88 3045 #define _PS_VPHASE_1C 0x69188 3046 #define PS_Y_PHASE_MASK REG_GENMASK(31, 16) 3047 #define PS_Y_PHASE(x) REG_FIELD_PREP(PS_Y_PHASE_MASK, (x)) 3048 #define PS_UV_RGB_PHASE_MASK REG_GENMASK(15, 0) 3049 #define PS_UV_RGB_PHASE(x) REG_FIELD_PREP(PS_UV_RGB_PHASE_MASK, (x)) 3050 #define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */ 3051 #define PS_PHASE_TRIP (1 << 0) 3052 3053 #define _PS_HPHASE_1A 0x68194 3054 #define _PS_HPHASE_2A 0x68294 3055 #define _PS_HPHASE_1B 0x68994 3056 #define _PS_HPHASE_2B 0x68A94 3057 #define _PS_HPHASE_1C 0x69194 3058 3059 #define _PS_ECC_STAT_1A 0x681D0 3060 #define _PS_ECC_STAT_2A 0x682D0 3061 #define _PS_ECC_STAT_1B 0x689D0 3062 #define _PS_ECC_STAT_2B 0x68AD0 3063 #define _PS_ECC_STAT_1C 0x691D0 3064 3065 #define _PS_COEF_SET0_INDEX_1A 0x68198 3066 #define _PS_COEF_SET0_INDEX_2A 0x68298 3067 #define _PS_COEF_SET0_INDEX_1B 0x68998 3068 #define _PS_COEF_SET0_INDEX_2B 0x68A98 3069 #define PS_COEF_INDEX_AUTO_INC REG_BIT(10) 3070 3071 #define _PS_COEF_SET0_DATA_1A 0x6819C 3072 #define _PS_COEF_SET0_DATA_2A 0x6829C 3073 #define _PS_COEF_SET0_DATA_1B 0x6899C 3074 #define _PS_COEF_SET0_DATA_2B 0x68A9C 3075 3076 #define _ID(id, a, b) _PICK_EVEN(id, a, b) 3077 #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \ 3078 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \ 3079 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL)) 3080 #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \ 3081 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \ 3082 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B)) 3083 #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \ 3084 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \ 3085 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B)) 3086 #define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \ 3087 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \ 3088 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B)) 3089 #define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \ 3090 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \ 3091 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B)) 3092 #define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \ 3093 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \ 3094 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B)) 3095 #define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \ 3096 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \ 3097 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B)) 3098 #define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \ 3099 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \ 3100 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B)) 3101 #define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \ 3102 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \ 3103 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)) 3104 #define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe, \ 3105 _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \ 3106 _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8) 3107 3108 #define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \ 3109 _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \ 3110 _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8) 3111 3112 /* Display Internal Timeout Register */ 3113 #define RM_TIMEOUT _MMIO(0x42060) 3114 #define MMIO_TIMEOUT_US(us) ((us) << 0) 3115 3116 /* interrupts */ 3117 #define DE_MASTER_IRQ_CONTROL (1 << 31) 3118 #define DE_SPRITEB_FLIP_DONE (1 << 29) 3119 #define DE_SPRITEA_FLIP_DONE (1 << 28) 3120 #define DE_PLANEB_FLIP_DONE (1 << 27) 3121 #define DE_PLANEA_FLIP_DONE (1 << 26) 3122 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane))) 3123 #define DE_PCU_EVENT (1 << 25) 3124 #define DE_GTT_FAULT (1 << 24) 3125 #define DE_POISON (1 << 23) 3126 #define DE_PERFORM_COUNTER (1 << 22) 3127 #define DE_PCH_EVENT (1 << 21) 3128 #define DE_AUX_CHANNEL_A (1 << 20) 3129 #define DE_DP_A_HOTPLUG (1 << 19) 3130 #define DE_GSE (1 << 18) 3131 #define DE_PIPEB_VBLANK (1 << 15) 3132 #define DE_PIPEB_EVEN_FIELD (1 << 14) 3133 #define DE_PIPEB_ODD_FIELD (1 << 13) 3134 #define DE_PIPEB_LINE_COMPARE (1 << 12) 3135 #define DE_PIPEB_VSYNC (1 << 11) 3136 #define DE_PIPEB_CRC_DONE (1 << 10) 3137 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) 3138 #define DE_PIPEA_VBLANK (1 << 7) 3139 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe))) 3140 #define DE_PIPEA_EVEN_FIELD (1 << 6) 3141 #define DE_PIPEA_ODD_FIELD (1 << 5) 3142 #define DE_PIPEA_LINE_COMPARE (1 << 4) 3143 #define DE_PIPEA_VSYNC (1 << 3) 3144 #define DE_PIPEA_CRC_DONE (1 << 2) 3145 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe))) 3146 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 3147 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe))) 3148 3149 /* More Ivybridge lolz */ 3150 #define DE_ERR_INT_IVB (1 << 30) 3151 #define DE_GSE_IVB (1 << 29) 3152 #define DE_PCH_EVENT_IVB (1 << 28) 3153 #define DE_DP_A_HOTPLUG_IVB (1 << 27) 3154 #define DE_AUX_CHANNEL_A_IVB (1 << 26) 3155 #define DE_EDP_PSR_INT_HSW (1 << 19) 3156 #define DE_SPRITEC_FLIP_DONE_IVB (1 << 14) 3157 #define DE_PLANEC_FLIP_DONE_IVB (1 << 13) 3158 #define DE_PIPEC_VBLANK_IVB (1 << 10) 3159 #define DE_SPRITEB_FLIP_DONE_IVB (1 << 9) 3160 #define DE_PLANEB_FLIP_DONE_IVB (1 << 8) 3161 #define DE_PIPEB_VBLANK_IVB (1 << 5) 3162 #define DE_SPRITEA_FLIP_DONE_IVB (1 << 4) 3163 #define DE_PLANEA_FLIP_DONE_IVB (1 << 3) 3164 #define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane))) 3165 #define DE_PIPEA_VBLANK_IVB (1 << 0) 3166 #define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5)) 3167 3168 #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */ 3169 #define MASTER_INTERRUPT_ENABLE (1 << 31) 3170 3171 #define DEISR _MMIO(0x44000) 3172 #define DEIMR _MMIO(0x44004) 3173 #define DEIIR _MMIO(0x44008) 3174 #define DEIER _MMIO(0x4400c) 3175 3176 #define GTISR _MMIO(0x44010) 3177 #define GTIMR _MMIO(0x44014) 3178 #define GTIIR _MMIO(0x44018) 3179 #define GTIER _MMIO(0x4401c) 3180 3181 #define GEN8_MASTER_IRQ _MMIO(0x44200) 3182 #define GEN8_MASTER_IRQ_CONTROL (1 << 31) 3183 #define GEN8_PCU_IRQ (1 << 30) 3184 #define GEN8_DE_PCH_IRQ (1 << 23) 3185 #define GEN8_DE_MISC_IRQ (1 << 22) 3186 #define GEN8_DE_PORT_IRQ (1 << 20) 3187 #define GEN8_DE_PIPE_C_IRQ (1 << 18) 3188 #define GEN8_DE_PIPE_B_IRQ (1 << 17) 3189 #define GEN8_DE_PIPE_A_IRQ (1 << 16) 3190 #define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe))) 3191 #define GEN8_GT_VECS_IRQ (1 << 6) 3192 #define GEN8_GT_GUC_IRQ (1 << 5) 3193 #define GEN8_GT_PM_IRQ (1 << 4) 3194 #define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */ 3195 #define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */ 3196 #define GEN8_GT_BCS_IRQ (1 << 1) 3197 #define GEN8_GT_RCS_IRQ (1 << 0) 3198 3199 #define XELPD_DISPLAY_ERR_FATAL_MASK _MMIO(0x4421c) 3200 3201 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which))) 3202 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which))) 3203 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which))) 3204 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which))) 3205 3206 #define GEN8_RCS_IRQ_SHIFT 0 3207 #define GEN8_BCS_IRQ_SHIFT 16 3208 #define GEN8_VCS0_IRQ_SHIFT 0 /* NB: VCS1 in bspec! */ 3209 #define GEN8_VCS1_IRQ_SHIFT 16 /* NB: VCS2 in bpsec! */ 3210 #define GEN8_VECS_IRQ_SHIFT 0 3211 #define GEN8_WD_IRQ_SHIFT 16 3212 3213 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe))) 3214 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe))) 3215 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe))) 3216 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe))) 3217 #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31) 3218 #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29) 3219 #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28) 3220 #define XELPD_PIPE_SOFT_UNDERRUN (1 << 22) 3221 #define XELPD_PIPE_HARD_UNDERRUN (1 << 21) 3222 #define GEN12_PIPE_VBLANK_UNMOD (1 << 19) 3223 #define GEN8_PIPE_CURSOR_FAULT (1 << 10) 3224 #define GEN8_PIPE_SPRITE_FAULT (1 << 9) 3225 #define GEN8_PIPE_PRIMARY_FAULT (1 << 8) 3226 #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5) 3227 #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4) 3228 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) 3229 #define GEN8_PIPE_VSYNC (1 << 1) 3230 #define GEN8_PIPE_VBLANK (1 << 0) 3231 #define GEN9_PIPE_CURSOR_FAULT (1 << 11) 3232 #define GEN11_PIPE_PLANE7_FAULT (1 << 22) 3233 #define GEN11_PIPE_PLANE6_FAULT (1 << 21) 3234 #define GEN11_PIPE_PLANE5_FAULT (1 << 20) 3235 #define GEN9_PIPE_PLANE4_FAULT (1 << 10) 3236 #define GEN9_PIPE_PLANE3_FAULT (1 << 9) 3237 #define GEN9_PIPE_PLANE2_FAULT (1 << 8) 3238 #define GEN9_PIPE_PLANE1_FAULT (1 << 7) 3239 #define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6) 3240 #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5) 3241 #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4) 3242 #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3) 3243 #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p))) 3244 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ 3245 (GEN8_PIPE_CURSOR_FAULT | \ 3246 GEN8_PIPE_SPRITE_FAULT | \ 3247 GEN8_PIPE_PRIMARY_FAULT) 3248 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \ 3249 (GEN9_PIPE_CURSOR_FAULT | \ 3250 GEN9_PIPE_PLANE4_FAULT | \ 3251 GEN9_PIPE_PLANE3_FAULT | \ 3252 GEN9_PIPE_PLANE2_FAULT | \ 3253 GEN9_PIPE_PLANE1_FAULT) 3254 #define GEN11_DE_PIPE_IRQ_FAULT_ERRORS \ 3255 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \ 3256 GEN11_PIPE_PLANE7_FAULT | \ 3257 GEN11_PIPE_PLANE6_FAULT | \ 3258 GEN11_PIPE_PLANE5_FAULT) 3259 #define RKL_DE_PIPE_IRQ_FAULT_ERRORS \ 3260 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \ 3261 GEN11_PIPE_PLANE5_FAULT) 3262 3263 #define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A) 3264 #define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1) 3265 3266 #define GEN8_DE_PORT_ISR _MMIO(0x44440) 3267 #define GEN8_DE_PORT_IMR _MMIO(0x44444) 3268 #define GEN8_DE_PORT_IIR _MMIO(0x44448) 3269 #define GEN8_DE_PORT_IER _MMIO(0x4444c) 3270 #define DSI1_NON_TE (1 << 31) 3271 #define DSI0_NON_TE (1 << 30) 3272 #define ICL_AUX_CHANNEL_E (1 << 29) 3273 #define ICL_AUX_CHANNEL_F (1 << 28) 3274 #define GEN9_AUX_CHANNEL_D (1 << 27) 3275 #define GEN9_AUX_CHANNEL_C (1 << 26) 3276 #define GEN9_AUX_CHANNEL_B (1 << 25) 3277 #define DSI1_TE (1 << 24) 3278 #define DSI0_TE (1 << 23) 3279 #define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin)) 3280 #define BXT_DE_PORT_HOTPLUG_MASK (GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \ 3281 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \ 3282 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)) 3283 #define BDW_DE_PORT_HOTPLUG_MASK GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) 3284 #define BXT_DE_PORT_GMBUS (1 << 1) 3285 #define GEN8_AUX_CHANNEL_A (1 << 0) 3286 #define TGL_DE_PORT_AUX_USBC6 REG_BIT(13) 3287 #define XELPD_DE_PORT_AUX_DDIE REG_BIT(13) 3288 #define TGL_DE_PORT_AUX_USBC5 REG_BIT(12) 3289 #define XELPD_DE_PORT_AUX_DDID REG_BIT(12) 3290 #define TGL_DE_PORT_AUX_USBC4 REG_BIT(11) 3291 #define TGL_DE_PORT_AUX_USBC3 REG_BIT(10) 3292 #define TGL_DE_PORT_AUX_USBC2 REG_BIT(9) 3293 #define TGL_DE_PORT_AUX_USBC1 REG_BIT(8) 3294 #define TGL_DE_PORT_AUX_DDIC REG_BIT(2) 3295 #define TGL_DE_PORT_AUX_DDIB REG_BIT(1) 3296 #define TGL_DE_PORT_AUX_DDIA REG_BIT(0) 3297 3298 #define GEN8_DE_MISC_ISR _MMIO(0x44460) 3299 #define GEN8_DE_MISC_IMR _MMIO(0x44464) 3300 #define GEN8_DE_MISC_IIR _MMIO(0x44468) 3301 #define GEN8_DE_MISC_IER _MMIO(0x4446c) 3302 #define XELPDP_PMDEMAND_RSPTOUT_ERR REG_BIT(27) 3303 #define GEN8_DE_MISC_GSE REG_BIT(27) 3304 #define GEN8_DE_EDP_PSR REG_BIT(19) 3305 #define XELPDP_PMDEMAND_RSP REG_BIT(3) 3306 3307 #define GEN8_PCU_ISR _MMIO(0x444e0) 3308 #define GEN8_PCU_IMR _MMIO(0x444e4) 3309 #define GEN8_PCU_IIR _MMIO(0x444e8) 3310 #define GEN8_PCU_IER _MMIO(0x444ec) 3311 3312 #define GEN11_GU_MISC_ISR _MMIO(0x444f0) 3313 #define GEN11_GU_MISC_IMR _MMIO(0x444f4) 3314 #define GEN11_GU_MISC_IIR _MMIO(0x444f8) 3315 #define GEN11_GU_MISC_IER _MMIO(0x444fc) 3316 #define GEN11_GU_MISC_GSE (1 << 27) 3317 3318 #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010) 3319 #define GEN11_MASTER_IRQ (1 << 31) 3320 #define GEN11_PCU_IRQ (1 << 30) 3321 #define GEN11_GU_MISC_IRQ (1 << 29) 3322 #define GEN11_DISPLAY_IRQ (1 << 16) 3323 #define GEN11_GT_DW_IRQ(x) (1 << (x)) 3324 #define GEN11_GT_DW1_IRQ (1 << 1) 3325 #define GEN11_GT_DW0_IRQ (1 << 0) 3326 3327 #define DG1_MSTR_TILE_INTR _MMIO(0x190008) 3328 #define DG1_MSTR_IRQ REG_BIT(31) 3329 #define DG1_MSTR_TILE(t) REG_BIT(t) 3330 3331 #define GEN11_DISPLAY_INT_CTL _MMIO(0x44200) 3332 #define GEN11_DISPLAY_IRQ_ENABLE (1 << 31) 3333 #define GEN11_AUDIO_CODEC_IRQ (1 << 24) 3334 #define GEN11_DE_PCH_IRQ (1 << 23) 3335 #define GEN11_DE_MISC_IRQ (1 << 22) 3336 #define GEN11_DE_HPD_IRQ (1 << 21) 3337 #define GEN11_DE_PORT_IRQ (1 << 20) 3338 #define GEN11_DE_PIPE_C (1 << 18) 3339 #define GEN11_DE_PIPE_B (1 << 17) 3340 #define GEN11_DE_PIPE_A (1 << 16) 3341 3342 #define GEN11_DE_HPD_ISR _MMIO(0x44470) 3343 #define GEN11_DE_HPD_IMR _MMIO(0x44474) 3344 #define GEN11_DE_HPD_IIR _MMIO(0x44478) 3345 #define GEN11_DE_HPD_IER _MMIO(0x4447c) 3346 #define GEN11_TC_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin)) 3347 #define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(HPD_PORT_TC6) | \ 3348 GEN11_TC_HOTPLUG(HPD_PORT_TC5) | \ 3349 GEN11_TC_HOTPLUG(HPD_PORT_TC4) | \ 3350 GEN11_TC_HOTPLUG(HPD_PORT_TC3) | \ 3351 GEN11_TC_HOTPLUG(HPD_PORT_TC2) | \ 3352 GEN11_TC_HOTPLUG(HPD_PORT_TC1)) 3353 #define GEN11_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin)) 3354 #define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(HPD_PORT_TC6) | \ 3355 GEN11_TBT_HOTPLUG(HPD_PORT_TC5) | \ 3356 GEN11_TBT_HOTPLUG(HPD_PORT_TC4) | \ 3357 GEN11_TBT_HOTPLUG(HPD_PORT_TC3) | \ 3358 GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \ 3359 GEN11_TBT_HOTPLUG(HPD_PORT_TC1)) 3360 3361 #define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030) 3362 #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038) 3363 #define GEN11_HOTPLUG_CTL_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4)) 3364 #define GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4)) 3365 #define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4)) 3366 #define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 << (_HPD_PIN_TC(hpd_pin) * 4)) 3367 3368 #define PICAINTERRUPT_ISR _MMIO(0x16FE50) 3369 #define PICAINTERRUPT_IMR _MMIO(0x16FE54) 3370 #define PICAINTERRUPT_IIR _MMIO(0x16FE58) 3371 #define PICAINTERRUPT_IER _MMIO(0x16FE5C) 3372 #define XELPDP_DP_ALT_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin)) 3373 #define XELPDP_DP_ALT_HOTPLUG_MASK REG_GENMASK(19, 16) 3374 #define XELPDP_AUX_TC(hpd_pin) REG_BIT(8 + _HPD_PIN_TC(hpd_pin)) 3375 #define XELPDP_AUX_TC_MASK REG_GENMASK(11, 8) 3376 #define XE2LPD_AUX_DDI(hpd_pin) REG_BIT(6 + _HPD_PIN_DDI(hpd_pin)) 3377 #define XE2LPD_AUX_DDI_MASK REG_GENMASK(7, 6) 3378 #define XELPDP_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin)) 3379 #define XELPDP_TBT_HOTPLUG_MASK REG_GENMASK(3, 0) 3380 3381 #define XELPDP_PORT_HOTPLUG_CTL(hpd_pin) _MMIO(0x16F270 + (_HPD_PIN_TC(hpd_pin) * 0x200)) 3382 #define XELPDP_TBT_HOTPLUG_ENABLE REG_BIT(6) 3383 #define XELPDP_TBT_HPD_LONG_DETECT REG_BIT(5) 3384 #define XELPDP_TBT_HPD_SHORT_DETECT REG_BIT(4) 3385 #define XELPDP_DP_ALT_HOTPLUG_ENABLE REG_BIT(2) 3386 #define XELPDP_DP_ALT_HPD_LONG_DETECT REG_BIT(1) 3387 #define XELPDP_DP_ALT_HPD_SHORT_DETECT REG_BIT(0) 3388 3389 #define XELPDP_INITIATE_PMDEMAND_REQUEST(dword) _MMIO(0x45230 + 4 * (dword)) 3390 #define XELPDP_PMDEMAND_QCLK_GV_BW_MASK REG_GENMASK(31, 16) 3391 #define XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK REG_GENMASK(14, 12) 3392 #define XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK REG_GENMASK(11, 8) 3393 #define XELPDP_PMDEMAND_PIPES_MASK REG_GENMASK(7, 6) 3394 #define XELPDP_PMDEMAND_DBUFS_MASK REG_GENMASK(5, 4) 3395 #define XELPDP_PMDEMAND_PHYS_MASK REG_GENMASK(2, 0) 3396 3397 #define XELPDP_PMDEMAND_REQ_ENABLE REG_BIT(31) 3398 #define XELPDP_PMDEMAND_CDCLK_FREQ_MASK REG_GENMASK(30, 20) 3399 #define XELPDP_PMDEMAND_DDICLK_FREQ_MASK REG_GENMASK(18, 8) 3400 #define XELPDP_PMDEMAND_SCALERS_MASK REG_GENMASK(6, 4) 3401 #define XELPDP_PMDEMAND_PLLS_MASK REG_GENMASK(2, 0) 3402 3403 #define GEN12_DCPR_STATUS_1 _MMIO(0x46440) 3404 #define XELPDP_PMDEMAND_INFLIGHT_STATUS REG_BIT(26) 3405 3406 #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004) 3407 /* Required on all Ironlake and Sandybridge according to the B-Spec. */ 3408 #define ILK_ELPIN_409_SELECT REG_BIT(25) 3409 #define ILK_DPARB_GATE REG_BIT(22) 3410 #define ILK_VSDPFD_FULL REG_BIT(21) 3411 3412 #define FUSE_STRAP _MMIO(0x42014) 3413 #define ILK_INTERNAL_GRAPHICS_DISABLE REG_BIT(31) 3414 #define ILK_INTERNAL_DISPLAY_DISABLE REG_BIT(30) 3415 #define ILK_DISPLAY_DEBUG_DISABLE REG_BIT(29) 3416 #define IVB_PIPE_C_DISABLE REG_BIT(28) 3417 #define ILK_HDCP_DISABLE REG_BIT(25) 3418 #define ILK_eDP_A_DISABLE REG_BIT(24) 3419 #define HSW_CDCLK_LIMIT REG_BIT(24) 3420 #define ILK_DESKTOP REG_BIT(23) 3421 #define HSW_CPU_SSC_ENABLE REG_BIT(21) 3422 3423 #define FUSE_STRAP3 _MMIO(0x42020) 3424 #define HSW_REF_CLK_SELECT REG_BIT(1) 3425 3426 #define ILK_DSPCLK_GATE_D _MMIO(0x42020) 3427 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE REG_BIT(28) 3428 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE REG_BIT(9) 3429 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE REG_BIT(8) 3430 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE REG_BIT(7) 3431 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE REG_BIT(5) 3432 3433 #define IVB_CHICKEN3 _MMIO(0x4200c) 3434 #define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE REG_BIT(5) 3435 #define CHICKEN3_DGMG_DONE_FIX_DISABLE REG_BIT(2) 3436 3437 #define CHICKEN_PAR1_1 _MMIO(0x42080) 3438 #define IGNORE_KVMR_PIPE_A REG_BIT(23) 3439 #define KBL_ARB_FILL_SPARE_22 REG_BIT(22) 3440 #define DIS_RAM_BYPASS_PSR2_MAN_TRACK REG_BIT(16) 3441 #define SKL_DE_COMPRESSED_HASH_MODE REG_BIT(15) 3442 #define HSW_MASK_VBL_TO_PIPE_IN_SRD REG_BIT(15) /* hsw/bdw */ 3443 #define FORCE_ARB_IDLE_PLANES REG_BIT(14) 3444 #define SKL_EDP_PSR_FIX_RDWRAP REG_BIT(3) 3445 #define IGNORE_PSR2_HW_TRACKING REG_BIT(1) 3446 3447 #define CHICKEN_PAR2_1 _MMIO(0x42090) 3448 #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT REG_BIT(14) 3449 3450 #define CHICKEN_MISC_2 _MMIO(0x42084) 3451 #define CHICKEN_MISC_DISABLE_DPT REG_BIT(30) /* adl,dg2 */ 3452 #define KBL_ARB_FILL_SPARE_14 REG_BIT(14) 3453 #define KBL_ARB_FILL_SPARE_13 REG_BIT(13) 3454 #define GLK_CL2_PWR_DOWN REG_BIT(12) 3455 #define GLK_CL1_PWR_DOWN REG_BIT(11) 3456 #define GLK_CL0_PWR_DOWN REG_BIT(10) 3457 3458 #define CHICKEN_MISC_3 _MMIO(0x42088) 3459 #define DP_MST_DPT_DPTP_ALIGN_WA(trans) REG_BIT(9 + (trans) - TRANSCODER_A) 3460 #define DP_MST_SHORT_HBLANK_WA(trans) REG_BIT(5 + (trans) - TRANSCODER_A) 3461 #define DP_MST_FEC_BS_JITTER_WA(trans) REG_BIT(0 + (trans) - TRANSCODER_A) 3462 3463 #define CHICKEN_MISC_4 _MMIO(0x4208c) 3464 #define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13) 3465 #define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0) 3466 #define CHICKEN_FBC_STRIDE(x) REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x)) 3467 3468 #define _CHICKEN_PIPESL_1_A 0x420b0 3469 #define _CHICKEN_PIPESL_1_B 0x420b4 3470 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) 3471 #define HSW_PRI_STRETCH_MAX_MASK REG_GENMASK(28, 27) 3472 #define HSW_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0) 3473 #define HSW_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1) 3474 #define HSW_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2) 3475 #define HSW_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3) 3476 #define HSW_SPR_STRETCH_MAX_MASK REG_GENMASK(26, 25) 3477 #define HSW_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0) 3478 #define HSW_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1) 3479 #define HSW_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2) 3480 #define HSW_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3) 3481 #define HSW_FBCQ_DIS REG_BIT(22) 3482 #define HSW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(15) /* hsw */ 3483 #define SKL_PSR_MASK_PLANE_FLIP REG_BIT(11) /* skl+ */ 3484 #define SKL_PLANE1_STRETCH_MAX_MASK REG_GENMASK(1, 0) 3485 #define SKL_PLANE1_STRETCH_MAX_X8 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0) 3486 #define SKL_PLANE1_STRETCH_MAX_X4 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1) 3487 #define SKL_PLANE1_STRETCH_MAX_X2 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2) 3488 #define SKL_PLANE1_STRETCH_MAX_X1 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3) 3489 #define BDW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(0) /* bdw */ 3490 3491 #define _CHICKEN_TRANS_A 0x420c0 3492 #define _CHICKEN_TRANS_B 0x420c4 3493 #define _CHICKEN_TRANS_C 0x420c8 3494 #define _CHICKEN_TRANS_EDP 0x420cc 3495 #define _CHICKEN_TRANS_D 0x420d8 3496 #define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \ 3497 [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \ 3498 [TRANSCODER_A] = _CHICKEN_TRANS_A, \ 3499 [TRANSCODER_B] = _CHICKEN_TRANS_B, \ 3500 [TRANSCODER_C] = _CHICKEN_TRANS_C, \ 3501 [TRANSCODER_D] = _CHICKEN_TRANS_D)) 3502 #define _MTL_CHICKEN_TRANS_A 0x604e0 3503 #define _MTL_CHICKEN_TRANS_B 0x614e0 3504 #define MTL_CHICKEN_TRANS(trans) _MMIO_TRANS((trans), \ 3505 _MTL_CHICKEN_TRANS_A, \ 3506 _MTL_CHICKEN_TRANS_B) 3507 #define PIPE_VBLANK_WITH_DELAY REG_BIT(31) /* tgl+ */ 3508 #define SKL_UNMASK_VBL_TO_PIPE_IN_SRD REG_BIT(30) /* skl+ */ 3509 #define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) 3510 #define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x) 3511 #define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */ 3512 #define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23) 3513 #define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19) 3514 #define ADLP_1_BASED_X_GRANULARITY REG_BIT(18) 3515 #define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18) 3516 #define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */ 3517 #define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */ 3518 #define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15) 3519 #define DP_FEC_BS_JITTER_WA REG_BIT(15) 3520 #define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12) 3521 #define DP_DSC_INSERT_SF_AT_EOL_WA REG_BIT(4) 3522 3523 #define DISP_ARB_CTL _MMIO(0x45000) 3524 #define DISP_FBC_MEMORY_WAKE REG_BIT(31) 3525 #define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13) 3526 #define DISP_FBC_WM_DIS REG_BIT(15) 3527 3528 #define DISP_ARB_CTL2 _MMIO(0x45004) 3529 #define DISP_DATA_PARTITION_5_6 REG_BIT(6) 3530 #define DISP_IPC_ENABLE REG_BIT(3) 3531 3532 #define GEN7_MSG_CTL _MMIO(0x45010) 3533 #define WAIT_FOR_PCH_RESET_ACK (1 << 1) 3534 #define WAIT_FOR_PCH_FLR_ACK (1 << 0) 3535 3536 #define _BW_BUDDY0_CTL 0x45130 3537 #define _BW_BUDDY1_CTL 0x45140 3538 #define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \ 3539 _BW_BUDDY0_CTL, \ 3540 _BW_BUDDY1_CTL)) 3541 #define BW_BUDDY_DISABLE REG_BIT(31) 3542 #define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16) 3543 #define BW_BUDDY_TLB_REQ_TIMER(x) REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x) 3544 3545 #define _BW_BUDDY0_PAGE_MASK 0x45134 3546 #define _BW_BUDDY1_PAGE_MASK 0x45144 3547 #define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \ 3548 _BW_BUDDY0_PAGE_MASK, \ 3549 _BW_BUDDY1_PAGE_MASK)) 3550 3551 #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) 3552 #define MTL_RESET_PICA_HANDSHAKE_EN REG_BIT(6) 3553 #define RESET_PCH_HANDSHAKE_ENABLE REG_BIT(4) 3554 3555 #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) 3556 #define LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31) 3557 #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30) 3558 #define LATENCY_REPORTING_REMOVED_PIPE_C REG_BIT(25) 3559 #define LATENCY_REPORTING_REMOVED_PIPE_B REG_BIT(24) 3560 #define LATENCY_REPORTING_REMOVED_PIPE_A REG_BIT(23) 3561 #define ICL_DELAY_PMRSP REG_BIT(22) 3562 #define DISABLE_FLR_SRC REG_BIT(15) 3563 #define MASK_WAKEMEM REG_BIT(13) 3564 #define DDI_CLOCK_REG_ACCESS REG_BIT(7) 3565 3566 #define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434) 3567 #define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27) 3568 #define DCPR_MASK_LPMODE REG_BIT(26) 3569 #define DCPR_SEND_RESP_IMM REG_BIT(25) 3570 #define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24) 3571 3572 #define XELPD_CHICKEN_DCPR_3 _MMIO(0x46438) 3573 #define DMD_RSP_TIMEOUT_DISABLE REG_BIT(19) 3574 3575 #define SKL_DFSM _MMIO(0x51000) 3576 #define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27) 3577 #define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25) 3578 #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23) 3579 #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23) 3580 #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23) 3581 #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23) 3582 #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23) 3583 #define ICL_DFSM_DMC_DISABLE (1 << 23) 3584 #define SKL_DFSM_PIPE_A_DISABLE (1 << 30) 3585 #define SKL_DFSM_PIPE_B_DISABLE (1 << 21) 3586 #define SKL_DFSM_PIPE_C_DISABLE (1 << 28) 3587 #define TGL_DFSM_PIPE_D_DISABLE (1 << 22) 3588 #define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7) 3589 3590 #define XE2LPD_DE_CAP _MMIO(0x41100) 3591 #define XE2LPD_DE_CAP_3DLUT_MASK REG_GENMASK(31, 30) 3592 #define XE2LPD_DE_CAP_DSC_MASK REG_GENMASK(29, 28) 3593 #define XE2LPD_DE_CAP_DSC_REMOVED 1 3594 #define XE2LPD_DE_CAP_SCALER_MASK REG_GENMASK(27, 26) 3595 #define XE2LPD_DE_CAP_SCALER_SINGLE 1 3596 3597 #define SKL_DSSM _MMIO(0x51004) 3598 #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29) 3599 #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29) 3600 #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29) 3601 #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29) 3602 3603 #define GMD_ID_DISPLAY _MMIO(0x510a0) 3604 #define GMD_ID_ARCH_MASK REG_GENMASK(31, 22) 3605 #define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14) 3606 #define GMD_ID_STEP REG_GENMASK(5, 0) 3607 3608 /*GEN11 chicken */ 3609 #define _PIPEA_CHICKEN 0x70038 3610 #define _PIPEB_CHICKEN 0x71038 3611 #define _PIPEC_CHICKEN 0x72038 3612 #define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\ 3613 _PIPEB_CHICKEN) 3614 #define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30) 3615 #define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30) 3616 #define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15) 3617 #define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12) 3618 #define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7) 3619 3620 /* PCH */ 3621 3622 #define PCH_DISPLAY_BASE 0xc0000u 3623 3624 /* south display engine interrupt: IBX */ 3625 #define SDE_AUDIO_POWER_D (1 << 27) 3626 #define SDE_AUDIO_POWER_C (1 << 26) 3627 #define SDE_AUDIO_POWER_B (1 << 25) 3628 #define SDE_AUDIO_POWER_SHIFT (25) 3629 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) 3630 #define SDE_GMBUS (1 << 24) 3631 #define SDE_AUDIO_HDCP_TRANSB (1 << 23) 3632 #define SDE_AUDIO_HDCP_TRANSA (1 << 22) 3633 #define SDE_AUDIO_HDCP_MASK (3 << 22) 3634 #define SDE_AUDIO_TRANSB (1 << 21) 3635 #define SDE_AUDIO_TRANSA (1 << 20) 3636 #define SDE_AUDIO_TRANS_MASK (3 << 20) 3637 #define SDE_POISON (1 << 19) 3638 /* 18 reserved */ 3639 #define SDE_FDI_RXB (1 << 17) 3640 #define SDE_FDI_RXA (1 << 16) 3641 #define SDE_FDI_MASK (3 << 16) 3642 #define SDE_AUXD (1 << 15) 3643 #define SDE_AUXC (1 << 14) 3644 #define SDE_AUXB (1 << 13) 3645 #define SDE_AUX_MASK (7 << 13) 3646 /* 12 reserved */ 3647 #define SDE_CRT_HOTPLUG (1 << 11) 3648 #define SDE_PORTD_HOTPLUG (1 << 10) 3649 #define SDE_PORTC_HOTPLUG (1 << 9) 3650 #define SDE_PORTB_HOTPLUG (1 << 8) 3651 #define SDE_SDVOB_HOTPLUG (1 << 6) 3652 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \ 3653 SDE_SDVOB_HOTPLUG | \ 3654 SDE_PORTB_HOTPLUG | \ 3655 SDE_PORTC_HOTPLUG | \ 3656 SDE_PORTD_HOTPLUG) 3657 #define SDE_TRANSB_CRC_DONE (1 << 5) 3658 #define SDE_TRANSB_CRC_ERR (1 << 4) 3659 #define SDE_TRANSB_FIFO_UNDER (1 << 3) 3660 #define SDE_TRANSA_CRC_DONE (1 << 2) 3661 #define SDE_TRANSA_CRC_ERR (1 << 1) 3662 #define SDE_TRANSA_FIFO_UNDER (1 << 0) 3663 #define SDE_TRANS_MASK (0x3f) 3664 3665 /* south display engine interrupt: CPT - CNP */ 3666 #define SDE_AUDIO_POWER_D_CPT (1 << 31) 3667 #define SDE_AUDIO_POWER_C_CPT (1 << 30) 3668 #define SDE_AUDIO_POWER_B_CPT (1 << 29) 3669 #define SDE_AUDIO_POWER_SHIFT_CPT 29 3670 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29) 3671 #define SDE_AUXD_CPT (1 << 27) 3672 #define SDE_AUXC_CPT (1 << 26) 3673 #define SDE_AUXB_CPT (1 << 25) 3674 #define SDE_AUX_MASK_CPT (7 << 25) 3675 #define SDE_PORTE_HOTPLUG_SPT (1 << 25) 3676 #define SDE_PORTA_HOTPLUG_SPT (1 << 24) 3677 #define SDE_PORTD_HOTPLUG_CPT (1 << 23) 3678 #define SDE_PORTC_HOTPLUG_CPT (1 << 22) 3679 #define SDE_PORTB_HOTPLUG_CPT (1 << 21) 3680 #define SDE_CRT_HOTPLUG_CPT (1 << 19) 3681 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18) 3682 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ 3683 SDE_SDVOB_HOTPLUG_CPT | \ 3684 SDE_PORTD_HOTPLUG_CPT | \ 3685 SDE_PORTC_HOTPLUG_CPT | \ 3686 SDE_PORTB_HOTPLUG_CPT) 3687 #define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \ 3688 SDE_PORTD_HOTPLUG_CPT | \ 3689 SDE_PORTC_HOTPLUG_CPT | \ 3690 SDE_PORTB_HOTPLUG_CPT | \ 3691 SDE_PORTA_HOTPLUG_SPT) 3692 #define SDE_GMBUS_CPT (1 << 17) 3693 #define SDE_ERROR_CPT (1 << 16) 3694 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) 3695 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) 3696 #define SDE_FDI_RXC_CPT (1 << 8) 3697 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) 3698 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) 3699 #define SDE_FDI_RXB_CPT (1 << 4) 3700 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) 3701 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) 3702 #define SDE_FDI_RXA_CPT (1 << 0) 3703 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \ 3704 SDE_AUDIO_CP_REQ_B_CPT | \ 3705 SDE_AUDIO_CP_REQ_A_CPT) 3706 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \ 3707 SDE_AUDIO_CP_CHG_B_CPT | \ 3708 SDE_AUDIO_CP_CHG_A_CPT) 3709 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \ 3710 SDE_FDI_RXB_CPT | \ 3711 SDE_FDI_RXA_CPT) 3712 3713 /* south display engine interrupt: ICP/TGP/MTP */ 3714 #define SDE_PICAINTERRUPT REG_BIT(31) 3715 #define SDE_GMBUS_ICP (1 << 23) 3716 #define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin)) 3717 #define SDE_TC_HOTPLUG_DG2(hpd_pin) REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */ 3718 #define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin)) 3719 #define SDE_DDI_HOTPLUG_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \ 3720 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \ 3721 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \ 3722 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A)) 3723 #define SDE_TC_HOTPLUG_MASK_ICP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \ 3724 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \ 3725 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \ 3726 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \ 3727 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \ 3728 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1)) 3729 3730 #define SDEISR _MMIO(0xc4000) 3731 #define SDEIMR _MMIO(0xc4004) 3732 #define SDEIIR _MMIO(0xc4008) 3733 #define SDEIER _MMIO(0xc400c) 3734 3735 #define SERR_INT _MMIO(0xc4040) 3736 #define SERR_INT_POISON (1 << 31) 3737 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) 3738 3739 /* digital port hotplug */ 3740 #define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */ 3741 #define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */ 3742 #define BXT_DDIA_HPD_INVERT (1 << 27) 3743 #define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */ 3744 #define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */ 3745 #define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */ 3746 #define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */ 3747 #define PORTD_HOTPLUG_ENABLE (1 << 20) 3748 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */ 3749 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */ 3750 #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */ 3751 #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */ 3752 #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */ 3753 #define PORTD_HOTPLUG_STATUS_MASK (3 << 16) 3754 #define PORTD_HOTPLUG_NO_DETECT (0 << 16) 3755 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) 3756 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16) 3757 #define PORTC_HOTPLUG_ENABLE (1 << 12) 3758 #define BXT_DDIC_HPD_INVERT (1 << 11) 3759 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */ 3760 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */ 3761 #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */ 3762 #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */ 3763 #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */ 3764 #define PORTC_HOTPLUG_STATUS_MASK (3 << 8) 3765 #define PORTC_HOTPLUG_NO_DETECT (0 << 8) 3766 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) 3767 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8) 3768 #define PORTB_HOTPLUG_ENABLE (1 << 4) 3769 #define BXT_DDIB_HPD_INVERT (1 << 3) 3770 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */ 3771 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */ 3772 #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */ 3773 #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */ 3774 #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */ 3775 #define PORTB_HOTPLUG_STATUS_MASK (3 << 0) 3776 #define PORTB_HOTPLUG_NO_DETECT (0 << 0) 3777 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) 3778 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0) 3779 #define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \ 3780 BXT_DDIB_HPD_INVERT | \ 3781 BXT_DDIC_HPD_INVERT) 3782 3783 #define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */ 3784 #define PORTE_HOTPLUG_ENABLE (1 << 4) 3785 #define PORTE_HOTPLUG_STATUS_MASK (3 << 0) 3786 #define PORTE_HOTPLUG_NO_DETECT (0 << 0) 3787 #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0) 3788 #define PORTE_HOTPLUG_LONG_DETECT (2 << 0) 3789 3790 /* This register is a reuse of PCH_PORT_HOTPLUG register. The 3791 * functionality covered in PCH_PORT_HOTPLUG is split into 3792 * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC. 3793 */ 3794 3795 #define SHOTPLUG_CTL_DDI _MMIO(0xc4030) 3796 #define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (_HPD_PIN_DDI(hpd_pin) * 4)) 3797 #define SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(hpd_pin) (0x4 << (_HPD_PIN_DDI(hpd_pin) * 4)) 3798 #define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4)) 3799 #define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin) (0x0 << (_HPD_PIN_DDI(hpd_pin) * 4)) 3800 #define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin) (0x1 << (_HPD_PIN_DDI(hpd_pin) * 4)) 3801 #define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin) (0x2 << (_HPD_PIN_DDI(hpd_pin) * 4)) 3802 #define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4)) 3803 3804 #define SHOTPLUG_CTL_TC _MMIO(0xc4034) 3805 #define ICP_TC_HPD_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4)) 3806 #define ICP_TC_HPD_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4)) 3807 #define ICP_TC_HPD_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4)) 3808 3809 #define SHPD_FILTER_CNT _MMIO(0xc4038) 3810 #define SHPD_FILTER_CNT_500_ADJ 0x001D9 3811 #define SHPD_FILTER_CNT_250 0x000F8 3812 3813 #define _PCH_DPLL_A 0xc6014 3814 #define _PCH_DPLL_B 0xc6018 3815 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) 3816 3817 #define _PCH_FPA0 0xc6040 3818 #define FP_CB_TUNE (0x3 << 22) 3819 #define _PCH_FPA1 0xc6044 3820 #define _PCH_FPB0 0xc6048 3821 #define _PCH_FPB1 0xc604c 3822 #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0) 3823 #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1) 3824 3825 #define PCH_DPLL_TEST _MMIO(0xc606c) 3826 3827 #define PCH_DREF_CONTROL _MMIO(0xC6200) 3828 #define DREF_CONTROL_MASK 0x7fc3 3829 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13) 3830 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13) 3831 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13) 3832 #define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13) 3833 #define DREF_SSC_SOURCE_DISABLE (0 << 11) 3834 #define DREF_SSC_SOURCE_ENABLE (2 << 11) 3835 #define DREF_SSC_SOURCE_MASK (3 << 11) 3836 #define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9) 3837 #define DREF_NONSPREAD_CK505_ENABLE (1 << 9) 3838 #define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9) 3839 #define DREF_NONSPREAD_SOURCE_MASK (3 << 9) 3840 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7) 3841 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7) 3842 #define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7) 3843 #define DREF_SSC4_DOWNSPREAD (0 << 6) 3844 #define DREF_SSC4_CENTERSPREAD (1 << 6) 3845 #define DREF_SSC1_DISABLE (0 << 1) 3846 #define DREF_SSC1_ENABLE (1 << 1) 3847 #define DREF_SSC4_DISABLE (0) 3848 #define DREF_SSC4_ENABLE (1) 3849 3850 #define PCH_RAWCLK_FREQ _MMIO(0xc6204) 3851 #define FDL_TP1_TIMER_SHIFT 12 3852 #define FDL_TP1_TIMER_MASK (3 << 12) 3853 #define FDL_TP2_TIMER_SHIFT 10 3854 #define FDL_TP2_TIMER_MASK (3 << 10) 3855 #define RAWCLK_FREQ_MASK 0x3ff 3856 #define CNP_RAWCLK_DIV_MASK (0x3ff << 16) 3857 #define CNP_RAWCLK_DIV(div) ((div) << 16) 3858 #define CNP_RAWCLK_FRAC_MASK (0xf << 26) 3859 #define CNP_RAWCLK_DEN(den) ((den) << 26) 3860 #define ICP_RAWCLK_NUM(num) ((num) << 11) 3861 3862 #define PCH_DPLL_TMR_CFG _MMIO(0xc6208) 3863 3864 #define PCH_SSC4_PARMS _MMIO(0xc6210) 3865 #define PCH_SSC4_AUX_PARMS _MMIO(0xc6214) 3866 3867 #define PCH_DPLL_SEL _MMIO(0xc7000) 3868 #define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4)) 3869 #define TRANS_DPLLA_SEL(pipe) 0 3870 #define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3)) 3871 3872 /* transcoder */ 3873 3874 #define _PCH_TRANS_HTOTAL_A 0xe0000 3875 #define TRANS_HTOTAL_SHIFT 16 3876 #define TRANS_HACTIVE_SHIFT 0 3877 #define _PCH_TRANS_HBLANK_A 0xe0004 3878 #define TRANS_HBLANK_END_SHIFT 16 3879 #define TRANS_HBLANK_START_SHIFT 0 3880 #define _PCH_TRANS_HSYNC_A 0xe0008 3881 #define TRANS_HSYNC_END_SHIFT 16 3882 #define TRANS_HSYNC_START_SHIFT 0 3883 #define _PCH_TRANS_VTOTAL_A 0xe000c 3884 #define TRANS_VTOTAL_SHIFT 16 3885 #define TRANS_VACTIVE_SHIFT 0 3886 #define _PCH_TRANS_VBLANK_A 0xe0010 3887 #define TRANS_VBLANK_END_SHIFT 16 3888 #define TRANS_VBLANK_START_SHIFT 0 3889 #define _PCH_TRANS_VSYNC_A 0xe0014 3890 #define TRANS_VSYNC_END_SHIFT 16 3891 #define TRANS_VSYNC_START_SHIFT 0 3892 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028 3893 3894 #define _PCH_TRANSA_DATA_M1 0xe0030 3895 #define _PCH_TRANSA_DATA_N1 0xe0034 3896 #define _PCH_TRANSA_DATA_M2 0xe0038 3897 #define _PCH_TRANSA_DATA_N2 0xe003c 3898 #define _PCH_TRANSA_LINK_M1 0xe0040 3899 #define _PCH_TRANSA_LINK_N1 0xe0044 3900 #define _PCH_TRANSA_LINK_M2 0xe0048 3901 #define _PCH_TRANSA_LINK_N2 0xe004c 3902 3903 /* Per-transcoder DIP controls (PCH) */ 3904 #define _VIDEO_DIP_CTL_A 0xe0200 3905 #define _VIDEO_DIP_DATA_A 0xe0208 3906 #define _VIDEO_DIP_GCP_A 0xe0210 3907 #define GCP_COLOR_INDICATION (1 << 2) 3908 #define GCP_DEFAULT_PHASE_ENABLE (1 << 1) 3909 #define GCP_AV_MUTE (1 << 0) 3910 3911 #define _VIDEO_DIP_CTL_B 0xe1200 3912 #define _VIDEO_DIP_DATA_B 0xe1208 3913 #define _VIDEO_DIP_GCP_B 0xe1210 3914 3915 #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) 3916 #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) 3917 #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) 3918 3919 /* Per-transcoder DIP controls (VLV) */ 3920 #define _VLV_VIDEO_DIP_CTL_A 0x60200 3921 #define _VLV_VIDEO_DIP_CTL_B 0x61170 3922 #define _CHV_VIDEO_DIP_CTL_C 0x611f0 3923 #define VLV_TVIDEO_DIP_CTL(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \ 3924 _VLV_VIDEO_DIP_CTL_A, \ 3925 _VLV_VIDEO_DIP_CTL_B, \ 3926 _CHV_VIDEO_DIP_CTL_C) 3927 3928 #define _VLV_VIDEO_DIP_DATA_A 0x60208 3929 #define _VLV_VIDEO_DIP_DATA_B 0x61174 3930 #define _CHV_VIDEO_DIP_DATA_C 0x611f4 3931 #define VLV_TVIDEO_DIP_DATA(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \ 3932 _VLV_VIDEO_DIP_DATA_A, \ 3933 _VLV_VIDEO_DIP_DATA_B, \ 3934 _CHV_VIDEO_DIP_DATA_C) 3935 3936 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A 0x60210 3937 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B 0x61178 3938 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C 0x611f8 3939 #define VLV_TVIDEO_DIP_GCP(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \ 3940 _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \ 3941 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, \ 3942 _CHV_VIDEO_DIP_GDCP_PAYLOAD_C) 3943 3944 /* Haswell DIP controls */ 3945 3946 #define _HSW_VIDEO_DIP_CTL_A 0x60200 3947 #define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220 3948 #define _HSW_VIDEO_DIP_VS_DATA_A 0x60260 3949 #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 3950 #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 3951 #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320 3952 #define _ADL_VIDEO_DIP_AS_DATA_A 0x60484 3953 #define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440 3954 #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240 3955 #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280 3956 #define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 3957 #define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300 3958 #define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344 3959 #define _HSW_VIDEO_DIP_GCP_A 0x60210 3960 3961 #define _HSW_VIDEO_DIP_CTL_B 0x61200 3962 #define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220 3963 #define _HSW_VIDEO_DIP_VS_DATA_B 0x61260 3964 #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 3965 #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 3966 #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320 3967 #define _ADL_VIDEO_DIP_AS_DATA_B 0x61484 3968 #define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440 3969 #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240 3970 #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280 3971 #define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 3972 #define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300 3973 #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344 3974 #define _HSW_VIDEO_DIP_GCP_B 0x61210 3975 3976 /* Icelake PPS_DATA and _ECC DIP Registers. 3977 * These are available for transcoders B,C and eDP. 3978 * Adding the _A so as to reuse the _MMIO_TRANS2 3979 * definition, with which it offsets to the right location. 3980 */ 3981 3982 #define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350 3983 #define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350 3984 #define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4 3985 #define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4 3986 3987 #define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_CTL_A) 3988 #define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GCP_A) 3989 #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4) 3990 #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4) 3991 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) 3992 #define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4) 3993 #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) 3994 #define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4) 3995 #define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4) 3996 #define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4) 3997 /*ADLP and later: */ 3998 #define ADL_TVIDEO_DIP_AS_SDP_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans,\ 3999 _ADL_VIDEO_DIP_AS_DATA_A + (i) * 4) 4000 4001 #define _HSW_STEREO_3D_CTL_A 0x70020 4002 #define S3D_ENABLE (1 << 31) 4003 #define _HSW_STEREO_3D_CTL_B 0x71020 4004 4005 #define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(dev_priv, trans, _HSW_STEREO_3D_CTL_A) 4006 4007 #define _PCH_TRANS_HTOTAL_B 0xe1000 4008 #define _PCH_TRANS_HBLANK_B 0xe1004 4009 #define _PCH_TRANS_HSYNC_B 0xe1008 4010 #define _PCH_TRANS_VTOTAL_B 0xe100c 4011 #define _PCH_TRANS_VBLANK_B 0xe1010 4012 #define _PCH_TRANS_VSYNC_B 0xe1014 4013 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 4014 4015 #define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B) 4016 #define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B) 4017 #define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B) 4018 #define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B) 4019 #define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B) 4020 #define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B) 4021 #define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B) 4022 4023 #define _PCH_TRANSB_DATA_M1 0xe1030 4024 #define _PCH_TRANSB_DATA_N1 0xe1034 4025 #define _PCH_TRANSB_DATA_M2 0xe1038 4026 #define _PCH_TRANSB_DATA_N2 0xe103c 4027 #define _PCH_TRANSB_LINK_M1 0xe1040 4028 #define _PCH_TRANSB_LINK_N1 0xe1044 4029 #define _PCH_TRANSB_LINK_M2 0xe1048 4030 #define _PCH_TRANSB_LINK_N2 0xe104c 4031 4032 #define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1) 4033 #define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1) 4034 #define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2) 4035 #define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2) 4036 #define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1) 4037 #define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1) 4038 #define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2) 4039 #define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2) 4040 4041 #define _PCH_TRANSACONF 0xf0008 4042 #define _PCH_TRANSBCONF 0xf1008 4043 #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF) 4044 #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */ 4045 #define TRANS_ENABLE REG_BIT(31) 4046 #define TRANS_STATE_ENABLE REG_BIT(30) 4047 #define TRANS_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* ibx */ 4048 #define TRANS_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */ 4049 #define TRANS_INTERLACE_MASK REG_GENMASK(23, 21) 4050 #define TRANS_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0) 4051 #define TRANS_INTERLACE_LEGACY_VSYNC_IBX REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */ 4052 #define TRANS_INTERLACE_INTERLACED REG_FIELD_PREP(TRANS_INTERLACE_MASK, 3) 4053 #define TRANS_BPC_MASK REG_GENMASK(7, 5) /* ibx */ 4054 #define TRANS_BPC_8 REG_FIELD_PREP(TRANS_BPC_MASK, 0) 4055 #define TRANS_BPC_10 REG_FIELD_PREP(TRANS_BPC_MASK, 1) 4056 #define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2) 4057 #define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, 3) 4058 4059 #define _TRANSA_CHICKEN1 0xf0060 4060 #define _TRANSB_CHICKEN1 0xf1060 4061 #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) 4062 #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE REG_BIT(10) 4063 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE REG_BIT(4) 4064 4065 #define _TRANSA_CHICKEN2 0xf0064 4066 #define _TRANSB_CHICKEN2 0xf1064 4067 #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) 4068 #define TRANS_CHICKEN2_TIMING_OVERRIDE REG_BIT(31) 4069 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED REG_BIT(29) 4070 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) 4071 #define TRANS_CHICKEN2_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */ 4072 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER REG_BIT(26) 4073 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH REG_BIT(25) 4074 4075 #define SOUTH_CHICKEN1 _MMIO(0xc2000) 4076 #define FDIA_PHASE_SYNC_SHIFT_OVR 19 4077 #define FDIA_PHASE_SYNC_SHIFT_EN 18 4078 #define INVERT_DDIE_HPD REG_BIT(28) 4079 #define INVERT_DDID_HPD_MTP REG_BIT(27) 4080 #define INVERT_TC4_HPD REG_BIT(26) 4081 #define INVERT_TC3_HPD REG_BIT(25) 4082 #define INVERT_TC2_HPD REG_BIT(24) 4083 #define INVERT_TC1_HPD REG_BIT(23) 4084 #define INVERT_DDID_HPD (1 << 18) 4085 #define INVERT_DDIC_HPD (1 << 17) 4086 #define INVERT_DDIB_HPD (1 << 16) 4087 #define INVERT_DDIA_HPD (1 << 15) 4088 #define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) 4089 #define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) 4090 #define FDI_BC_BIFURCATION_SELECT (1 << 12) 4091 #define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8) 4092 #define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8) 4093 #define SBCLK_RUN_REFCLK_DIS (1 << 7) 4094 #define ICP_SECOND_PPS_IO_SELECT REG_BIT(2) 4095 #define SPT_PWM_GRANULARITY (1 << 0) 4096 #define SOUTH_CHICKEN2 _MMIO(0xc2004) 4097 #define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13) 4098 #define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12) 4099 #define LPT_PWM_GRANULARITY (1 << 5) 4100 #define DPLS_EDP_PPS_FIX_DIS (1 << 0) 4101 4102 #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020) 4103 #define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31) 4104 #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30) 4105 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29) 4106 #define PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15) 4107 #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14) 4108 #define CNP_PWM_CGE_GATING_DISABLE (1 << 13) 4109 #define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12) 4110 4111 #define _PCH_DP_B 0xe4100 4112 #define PCH_DP_B _MMIO(_PCH_DP_B) 4113 #define _PCH_DPB_AUX_CH_CTL 0xe4110 4114 #define _PCH_DPB_AUX_CH_DATA1 0xe4114 4115 #define _PCH_DPB_AUX_CH_DATA2 0xe4118 4116 #define _PCH_DPB_AUX_CH_DATA3 0xe411c 4117 #define _PCH_DPB_AUX_CH_DATA4 0xe4120 4118 #define _PCH_DPB_AUX_CH_DATA5 0xe4124 4119 4120 #define _PCH_DP_C 0xe4200 4121 #define PCH_DP_C _MMIO(_PCH_DP_C) 4122 #define _PCH_DPC_AUX_CH_CTL 0xe4210 4123 #define _PCH_DPC_AUX_CH_DATA1 0xe4214 4124 #define _PCH_DPC_AUX_CH_DATA2 0xe4218 4125 #define _PCH_DPC_AUX_CH_DATA3 0xe421c 4126 #define _PCH_DPC_AUX_CH_DATA4 0xe4220 4127 #define _PCH_DPC_AUX_CH_DATA5 0xe4224 4128 4129 #define _PCH_DP_D 0xe4300 4130 #define PCH_DP_D _MMIO(_PCH_DP_D) 4131 #define _PCH_DPD_AUX_CH_CTL 0xe4310 4132 #define _PCH_DPD_AUX_CH_DATA1 0xe4314 4133 #define _PCH_DPD_AUX_CH_DATA2 0xe4318 4134 #define _PCH_DPD_AUX_CH_DATA3 0xe431c 4135 #define _PCH_DPD_AUX_CH_DATA4 0xe4320 4136 #define _PCH_DPD_AUX_CH_DATA5 0xe4324 4137 4138 #define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL) 4139 #define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ 4140 4141 /* CPT */ 4142 #define _TRANS_DP_CTL_A 0xe0300 4143 #define _TRANS_DP_CTL_B 0xe1300 4144 #define _TRANS_DP_CTL_C 0xe2300 4145 #define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B) 4146 #define TRANS_DP_OUTPUT_ENABLE REG_BIT(31) 4147 #define TRANS_DP_PORT_SEL_MASK REG_GENMASK(30, 29) 4148 #define TRANS_DP_PORT_SEL_NONE REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, 3) 4149 #define TRANS_DP_PORT_SEL(port) REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B) 4150 #define TRANS_DP_AUDIO_ONLY REG_BIT(26) 4151 #define TRANS_DP_ENH_FRAMING REG_BIT(18) 4152 #define TRANS_DP_BPC_MASK REG_GENMASK(10, 9) 4153 #define TRANS_DP_BPC_8 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0) 4154 #define TRANS_DP_BPC_10 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 1) 4155 #define TRANS_DP_BPC_6 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 2) 4156 #define TRANS_DP_BPC_12 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 3) 4157 #define TRANS_DP_VSYNC_ACTIVE_HIGH REG_BIT(4) 4158 #define TRANS_DP_HSYNC_ACTIVE_HIGH REG_BIT(3) 4159 4160 #define _TRANS_DP2_CTL_A 0x600a0 4161 #define _TRANS_DP2_CTL_B 0x610a0 4162 #define _TRANS_DP2_CTL_C 0x620a0 4163 #define _TRANS_DP2_CTL_D 0x630a0 4164 #define TRANS_DP2_CTL(trans) _MMIO_TRANS(trans, _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B) 4165 #define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31) 4166 #define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30) 4167 #define TRANS_DP2_DEBUG_ENABLE REG_BIT(23) 4168 4169 #define _TRANS_DP2_VFREQHIGH_A 0x600a4 4170 #define _TRANS_DP2_VFREQHIGH_B 0x610a4 4171 #define _TRANS_DP2_VFREQHIGH_C 0x620a4 4172 #define _TRANS_DP2_VFREQHIGH_D 0x630a4 4173 #define TRANS_DP2_VFREQHIGH(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQHIGH_A, _TRANS_DP2_VFREQHIGH_B) 4174 #define TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK REG_GENMASK(31, 8) 4175 #define TRANS_DP2_VFREQ_PIXEL_CLOCK(clk_hz) REG_FIELD_PREP(TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK, (clk_hz)) 4176 4177 #define _TRANS_DP2_VFREQLOW_A 0x600a8 4178 #define _TRANS_DP2_VFREQLOW_B 0x610a8 4179 #define _TRANS_DP2_VFREQLOW_C 0x620a8 4180 #define _TRANS_DP2_VFREQLOW_D 0x630a8 4181 #define TRANS_DP2_VFREQLOW(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQLOW_A, _TRANS_DP2_VFREQLOW_B) 4182 4183 /* SNB eDP training params */ 4184 /* SNB A-stepping */ 4185 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) 4186 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) 4187 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) 4188 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22) 4189 /* SNB B-stepping */ 4190 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22) 4191 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22) 4192 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22) 4193 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22) 4194 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22) 4195 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22) 4196 4197 /* IVB */ 4198 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22) 4199 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22) 4200 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22) 4201 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22) 4202 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22) 4203 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22) 4204 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22) 4205 4206 /* legacy values */ 4207 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22) 4208 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22) 4209 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22) 4210 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22) 4211 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22) 4212 4213 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22) 4214 4215 #define VLV_PMWGICZ _MMIO(0x1300a4) 4216 4217 #define HSW_EDRAM_CAP _MMIO(0x120010) 4218 #define EDRAM_ENABLED 0x1 4219 #define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf) 4220 #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7) 4221 #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3) 4222 4223 #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C) 4224 #define PIXEL_OVERLAP_CNT_MASK (3 << 30) 4225 #define PIXEL_OVERLAP_CNT_SHIFT 30 4226 4227 #define GEN6_PCODE_MAILBOX _MMIO(0x138124) 4228 #define GEN6_PCODE_READY (1 << 31) 4229 #define GEN6_PCODE_MB_PARAM2 REG_GENMASK(23, 16) 4230 #define GEN6_PCODE_MB_PARAM1 REG_GENMASK(15, 8) 4231 #define GEN6_PCODE_MB_COMMAND REG_GENMASK(7, 0) 4232 #define GEN6_PCODE_ERROR_MASK 0xFF 4233 #define GEN6_PCODE_SUCCESS 0x0 4234 #define GEN6_PCODE_ILLEGAL_CMD 0x1 4235 #define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2 4236 #define GEN6_PCODE_TIMEOUT 0x3 4237 #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF 4238 #define GEN7_PCODE_TIMEOUT 0x2 4239 #define GEN7_PCODE_ILLEGAL_DATA 0x3 4240 #define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4 4241 #define GEN11_PCODE_LOCKED 0x6 4242 #define GEN11_PCODE_REJECTED 0x11 4243 #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10 4244 #define GEN6_PCODE_WRITE_RC6VIDS 0x4 4245 #define GEN6_PCODE_READ_RC6VIDS 0x5 4246 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) 4247 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) 4248 #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18 4249 #define GEN9_PCODE_READ_MEM_LATENCY 0x6 4250 #define GEN9_MEM_LATENCY_LEVEL_3_7_MASK REG_GENMASK(31, 24) 4251 #define GEN9_MEM_LATENCY_LEVEL_2_6_MASK REG_GENMASK(23, 16) 4252 #define GEN9_MEM_LATENCY_LEVEL_1_5_MASK REG_GENMASK(15, 8) 4253 #define GEN9_MEM_LATENCY_LEVEL_0_4_MASK REG_GENMASK(7, 0) 4254 #define SKL_PCODE_LOAD_HDCP_KEYS 0x5 4255 #define SKL_PCODE_CDCLK_CONTROL 0x7 4256 #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3 4257 #define SKL_CDCLK_READY_FOR_CHANGE 0x1 4258 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 4259 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 4260 #define GEN6_READ_OC_PARAMS 0xc 4261 #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd 4262 #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8) 4263 #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8)) 4264 #define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO ((0) | (0x2 << 8)) 4265 #define DISPLAY_TO_PCODE_CDCLK_MAX 0x28D 4266 #define DISPLAY_TO_PCODE_VOLTAGE_MASK REG_GENMASK(1, 0) 4267 #define DISPLAY_TO_PCODE_VOLTAGE_MAX DISPLAY_TO_PCODE_VOLTAGE_MASK 4268 #define DISPLAY_TO_PCODE_CDCLK_VALID REG_BIT(27) 4269 #define DISPLAY_TO_PCODE_PIPE_COUNT_VALID REG_BIT(31) 4270 #define DISPLAY_TO_PCODE_CDCLK_MASK REG_GENMASK(25, 16) 4271 #define DISPLAY_TO_PCODE_PIPE_COUNT_MASK REG_GENMASK(30, 28) 4272 #define DISPLAY_TO_PCODE_CDCLK(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_CDCLK_MASK, (x)) 4273 #define DISPLAY_TO_PCODE_PIPE_COUNT(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_PIPE_COUNT_MASK, (x)) 4274 #define DISPLAY_TO_PCODE_VOLTAGE(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_VOLTAGE_MASK, (x)) 4275 #define DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes, voltage_level) \ 4276 ((DISPLAY_TO_PCODE_CDCLK(cdclk)) | \ 4277 (DISPLAY_TO_PCODE_PIPE_COUNT(num_pipes)) | \ 4278 (DISPLAY_TO_PCODE_VOLTAGE(voltage_level))) 4279 #define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe 4280 #define ICL_PCODE_REP_QGV_MASK REG_GENMASK(1, 0) 4281 #define ICL_PCODE_REP_QGV_SAFE REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0) 4282 #define ICL_PCODE_REP_QGV_POLL REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1) 4283 #define ICL_PCODE_REP_QGV_REJECTED REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2) 4284 #define ADLS_PCODE_REP_PSF_MASK REG_GENMASK(3, 2) 4285 #define ADLS_PCODE_REP_PSF_SAFE REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0) 4286 #define ADLS_PCODE_REP_PSF_POLL REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1) 4287 #define ADLS_PCODE_REP_PSF_REJECTED REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2) 4288 #define ICL_PCODE_REQ_QGV_PT_MASK REG_GENMASK(7, 0) 4289 #define ICL_PCODE_REQ_QGV_PT(x) REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x)) 4290 #define ADLS_PCODE_REQ_PSF_PT_MASK REG_GENMASK(10, 8) 4291 #define ADLS_PCODE_REQ_PSF_PT(x) REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x)) 4292 #define GEN6_PCODE_READ_D_COMP 0x10 4293 #define GEN6_PCODE_WRITE_D_COMP 0x11 4294 #define ICL_PCODE_EXIT_TCCOLD 0x12 4295 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17 4296 #define DISPLAY_IPS_CONTROL 0x19 4297 #define TGL_PCODE_TCCOLD 0x26 4298 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0) 4299 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0 4300 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0) 4301 /* See also IPS_CTL */ 4302 #define IPS_PCODE_CONTROL (1 << 30) 4303 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A 4304 #define GEN9_PCODE_SAGV_CONTROL 0x21 4305 #define GEN9_SAGV_DISABLE 0x0 4306 #define GEN9_SAGV_IS_DISABLED 0x1 4307 #define GEN9_SAGV_ENABLE 0x3 4308 #define DG1_PCODE_STATUS 0x7E 4309 #define DG1_UNCORE_GET_INIT_STATUS 0x0 4310 #define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1 4311 #define PCODE_POWER_SETUP 0x7C 4312 #define POWER_SETUP_SUBCOMMAND_READ_I1 0x4 4313 #define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5 4314 #define POWER_SETUP_I1_WATTS REG_BIT(31) 4315 #define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */ 4316 #define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0) 4317 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23 4318 #define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* pvc */ 4319 /* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */ 4320 #define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0 4321 #define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1 4322 /* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */ 4323 /* XEHP_PCODE_FREQUENCY_CONFIG param2 */ 4324 #define PCODE_MBOX_DOMAIN_NONE 0x0 4325 #define PCODE_MBOX_DOMAIN_MEDIAFF 0x3 4326 #define GEN6_PCODE_DATA _MMIO(0x138128) 4327 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 4328 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 4329 #define GEN6_PCODE_DATA1 _MMIO(0x13812C) 4330 4331 #define MTL_PCODE_STOLEN_ACCESS _MMIO(0x138914) 4332 #define STOLEN_ACCESS_ALLOWED 0x1 4333 4334 /* IVYBRIDGE DPF */ 4335 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */ 4336 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14) 4337 #define GEN7_PARITY_ERROR_VALID (1 << 13) 4338 #define GEN7_L3CDERRST1_BANK_MASK (3 << 11) 4339 #define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8) 4340 #define GEN7_PARITY_ERROR_ROW(reg) \ 4341 (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14) 4342 #define GEN7_PARITY_ERROR_BANK(reg) \ 4343 (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11) 4344 #define GEN7_PARITY_ERROR_SUBBANK(reg) \ 4345 (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) 4346 #define GEN7_L3CDERRST1_ENABLE (1 << 7) 4347 4348 /* These are the 4 32-bit write offset registers for each stream 4349 * output buffer. It determines the offset from the 4350 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. 4351 */ 4352 #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4) 4353 4354 /* 4355 * HSW - ICL power wells 4356 * 4357 * Platforms have up to 3 power well control register sets, each set 4358 * controlling up to 16 power wells via a request/status HW flag tuple: 4359 * - main (HSW_PWR_WELL_CTL[1-4]) 4360 * - AUX (ICL_PWR_WELL_CTL_AUX[1-4]) 4361 * - DDI (ICL_PWR_WELL_CTL_DDI[1-4]) 4362 * Each control register set consists of up to 4 registers used by different 4363 * sources that can request a power well to be enabled: 4364 * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1) 4365 * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2) 4366 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set) 4367 * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4) 4368 */ 4369 #define HSW_PWR_WELL_CTL1 _MMIO(0x45400) 4370 #define HSW_PWR_WELL_CTL2 _MMIO(0x45404) 4371 #define HSW_PWR_WELL_CTL3 _MMIO(0x45408) 4372 #define HSW_PWR_WELL_CTL4 _MMIO(0x4540C) 4373 #define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2)) 4374 #define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2)) 4375 4376 /* HSW/BDW power well */ 4377 #define HSW_PW_CTL_IDX_GLOBAL 15 4378 4379 /* SKL/BXT/GLK power wells */ 4380 #define SKL_PW_CTL_IDX_PW_2 15 4381 #define SKL_PW_CTL_IDX_PW_1 14 4382 #define GLK_PW_CTL_IDX_AUX_C 10 4383 #define GLK_PW_CTL_IDX_AUX_B 9 4384 #define GLK_PW_CTL_IDX_AUX_A 8 4385 #define SKL_PW_CTL_IDX_DDI_D 4 4386 #define SKL_PW_CTL_IDX_DDI_C 3 4387 #define SKL_PW_CTL_IDX_DDI_B 2 4388 #define SKL_PW_CTL_IDX_DDI_A_E 1 4389 #define GLK_PW_CTL_IDX_DDI_A 1 4390 #define SKL_PW_CTL_IDX_MISC_IO 0 4391 4392 /* ICL/TGL - power wells */ 4393 #define TGL_PW_CTL_IDX_PW_5 4 4394 #define ICL_PW_CTL_IDX_PW_4 3 4395 #define ICL_PW_CTL_IDX_PW_3 2 4396 #define ICL_PW_CTL_IDX_PW_2 1 4397 #define ICL_PW_CTL_IDX_PW_1 0 4398 4399 /* XE_LPD - power wells */ 4400 #define XELPD_PW_CTL_IDX_PW_D 8 4401 #define XELPD_PW_CTL_IDX_PW_C 7 4402 #define XELPD_PW_CTL_IDX_PW_B 6 4403 #define XELPD_PW_CTL_IDX_PW_A 5 4404 4405 #define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440) 4406 #define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444) 4407 #define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C) 4408 #define TGL_PW_CTL_IDX_AUX_TBT6 14 4409 #define TGL_PW_CTL_IDX_AUX_TBT5 13 4410 #define TGL_PW_CTL_IDX_AUX_TBT4 12 4411 #define ICL_PW_CTL_IDX_AUX_TBT4 11 4412 #define TGL_PW_CTL_IDX_AUX_TBT3 11 4413 #define ICL_PW_CTL_IDX_AUX_TBT3 10 4414 #define TGL_PW_CTL_IDX_AUX_TBT2 10 4415 #define ICL_PW_CTL_IDX_AUX_TBT2 9 4416 #define TGL_PW_CTL_IDX_AUX_TBT1 9 4417 #define ICL_PW_CTL_IDX_AUX_TBT1 8 4418 #define TGL_PW_CTL_IDX_AUX_TC6 8 4419 #define XELPD_PW_CTL_IDX_AUX_E 8 4420 #define TGL_PW_CTL_IDX_AUX_TC5 7 4421 #define XELPD_PW_CTL_IDX_AUX_D 7 4422 #define TGL_PW_CTL_IDX_AUX_TC4 6 4423 #define ICL_PW_CTL_IDX_AUX_F 5 4424 #define TGL_PW_CTL_IDX_AUX_TC3 5 4425 #define ICL_PW_CTL_IDX_AUX_E 4 4426 #define TGL_PW_CTL_IDX_AUX_TC2 4 4427 #define ICL_PW_CTL_IDX_AUX_D 3 4428 #define TGL_PW_CTL_IDX_AUX_TC1 3 4429 #define ICL_PW_CTL_IDX_AUX_C 2 4430 #define ICL_PW_CTL_IDX_AUX_B 1 4431 #define ICL_PW_CTL_IDX_AUX_A 0 4432 4433 #define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450) 4434 #define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454) 4435 #define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C) 4436 #define XELPD_PW_CTL_IDX_DDI_E 8 4437 #define TGL_PW_CTL_IDX_DDI_TC6 8 4438 #define XELPD_PW_CTL_IDX_DDI_D 7 4439 #define TGL_PW_CTL_IDX_DDI_TC5 7 4440 #define TGL_PW_CTL_IDX_DDI_TC4 6 4441 #define ICL_PW_CTL_IDX_DDI_F 5 4442 #define TGL_PW_CTL_IDX_DDI_TC3 5 4443 #define ICL_PW_CTL_IDX_DDI_E 4 4444 #define TGL_PW_CTL_IDX_DDI_TC2 4 4445 #define ICL_PW_CTL_IDX_DDI_D 3 4446 #define TGL_PW_CTL_IDX_DDI_TC1 3 4447 #define ICL_PW_CTL_IDX_DDI_C 2 4448 #define ICL_PW_CTL_IDX_DDI_B 1 4449 #define ICL_PW_CTL_IDX_DDI_A 0 4450 4451 /* HSW - power well misc debug registers */ 4452 #define HSW_PWR_WELL_CTL5 _MMIO(0x45410) 4453 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31) 4454 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20) 4455 #define HSW_PWR_WELL_FORCE_ON (1 << 19) 4456 #define HSW_PWR_WELL_CTL6 _MMIO(0x45414) 4457 4458 /* SKL Fuse Status */ 4459 enum skl_power_gate { 4460 SKL_PG0, 4461 SKL_PG1, 4462 SKL_PG2, 4463 ICL_PG3, 4464 ICL_PG4, 4465 }; 4466 4467 #define SKL_FUSE_STATUS _MMIO(0x42000) 4468 #define SKL_FUSE_DOWNLOAD_STATUS (1 << 31) 4469 /* 4470 * PG0 is HW controlled, so doesn't have a corresponding power well control knob 4471 * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2 4472 */ 4473 #define SKL_PW_CTL_IDX_TO_PG(pw_idx) \ 4474 ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1) 4475 /* 4476 * PG0 is HW controlled, so doesn't have a corresponding power well control knob 4477 * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4 4478 */ 4479 #define ICL_PW_CTL_IDX_TO_PG(pw_idx) \ 4480 ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1) 4481 #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg))) 4482 4483 /* Per-pipe DDI Function Control */ 4484 #define _TRANS_DDI_FUNC_CTL_A 0x60400 4485 #define _TRANS_DDI_FUNC_CTL_B 0x61400 4486 #define _TRANS_DDI_FUNC_CTL_C 0x62400 4487 #define _TRANS_DDI_FUNC_CTL_D 0x63400 4488 #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400 4489 #define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400 4490 #define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00 4491 #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL_A) 4492 4493 #define TRANS_DDI_FUNC_ENABLE (1 << 31) 4494 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ 4495 #define TRANS_DDI_PORT_SHIFT 28 4496 #define TGL_TRANS_DDI_PORT_SHIFT 27 4497 #define TRANS_DDI_PORT_MASK (7 << TRANS_DDI_PORT_SHIFT) 4498 #define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT) 4499 #define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT) 4500 #define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT) 4501 #define TRANS_DDI_MODE_SELECT_MASK (7 << 24) 4502 #define TRANS_DDI_MODE_SELECT_HDMI (0 << 24) 4503 #define TRANS_DDI_MODE_SELECT_DVI (1 << 24) 4504 #define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24) 4505 #define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24) 4506 #define TRANS_DDI_MODE_SELECT_FDI_OR_128B132B (4 << 24) 4507 #define TRANS_DDI_BPC_MASK (7 << 20) 4508 #define TRANS_DDI_BPC_8 (0 << 20) 4509 #define TRANS_DDI_BPC_10 (1 << 20) 4510 #define TRANS_DDI_BPC_6 (2 << 20) 4511 #define TRANS_DDI_BPC_12 (3 << 20) 4512 #define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18) 4513 #define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x) REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x)) 4514 #define TRANS_DDI_PVSYNC (1 << 17) 4515 #define TRANS_DDI_PHSYNC (1 << 16) 4516 #define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15) 4517 #define TRANS_DDI_EDP_INPUT_MASK (7 << 12) 4518 #define TRANS_DDI_EDP_INPUT_A_ON (0 << 12) 4519 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12) 4520 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12) 4521 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12) 4522 #define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12) 4523 #define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10) 4524 #define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \ 4525 REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans) 4526 #define TRANS_DDI_HDCP_SIGNALLING (1 << 9) 4527 #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8) 4528 #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7) 4529 #define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6) 4530 #define TRANS_DDI_HDCP_SELECT REG_BIT(5) 4531 #define TRANS_DDI_BFI_ENABLE (1 << 4) 4532 #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4) 4533 #define TRANS_DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1) 4534 #define TRANS_DDI_PORT_WIDTH(width) REG_FIELD_PREP(TRANS_DDI_PORT_WIDTH_MASK, (width) - 1) 4535 #define TRANS_DDI_HDMI_SCRAMBLING (1 << 0) 4536 #define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \ 4537 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \ 4538 | TRANS_DDI_HDMI_SCRAMBLING) 4539 4540 #define _TRANS_DDI_FUNC_CTL2_A 0x60404 4541 #define _TRANS_DDI_FUNC_CTL2_B 0x61404 4542 #define _TRANS_DDI_FUNC_CTL2_C 0x62404 4543 #define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404 4544 #define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404 4545 #define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04 4546 #define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL2_A) 4547 #define PORT_SYNC_MODE_ENABLE REG_BIT(4) 4548 #define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0) 4549 #define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x)) 4550 4551 #define TRANS_CMTG_CHICKEN _MMIO(0x6fa90) 4552 #define DISABLE_DPT_CLK_GATING REG_BIT(1) 4553 4554 /* DisplayPort Transport Control */ 4555 #define _DP_TP_CTL_A 0x64040 4556 #define _DP_TP_CTL_B 0x64140 4557 #define _TGL_DP_TP_CTL_A 0x60540 4558 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) 4559 #define TGL_DP_TP_CTL(tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_CTL_A) 4560 #define DP_TP_CTL_ENABLE (1 << 31) 4561 #define DP_TP_CTL_FEC_ENABLE (1 << 30) 4562 #define DP_TP_CTL_MODE_SST (0 << 27) 4563 #define DP_TP_CTL_MODE_MST (1 << 27) 4564 #define DP_TP_CTL_FORCE_ACT (1 << 25) 4565 #define DP_TP_CTL_TRAIN_PAT4_SEL_MASK (3 << 19) 4566 #define DP_TP_CTL_TRAIN_PAT4_SEL_TP4A (0 << 19) 4567 #define DP_TP_CTL_TRAIN_PAT4_SEL_TP4B (1 << 19) 4568 #define DP_TP_CTL_TRAIN_PAT4_SEL_TP4C (2 << 19) 4569 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18) 4570 #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15) 4571 #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8) 4572 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8) 4573 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1 << 8) 4574 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4 << 8) 4575 #define DP_TP_CTL_LINK_TRAIN_PAT4 (5 << 8) 4576 #define DP_TP_CTL_LINK_TRAIN_IDLE (2 << 8) 4577 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3 << 8) 4578 #define DP_TP_CTL_SCRAMBLE_DISABLE (1 << 7) 4579 4580 /* DisplayPort Transport Status */ 4581 #define _DP_TP_STATUS_A 0x64044 4582 #define _DP_TP_STATUS_B 0x64144 4583 #define _TGL_DP_TP_STATUS_A 0x60544 4584 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B) 4585 #define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_STATUS_A) 4586 #define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28) 4587 #define DP_TP_STATUS_IDLE_DONE (1 << 25) 4588 #define DP_TP_STATUS_ACT_SENT (1 << 24) 4589 #define DP_TP_STATUS_MODE_STATUS_MST (1 << 23) 4590 #define DP_TP_STATUS_AUTOTRAIN_DONE (1 << 12) 4591 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8) 4592 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4) 4593 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0) 4594 4595 /* DDI Buffer Control */ 4596 #define _DDI_BUF_CTL_A 0x64000 4597 #define _DDI_BUF_CTL_B 0x64100 4598 /* Known as DDI_CTL_DE in MTL+ */ 4599 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B) 4600 #define DDI_BUF_CTL_ENABLE (1 << 31) 4601 #define XE2LPD_DDI_BUF_D2D_LINK_ENABLE REG_BIT(29) 4602 #define XE2LPD_DDI_BUF_D2D_LINK_STATE REG_BIT(28) 4603 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24) 4604 #define DDI_BUF_EMP_MASK (0xf << 24) 4605 #define DDI_BUF_PHY_LINK_RATE(r) ((r) << 20) 4606 #define DDI_BUF_PORT_DATA_MASK REG_GENMASK(19, 18) 4607 #define DDI_BUF_PORT_DATA_10BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 0) 4608 #define DDI_BUF_PORT_DATA_20BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 1) 4609 #define DDI_BUF_PORT_DATA_40BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 2) 4610 #define DDI_BUF_PORT_REVERSAL (1 << 16) 4611 #define DDI_BUF_IS_IDLE (1 << 7) 4612 #define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6) 4613 #define DDI_A_4_LANES (1 << 4) 4614 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) 4615 #define DDI_PORT_WIDTH_MASK (7 << 1) 4616 #define DDI_PORT_WIDTH_SHIFT 1 4617 #define DDI_INIT_DISPLAY_DETECTED (1 << 0) 4618 4619 /* DDI Buffer Translations */ 4620 #define _DDI_BUF_TRANS_A 0x64E00 4621 #define _DDI_BUF_TRANS_B 0x64E60 4622 #define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8) 4623 #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31) 4624 #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4) 4625 4626 /* DDI DP Compliance Control */ 4627 #define _DDI_DP_COMP_CTL_A 0x605F0 4628 #define _DDI_DP_COMP_CTL_B 0x615F0 4629 #define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B) 4630 #define DDI_DP_COMP_CTL_ENABLE (1 << 31) 4631 #define DDI_DP_COMP_CTL_D10_2 (0 << 28) 4632 #define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28) 4633 #define DDI_DP_COMP_CTL_PRBS7 (2 << 28) 4634 #define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28) 4635 #define DDI_DP_COMP_CTL_HBR2 (4 << 28) 4636 #define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28) 4637 #define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0) 4638 4639 /* DDI DP Compliance Pattern */ 4640 #define _DDI_DP_COMP_PAT_A 0x605F4 4641 #define _DDI_DP_COMP_PAT_B 0x615F4 4642 #define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4) 4643 4644 /* Sideband Interface (SBI) is programmed indirectly, via 4645 * SBI_ADDR, which contains the register offset; and SBI_DATA, 4646 * which contains the payload */ 4647 #define SBI_ADDR _MMIO(0xC6000) 4648 #define SBI_DATA _MMIO(0xC6004) 4649 #define SBI_CTL_STAT _MMIO(0xC6008) 4650 #define SBI_CTL_DEST_ICLK (0x0 << 16) 4651 #define SBI_CTL_DEST_MPHY (0x1 << 16) 4652 #define SBI_CTL_OP_IORD (0x2 << 8) 4653 #define SBI_CTL_OP_IOWR (0x3 << 8) 4654 #define SBI_CTL_OP_CRRD (0x6 << 8) 4655 #define SBI_CTL_OP_CRWR (0x7 << 8) 4656 #define SBI_RESPONSE_FAIL (0x1 << 1) 4657 #define SBI_RESPONSE_SUCCESS (0x0 << 1) 4658 #define SBI_BUSY (0x1 << 0) 4659 #define SBI_READY (0x0 << 0) 4660 4661 /* SBI offsets */ 4662 #define SBI_SSCDIVINTPHASE 0x0200 4663 #define SBI_SSCDIVINTPHASE6 0x0600 4664 #define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1 4665 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1) 4666 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1) 4667 #define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8 4668 #define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8) 4669 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8) 4670 #define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15) 4671 #define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0) 4672 #define SBI_SSCDITHPHASE 0x0204 4673 #define SBI_SSCCTL 0x020c 4674 #define SBI_SSCCTL6 0x060C 4675 #define SBI_SSCCTL_PATHALT (1 << 3) 4676 #define SBI_SSCCTL_DISABLE (1 << 0) 4677 #define SBI_SSCAUXDIV6 0x0610 4678 #define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4 4679 #define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4) 4680 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4) 4681 #define SBI_DBUFF0 0x2a00 4682 #define SBI_GEN0 0x1f00 4683 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0) 4684 4685 /* LPT PIXCLK_GATE */ 4686 #define PIXCLK_GATE _MMIO(0xC6020) 4687 #define PIXCLK_GATE_UNGATE (1 << 0) 4688 #define PIXCLK_GATE_GATE (0 << 0) 4689 4690 /* SPLL */ 4691 #define SPLL_CTL _MMIO(0x46020) 4692 #define SPLL_PLL_ENABLE (1 << 31) 4693 #define SPLL_REF_BCLK (0 << 28) 4694 #define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */ 4695 #define SPLL_REF_NON_SSC_HSW (2 << 28) 4696 #define SPLL_REF_PCH_SSC_BDW (2 << 28) 4697 #define SPLL_REF_LCPLL (3 << 28) 4698 #define SPLL_REF_MASK (3 << 28) 4699 #define SPLL_FREQ_810MHz (0 << 26) 4700 #define SPLL_FREQ_1350MHz (1 << 26) 4701 #define SPLL_FREQ_2700MHz (2 << 26) 4702 #define SPLL_FREQ_MASK (3 << 26) 4703 4704 /* WRPLL */ 4705 #define _WRPLL_CTL1 0x46040 4706 #define _WRPLL_CTL2 0x46060 4707 #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2) 4708 #define WRPLL_PLL_ENABLE (1 << 31) 4709 #define WRPLL_REF_BCLK (0 << 28) 4710 #define WRPLL_REF_PCH_SSC (1 << 28) 4711 #define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */ 4712 #define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */ 4713 #define WRPLL_REF_LCPLL (3 << 28) 4714 #define WRPLL_REF_MASK (3 << 28) 4715 /* WRPLL divider programming */ 4716 #define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0) 4717 #define WRPLL_DIVIDER_REF_MASK (0xff) 4718 #define WRPLL_DIVIDER_POST(x) ((x) << 8) 4719 #define WRPLL_DIVIDER_POST_MASK (0x3f << 8) 4720 #define WRPLL_DIVIDER_POST_SHIFT 8 4721 #define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16) 4722 #define WRPLL_DIVIDER_FB_SHIFT 16 4723 #define WRPLL_DIVIDER_FB_MASK (0xff << 16) 4724 4725 /* Port clock selection */ 4726 #define _PORT_CLK_SEL_A 0x46100 4727 #define _PORT_CLK_SEL_B 0x46104 4728 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B) 4729 #define PORT_CLK_SEL_MASK REG_GENMASK(31, 29) 4730 #define PORT_CLK_SEL_LCPLL_2700 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 0) 4731 #define PORT_CLK_SEL_LCPLL_1350 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 1) 4732 #define PORT_CLK_SEL_LCPLL_810 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 2) 4733 #define PORT_CLK_SEL_SPLL REG_FIELD_PREP(PORT_CLK_SEL_MASK, 3) 4734 #define PORT_CLK_SEL_WRPLL(pll) REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4 + (pll)) 4735 #define PORT_CLK_SEL_WRPLL1 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4) 4736 #define PORT_CLK_SEL_WRPLL2 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 5) 4737 #define PORT_CLK_SEL_NONE REG_FIELD_PREP(PORT_CLK_SEL_MASK, 7) 4738 4739 /* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */ 4740 #define DDI_CLK_SEL(port) PORT_CLK_SEL(port) 4741 #define DDI_CLK_SEL_MASK REG_GENMASK(31, 28) 4742 #define DDI_CLK_SEL_NONE REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x0) 4743 #define DDI_CLK_SEL_MG REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x8) 4744 #define DDI_CLK_SEL_TBT_162 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xC) 4745 #define DDI_CLK_SEL_TBT_270 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xD) 4746 #define DDI_CLK_SEL_TBT_540 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xE) 4747 #define DDI_CLK_SEL_TBT_810 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xF) 4748 4749 /* Transcoder clock selection */ 4750 #define _TRANS_CLK_SEL_A 0x46140 4751 #define _TRANS_CLK_SEL_B 0x46144 4752 #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B) 4753 /* For each transcoder, we need to select the corresponding port clock */ 4754 #define TRANS_CLK_SEL_DISABLED (0x0 << 29) 4755 #define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29) 4756 #define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28) 4757 #define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28) 4758 4759 4760 #define CDCLK_FREQ _MMIO(0x46200) 4761 4762 #define _TRANSA_MSA_MISC 0x60410 4763 #define _TRANSB_MSA_MISC 0x61410 4764 #define _TRANSC_MSA_MISC 0x62410 4765 #define _TRANS_EDP_MSA_MISC 0x6f410 4766 #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(dev_priv, tran, _TRANSA_MSA_MISC) 4767 /* See DP_MSA_MISC_* for the bit definitions */ 4768 4769 #define _TRANS_A_SET_CONTEXT_LATENCY 0x6007C 4770 #define _TRANS_B_SET_CONTEXT_LATENCY 0x6107C 4771 #define _TRANS_C_SET_CONTEXT_LATENCY 0x6207C 4772 #define _TRANS_D_SET_CONTEXT_LATENCY 0x6307C 4773 #define TRANS_SET_CONTEXT_LATENCY(tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_A_SET_CONTEXT_LATENCY) 4774 #define TRANS_SET_CONTEXT_LATENCY_MASK REG_GENMASK(15, 0) 4775 #define TRANS_SET_CONTEXT_LATENCY_VALUE(x) REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x)) 4776 4777 /* LCPLL Control */ 4778 #define LCPLL_CTL _MMIO(0x130040) 4779 #define LCPLL_PLL_DISABLE (1 << 31) 4780 #define LCPLL_PLL_LOCK (1 << 30) 4781 #define LCPLL_REF_NON_SSC (0 << 28) 4782 #define LCPLL_REF_BCLK (2 << 28) 4783 #define LCPLL_REF_PCH_SSC (3 << 28) 4784 #define LCPLL_REF_MASK (3 << 28) 4785 #define LCPLL_CLK_FREQ_MASK (3 << 26) 4786 #define LCPLL_CLK_FREQ_450 (0 << 26) 4787 #define LCPLL_CLK_FREQ_54O_BDW (1 << 26) 4788 #define LCPLL_CLK_FREQ_337_5_BDW (2 << 26) 4789 #define LCPLL_CLK_FREQ_675_BDW (3 << 26) 4790 #define LCPLL_CD_CLOCK_DISABLE (1 << 25) 4791 #define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24) 4792 #define LCPLL_CD2X_CLOCK_DISABLE (1 << 23) 4793 #define LCPLL_POWER_DOWN_ALLOW (1 << 22) 4794 #define LCPLL_CD_SOURCE_FCLK (1 << 21) 4795 #define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19) 4796 4797 /* 4798 * SKL Clocks 4799 */ 4800 4801 /* CDCLK_CTL */ 4802 #define CDCLK_CTL _MMIO(0x46000) 4803 #define CDCLK_FREQ_SEL_MASK REG_GENMASK(27, 26) 4804 #define CDCLK_FREQ_450_432 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 0) 4805 #define CDCLK_FREQ_540 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1) 4806 #define CDCLK_FREQ_337_308 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2) 4807 #define CDCLK_FREQ_675_617 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3) 4808 #define MDCLK_SOURCE_SEL_MASK REG_GENMASK(25, 25) 4809 #define MDCLK_SOURCE_SEL_CD2XCLK REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 0) 4810 #define MDCLK_SOURCE_SEL_CDCLK_PLL REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 1) 4811 #define BXT_CDCLK_CD2X_DIV_SEL_MASK REG_GENMASK(23, 22) 4812 #define BXT_CDCLK_CD2X_DIV_SEL_1 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0) 4813 #define BXT_CDCLK_CD2X_DIV_SEL_1_5 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1) 4814 #define BXT_CDCLK_CD2X_DIV_SEL_2 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 2) 4815 #define BXT_CDCLK_CD2X_DIV_SEL_4 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 3) 4816 #define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20) 4817 #define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19) 4818 #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3) 4819 #define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19) 4820 #define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19) 4821 #define TGL_CDCLK_CD2X_PIPE(pipe) BXT_CDCLK_CD2X_PIPE(pipe) 4822 #define TGL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE_NONE 4823 #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16) 4824 #define CDCLK_FREQ_DECIMAL_MASK (0x7ff) 4825 4826 /* CDCLK_SQUASH_CTL */ 4827 #define CDCLK_SQUASH_CTL _MMIO(0x46008) 4828 #define CDCLK_SQUASH_ENABLE REG_BIT(31) 4829 #define CDCLK_SQUASH_WINDOW_SIZE_MASK REG_GENMASK(27, 24) 4830 #define CDCLK_SQUASH_WINDOW_SIZE(x) REG_FIELD_PREP(CDCLK_SQUASH_WINDOW_SIZE_MASK, (x)) 4831 #define CDCLK_SQUASH_WAVEFORM_MASK REG_GENMASK(15, 0) 4832 #define CDCLK_SQUASH_WAVEFORM(x) REG_FIELD_PREP(CDCLK_SQUASH_WAVEFORM_MASK, (x)) 4833 4834 /* LCPLL_CTL */ 4835 #define LCPLL1_CTL _MMIO(0x46010) 4836 #define LCPLL2_CTL _MMIO(0x46014) 4837 #define LCPLL_PLL_ENABLE (1 << 31) 4838 4839 /* DPLL control1 */ 4840 #define DPLL_CTRL1 _MMIO(0x6C058) 4841 #define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5)) 4842 #define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4)) 4843 #define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1)) 4844 #define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1) 4845 #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1)) 4846 #define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6)) 4847 #define DPLL_CTRL1_LINK_RATE_2700 0 4848 #define DPLL_CTRL1_LINK_RATE_1350 1 4849 #define DPLL_CTRL1_LINK_RATE_810 2 4850 #define DPLL_CTRL1_LINK_RATE_1620 3 4851 #define DPLL_CTRL1_LINK_RATE_1080 4 4852 #define DPLL_CTRL1_LINK_RATE_2160 5 4853 4854 /* DPLL control2 */ 4855 #define DPLL_CTRL2 _MMIO(0x6C05C) 4856 #define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15)) 4857 #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1)) 4858 #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1) 4859 #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1)) 4860 #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3)) 4861 4862 /* DPLL Status */ 4863 #define DPLL_STATUS _MMIO(0x6C060) 4864 #define DPLL_LOCK(id) (1 << ((id) * 8)) 4865 4866 /* DPLL cfg */ 4867 #define _DPLL1_CFGCR1 0x6C040 4868 #define _DPLL2_CFGCR1 0x6C048 4869 #define _DPLL3_CFGCR1 0x6C050 4870 #define DPLL_CFGCR1_FREQ_ENABLE (1 << 31) 4871 #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9) 4872 #define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9) 4873 #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff) 4874 4875 #define _DPLL1_CFGCR2 0x6C044 4876 #define _DPLL2_CFGCR2 0x6C04C 4877 #define _DPLL3_CFGCR2 0x6C054 4878 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8) 4879 #define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8) 4880 #define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7) 4881 #define DPLL_CFGCR2_KDIV_MASK (3 << 5) 4882 #define DPLL_CFGCR2_KDIV(x) ((x) << 5) 4883 #define DPLL_CFGCR2_KDIV_5 (0 << 5) 4884 #define DPLL_CFGCR2_KDIV_2 (1 << 5) 4885 #define DPLL_CFGCR2_KDIV_3 (2 << 5) 4886 #define DPLL_CFGCR2_KDIV_1 (3 << 5) 4887 #define DPLL_CFGCR2_PDIV_MASK (7 << 2) 4888 #define DPLL_CFGCR2_PDIV(x) ((x) << 2) 4889 #define DPLL_CFGCR2_PDIV_1 (0 << 2) 4890 #define DPLL_CFGCR2_PDIV_2 (1 << 2) 4891 #define DPLL_CFGCR2_PDIV_3 (2 << 2) 4892 #define DPLL_CFGCR2_PDIV_7 (4 << 2) 4893 #define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2) 4894 #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3) 4895 4896 #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1) 4897 #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2) 4898 4899 /* ICL Clocks */ 4900 #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280) 4901 #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24, 4, 5)) 4902 #define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10) 4903 #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \ 4904 (tc_port) + 12 : \ 4905 (tc_port) - TC_PORT_4 + 21)) 4906 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2) 4907 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 4908 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 4909 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27) 4910 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \ 4911 (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 4912 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \ 4913 ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 4914 4915 /* 4916 * DG1 Clocks 4917 * First registers controls the first A and B, while the second register 4918 * controls the phy C and D. The bits on these registers are the 4919 * same, but refer to different phys 4920 */ 4921 #define _DG1_DPCLKA_CFGCR0 0x164280 4922 #define _DG1_DPCLKA1_CFGCR0 0x16C280 4923 #define _DG1_DPCLKA_PHY_IDX(phy) ((phy) % 2) 4924 #define _DG1_DPCLKA_PLL_IDX(pll) ((pll) % 2) 4925 #define DG1_DPCLKA_CFGCR0(phy) _MMIO_PHY((phy) / 2, \ 4926 _DG1_DPCLKA_CFGCR0, \ 4927 _DG1_DPCLKA1_CFGCR0) 4928 #define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT(_DG1_DPCLKA_PHY_IDX(phy) + 10) 4929 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) (_DG1_DPCLKA_PHY_IDX(phy) * 2) 4930 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (_DG1_DPCLKA_PLL_IDX(pll) << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 4931 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 4932 4933 /* ADLS Clocks */ 4934 #define _ADLS_DPCLKA_CFGCR0 0x164280 4935 #define _ADLS_DPCLKA_CFGCR1 0x1642BC 4936 #define ADLS_DPCLKA_CFGCR(phy) _MMIO_PHY((phy) / 3, \ 4937 _ADLS_DPCLKA_CFGCR0, \ 4938 _ADLS_DPCLKA_CFGCR1) 4939 #define ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy) (((phy) % 3) * 2) 4940 /* ADLS DPCLKA_CFGCR0 DDI mask */ 4941 #define ADLS_DPCLKA_DDII_SEL_MASK REG_GENMASK(5, 4) 4942 #define ADLS_DPCLKA_DDIB_SEL_MASK REG_GENMASK(3, 2) 4943 #define ADLS_DPCLKA_DDIA_SEL_MASK REG_GENMASK(1, 0) 4944 /* ADLS DPCLKA_CFGCR1 DDI mask */ 4945 #define ADLS_DPCLKA_DDIK_SEL_MASK REG_GENMASK(3, 2) 4946 #define ADLS_DPCLKA_DDIJ_SEL_MASK REG_GENMASK(1, 0) 4947 #define ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy) _PICK((phy), \ 4948 ADLS_DPCLKA_DDIA_SEL_MASK, \ 4949 ADLS_DPCLKA_DDIB_SEL_MASK, \ 4950 ADLS_DPCLKA_DDII_SEL_MASK, \ 4951 ADLS_DPCLKA_DDIJ_SEL_MASK, \ 4952 ADLS_DPCLKA_DDIK_SEL_MASK) 4953 4954 /* ICL PLL */ 4955 #define _DPLL0_ENABLE 0x46010 4956 #define _DPLL1_ENABLE 0x46014 4957 #define _ADLS_DPLL2_ENABLE 0x46018 4958 #define _ADLS_DPLL3_ENABLE 0x46030 4959 #define PLL_ENABLE REG_BIT(31) 4960 #define PLL_LOCK REG_BIT(30) 4961 #define PLL_POWER_ENABLE REG_BIT(27) 4962 #define PLL_POWER_STATE REG_BIT(26) 4963 #define ICL_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \ 4964 _DPLL0_ENABLE, _DPLL1_ENABLE, \ 4965 _ADLS_DPLL3_ENABLE, _ADLS_DPLL3_ENABLE)) 4966 4967 #define _DG2_PLL3_ENABLE 0x4601C 4968 4969 #define DG2_PLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \ 4970 _DPLL0_ENABLE, _DPLL1_ENABLE, \ 4971 _DG2_PLL3_ENABLE, _DG2_PLL3_ENABLE)) 4972 4973 #define TBT_PLL_ENABLE _MMIO(0x46020) 4974 4975 #define _MG_PLL1_ENABLE 0x46030 4976 #define _MG_PLL2_ENABLE 0x46034 4977 #define _MG_PLL3_ENABLE 0x46038 4978 #define _MG_PLL4_ENABLE 0x4603C 4979 /* Bits are the same as _DPLL0_ENABLE */ 4980 #define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \ 4981 _MG_PLL2_ENABLE) 4982 4983 /* DG1 PLL */ 4984 #define DG1_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ 4985 _DPLL0_ENABLE, _DPLL1_ENABLE, \ 4986 _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)) 4987 4988 /* ADL-P Type C PLL */ 4989 #define PORTTC1_PLL_ENABLE 0x46038 4990 #define PORTTC2_PLL_ENABLE 0x46040 4991 4992 #define ADLP_PORTTC_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), \ 4993 PORTTC1_PLL_ENABLE, \ 4994 PORTTC2_PLL_ENABLE) 4995 4996 #define _ICL_DPLL0_CFGCR0 0x164000 4997 #define _ICL_DPLL1_CFGCR0 0x164080 4998 #define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \ 4999 _ICL_DPLL1_CFGCR0) 5000 #define DPLL_CFGCR0_HDMI_MODE (1 << 30) 5001 #define DPLL_CFGCR0_SSC_ENABLE (1 << 29) 5002 #define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25) 5003 #define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25) 5004 #define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25) 5005 #define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25) 5006 #define DPLL_CFGCR0_LINK_RATE_810 (2 << 25) 5007 #define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25) 5008 #define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25) 5009 #define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25) 5010 #define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25) 5011 #define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25) 5012 #define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10) 5013 #define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10) 5014 #define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10) 5015 #define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff) 5016 5017 #define _ICL_DPLL0_CFGCR1 0x164004 5018 #define _ICL_DPLL1_CFGCR1 0x164084 5019 #define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \ 5020 _ICL_DPLL1_CFGCR1) 5021 #define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10) 5022 #define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10) 5023 #define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10) 5024 #define DPLL_CFGCR1_QDIV_MODE_SHIFT (9) 5025 #define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9) 5026 #define DPLL_CFGCR1_KDIV_MASK (7 << 6) 5027 #define DPLL_CFGCR1_KDIV_SHIFT (6) 5028 #define DPLL_CFGCR1_KDIV(x) ((x) << 6) 5029 #define DPLL_CFGCR1_KDIV_1 (1 << 6) 5030 #define DPLL_CFGCR1_KDIV_2 (2 << 6) 5031 #define DPLL_CFGCR1_KDIV_3 (4 << 6) 5032 #define DPLL_CFGCR1_PDIV_MASK (0xf << 2) 5033 #define DPLL_CFGCR1_PDIV_SHIFT (2) 5034 #define DPLL_CFGCR1_PDIV(x) ((x) << 2) 5035 #define DPLL_CFGCR1_PDIV_2 (1 << 2) 5036 #define DPLL_CFGCR1_PDIV_3 (2 << 2) 5037 #define DPLL_CFGCR1_PDIV_5 (4 << 2) 5038 #define DPLL_CFGCR1_PDIV_7 (8 << 2) 5039 #define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0) 5040 #define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0) 5041 #define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0) 5042 5043 #define _TGL_DPLL0_CFGCR0 0x164284 5044 #define _TGL_DPLL1_CFGCR0 0x16428C 5045 #define _TGL_TBTPLL_CFGCR0 0x16429C 5046 #define TGL_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ 5047 _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \ 5048 _TGL_TBTPLL_CFGCR0, _TGL_TBTPLL_CFGCR0)) 5049 #define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \ 5050 _TGL_DPLL1_CFGCR0) 5051 5052 #define _TGL_DPLL0_DIV0 0x164B00 5053 #define _TGL_DPLL1_DIV0 0x164C00 5054 #define TGL_DPLL0_DIV0(pll) _MMIO_PLL(pll, _TGL_DPLL0_DIV0, _TGL_DPLL1_DIV0) 5055 #define TGL_DPLL0_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25) 5056 #define TGL_DPLL0_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(TGL_DPLL0_DIV0_AFC_STARTUP_MASK, (val)) 5057 5058 #define _TGL_DPLL0_CFGCR1 0x164288 5059 #define _TGL_DPLL1_CFGCR1 0x164290 5060 #define _TGL_TBTPLL_CFGCR1 0x1642A0 5061 #define TGL_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ 5062 _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \ 5063 _TGL_TBTPLL_CFGCR1, _TGL_TBTPLL_CFGCR1)) 5064 #define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \ 5065 _TGL_DPLL1_CFGCR1) 5066 5067 #define _DG1_DPLL2_CFGCR0 0x16C284 5068 #define _DG1_DPLL3_CFGCR0 0x16C28C 5069 #define DG1_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ 5070 _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \ 5071 _DG1_DPLL2_CFGCR0, _DG1_DPLL3_CFGCR0)) 5072 5073 #define _DG1_DPLL2_CFGCR1 0x16C288 5074 #define _DG1_DPLL3_CFGCR1 0x16C290 5075 #define DG1_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ 5076 _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \ 5077 _DG1_DPLL2_CFGCR1, _DG1_DPLL3_CFGCR1)) 5078 5079 /* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */ 5080 #define _ADLS_DPLL4_CFGCR0 0x164294 5081 #define _ADLS_DPLL3_CFGCR0 0x1642C0 5082 #define ADLS_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ 5083 _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \ 5084 _ADLS_DPLL4_CFGCR0, _ADLS_DPLL3_CFGCR0)) 5085 5086 #define _ADLS_DPLL4_CFGCR1 0x164298 5087 #define _ADLS_DPLL3_CFGCR1 0x1642C4 5088 #define ADLS_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ 5089 _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \ 5090 _ADLS_DPLL4_CFGCR1, _ADLS_DPLL3_CFGCR1)) 5091 5092 /* BXT display engine PLL */ 5093 #define BXT_DE_PLL_CTL _MMIO(0x6d000) 5094 #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */ 5095 #define BXT_DE_PLL_RATIO_MASK 0xff 5096 5097 #define BXT_DE_PLL_ENABLE _MMIO(0x46070) 5098 #define BXT_DE_PLL_PLL_ENABLE (1 << 31) 5099 #define BXT_DE_PLL_LOCK (1 << 30) 5100 #define BXT_DE_PLL_FREQ_REQ (1 << 23) 5101 #define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22) 5102 #define ICL_CDCLK_PLL_RATIO(x) (x) 5103 #define ICL_CDCLK_PLL_RATIO_MASK 0xff 5104 5105 /* GEN9 DC */ 5106 #define DC_STATE_EN _MMIO(0x45504) 5107 #define DC_STATE_DISABLE 0 5108 #define DC_STATE_EN_DC3CO REG_BIT(30) 5109 #define DC_STATE_DC3CO_STATUS REG_BIT(29) 5110 #define HOLD_PHY_CLKREQ_PG1_LATCH REG_BIT(21) 5111 #define HOLD_PHY_PG1_LATCH REG_BIT(20) 5112 #define DC_STATE_EN_UPTO_DC5 (1 << 0) 5113 #define DC_STATE_EN_DC9 (1 << 3) 5114 #define DC_STATE_EN_UPTO_DC6 (2 << 0) 5115 #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3 5116 5117 #define DC_STATE_DEBUG _MMIO(0x45520) 5118 #define DC_STATE_DEBUG_MASK_CORES (1 << 0) 5119 #define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1) 5120 5121 #define D_COMP_BDW _MMIO(0x138144) 5122 5123 /* Pipe WM_LINETIME - watermark line time */ 5124 #define _WM_LINETIME_A 0x45270 5125 #define _WM_LINETIME_B 0x45274 5126 #define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B) 5127 #define HSW_LINETIME_MASK REG_GENMASK(8, 0) 5128 #define HSW_LINETIME(x) REG_FIELD_PREP(HSW_LINETIME_MASK, (x)) 5129 #define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16) 5130 #define HSW_IPS_LINETIME(x) REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x)) 5131 5132 /* SFUSE_STRAP */ 5133 #define SFUSE_STRAP _MMIO(0xc2014) 5134 #define SFUSE_STRAP_FUSE_LOCK (1 << 13) 5135 #define SFUSE_STRAP_RAW_FREQUENCY (1 << 8) 5136 #define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7) 5137 #define SFUSE_STRAP_CRT_DISABLED (1 << 6) 5138 #define SFUSE_STRAP_DDIF_DETECTED (1 << 3) 5139 #define SFUSE_STRAP_DDIB_DETECTED (1 << 2) 5140 #define SFUSE_STRAP_DDIC_DETECTED (1 << 1) 5141 #define SFUSE_STRAP_DDID_DETECTED (1 << 0) 5142 5143 #define WM_MISC _MMIO(0x45260) 5144 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0) 5145 5146 #define WM_DBG _MMIO(0x45280) 5147 #define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0) 5148 #define WM_DBG_DISALLOW_MAXFIFO (1 << 1) 5149 #define WM_DBG_DISALLOW_SPRITE (1 << 2) 5150 5151 #define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4) 5152 5153 /* Plane CSC Registers */ 5154 #define _PLANE_CSC_RY_GY_1_A 0x70210 5155 #define _PLANE_CSC_RY_GY_2_A 0x70310 5156 5157 #define _PLANE_CSC_RY_GY_1_B 0x71210 5158 #define _PLANE_CSC_RY_GY_2_B 0x71310 5159 5160 #define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \ 5161 _PLANE_CSC_RY_GY_1_B) 5162 #define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_2_A, \ 5163 _PLANE_CSC_RY_GY_2_B) 5164 #define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \ 5165 _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \ 5166 _PLANE_CSC_RY_GY_2(pipe) + (index) * 4) 5167 5168 #define _PLANE_CSC_PREOFF_HI_1_A 0x70228 5169 #define _PLANE_CSC_PREOFF_HI_2_A 0x70328 5170 5171 #define _PLANE_CSC_PREOFF_HI_1_B 0x71228 5172 #define _PLANE_CSC_PREOFF_HI_2_B 0x71328 5173 5174 #define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \ 5175 _PLANE_CSC_PREOFF_HI_1_B) 5176 #define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \ 5177 _PLANE_CSC_PREOFF_HI_2_B) 5178 #define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \ 5179 (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \ 5180 (index) * 4) 5181 5182 #define _PLANE_CSC_POSTOFF_HI_1_A 0x70234 5183 #define _PLANE_CSC_POSTOFF_HI_2_A 0x70334 5184 5185 #define _PLANE_CSC_POSTOFF_HI_1_B 0x71234 5186 #define _PLANE_CSC_POSTOFF_HI_2_B 0x71334 5187 5188 #define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \ 5189 _PLANE_CSC_POSTOFF_HI_1_B) 5190 #define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \ 5191 _PLANE_CSC_POSTOFF_HI_2_B) 5192 #define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \ 5193 (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \ 5194 (index) * 4) 5195 5196 /* Gen4+ Timestamp and Pipe Frame time stamp registers */ 5197 #define GEN4_TIMESTAMP _MMIO(0x2358) 5198 #define ILK_TIMESTAMP_HI _MMIO(0x70070) 5199 #define IVB_TIMESTAMP_CTR _MMIO(0x44070) 5200 5201 #define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074) 5202 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0 5203 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff 5204 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12 5205 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12) 5206 5207 /* g4x+, except vlv/chv! */ 5208 #define _PIPE_FRMTMSTMP_A 0x70048 5209 #define _PIPE_FRMTMSTMP_B 0x71048 5210 #define PIPE_FRMTMSTMP(pipe) \ 5211 _MMIO_PIPE(pipe, _PIPE_FRMTMSTMP_A, _PIPE_FRMTMSTMP_B) 5212 5213 /* g4x+, except vlv/chv! */ 5214 #define _PIPE_FLIPTMSTMP_A 0x7004C 5215 #define _PIPE_FLIPTMSTMP_B 0x7104C 5216 #define PIPE_FLIPTMSTMP(pipe) \ 5217 _MMIO_PIPE(pipe, _PIPE_FLIPTMSTMP_A, _PIPE_FLIPTMSTMP_B) 5218 5219 /* tgl+ */ 5220 #define _PIPE_FLIPDONETMSTMP_A 0x70054 5221 #define _PIPE_FLIPDONETMSTMP_B 0x71054 5222 #define PIPE_FLIPDONETIMSTMP(pipe) \ 5223 _MMIO_PIPE(pipe, _PIPE_FLIPDONETMSTMP_A, _PIPE_FLIPDONETMSTMP_B) 5224 5225 #define _VLV_PIPE_MSA_MISC_A 0x70048 5226 #define VLV_PIPE_MSA_MISC(pipe) \ 5227 _MMIO_PIPE2(dev_priv, pipe, _VLV_PIPE_MSA_MISC_A) 5228 #define VLV_MSA_MISC1_HW_ENABLE REG_BIT(31) 5229 #define VLV_MSA_MISC1_SW_S3D_MASK REG_GENMASK(2, 0) /* MSA MISC1 3:1 */ 5230 5231 #define GGC _MMIO(0x108040) 5232 #define GMS_MASK REG_GENMASK(15, 8) 5233 #define GGMS_MASK REG_GENMASK(7, 6) 5234 5235 #define GEN6_GSMBASE _MMIO(0x108100) 5236 #define GEN6_DSMBASE _MMIO(0x1080C0) 5237 #define GEN6_BDSM_MASK REG_GENMASK64(31, 20) 5238 #define GEN11_BDSM_MASK REG_GENMASK64(63, 20) 5239 5240 #define XEHP_CLOCK_GATE_DIS _MMIO(0x101014) 5241 #define SGSI_SIDECLK_DIS REG_BIT(17) 5242 #define SGGI_DIS REG_BIT(15) 5243 #define SGR_DIS REG_BIT(13) 5244 5245 #define _ICL_PHY_MISC_A 0x64C00 5246 #define _ICL_PHY_MISC_B 0x64C04 5247 #define _DG2_PHY_MISC_TC1 0x64C14 /* TC1="PHY E" but offset as if "PHY F" */ 5248 #define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, _ICL_PHY_MISC_B) 5249 #define DG2_PHY_MISC(port) ((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \ 5250 ICL_PHY_MISC(port)) 5251 #define ICL_PHY_MISC_MUX_DDID (1 << 28) 5252 #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23) 5253 #define DG2_PHY_DP_TX_ACK_MASK REG_GENMASK(23, 20) 5254 5255 #define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0) 5256 #define MODULAR_FIA_MASK (1 << 4) 5257 #define TC_LIVE_STATE_TBT(idx) (1 << ((idx) * 8 + 6)) 5258 #define TC_LIVE_STATE_TC(idx) (1 << ((idx) * 8 + 5)) 5259 #define DP_LANE_ASSIGNMENT_SHIFT(idx) ((idx) * 8) 5260 #define DP_LANE_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 8)) 5261 #define DP_LANE_ASSIGNMENT(idx, x) ((x) << ((idx) * 8)) 5262 5263 #define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890) 5264 #define DP_PHY_MODE_STATUS_COMPLETED(idx) (1 << (idx)) 5265 5266 #define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894) 5267 #define DP_PHY_MODE_STATUS_NOT_SAFE(idx) (1 << (idx)) 5268 5269 #define PORT_TX_DFLEXPA1(fia) _MMIO_FIA((fia), 0x00880) 5270 #define DP_PIN_ASSIGNMENT_SHIFT(idx) ((idx) * 4) 5271 #define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4)) 5272 #define DP_PIN_ASSIGNMENT(idx, x) ((x) << ((idx) * 4)) 5273 5274 #define _TCSS_DDI_STATUS_1 0x161500 5275 #define _TCSS_DDI_STATUS_2 0x161504 5276 #define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \ 5277 _TCSS_DDI_STATUS_1, \ 5278 _TCSS_DDI_STATUS_2)) 5279 #define TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK REG_GENMASK(28, 25) 5280 #define TCSS_DDI_STATUS_READY REG_BIT(2) 5281 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1) 5282 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0) 5283 5284 #define PRIMARY_SPI_TRIGGER _MMIO(0x102040) 5285 #define PRIMARY_SPI_ADDRESS _MMIO(0x102080) 5286 #define PRIMARY_SPI_REGIONID _MMIO(0x102084) 5287 #define SPI_STATIC_REGIONS _MMIO(0x102090) 5288 #define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0) 5289 #define OROM_OFFSET _MMIO(0x1020c0) 5290 #define OROM_OFFSET_MASK REG_GENMASK(20, 16) 5291 5292 #define CLKREQ_POLICY _MMIO(0x101038) 5293 #define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1) 5294 5295 #define CLKGATE_DIS_MISC _MMIO(0x46534) 5296 #define CLKGATE_DIS_MISC_DMASC_GATING_DIS REG_BIT(21) 5297 5298 #define _MTL_CLKGATE_DIS_TRANS_A 0x604E8 5299 #define _MTL_CLKGATE_DIS_TRANS_B 0x614E8 5300 #define MTL_CLKGATE_DIS_TRANS(trans) _MMIO_TRANS2(dev_priv, trans, _MTL_CLKGATE_DIS_TRANS_A) 5301 #define MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS REG_BIT(7) 5302 5303 #define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700) 5304 #define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8) 5305 #define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4) 5306 #define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0) 5307 5308 #define MTL_MEM_SS_INFO_QGV_POINT_OFFSET 0x45710 5309 #define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8) 5310 #define MTL_TRCD_MASK REG_GENMASK(31, 24) 5311 #define MTL_TRP_MASK REG_GENMASK(23, 16) 5312 #define MTL_DCLK_MASK REG_GENMASK(15, 0) 5313 5314 #define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8 + 4) 5315 #define MTL_TRAS_MASK REG_GENMASK(16, 8) 5316 #define MTL_TRDPRE_MASK REG_GENMASK(7, 0) 5317 5318 #define MTL_MEDIA_GSI_BASE 0x380000 5319 5320 #endif /* _I915_REG_H_ */ 5321