xref: /linux/drivers/gpu/drm/i915/i915_reg.h (revision b889fcf63cb62e7fdb7816565e28f44dbe4a76a5)
1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2  * All Rights Reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the
6  * "Software"), to deal in the Software without restriction, including
7  * without limitation the rights to use, copy, modify, merge, publish,
8  * distribute, sub license, and/or sell copies of the Software, and to
9  * permit persons to whom the Software is furnished to do so, subject to
10  * the following conditions:
11  *
12  * The above copyright notice and this permission notice (including the
13  * next paragraph) shall be included in all copies or substantial portions
14  * of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23  */
24 
25 #ifndef _I915_REG_H_
26 #define _I915_REG_H_
27 
28 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
29 #define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
30 
31 #define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
32 
33 #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))
34 #define _MASKED_BIT_DISABLE(a) ((a) << 16)
35 
36 /*
37  * The Bridge device's PCI config space has information about the
38  * fb aperture size and the amount of pre-reserved memory.
39  * This is all handled in the intel-gtt.ko module. i915.ko only
40  * cares about the vga bit for the vga rbiter.
41  */
42 #define INTEL_GMCH_CTRL		0x52
43 #define INTEL_GMCH_VGA_DISABLE  (1 << 1)
44 #define SNB_GMCH_CTRL		0x50
45 #define    SNB_GMCH_GGMS_SHIFT	8 /* GTT Graphics Memory Size */
46 #define    SNB_GMCH_GGMS_MASK	0x3
47 #define    SNB_GMCH_GMS_SHIFT   3 /* Graphics Mode Select */
48 #define    SNB_GMCH_GMS_MASK    0x1f
49 #define    IVB_GMCH_GMS_SHIFT   4
50 #define    IVB_GMCH_GMS_MASK    0xf
51 
52 
53 /* PCI config space */
54 
55 #define HPLLCC	0xc0 /* 855 only */
56 #define   GC_CLOCK_CONTROL_MASK		(0xf << 0)
57 #define   GC_CLOCK_133_200		(0 << 0)
58 #define   GC_CLOCK_100_200		(1 << 0)
59 #define   GC_CLOCK_100_133		(2 << 0)
60 #define   GC_CLOCK_166_250		(3 << 0)
61 #define GCFGC2	0xda
62 #define GCFGC	0xf0 /* 915+ only */
63 #define   GC_LOW_FREQUENCY_ENABLE	(1 << 7)
64 #define   GC_DISPLAY_CLOCK_190_200_MHZ	(0 << 4)
65 #define   GC_DISPLAY_CLOCK_333_MHZ	(4 << 4)
66 #define   GC_DISPLAY_CLOCK_MASK		(7 << 4)
67 #define   GM45_GC_RENDER_CLOCK_MASK	(0xf << 0)
68 #define   GM45_GC_RENDER_CLOCK_266_MHZ	(8 << 0)
69 #define   GM45_GC_RENDER_CLOCK_320_MHZ	(9 << 0)
70 #define   GM45_GC_RENDER_CLOCK_400_MHZ	(0xb << 0)
71 #define   GM45_GC_RENDER_CLOCK_533_MHZ	(0xc << 0)
72 #define   I965_GC_RENDER_CLOCK_MASK	(0xf << 0)
73 #define   I965_GC_RENDER_CLOCK_267_MHZ	(2 << 0)
74 #define   I965_GC_RENDER_CLOCK_333_MHZ	(3 << 0)
75 #define   I965_GC_RENDER_CLOCK_444_MHZ	(4 << 0)
76 #define   I965_GC_RENDER_CLOCK_533_MHZ	(5 << 0)
77 #define   I945_GC_RENDER_CLOCK_MASK	(7 << 0)
78 #define   I945_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
79 #define   I945_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
80 #define   I945_GC_RENDER_CLOCK_250_MHZ	(3 << 0)
81 #define   I945_GC_RENDER_CLOCK_400_MHZ	(5 << 0)
82 #define   I915_GC_RENDER_CLOCK_MASK	(7 << 0)
83 #define   I915_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
84 #define   I915_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
85 #define   I915_GC_RENDER_CLOCK_333_MHZ	(4 << 0)
86 #define LBB	0xf4
87 
88 /* Graphics reset regs */
89 #define I965_GDRST 0xc0 /* PCI config register */
90 #define ILK_GDSR 0x2ca4 /* MCHBAR offset */
91 #define  GRDOM_FULL	(0<<2)
92 #define  GRDOM_RENDER	(1<<2)
93 #define  GRDOM_MEDIA	(3<<2)
94 #define  GRDOM_RESET_ENABLE (1<<0)
95 
96 #define GEN6_MBCUNIT_SNPCR	0x900c /* for LLC config */
97 #define   GEN6_MBC_SNPCR_SHIFT	21
98 #define   GEN6_MBC_SNPCR_MASK	(3<<21)
99 #define   GEN6_MBC_SNPCR_MAX	(0<<21)
100 #define   GEN6_MBC_SNPCR_MED	(1<<21)
101 #define   GEN6_MBC_SNPCR_LOW	(2<<21)
102 #define   GEN6_MBC_SNPCR_MIN	(3<<21) /* only 1/16th of the cache is shared */
103 
104 #define GEN6_MBCTL		0x0907c
105 #define   GEN6_MBCTL_ENABLE_BOOT_FETCH	(1 << 4)
106 #define   GEN6_MBCTL_CTX_FETCH_NEEDED	(1 << 3)
107 #define   GEN6_MBCTL_BME_UPDATE_ENABLE	(1 << 2)
108 #define   GEN6_MBCTL_MAE_UPDATE_ENABLE	(1 << 1)
109 #define   GEN6_MBCTL_BOOT_FETCH_MECH	(1 << 0)
110 
111 #define GEN6_GDRST	0x941c
112 #define  GEN6_GRDOM_FULL		(1 << 0)
113 #define  GEN6_GRDOM_RENDER		(1 << 1)
114 #define  GEN6_GRDOM_MEDIA		(1 << 2)
115 #define  GEN6_GRDOM_BLT			(1 << 3)
116 
117 #define RING_PP_DIR_BASE(ring)		((ring)->mmio_base+0x228)
118 #define RING_PP_DIR_BASE_READ(ring)	((ring)->mmio_base+0x518)
119 #define RING_PP_DIR_DCLV(ring)		((ring)->mmio_base+0x220)
120 #define   PP_DIR_DCLV_2G		0xffffffff
121 
122 #define GAM_ECOCHK			0x4090
123 #define   ECOCHK_SNB_BIT		(1<<10)
124 #define   ECOCHK_PPGTT_CACHE64B		(0x3<<3)
125 #define   ECOCHK_PPGTT_CACHE4B		(0x0<<3)
126 
127 #define GAC_ECO_BITS			0x14090
128 #define   ECOBITS_PPGTT_CACHE64B	(3<<8)
129 #define   ECOBITS_PPGTT_CACHE4B		(0<<8)
130 
131 #define GAB_CTL				0x24000
132 #define   GAB_CTL_CONT_AFTER_PAGEFAULT	(1<<8)
133 
134 /* VGA stuff */
135 
136 #define VGA_ST01_MDA 0x3ba
137 #define VGA_ST01_CGA 0x3da
138 
139 #define VGA_MSR_WRITE 0x3c2
140 #define VGA_MSR_READ 0x3cc
141 #define   VGA_MSR_MEM_EN (1<<1)
142 #define   VGA_MSR_CGA_MODE (1<<0)
143 
144 #define VGA_SR_INDEX 0x3c4
145 #define VGA_SR_DATA 0x3c5
146 
147 #define VGA_AR_INDEX 0x3c0
148 #define   VGA_AR_VID_EN (1<<5)
149 #define VGA_AR_DATA_WRITE 0x3c0
150 #define VGA_AR_DATA_READ 0x3c1
151 
152 #define VGA_GR_INDEX 0x3ce
153 #define VGA_GR_DATA 0x3cf
154 /* GR05 */
155 #define   VGA_GR_MEM_READ_MODE_SHIFT 3
156 #define     VGA_GR_MEM_READ_MODE_PLANE 1
157 /* GR06 */
158 #define   VGA_GR_MEM_MODE_MASK 0xc
159 #define   VGA_GR_MEM_MODE_SHIFT 2
160 #define   VGA_GR_MEM_A0000_AFFFF 0
161 #define   VGA_GR_MEM_A0000_BFFFF 1
162 #define   VGA_GR_MEM_B0000_B7FFF 2
163 #define   VGA_GR_MEM_B0000_BFFFF 3
164 
165 #define VGA_DACMASK 0x3c6
166 #define VGA_DACRX 0x3c7
167 #define VGA_DACWX 0x3c8
168 #define VGA_DACDATA 0x3c9
169 
170 #define VGA_CR_INDEX_MDA 0x3b4
171 #define VGA_CR_DATA_MDA 0x3b5
172 #define VGA_CR_INDEX_CGA 0x3d4
173 #define VGA_CR_DATA_CGA 0x3d5
174 
175 /*
176  * Memory interface instructions used by the kernel
177  */
178 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
179 
180 #define MI_NOOP			MI_INSTR(0, 0)
181 #define MI_USER_INTERRUPT	MI_INSTR(0x02, 0)
182 #define MI_WAIT_FOR_EVENT       MI_INSTR(0x03, 0)
183 #define   MI_WAIT_FOR_OVERLAY_FLIP	(1<<16)
184 #define   MI_WAIT_FOR_PLANE_B_FLIP      (1<<6)
185 #define   MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)
186 #define   MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
187 #define MI_FLUSH		MI_INSTR(0x04, 0)
188 #define   MI_READ_FLUSH		(1 << 0)
189 #define   MI_EXE_FLUSH		(1 << 1)
190 #define   MI_NO_WRITE_FLUSH	(1 << 2)
191 #define   MI_SCENE_COUNT	(1 << 3) /* just increment scene count */
192 #define   MI_END_SCENE		(1 << 4) /* flush binner and incr scene count */
193 #define   MI_INVALIDATE_ISP	(1 << 5) /* invalidate indirect state pointers */
194 #define MI_BATCH_BUFFER_END	MI_INSTR(0x0a, 0)
195 #define MI_SUSPEND_FLUSH	MI_INSTR(0x0b, 0)
196 #define   MI_SUSPEND_FLUSH_EN	(1<<0)
197 #define MI_REPORT_HEAD		MI_INSTR(0x07, 0)
198 #define MI_OVERLAY_FLIP		MI_INSTR(0x11, 0)
199 #define   MI_OVERLAY_CONTINUE	(0x0<<21)
200 #define   MI_OVERLAY_ON		(0x1<<21)
201 #define   MI_OVERLAY_OFF	(0x2<<21)
202 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
203 #define MI_DISPLAY_FLIP		MI_INSTR(0x14, 2)
204 #define MI_DISPLAY_FLIP_I915	MI_INSTR(0x14, 1)
205 #define   MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
206 /* IVB has funny definitions for which plane to flip. */
207 #define   MI_DISPLAY_FLIP_IVB_PLANE_A  (0 << 19)
208 #define   MI_DISPLAY_FLIP_IVB_PLANE_B  (1 << 19)
209 #define   MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
210 #define   MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
211 #define   MI_DISPLAY_FLIP_IVB_PLANE_C  (4 << 19)
212 #define   MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
213 #define MI_ARB_ON_OFF		MI_INSTR(0x08, 0)
214 #define   MI_ARB_ENABLE			(1<<0)
215 #define   MI_ARB_DISABLE		(0<<0)
216 
217 #define MI_SET_CONTEXT		MI_INSTR(0x18, 0)
218 #define   MI_MM_SPACE_GTT		(1<<8)
219 #define   MI_MM_SPACE_PHYSICAL		(0<<8)
220 #define   MI_SAVE_EXT_STATE_EN		(1<<3)
221 #define   MI_RESTORE_EXT_STATE_EN	(1<<2)
222 #define   MI_FORCE_RESTORE		(1<<1)
223 #define   MI_RESTORE_INHIBIT		(1<<0)
224 #define MI_STORE_DWORD_IMM	MI_INSTR(0x20, 1)
225 #define   MI_MEM_VIRTUAL	(1 << 22) /* 965+ only */
226 #define MI_STORE_DWORD_INDEX	MI_INSTR(0x21, 1)
227 #define   MI_STORE_DWORD_INDEX_SHIFT 2
228 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
229  * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
230  *   simply ignores the register load under certain conditions.
231  * - One can actually load arbitrary many arbitrary registers: Simply issue x
232  *   address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
233  */
234 #define MI_LOAD_REGISTER_IMM(x)	MI_INSTR(0x22, 2*x-1)
235 #define MI_FLUSH_DW		MI_INSTR(0x26, 1) /* for GEN6 */
236 #define   MI_FLUSH_DW_STORE_INDEX	(1<<21)
237 #define   MI_INVALIDATE_TLB		(1<<18)
238 #define   MI_FLUSH_DW_OP_STOREDW	(1<<14)
239 #define   MI_INVALIDATE_BSD		(1<<7)
240 #define   MI_FLUSH_DW_USE_GTT		(1<<2)
241 #define   MI_FLUSH_DW_USE_PPGTT		(0<<2)
242 #define MI_BATCH_BUFFER		MI_INSTR(0x30, 1)
243 #define   MI_BATCH_NON_SECURE		(1)
244 /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
245 #define   MI_BATCH_NON_SECURE_I965 	(1<<8)
246 #define   MI_BATCH_PPGTT_HSW		(1<<8)
247 #define   MI_BATCH_NON_SECURE_HSW 	(1<<13)
248 #define MI_BATCH_BUFFER_START	MI_INSTR(0x31, 0)
249 #define   MI_BATCH_GTT		    (2<<6) /* aliased with (1<<7) on gen4 */
250 #define MI_SEMAPHORE_MBOX	MI_INSTR(0x16, 1) /* gen6+ */
251 #define  MI_SEMAPHORE_GLOBAL_GTT    (1<<22)
252 #define  MI_SEMAPHORE_UPDATE	    (1<<21)
253 #define  MI_SEMAPHORE_COMPARE	    (1<<20)
254 #define  MI_SEMAPHORE_REGISTER	    (1<<18)
255 #define  MI_SEMAPHORE_SYNC_RV	    (2<<16)
256 #define  MI_SEMAPHORE_SYNC_RB	    (0<<16)
257 #define  MI_SEMAPHORE_SYNC_VR	    (0<<16)
258 #define  MI_SEMAPHORE_SYNC_VB	    (2<<16)
259 #define  MI_SEMAPHORE_SYNC_BR	    (2<<16)
260 #define  MI_SEMAPHORE_SYNC_BV	    (0<<16)
261 #define  MI_SEMAPHORE_SYNC_INVALID  (1<<0)
262 /*
263  * 3D instructions used by the kernel
264  */
265 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
266 
267 #define GFX_OP_RASTER_RULES    ((0x3<<29)|(0x7<<24))
268 #define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
269 #define   SC_UPDATE_SCISSOR       (0x1<<1)
270 #define   SC_ENABLE_MASK          (0x1<<0)
271 #define   SC_ENABLE               (0x1<<0)
272 #define GFX_OP_LOAD_INDIRECT   ((0x3<<29)|(0x1d<<24)|(0x7<<16))
273 #define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
274 #define   SCI_YMIN_MASK      (0xffff<<16)
275 #define   SCI_XMIN_MASK      (0xffff<<0)
276 #define   SCI_YMAX_MASK      (0xffff<<16)
277 #define   SCI_XMAX_MASK      (0xffff<<0)
278 #define GFX_OP_SCISSOR_ENABLE	 ((0x3<<29)|(0x1c<<24)|(0x10<<19))
279 #define GFX_OP_SCISSOR_RECT	 ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
280 #define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
281 #define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
282 #define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
283 #define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
284 #define GFX_OP_DESTBUFFER_INFO	 ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
285 #define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
286 #define GFX_OP_DRAWRECT_INFO_I965  ((0x7900<<16)|0x2)
287 #define SRC_COPY_BLT_CMD                ((2<<29)|(0x43<<22)|4)
288 #define XY_SRC_COPY_BLT_CMD		((2<<29)|(0x53<<22)|6)
289 #define XY_MONO_SRC_COPY_IMM_BLT	((2<<29)|(0x71<<22)|5)
290 #define XY_SRC_COPY_BLT_WRITE_ALPHA	(1<<21)
291 #define XY_SRC_COPY_BLT_WRITE_RGB	(1<<20)
292 #define   BLT_DEPTH_8			(0<<24)
293 #define   BLT_DEPTH_16_565		(1<<24)
294 #define   BLT_DEPTH_16_1555		(2<<24)
295 #define   BLT_DEPTH_32			(3<<24)
296 #define   BLT_ROP_GXCOPY		(0xcc<<16)
297 #define XY_SRC_COPY_BLT_SRC_TILED	(1<<15) /* 965+ only */
298 #define XY_SRC_COPY_BLT_DST_TILED	(1<<11) /* 965+ only */
299 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
300 #define   ASYNC_FLIP                (1<<22)
301 #define   DISPLAY_PLANE_A           (0<<20)
302 #define   DISPLAY_PLANE_B           (1<<20)
303 #define GFX_OP_PIPE_CONTROL(len)	((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
304 #define   PIPE_CONTROL_CS_STALL				(1<<20)
305 #define   PIPE_CONTROL_TLB_INVALIDATE			(1<<18)
306 #define   PIPE_CONTROL_QW_WRITE				(1<<14)
307 #define   PIPE_CONTROL_DEPTH_STALL			(1<<13)
308 #define   PIPE_CONTROL_WRITE_FLUSH			(1<<12)
309 #define   PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH	(1<<12) /* gen6+ */
310 #define   PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE	(1<<11) /* MBZ on Ironlake */
311 #define   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE		(1<<10) /* GM45+ only */
312 #define   PIPE_CONTROL_INDIRECT_STATE_DISABLE		(1<<9)
313 #define   PIPE_CONTROL_NOTIFY				(1<<8)
314 #define   PIPE_CONTROL_VF_CACHE_INVALIDATE		(1<<4)
315 #define   PIPE_CONTROL_CONST_CACHE_INVALIDATE		(1<<3)
316 #define   PIPE_CONTROL_STATE_CACHE_INVALIDATE		(1<<2)
317 #define   PIPE_CONTROL_STALL_AT_SCOREBOARD		(1<<1)
318 #define   PIPE_CONTROL_DEPTH_CACHE_FLUSH		(1<<0)
319 #define   PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
320 
321 
322 /*
323  * Reset registers
324  */
325 #define DEBUG_RESET_I830		0x6070
326 #define  DEBUG_RESET_FULL		(1<<7)
327 #define  DEBUG_RESET_RENDER		(1<<8)
328 #define  DEBUG_RESET_DISPLAY		(1<<9)
329 
330 /*
331  * DPIO - a special bus for various display related registers to hide behind:
332  *  0x800c: m1, m2, n, p1, p2, k dividers
333  *  0x8014: REF and SFR select
334  *  0x8014: N divider, VCO select
335  *  0x801c/3c: core clock bits
336  *  0x8048/68: low pass filter coefficients
337  *  0x8100: fast clock controls
338  */
339 #define DPIO_PKT			0x2100
340 #define  DPIO_RID			(0<<24)
341 #define  DPIO_OP_WRITE			(1<<16)
342 #define  DPIO_OP_READ			(0<<16)
343 #define  DPIO_PORTID			(0x12<<8)
344 #define  DPIO_BYTE			(0xf<<4)
345 #define  DPIO_BUSY			(1<<0) /* status only */
346 #define DPIO_DATA			0x2104
347 #define DPIO_REG			0x2108
348 #define DPIO_CTL			0x2110
349 #define  DPIO_MODSEL1			(1<<3) /* if ref clk b == 27 */
350 #define  DPIO_MODSEL0			(1<<2) /* if ref clk a == 27 */
351 #define  DPIO_SFR_BYPASS		(1<<1)
352 #define  DPIO_RESET			(1<<0)
353 
354 #define _DPIO_DIV_A			0x800c
355 #define   DPIO_POST_DIV_SHIFT		(28) /* 3 bits */
356 #define   DPIO_K_SHIFT			(24) /* 4 bits */
357 #define   DPIO_P1_SHIFT			(21) /* 3 bits */
358 #define   DPIO_P2_SHIFT			(16) /* 5 bits */
359 #define   DPIO_N_SHIFT			(12) /* 4 bits */
360 #define   DPIO_ENABLE_CALIBRATION	(1<<11)
361 #define   DPIO_M1DIV_SHIFT		(8) /* 3 bits */
362 #define   DPIO_M2DIV_MASK		0xff
363 #define _DPIO_DIV_B			0x802c
364 #define DPIO_DIV(pipe) _PIPE(pipe, _DPIO_DIV_A, _DPIO_DIV_B)
365 
366 #define _DPIO_REFSFR_A			0x8014
367 #define   DPIO_REFSEL_OVERRIDE		27
368 #define   DPIO_PLL_MODESEL_SHIFT	24 /* 3 bits */
369 #define   DPIO_BIAS_CURRENT_CTL_SHIFT	21 /* 3 bits, always 0x7 */
370 #define   DPIO_PLL_REFCLK_SEL_SHIFT	16 /* 2 bits */
371 #define   DPIO_PLL_REFCLK_SEL_MASK	3
372 #define   DPIO_DRIVER_CTL_SHIFT		12 /* always set to 0x8 */
373 #define   DPIO_CLK_BIAS_CTL_SHIFT	8 /* always set to 0x5 */
374 #define _DPIO_REFSFR_B			0x8034
375 #define DPIO_REFSFR(pipe) _PIPE(pipe, _DPIO_REFSFR_A, _DPIO_REFSFR_B)
376 
377 #define _DPIO_CORE_CLK_A		0x801c
378 #define _DPIO_CORE_CLK_B		0x803c
379 #define DPIO_CORE_CLK(pipe) _PIPE(pipe, _DPIO_CORE_CLK_A, _DPIO_CORE_CLK_B)
380 
381 #define _DPIO_LFP_COEFF_A		0x8048
382 #define _DPIO_LFP_COEFF_B		0x8068
383 #define DPIO_LFP_COEFF(pipe) _PIPE(pipe, _DPIO_LFP_COEFF_A, _DPIO_LFP_COEFF_B)
384 
385 #define DPIO_FASTCLK_DISABLE		0x8100
386 
387 #define DPIO_DATA_CHANNEL1		0x8220
388 #define DPIO_DATA_CHANNEL2		0x8420
389 
390 /*
391  * Fence registers
392  */
393 #define FENCE_REG_830_0			0x2000
394 #define FENCE_REG_945_8			0x3000
395 #define   I830_FENCE_START_MASK		0x07f80000
396 #define   I830_FENCE_TILING_Y_SHIFT	12
397 #define   I830_FENCE_SIZE_BITS(size)	((ffs((size) >> 19) - 1) << 8)
398 #define   I830_FENCE_PITCH_SHIFT	4
399 #define   I830_FENCE_REG_VALID		(1<<0)
400 #define   I915_FENCE_MAX_PITCH_VAL	4
401 #define   I830_FENCE_MAX_PITCH_VAL	6
402 #define   I830_FENCE_MAX_SIZE_VAL	(1<<8)
403 
404 #define   I915_FENCE_START_MASK		0x0ff00000
405 #define   I915_FENCE_SIZE_BITS(size)	((ffs((size) >> 20) - 1) << 8)
406 
407 #define FENCE_REG_965_0			0x03000
408 #define   I965_FENCE_PITCH_SHIFT	2
409 #define   I965_FENCE_TILING_Y_SHIFT	1
410 #define   I965_FENCE_REG_VALID		(1<<0)
411 #define   I965_FENCE_MAX_PITCH_VAL	0x0400
412 
413 #define FENCE_REG_SANDYBRIDGE_0		0x100000
414 #define   SANDYBRIDGE_FENCE_PITCH_SHIFT	32
415 
416 /* control register for cpu gtt access */
417 #define TILECTL				0x101000
418 #define   TILECTL_SWZCTL			(1 << 0)
419 #define   TILECTL_TLB_PREFETCH_DIS	(1 << 2)
420 #define   TILECTL_BACKSNOOP_DIS		(1 << 3)
421 
422 /*
423  * Instruction and interrupt control regs
424  */
425 #define PGTBL_ER	0x02024
426 #define RENDER_RING_BASE	0x02000
427 #define BSD_RING_BASE		0x04000
428 #define GEN6_BSD_RING_BASE	0x12000
429 #define BLT_RING_BASE		0x22000
430 #define RING_TAIL(base)		((base)+0x30)
431 #define RING_HEAD(base)		((base)+0x34)
432 #define RING_START(base)	((base)+0x38)
433 #define RING_CTL(base)		((base)+0x3c)
434 #define RING_SYNC_0(base)	((base)+0x40)
435 #define RING_SYNC_1(base)	((base)+0x44)
436 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
437 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
438 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
439 #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
440 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
441 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
442 #define RING_MAX_IDLE(base)	((base)+0x54)
443 #define RING_HWS_PGA(base)	((base)+0x80)
444 #define RING_HWS_PGA_GEN6(base)	((base)+0x2080)
445 #define ARB_MODE		0x04030
446 #define   ARB_MODE_SWIZZLE_SNB	(1<<4)
447 #define   ARB_MODE_SWIZZLE_IVB	(1<<5)
448 #define RENDER_HWS_PGA_GEN7	(0x04080)
449 #define RING_FAULT_REG(ring)	(0x4094 + 0x100*(ring)->id)
450 #define DONE_REG		0x40b0
451 #define BSD_HWS_PGA_GEN7	(0x04180)
452 #define BLT_HWS_PGA_GEN7	(0x04280)
453 #define RING_ACTHD(base)	((base)+0x74)
454 #define RING_NOPID(base)	((base)+0x94)
455 #define RING_IMR(base)		((base)+0xa8)
456 #define RING_TIMESTAMP(base)	((base)+0x358)
457 #define   TAIL_ADDR		0x001FFFF8
458 #define   HEAD_WRAP_COUNT	0xFFE00000
459 #define   HEAD_WRAP_ONE		0x00200000
460 #define   HEAD_ADDR		0x001FFFFC
461 #define   RING_NR_PAGES		0x001FF000
462 #define   RING_REPORT_MASK	0x00000006
463 #define   RING_REPORT_64K	0x00000002
464 #define   RING_REPORT_128K	0x00000004
465 #define   RING_NO_REPORT	0x00000000
466 #define   RING_VALID_MASK	0x00000001
467 #define   RING_VALID		0x00000001
468 #define   RING_INVALID		0x00000000
469 #define   RING_WAIT_I8XX	(1<<0) /* gen2, PRBx_HEAD */
470 #define   RING_WAIT		(1<<11) /* gen3+, PRBx_CTL */
471 #define   RING_WAIT_SEMAPHORE	(1<<10) /* gen6+ */
472 #if 0
473 #define PRB0_TAIL	0x02030
474 #define PRB0_HEAD	0x02034
475 #define PRB0_START	0x02038
476 #define PRB0_CTL	0x0203c
477 #define PRB1_TAIL	0x02040 /* 915+ only */
478 #define PRB1_HEAD	0x02044 /* 915+ only */
479 #define PRB1_START	0x02048 /* 915+ only */
480 #define PRB1_CTL	0x0204c /* 915+ only */
481 #endif
482 #define IPEIR_I965	0x02064
483 #define IPEHR_I965	0x02068
484 #define INSTDONE_I965	0x0206c
485 #define GEN7_INSTDONE_1		0x0206c
486 #define GEN7_SC_INSTDONE	0x07100
487 #define GEN7_SAMPLER_INSTDONE	0x0e160
488 #define GEN7_ROW_INSTDONE	0x0e164
489 #define I915_NUM_INSTDONE_REG	4
490 #define RING_IPEIR(base)	((base)+0x64)
491 #define RING_IPEHR(base)	((base)+0x68)
492 #define RING_INSTDONE(base)	((base)+0x6c)
493 #define RING_INSTPS(base)	((base)+0x70)
494 #define RING_DMA_FADD(base)	((base)+0x78)
495 #define RING_INSTPM(base)	((base)+0xc0)
496 #define INSTPS		0x02070 /* 965+ only */
497 #define INSTDONE1	0x0207c /* 965+ only */
498 #define ACTHD_I965	0x02074
499 #define HWS_PGA		0x02080
500 #define HWS_ADDRESS_MASK	0xfffff000
501 #define HWS_START_ADDRESS_SHIFT	4
502 #define PWRCTXA		0x2088 /* 965GM+ only */
503 #define   PWRCTX_EN	(1<<0)
504 #define IPEIR		0x02088
505 #define IPEHR		0x0208c
506 #define INSTDONE	0x02090
507 #define NOPID		0x02094
508 #define HWSTAM		0x02098
509 #define DMA_FADD_I8XX	0x020d0
510 
511 #define ERROR_GEN6	0x040a0
512 #define GEN7_ERR_INT	0x44040
513 #define   ERR_INT_MMIO_UNCLAIMED (1<<13)
514 
515 /* GM45+ chicken bits -- debug workaround bits that may be required
516  * for various sorts of correct behavior.  The top 16 bits of each are
517  * the enables for writing to the corresponding low bit.
518  */
519 #define _3D_CHICKEN	0x02084
520 #define _3D_CHICKEN2	0x0208c
521 /* Disables pipelining of read flushes past the SF-WIZ interface.
522  * Required on all Ironlake steppings according to the B-Spec, but the
523  * particular danger of not doing so is not specified.
524  */
525 # define _3D_CHICKEN2_WM_READ_PIPELINED			(1 << 14)
526 #define _3D_CHICKEN3	0x02090
527 #define  _3D_CHICKEN_SF_DISABLE_OBJEND_CULL		(1 << 10)
528 #define  _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL		(1 << 5)
529 
530 #define MI_MODE		0x0209c
531 # define VS_TIMER_DISPATCH				(1 << 6)
532 # define MI_FLUSH_ENABLE				(1 << 12)
533 
534 #define GEN6_GT_MODE	0x20d0
535 #define   GEN6_GT_MODE_HI	(1 << 9)
536 
537 #define GFX_MODE	0x02520
538 #define GFX_MODE_GEN7	0x0229c
539 #define RING_MODE_GEN7(ring)	((ring)->mmio_base+0x29c)
540 #define   GFX_RUN_LIST_ENABLE		(1<<15)
541 #define   GFX_TLB_INVALIDATE_ALWAYS	(1<<13)
542 #define   GFX_SURFACE_FAULT_ENABLE	(1<<12)
543 #define   GFX_REPLAY_MODE		(1<<11)
544 #define   GFX_PSMI_GRANULARITY		(1<<10)
545 #define   GFX_PPGTT_ENABLE		(1<<9)
546 
547 #define VLV_DISPLAY_BASE 0x180000
548 
549 #define SCPD0		0x0209c /* 915+ only */
550 #define IER		0x020a0
551 #define IIR		0x020a4
552 #define IMR		0x020a8
553 #define ISR		0x020ac
554 #define VLV_GUNIT_CLOCK_GATE	0x182060
555 #define   GCFG_DIS		(1<<8)
556 #define VLV_IIR_RW	0x182084
557 #define VLV_IER		0x1820a0
558 #define VLV_IIR		0x1820a4
559 #define VLV_IMR		0x1820a8
560 #define VLV_ISR		0x1820ac
561 #define   I915_PIPE_CONTROL_NOTIFY_INTERRUPT		(1<<18)
562 #define   I915_DISPLAY_PORT_INTERRUPT			(1<<17)
563 #define   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT	(1<<15)
564 #define   I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT	(1<<14) /* p-state */
565 #define   I915_HWB_OOM_INTERRUPT			(1<<13)
566 #define   I915_SYNC_STATUS_INTERRUPT			(1<<12)
567 #define   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT	(1<<11)
568 #define   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT	(1<<10)
569 #define   I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT	(1<<9)
570 #define   I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT	(1<<8)
571 #define   I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT		(1<<7)
572 #define   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT		(1<<6)
573 #define   I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT		(1<<5)
574 #define   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT		(1<<4)
575 #define   I915_DEBUG_INTERRUPT				(1<<2)
576 #define   I915_USER_INTERRUPT				(1<<1)
577 #define   I915_ASLE_INTERRUPT				(1<<0)
578 #define   I915_BSD_USER_INTERRUPT                      (1<<25)
579 #define EIR		0x020b0
580 #define EMR		0x020b4
581 #define ESR		0x020b8
582 #define   GM45_ERROR_PAGE_TABLE				(1<<5)
583 #define   GM45_ERROR_MEM_PRIV				(1<<4)
584 #define   I915_ERROR_PAGE_TABLE				(1<<4)
585 #define   GM45_ERROR_CP_PRIV				(1<<3)
586 #define   I915_ERROR_MEMORY_REFRESH			(1<<1)
587 #define   I915_ERROR_INSTRUCTION			(1<<0)
588 #define INSTPM	        0x020c0
589 #define   INSTPM_SELF_EN (1<<12) /* 915GM only */
590 #define   INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts
591 					will not assert AGPBUSY# and will only
592 					be delivered when out of C3. */
593 #define   INSTPM_FORCE_ORDERING				(1<<7) /* GEN6+ */
594 #define ACTHD	        0x020c8
595 #define FW_BLC		0x020d8
596 #define FW_BLC2		0x020dc
597 #define FW_BLC_SELF	0x020e0 /* 915+ only */
598 #define   FW_BLC_SELF_EN_MASK      (1<<31)
599 #define   FW_BLC_SELF_FIFO_MASK    (1<<16) /* 945 only */
600 #define   FW_BLC_SELF_EN           (1<<15) /* 945 only */
601 #define MM_BURST_LENGTH     0x00700000
602 #define MM_FIFO_WATERMARK   0x0001F000
603 #define LM_BURST_LENGTH     0x00000700
604 #define LM_FIFO_WATERMARK   0x0000001F
605 #define MI_ARB_STATE	0x020e4 /* 915+ only */
606 
607 /* Make render/texture TLB fetches lower priorty than associated data
608  *   fetches. This is not turned on by default
609  */
610 #define   MI_ARB_RENDER_TLB_LOW_PRIORITY	(1 << 15)
611 
612 /* Isoch request wait on GTT enable (Display A/B/C streams).
613  * Make isoch requests stall on the TLB update. May cause
614  * display underruns (test mode only)
615  */
616 #define   MI_ARB_ISOCH_WAIT_GTT			(1 << 14)
617 
618 /* Block grant count for isoch requests when block count is
619  * set to a finite value.
620  */
621 #define   MI_ARB_BLOCK_GRANT_MASK		(3 << 12)
622 #define   MI_ARB_BLOCK_GRANT_8			(0 << 12)	/* for 3 display planes */
623 #define   MI_ARB_BLOCK_GRANT_4			(1 << 12)	/* for 2 display planes */
624 #define   MI_ARB_BLOCK_GRANT_2			(2 << 12)	/* for 1 display plane */
625 #define   MI_ARB_BLOCK_GRANT_0			(3 << 12)	/* don't use */
626 
627 /* Enable render writes to complete in C2/C3/C4 power states.
628  * If this isn't enabled, render writes are prevented in low
629  * power states. That seems bad to me.
630  */
631 #define   MI_ARB_C3_LP_WRITE_ENABLE		(1 << 11)
632 
633 /* This acknowledges an async flip immediately instead
634  * of waiting for 2TLB fetches.
635  */
636 #define   MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE	(1 << 10)
637 
638 /* Enables non-sequential data reads through arbiter
639  */
640 #define   MI_ARB_DUAL_DATA_PHASE_DISABLE	(1 << 9)
641 
642 /* Disable FSB snooping of cacheable write cycles from binner/render
643  * command stream
644  */
645 #define   MI_ARB_CACHE_SNOOP_DISABLE		(1 << 8)
646 
647 /* Arbiter time slice for non-isoch streams */
648 #define   MI_ARB_TIME_SLICE_MASK		(7 << 5)
649 #define   MI_ARB_TIME_SLICE_1			(0 << 5)
650 #define   MI_ARB_TIME_SLICE_2			(1 << 5)
651 #define   MI_ARB_TIME_SLICE_4			(2 << 5)
652 #define   MI_ARB_TIME_SLICE_6			(3 << 5)
653 #define   MI_ARB_TIME_SLICE_8			(4 << 5)
654 #define   MI_ARB_TIME_SLICE_10			(5 << 5)
655 #define   MI_ARB_TIME_SLICE_14			(6 << 5)
656 #define   MI_ARB_TIME_SLICE_16			(7 << 5)
657 
658 /* Low priority grace period page size */
659 #define   MI_ARB_LOW_PRIORITY_GRACE_4KB		(0 << 4)	/* default */
660 #define   MI_ARB_LOW_PRIORITY_GRACE_8KB		(1 << 4)
661 
662 /* Disable display A/B trickle feed */
663 #define   MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE	(1 << 2)
664 
665 /* Set display plane priority */
666 #define   MI_ARB_DISPLAY_PRIORITY_A_B		(0 << 0)	/* display A > display B */
667 #define   MI_ARB_DISPLAY_PRIORITY_B_A		(1 << 0)	/* display B > display A */
668 
669 #define CACHE_MODE_0	0x02120 /* 915+ only */
670 #define   CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
671 #define   CM0_IZ_OPT_DISABLE      (1<<6)
672 #define   CM0_ZR_OPT_DISABLE      (1<<5)
673 #define	  CM0_STC_EVICT_DISABLE_LRA_SNB	(1<<5)
674 #define   CM0_DEPTH_EVICT_DISABLE (1<<4)
675 #define   CM0_COLOR_EVICT_DISABLE (1<<3)
676 #define   CM0_DEPTH_WRITE_DISABLE (1<<1)
677 #define   CM0_RC_OP_FLUSH_DISABLE (1<<0)
678 #define BB_ADDR		0x02140 /* 8 bytes */
679 #define GFX_FLSH_CNTL	0x02170 /* 915+ only */
680 #define GFX_FLSH_CNTL_GEN6	0x101008
681 #define   GFX_FLSH_CNTL_EN	(1<<0)
682 #define ECOSKPD		0x021d0
683 #define   ECO_GATING_CX_ONLY	(1<<3)
684 #define   ECO_FLIP_DONE		(1<<0)
685 
686 #define CACHE_MODE_1		0x7004 /* IVB+ */
687 #define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
688 
689 /* GEN6 interrupt control
690  * Note that the per-ring interrupt bits do alias with the global interrupt bits
691  * in GTIMR. */
692 #define GEN6_RENDER_HWSTAM	0x2098
693 #define GEN6_RENDER_IMR		0x20a8
694 #define   GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT		(1 << 8)
695 #define   GEN6_RENDER_PPGTT_PAGE_FAULT			(1 << 7)
696 #define   GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED		(1 << 6)
697 #define   GEN6_RENDER_L3_PARITY_ERROR			(1 << 5)
698 #define   GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT	(1 << 4)
699 #define   GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR	(1 << 3)
700 #define   GEN6_RENDER_SYNC_STATUS			(1 << 2)
701 #define   GEN6_RENDER_DEBUG_INTERRUPT			(1 << 1)
702 #define   GEN6_RENDER_USER_INTERRUPT			(1 << 0)
703 
704 #define GEN6_BLITTER_HWSTAM	0x22098
705 #define GEN6_BLITTER_IMR	0x220a8
706 #define   GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT	(1 << 26)
707 #define   GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR	(1 << 25)
708 #define   GEN6_BLITTER_SYNC_STATUS			(1 << 24)
709 #define   GEN6_BLITTER_USER_INTERRUPT			(1 << 22)
710 
711 #define GEN6_BLITTER_ECOSKPD	0x221d0
712 #define   GEN6_BLITTER_LOCK_SHIFT			16
713 #define   GEN6_BLITTER_FBC_NOTIFY			(1<<3)
714 
715 #define GEN6_BSD_SLEEP_PSMI_CONTROL	0x12050
716 #define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
717 #define   GEN6_BSD_SLEEP_FLUSH_DISABLE	(1 << 2)
718 #define   GEN6_BSD_SLEEP_INDICATOR	(1 << 3)
719 #define   GEN6_BSD_GO_INDICATOR		(1 << 4)
720 
721 #define GEN6_BSD_HWSTAM			0x12098
722 #define GEN6_BSD_IMR			0x120a8
723 #define   GEN6_BSD_USER_INTERRUPT	(1 << 12)
724 
725 #define GEN6_BSD_RNCID			0x12198
726 
727 #define GEN7_FF_THREAD_MODE		0x20a0
728 #define   GEN7_FF_SCHED_MASK		0x0077070
729 #define   GEN7_FF_TS_SCHED_HS1		(0x5<<16)
730 #define   GEN7_FF_TS_SCHED_HS0		(0x3<<16)
731 #define   GEN7_FF_TS_SCHED_LOAD_BALANCE	(0x1<<16)
732 #define   GEN7_FF_TS_SCHED_HW		(0x0<<16) /* Default */
733 #define   GEN7_FF_VS_SCHED_HS1		(0x5<<12)
734 #define   GEN7_FF_VS_SCHED_HS0		(0x3<<12)
735 #define   GEN7_FF_VS_SCHED_LOAD_BALANCE	(0x1<<12) /* Default */
736 #define   GEN7_FF_VS_SCHED_HW		(0x0<<12)
737 #define   GEN7_FF_DS_SCHED_HS1		(0x5<<4)
738 #define   GEN7_FF_DS_SCHED_HS0		(0x3<<4)
739 #define   GEN7_FF_DS_SCHED_LOAD_BALANCE	(0x1<<4)  /* Default */
740 #define   GEN7_FF_DS_SCHED_HW		(0x0<<4)
741 
742 /*
743  * Framebuffer compression (915+ only)
744  */
745 
746 #define FBC_CFB_BASE		0x03200 /* 4k page aligned */
747 #define FBC_LL_BASE		0x03204 /* 4k page aligned */
748 #define FBC_CONTROL		0x03208
749 #define   FBC_CTL_EN		(1<<31)
750 #define   FBC_CTL_PERIODIC	(1<<30)
751 #define   FBC_CTL_INTERVAL_SHIFT (16)
752 #define   FBC_CTL_UNCOMPRESSIBLE (1<<14)
753 #define   FBC_CTL_C3_IDLE	(1<<13)
754 #define   FBC_CTL_STRIDE_SHIFT	(5)
755 #define   FBC_CTL_FENCENO	(1<<0)
756 #define FBC_COMMAND		0x0320c
757 #define   FBC_CMD_COMPRESS	(1<<0)
758 #define FBC_STATUS		0x03210
759 #define   FBC_STAT_COMPRESSING	(1<<31)
760 #define   FBC_STAT_COMPRESSED	(1<<30)
761 #define   FBC_STAT_MODIFIED	(1<<29)
762 #define   FBC_STAT_CURRENT_LINE	(1<<0)
763 #define FBC_CONTROL2		0x03214
764 #define   FBC_CTL_FENCE_DBL	(0<<4)
765 #define   FBC_CTL_IDLE_IMM	(0<<2)
766 #define   FBC_CTL_IDLE_FULL	(1<<2)
767 #define   FBC_CTL_IDLE_LINE	(2<<2)
768 #define   FBC_CTL_IDLE_DEBUG	(3<<2)
769 #define   FBC_CTL_CPU_FENCE	(1<<1)
770 #define   FBC_CTL_PLANEA	(0<<0)
771 #define   FBC_CTL_PLANEB	(1<<0)
772 #define FBC_FENCE_OFF		0x0321b
773 #define FBC_TAG			0x03300
774 
775 #define FBC_LL_SIZE		(1536)
776 
777 /* Framebuffer compression for GM45+ */
778 #define DPFC_CB_BASE		0x3200
779 #define DPFC_CONTROL		0x3208
780 #define   DPFC_CTL_EN		(1<<31)
781 #define   DPFC_CTL_PLANEA	(0<<30)
782 #define   DPFC_CTL_PLANEB	(1<<30)
783 #define   DPFC_CTL_FENCE_EN	(1<<29)
784 #define   DPFC_CTL_PERSISTENT_MODE	(1<<25)
785 #define   DPFC_SR_EN		(1<<10)
786 #define   DPFC_CTL_LIMIT_1X	(0<<6)
787 #define   DPFC_CTL_LIMIT_2X	(1<<6)
788 #define   DPFC_CTL_LIMIT_4X	(2<<6)
789 #define DPFC_RECOMP_CTL		0x320c
790 #define   DPFC_RECOMP_STALL_EN	(1<<27)
791 #define   DPFC_RECOMP_STALL_WM_SHIFT (16)
792 #define   DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
793 #define   DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
794 #define   DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
795 #define DPFC_STATUS		0x3210
796 #define   DPFC_INVAL_SEG_SHIFT  (16)
797 #define   DPFC_INVAL_SEG_MASK	(0x07ff0000)
798 #define   DPFC_COMP_SEG_SHIFT	(0)
799 #define   DPFC_COMP_SEG_MASK	(0x000003ff)
800 #define DPFC_STATUS2		0x3214
801 #define DPFC_FENCE_YOFF		0x3218
802 #define DPFC_CHICKEN		0x3224
803 #define   DPFC_HT_MODIFY	(1<<31)
804 
805 /* Framebuffer compression for Ironlake */
806 #define ILK_DPFC_CB_BASE	0x43200
807 #define ILK_DPFC_CONTROL	0x43208
808 /* The bit 28-8 is reserved */
809 #define   DPFC_RESERVED		(0x1FFFFF00)
810 #define ILK_DPFC_RECOMP_CTL	0x4320c
811 #define ILK_DPFC_STATUS		0x43210
812 #define ILK_DPFC_FENCE_YOFF	0x43218
813 #define ILK_DPFC_CHICKEN	0x43224
814 #define ILK_FBC_RT_BASE		0x2128
815 #define   ILK_FBC_RT_VALID	(1<<0)
816 
817 #define ILK_DISPLAY_CHICKEN1	0x42000
818 #define   ILK_FBCQ_DIS		(1<<22)
819 #define	  ILK_PABSTRETCH_DIS	(1<<21)
820 
821 
822 /*
823  * Framebuffer compression for Sandybridge
824  *
825  * The following two registers are of type GTTMMADR
826  */
827 #define SNB_DPFC_CTL_SA		0x100100
828 #define   SNB_CPU_FENCE_ENABLE	(1<<29)
829 #define DPFC_CPU_FENCE_OFFSET	0x100104
830 
831 
832 /*
833  * GPIO regs
834  */
835 #define GPIOA			0x5010
836 #define GPIOB			0x5014
837 #define GPIOC			0x5018
838 #define GPIOD			0x501c
839 #define GPIOE			0x5020
840 #define GPIOF			0x5024
841 #define GPIOG			0x5028
842 #define GPIOH			0x502c
843 # define GPIO_CLOCK_DIR_MASK		(1 << 0)
844 # define GPIO_CLOCK_DIR_IN		(0 << 1)
845 # define GPIO_CLOCK_DIR_OUT		(1 << 1)
846 # define GPIO_CLOCK_VAL_MASK		(1 << 2)
847 # define GPIO_CLOCK_VAL_OUT		(1 << 3)
848 # define GPIO_CLOCK_VAL_IN		(1 << 4)
849 # define GPIO_CLOCK_PULLUP_DISABLE	(1 << 5)
850 # define GPIO_DATA_DIR_MASK		(1 << 8)
851 # define GPIO_DATA_DIR_IN		(0 << 9)
852 # define GPIO_DATA_DIR_OUT		(1 << 9)
853 # define GPIO_DATA_VAL_MASK		(1 << 10)
854 # define GPIO_DATA_VAL_OUT		(1 << 11)
855 # define GPIO_DATA_VAL_IN		(1 << 12)
856 # define GPIO_DATA_PULLUP_DISABLE	(1 << 13)
857 
858 #define GMBUS0			0x5100 /* clock/port select */
859 #define   GMBUS_RATE_100KHZ	(0<<8)
860 #define   GMBUS_RATE_50KHZ	(1<<8)
861 #define   GMBUS_RATE_400KHZ	(2<<8) /* reserved on Pineview */
862 #define   GMBUS_RATE_1MHZ	(3<<8) /* reserved on Pineview */
863 #define   GMBUS_HOLD_EXT	(1<<7) /* 300ns hold time, rsvd on Pineview */
864 #define   GMBUS_PORT_DISABLED	0
865 #define   GMBUS_PORT_SSC	1
866 #define   GMBUS_PORT_VGADDC	2
867 #define   GMBUS_PORT_PANEL	3
868 #define   GMBUS_PORT_DPC	4 /* HDMIC */
869 #define   GMBUS_PORT_DPB	5 /* SDVO, HDMIB */
870 #define   GMBUS_PORT_DPD	6 /* HDMID */
871 #define   GMBUS_PORT_RESERVED	7 /* 7 reserved */
872 #define   GMBUS_NUM_PORTS	(GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1)
873 #define GMBUS1			0x5104 /* command/status */
874 #define   GMBUS_SW_CLR_INT	(1<<31)
875 #define   GMBUS_SW_RDY		(1<<30)
876 #define   GMBUS_ENT		(1<<29) /* enable timeout */
877 #define   GMBUS_CYCLE_NONE	(0<<25)
878 #define   GMBUS_CYCLE_WAIT	(1<<25)
879 #define   GMBUS_CYCLE_INDEX	(2<<25)
880 #define   GMBUS_CYCLE_STOP	(4<<25)
881 #define   GMBUS_BYTE_COUNT_SHIFT 16
882 #define   GMBUS_SLAVE_INDEX_SHIFT 8
883 #define   GMBUS_SLAVE_ADDR_SHIFT 1
884 #define   GMBUS_SLAVE_READ	(1<<0)
885 #define   GMBUS_SLAVE_WRITE	(0<<0)
886 #define GMBUS2			0x5108 /* status */
887 #define   GMBUS_INUSE		(1<<15)
888 #define   GMBUS_HW_WAIT_PHASE	(1<<14)
889 #define   GMBUS_STALL_TIMEOUT	(1<<13)
890 #define   GMBUS_INT		(1<<12)
891 #define   GMBUS_HW_RDY		(1<<11)
892 #define   GMBUS_SATOER		(1<<10)
893 #define   GMBUS_ACTIVE		(1<<9)
894 #define GMBUS3			0x510c /* data buffer bytes 3-0 */
895 #define GMBUS4			0x5110 /* interrupt mask (Pineview+) */
896 #define   GMBUS_SLAVE_TIMEOUT_EN (1<<4)
897 #define   GMBUS_NAK_EN		(1<<3)
898 #define   GMBUS_IDLE_EN		(1<<2)
899 #define   GMBUS_HW_WAIT_EN	(1<<1)
900 #define   GMBUS_HW_RDY_EN	(1<<0)
901 #define GMBUS5			0x5120 /* byte index */
902 #define   GMBUS_2BYTE_INDEX_EN	(1<<31)
903 
904 /*
905  * Clock control & power management
906  */
907 
908 #define VGA0	0x6000
909 #define VGA1	0x6004
910 #define VGA_PD	0x6010
911 #define   VGA0_PD_P2_DIV_4	(1 << 7)
912 #define   VGA0_PD_P1_DIV_2	(1 << 5)
913 #define   VGA0_PD_P1_SHIFT	0
914 #define   VGA0_PD_P1_MASK	(0x1f << 0)
915 #define   VGA1_PD_P2_DIV_4	(1 << 15)
916 #define   VGA1_PD_P1_DIV_2	(1 << 13)
917 #define   VGA1_PD_P1_SHIFT	8
918 #define   VGA1_PD_P1_MASK	(0x1f << 8)
919 #define _DPLL_A	0x06014
920 #define _DPLL_B	0x06018
921 #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
922 #define   DPLL_VCO_ENABLE		(1 << 31)
923 #define   DPLL_DVO_HIGH_SPEED		(1 << 30)
924 #define   DPLL_EXT_BUFFER_ENABLE_VLV	(1 << 30)
925 #define   DPLL_SYNCLOCK_ENABLE		(1 << 29)
926 #define   DPLL_REFA_CLK_ENABLE_VLV	(1 << 29)
927 #define   DPLL_VGA_MODE_DIS		(1 << 28)
928 #define   DPLLB_MODE_DAC_SERIAL		(1 << 26) /* i915 */
929 #define   DPLLB_MODE_LVDS		(2 << 26) /* i915 */
930 #define   DPLL_MODE_MASK		(3 << 26)
931 #define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
932 #define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
933 #define   DPLLB_LVDS_P2_CLOCK_DIV_14	(0 << 24) /* i915 */
934 #define   DPLLB_LVDS_P2_CLOCK_DIV_7	(1 << 24) /* i915 */
935 #define   DPLL_P2_CLOCK_DIV_MASK	0x03000000 /* i915 */
936 #define   DPLL_FPA01_P1_POST_DIV_MASK	0x00ff0000 /* i915 */
937 #define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW	0x00ff8000 /* Pineview */
938 #define   DPLL_LOCK_VLV			(1<<15)
939 #define   DPLL_INTEGRATED_CLOCK_VLV	(1<<13)
940 
941 #define SRX_INDEX		0x3c4
942 #define SRX_DATA		0x3c5
943 #define SR01			1
944 #define SR01_SCREEN_OFF		(1<<5)
945 
946 #define PPCR			0x61204
947 #define PPCR_ON			(1<<0)
948 
949 #define DVOB			0x61140
950 #define DVOB_ON			(1<<31)
951 #define DVOC			0x61160
952 #define DVOC_ON			(1<<31)
953 #define LVDS			0x61180
954 #define LVDS_ON			(1<<31)
955 
956 /* Scratch pad debug 0 reg:
957  */
958 #define   DPLL_FPA01_P1_POST_DIV_MASK_I830	0x001f0000
959 /*
960  * The i830 generation, in LVDS mode, defines P1 as the bit number set within
961  * this field (only one bit may be set).
962  */
963 #define   DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS	0x003f0000
964 #define   DPLL_FPA01_P1_POST_DIV_SHIFT	16
965 #define   DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
966 /* i830, required in DVO non-gang */
967 #define   PLL_P2_DIVIDE_BY_4		(1 << 23)
968 #define   PLL_P1_DIVIDE_BY_TWO		(1 << 21) /* i830 */
969 #define   PLL_REF_INPUT_DREFCLK		(0 << 13)
970 #define   PLL_REF_INPUT_TVCLKINA	(1 << 13) /* i830 */
971 #define   PLL_REF_INPUT_TVCLKINBC	(2 << 13) /* SDVO TVCLKIN */
972 #define   PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
973 #define   PLL_REF_INPUT_MASK		(3 << 13)
974 #define   PLL_LOAD_PULSE_PHASE_SHIFT		9
975 /* Ironlake */
976 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT     9
977 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK      (7 << 9)
978 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x)	(((x)-1) << 9)
979 # define DPLL_FPA1_P1_POST_DIV_SHIFT            0
980 # define DPLL_FPA1_P1_POST_DIV_MASK             0xff
981 
982 /*
983  * Parallel to Serial Load Pulse phase selection.
984  * Selects the phase for the 10X DPLL clock for the PCIe
985  * digital display port. The range is 4 to 13; 10 or more
986  * is just a flip delay. The default is 6
987  */
988 #define   PLL_LOAD_PULSE_PHASE_MASK		(0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
989 #define   DISPLAY_RATE_SELECT_FPA1		(1 << 8)
990 /*
991  * SDVO multiplier for 945G/GM. Not used on 965.
992  */
993 #define   SDVO_MULTIPLIER_MASK			0x000000ff
994 #define   SDVO_MULTIPLIER_SHIFT_HIRES		4
995 #define   SDVO_MULTIPLIER_SHIFT_VGA		0
996 #define _DPLL_A_MD 0x0601c /* 965+ only */
997 /*
998  * UDI pixel divider, controlling how many pixels are stuffed into a packet.
999  *
1000  * Value is pixels minus 1.  Must be set to 1 pixel for SDVO.
1001  */
1002 #define   DPLL_MD_UDI_DIVIDER_MASK		0x3f000000
1003 #define   DPLL_MD_UDI_DIVIDER_SHIFT		24
1004 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
1005 #define   DPLL_MD_VGA_UDI_DIVIDER_MASK		0x003f0000
1006 #define   DPLL_MD_VGA_UDI_DIVIDER_SHIFT		16
1007 /*
1008  * SDVO/UDI pixel multiplier.
1009  *
1010  * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
1011  * clock rate is 10 times the DPLL clock.  At low resolution/refresh rate
1012  * modes, the bus rate would be below the limits, so SDVO allows for stuffing
1013  * dummy bytes in the datastream at an increased clock rate, with both sides of
1014  * the link knowing how many bytes are fill.
1015  *
1016  * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
1017  * rate to 130Mhz to get a bus rate of 1.30Ghz.  The DPLL clock rate would be
1018  * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
1019  * through an SDVO command.
1020  *
1021  * This register field has values of multiplication factor minus 1, with
1022  * a maximum multiplier of 5 for SDVO.
1023  */
1024 #define   DPLL_MD_UDI_MULTIPLIER_MASK		0x00003f00
1025 #define   DPLL_MD_UDI_MULTIPLIER_SHIFT		8
1026 /*
1027  * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
1028  * This best be set to the default value (3) or the CRT won't work. No,
1029  * I don't entirely understand what this does...
1030  */
1031 #define   DPLL_MD_VGA_UDI_MULTIPLIER_MASK	0x0000003f
1032 #define   DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT	0
1033 #define _DPLL_B_MD 0x06020 /* 965+ only */
1034 #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
1035 
1036 #define _FPA0	0x06040
1037 #define _FPA1	0x06044
1038 #define _FPB0	0x06048
1039 #define _FPB1	0x0604c
1040 #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
1041 #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
1042 #define   FP_N_DIV_MASK		0x003f0000
1043 #define   FP_N_PINEVIEW_DIV_MASK	0x00ff0000
1044 #define   FP_N_DIV_SHIFT		16
1045 #define   FP_M1_DIV_MASK	0x00003f00
1046 #define   FP_M1_DIV_SHIFT		 8
1047 #define   FP_M2_DIV_MASK	0x0000003f
1048 #define   FP_M2_PINEVIEW_DIV_MASK	0x000000ff
1049 #define   FP_M2_DIV_SHIFT		 0
1050 #define DPLL_TEST	0x606c
1051 #define   DPLLB_TEST_SDVO_DIV_1		(0 << 22)
1052 #define   DPLLB_TEST_SDVO_DIV_2		(1 << 22)
1053 #define   DPLLB_TEST_SDVO_DIV_4		(2 << 22)
1054 #define   DPLLB_TEST_SDVO_DIV_MASK	(3 << 22)
1055 #define   DPLLB_TEST_N_BYPASS		(1 << 19)
1056 #define   DPLLB_TEST_M_BYPASS		(1 << 18)
1057 #define   DPLLB_INPUT_BUFFER_ENABLE	(1 << 16)
1058 #define   DPLLA_TEST_N_BYPASS		(1 << 3)
1059 #define   DPLLA_TEST_M_BYPASS		(1 << 2)
1060 #define   DPLLA_INPUT_BUFFER_ENABLE	(1 << 0)
1061 #define D_STATE		0x6104
1062 #define  DSTATE_GFX_RESET_I830			(1<<6)
1063 #define  DSTATE_PLL_D3_OFF			(1<<3)
1064 #define  DSTATE_GFX_CLOCK_GATING		(1<<1)
1065 #define  DSTATE_DOT_CLOCK_GATING		(1<<0)
1066 #define DSPCLK_GATE_D		0x6200
1067 # define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */
1068 # define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */
1069 # define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */
1070 # define VRDUNIT_CLOCK_GATE_DISABLE		(1 << 27) /* 965 */
1071 # define AUDUNIT_CLOCK_GATE_DISABLE		(1 << 26) /* 965 */
1072 # define DPUNIT_A_CLOCK_GATE_DISABLE		(1 << 25) /* 965 */
1073 # define DPCUNIT_CLOCK_GATE_DISABLE		(1 << 24) /* 965 */
1074 # define TVRUNIT_CLOCK_GATE_DISABLE		(1 << 23) /* 915-945 */
1075 # define TVCUNIT_CLOCK_GATE_DISABLE		(1 << 22) /* 915-945 */
1076 # define TVFUNIT_CLOCK_GATE_DISABLE		(1 << 21) /* 915-945 */
1077 # define TVEUNIT_CLOCK_GATE_DISABLE		(1 << 20) /* 915-945 */
1078 # define DVSUNIT_CLOCK_GATE_DISABLE		(1 << 19) /* 915-945 */
1079 # define DSSUNIT_CLOCK_GATE_DISABLE		(1 << 18) /* 915-945 */
1080 # define DDBUNIT_CLOCK_GATE_DISABLE		(1 << 17) /* 915-945 */
1081 # define DPRUNIT_CLOCK_GATE_DISABLE		(1 << 16) /* 915-945 */
1082 # define DPFUNIT_CLOCK_GATE_DISABLE		(1 << 15) /* 915-945 */
1083 # define DPBMUNIT_CLOCK_GATE_DISABLE		(1 << 14) /* 915-945 */
1084 # define DPLSUNIT_CLOCK_GATE_DISABLE		(1 << 13) /* 915-945 */
1085 # define DPLUNIT_CLOCK_GATE_DISABLE		(1 << 12) /* 915-945 */
1086 # define DPOUNIT_CLOCK_GATE_DISABLE		(1 << 11)
1087 # define DPBUNIT_CLOCK_GATE_DISABLE		(1 << 10)
1088 # define DCUNIT_CLOCK_GATE_DISABLE		(1 << 9)
1089 # define DPUNIT_CLOCK_GATE_DISABLE		(1 << 8)
1090 # define VRUNIT_CLOCK_GATE_DISABLE		(1 << 7) /* 915+: reserved */
1091 # define OVHUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 830-865 */
1092 # define DPIOUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 915-945 */
1093 # define OVFUNIT_CLOCK_GATE_DISABLE		(1 << 5)
1094 # define OVBUNIT_CLOCK_GATE_DISABLE		(1 << 4)
1095 /**
1096  * This bit must be set on the 830 to prevent hangs when turning off the
1097  * overlay scaler.
1098  */
1099 # define OVRUNIT_CLOCK_GATE_DISABLE		(1 << 3)
1100 # define OVCUNIT_CLOCK_GATE_DISABLE		(1 << 2)
1101 # define OVUUNIT_CLOCK_GATE_DISABLE		(1 << 1)
1102 # define ZVUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 830 */
1103 # define OVLUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 845,865 */
1104 
1105 #define RENCLK_GATE_D1		0x6204
1106 # define BLITTER_CLOCK_GATE_DISABLE		(1 << 13) /* 945GM only */
1107 # define MPEG_CLOCK_GATE_DISABLE		(1 << 12) /* 945GM only */
1108 # define PC_FE_CLOCK_GATE_DISABLE		(1 << 11)
1109 # define PC_BE_CLOCK_GATE_DISABLE		(1 << 10)
1110 # define WINDOWER_CLOCK_GATE_DISABLE		(1 << 9)
1111 # define INTERPOLATOR_CLOCK_GATE_DISABLE	(1 << 8)
1112 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE	(1 << 7)
1113 # define MOTION_COMP_CLOCK_GATE_DISABLE		(1 << 6)
1114 # define MAG_CLOCK_GATE_DISABLE			(1 << 5)
1115 /** This bit must be unset on 855,865 */
1116 # define MECI_CLOCK_GATE_DISABLE		(1 << 4)
1117 # define DCMP_CLOCK_GATE_DISABLE		(1 << 3)
1118 # define MEC_CLOCK_GATE_DISABLE			(1 << 2)
1119 # define MECO_CLOCK_GATE_DISABLE		(1 << 1)
1120 /** This bit must be set on 855,865. */
1121 # define SV_CLOCK_GATE_DISABLE			(1 << 0)
1122 # define I915_MPEG_CLOCK_GATE_DISABLE		(1 << 16)
1123 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE	(1 << 15)
1124 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE	(1 << 14)
1125 # define I915_BD_BF_CLOCK_GATE_DISABLE		(1 << 13)
1126 # define I915_SF_SE_CLOCK_GATE_DISABLE		(1 << 12)
1127 # define I915_WM_CLOCK_GATE_DISABLE		(1 << 11)
1128 # define I915_IZ_CLOCK_GATE_DISABLE		(1 << 10)
1129 # define I915_PI_CLOCK_GATE_DISABLE		(1 << 9)
1130 # define I915_DI_CLOCK_GATE_DISABLE		(1 << 8)
1131 # define I915_SH_SV_CLOCK_GATE_DISABLE		(1 << 7)
1132 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE	(1 << 6)
1133 # define I915_SC_CLOCK_GATE_DISABLE		(1 << 5)
1134 # define I915_FL_CLOCK_GATE_DISABLE		(1 << 4)
1135 # define I915_DM_CLOCK_GATE_DISABLE		(1 << 3)
1136 # define I915_PS_CLOCK_GATE_DISABLE		(1 << 2)
1137 # define I915_CC_CLOCK_GATE_DISABLE		(1 << 1)
1138 # define I915_BY_CLOCK_GATE_DISABLE		(1 << 0)
1139 
1140 # define I965_RCZ_CLOCK_GATE_DISABLE		(1 << 30)
1141 /** This bit must always be set on 965G/965GM */
1142 # define I965_RCC_CLOCK_GATE_DISABLE		(1 << 29)
1143 # define I965_RCPB_CLOCK_GATE_DISABLE		(1 << 28)
1144 # define I965_DAP_CLOCK_GATE_DISABLE		(1 << 27)
1145 # define I965_ROC_CLOCK_GATE_DISABLE		(1 << 26)
1146 # define I965_GW_CLOCK_GATE_DISABLE		(1 << 25)
1147 # define I965_TD_CLOCK_GATE_DISABLE		(1 << 24)
1148 /** This bit must always be set on 965G */
1149 # define I965_ISC_CLOCK_GATE_DISABLE		(1 << 23)
1150 # define I965_IC_CLOCK_GATE_DISABLE		(1 << 22)
1151 # define I965_EU_CLOCK_GATE_DISABLE		(1 << 21)
1152 # define I965_IF_CLOCK_GATE_DISABLE		(1 << 20)
1153 # define I965_TC_CLOCK_GATE_DISABLE		(1 << 19)
1154 # define I965_SO_CLOCK_GATE_DISABLE		(1 << 17)
1155 # define I965_FBC_CLOCK_GATE_DISABLE		(1 << 16)
1156 # define I965_MARI_CLOCK_GATE_DISABLE		(1 << 15)
1157 # define I965_MASF_CLOCK_GATE_DISABLE		(1 << 14)
1158 # define I965_MAWB_CLOCK_GATE_DISABLE		(1 << 13)
1159 # define I965_EM_CLOCK_GATE_DISABLE		(1 << 12)
1160 # define I965_UC_CLOCK_GATE_DISABLE		(1 << 11)
1161 # define I965_SI_CLOCK_GATE_DISABLE		(1 << 6)
1162 # define I965_MT_CLOCK_GATE_DISABLE		(1 << 5)
1163 # define I965_PL_CLOCK_GATE_DISABLE		(1 << 4)
1164 # define I965_DG_CLOCK_GATE_DISABLE		(1 << 3)
1165 # define I965_QC_CLOCK_GATE_DISABLE		(1 << 2)
1166 # define I965_FT_CLOCK_GATE_DISABLE		(1 << 1)
1167 # define I965_DM_CLOCK_GATE_DISABLE		(1 << 0)
1168 
1169 #define RENCLK_GATE_D2		0x6208
1170 #define VF_UNIT_CLOCK_GATE_DISABLE		(1 << 9)
1171 #define GS_UNIT_CLOCK_GATE_DISABLE		(1 << 7)
1172 #define CL_UNIT_CLOCK_GATE_DISABLE		(1 << 6)
1173 #define RAMCLK_GATE_D		0x6210		/* CRL only */
1174 #define DEUC			0x6214          /* CRL only */
1175 
1176 #define FW_BLC_SELF_VLV		0x6500
1177 #define  FW_CSPWRDWNEN		(1<<15)
1178 
1179 /*
1180  * Palette regs
1181  */
1182 
1183 #define _PALETTE_A		0x0a000
1184 #define _PALETTE_B		0x0a800
1185 #define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
1186 
1187 /* MCH MMIO space */
1188 
1189 /*
1190  * MCHBAR mirror.
1191  *
1192  * This mirrors the MCHBAR MMIO space whose location is determined by
1193  * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
1194  * every way.  It is not accessible from the CP register read instructions.
1195  *
1196  */
1197 #define MCHBAR_MIRROR_BASE	0x10000
1198 
1199 #define MCHBAR_MIRROR_BASE_SNB	0x140000
1200 
1201 /** 915-945 and GM965 MCH register controlling DRAM channel access */
1202 #define DCC			0x10200
1203 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL		(0 << 0)
1204 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC	(1 << 0)
1205 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED	(2 << 0)
1206 #define DCC_ADDRESSING_MODE_MASK			(3 << 0)
1207 #define DCC_CHANNEL_XOR_DISABLE				(1 << 10)
1208 #define DCC_CHANNEL_XOR_BIT_17				(1 << 9)
1209 
1210 /** Pineview MCH register contains DDR3 setting */
1211 #define CSHRDDR3CTL            0x101a8
1212 #define CSHRDDR3CTL_DDR3       (1 << 2)
1213 
1214 /** 965 MCH register controlling DRAM channel configuration */
1215 #define C0DRB3			0x10206
1216 #define C1DRB3			0x10606
1217 
1218 /** snb MCH registers for reading the DRAM channel configuration */
1219 #define MAD_DIMM_C0			(MCHBAR_MIRROR_BASE_SNB + 0x5004)
1220 #define MAD_DIMM_C1			(MCHBAR_MIRROR_BASE_SNB + 0x5008)
1221 #define MAD_DIMM_C2			(MCHBAR_MIRROR_BASE_SNB + 0x500C)
1222 #define   MAD_DIMM_ECC_MASK		(0x3 << 24)
1223 #define   MAD_DIMM_ECC_OFF		(0x0 << 24)
1224 #define   MAD_DIMM_ECC_IO_ON_LOGIC_OFF	(0x1 << 24)
1225 #define   MAD_DIMM_ECC_IO_OFF_LOGIC_ON	(0x2 << 24)
1226 #define   MAD_DIMM_ECC_ON		(0x3 << 24)
1227 #define   MAD_DIMM_ENH_INTERLEAVE	(0x1 << 22)
1228 #define   MAD_DIMM_RANK_INTERLEAVE	(0x1 << 21)
1229 #define   MAD_DIMM_B_WIDTH_X16		(0x1 << 20) /* X8 chips if unset */
1230 #define   MAD_DIMM_A_WIDTH_X16		(0x1 << 19) /* X8 chips if unset */
1231 #define   MAD_DIMM_B_DUAL_RANK		(0x1 << 18)
1232 #define   MAD_DIMM_A_DUAL_RANK		(0x1 << 17)
1233 #define   MAD_DIMM_A_SELECT		(0x1 << 16)
1234 /* DIMM sizes are in multiples of 256mb. */
1235 #define   MAD_DIMM_B_SIZE_SHIFT		8
1236 #define   MAD_DIMM_B_SIZE_MASK		(0xff << MAD_DIMM_B_SIZE_SHIFT)
1237 #define   MAD_DIMM_A_SIZE_SHIFT		0
1238 #define   MAD_DIMM_A_SIZE_MASK		(0xff << MAD_DIMM_A_SIZE_SHIFT)
1239 
1240 
1241 /* Clocking configuration register */
1242 #define CLKCFG			0x10c00
1243 #define CLKCFG_FSB_400					(5 << 0)	/* hrawclk 100 */
1244 #define CLKCFG_FSB_533					(1 << 0)	/* hrawclk 133 */
1245 #define CLKCFG_FSB_667					(3 << 0)	/* hrawclk 166 */
1246 #define CLKCFG_FSB_800					(2 << 0)	/* hrawclk 200 */
1247 #define CLKCFG_FSB_1067					(6 << 0)	/* hrawclk 266 */
1248 #define CLKCFG_FSB_1333					(7 << 0)	/* hrawclk 333 */
1249 /* Note, below two are guess */
1250 #define CLKCFG_FSB_1600					(4 << 0)	/* hrawclk 400 */
1251 #define CLKCFG_FSB_1600_ALT				(0 << 0)	/* hrawclk 400 */
1252 #define CLKCFG_FSB_MASK					(7 << 0)
1253 #define CLKCFG_MEM_533					(1 << 4)
1254 #define CLKCFG_MEM_667					(2 << 4)
1255 #define CLKCFG_MEM_800					(3 << 4)
1256 #define CLKCFG_MEM_MASK					(7 << 4)
1257 
1258 #define TSC1			0x11001
1259 #define   TSE			(1<<0)
1260 #define TR1			0x11006
1261 #define TSFS			0x11020
1262 #define   TSFS_SLOPE_MASK	0x0000ff00
1263 #define   TSFS_SLOPE_SHIFT	8
1264 #define   TSFS_INTR_MASK	0x000000ff
1265 
1266 #define CRSTANDVID		0x11100
1267 #define PXVFREQ_BASE		0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
1268 #define   PXVFREQ_PX_MASK	0x7f000000
1269 #define   PXVFREQ_PX_SHIFT	24
1270 #define VIDFREQ_BASE		0x11110
1271 #define VIDFREQ1		0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
1272 #define VIDFREQ2		0x11114
1273 #define VIDFREQ3		0x11118
1274 #define VIDFREQ4		0x1111c
1275 #define   VIDFREQ_P0_MASK	0x1f000000
1276 #define   VIDFREQ_P0_SHIFT	24
1277 #define   VIDFREQ_P0_CSCLK_MASK	0x00f00000
1278 #define   VIDFREQ_P0_CSCLK_SHIFT 20
1279 #define   VIDFREQ_P0_CRCLK_MASK	0x000f0000
1280 #define   VIDFREQ_P0_CRCLK_SHIFT 16
1281 #define   VIDFREQ_P1_MASK	0x00001f00
1282 #define   VIDFREQ_P1_SHIFT	8
1283 #define   VIDFREQ_P1_CSCLK_MASK	0x000000f0
1284 #define   VIDFREQ_P1_CSCLK_SHIFT 4
1285 #define   VIDFREQ_P1_CRCLK_MASK	0x0000000f
1286 #define INTTOEXT_BASE_ILK	0x11300
1287 #define INTTOEXT_BASE		0x11120 /* INTTOEXT1-8 (0x1113c) */
1288 #define   INTTOEXT_MAP3_SHIFT	24
1289 #define   INTTOEXT_MAP3_MASK	(0x1f << INTTOEXT_MAP3_SHIFT)
1290 #define   INTTOEXT_MAP2_SHIFT	16
1291 #define   INTTOEXT_MAP2_MASK	(0x1f << INTTOEXT_MAP2_SHIFT)
1292 #define   INTTOEXT_MAP1_SHIFT	8
1293 #define   INTTOEXT_MAP1_MASK	(0x1f << INTTOEXT_MAP1_SHIFT)
1294 #define   INTTOEXT_MAP0_SHIFT	0
1295 #define   INTTOEXT_MAP0_MASK	(0x1f << INTTOEXT_MAP0_SHIFT)
1296 #define MEMSWCTL		0x11170 /* Ironlake only */
1297 #define   MEMCTL_CMD_MASK	0xe000
1298 #define   MEMCTL_CMD_SHIFT	13
1299 #define   MEMCTL_CMD_RCLK_OFF	0
1300 #define   MEMCTL_CMD_RCLK_ON	1
1301 #define   MEMCTL_CMD_CHFREQ	2
1302 #define   MEMCTL_CMD_CHVID	3
1303 #define   MEMCTL_CMD_VMMOFF	4
1304 #define   MEMCTL_CMD_VMMON	5
1305 #define   MEMCTL_CMD_STS	(1<<12) /* write 1 triggers command, clears
1306 					   when command complete */
1307 #define   MEMCTL_FREQ_MASK	0x0f00 /* jitter, from 0-15 */
1308 #define   MEMCTL_FREQ_SHIFT	8
1309 #define   MEMCTL_SFCAVM		(1<<7)
1310 #define   MEMCTL_TGT_VID_MASK	0x007f
1311 #define MEMIHYST		0x1117c
1312 #define MEMINTREN		0x11180 /* 16 bits */
1313 #define   MEMINT_RSEXIT_EN	(1<<8)
1314 #define   MEMINT_CX_SUPR_EN	(1<<7)
1315 #define   MEMINT_CONT_BUSY_EN	(1<<6)
1316 #define   MEMINT_AVG_BUSY_EN	(1<<5)
1317 #define   MEMINT_EVAL_CHG_EN	(1<<4)
1318 #define   MEMINT_MON_IDLE_EN	(1<<3)
1319 #define   MEMINT_UP_EVAL_EN	(1<<2)
1320 #define   MEMINT_DOWN_EVAL_EN	(1<<1)
1321 #define   MEMINT_SW_CMD_EN	(1<<0)
1322 #define MEMINTRSTR		0x11182 /* 16 bits */
1323 #define   MEM_RSEXIT_MASK	0xc000
1324 #define   MEM_RSEXIT_SHIFT	14
1325 #define   MEM_CONT_BUSY_MASK	0x3000
1326 #define   MEM_CONT_BUSY_SHIFT	12
1327 #define   MEM_AVG_BUSY_MASK	0x0c00
1328 #define   MEM_AVG_BUSY_SHIFT	10
1329 #define   MEM_EVAL_CHG_MASK	0x0300
1330 #define   MEM_EVAL_BUSY_SHIFT	8
1331 #define   MEM_MON_IDLE_MASK	0x00c0
1332 #define   MEM_MON_IDLE_SHIFT	6
1333 #define   MEM_UP_EVAL_MASK	0x0030
1334 #define   MEM_UP_EVAL_SHIFT	4
1335 #define   MEM_DOWN_EVAL_MASK	0x000c
1336 #define   MEM_DOWN_EVAL_SHIFT	2
1337 #define   MEM_SW_CMD_MASK	0x0003
1338 #define   MEM_INT_STEER_GFX	0
1339 #define   MEM_INT_STEER_CMR	1
1340 #define   MEM_INT_STEER_SMI	2
1341 #define   MEM_INT_STEER_SCI	3
1342 #define MEMINTRSTS		0x11184
1343 #define   MEMINT_RSEXIT		(1<<7)
1344 #define   MEMINT_CONT_BUSY	(1<<6)
1345 #define   MEMINT_AVG_BUSY	(1<<5)
1346 #define   MEMINT_EVAL_CHG	(1<<4)
1347 #define   MEMINT_MON_IDLE	(1<<3)
1348 #define   MEMINT_UP_EVAL	(1<<2)
1349 #define   MEMINT_DOWN_EVAL	(1<<1)
1350 #define   MEMINT_SW_CMD		(1<<0)
1351 #define MEMMODECTL		0x11190
1352 #define   MEMMODE_BOOST_EN	(1<<31)
1353 #define   MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
1354 #define   MEMMODE_BOOST_FREQ_SHIFT 24
1355 #define   MEMMODE_IDLE_MODE_MASK 0x00030000
1356 #define   MEMMODE_IDLE_MODE_SHIFT 16
1357 #define   MEMMODE_IDLE_MODE_EVAL 0
1358 #define   MEMMODE_IDLE_MODE_CONT 1
1359 #define   MEMMODE_HWIDLE_EN	(1<<15)
1360 #define   MEMMODE_SWMODE_EN	(1<<14)
1361 #define   MEMMODE_RCLK_GATE	(1<<13)
1362 #define   MEMMODE_HW_UPDATE	(1<<12)
1363 #define   MEMMODE_FSTART_MASK	0x00000f00 /* starting jitter, 0-15 */
1364 #define   MEMMODE_FSTART_SHIFT	8
1365 #define   MEMMODE_FMAX_MASK	0x000000f0 /* max jitter, 0-15 */
1366 #define   MEMMODE_FMAX_SHIFT	4
1367 #define   MEMMODE_FMIN_MASK	0x0000000f /* min jitter, 0-15 */
1368 #define RCBMAXAVG		0x1119c
1369 #define MEMSWCTL2		0x1119e /* Cantiga only */
1370 #define   SWMEMCMD_RENDER_OFF	(0 << 13)
1371 #define   SWMEMCMD_RENDER_ON	(1 << 13)
1372 #define   SWMEMCMD_SWFREQ	(2 << 13)
1373 #define   SWMEMCMD_TARVID	(3 << 13)
1374 #define   SWMEMCMD_VRM_OFF	(4 << 13)
1375 #define   SWMEMCMD_VRM_ON	(5 << 13)
1376 #define   CMDSTS		(1<<12)
1377 #define   SFCAVM		(1<<11)
1378 #define   SWFREQ_MASK		0x0380 /* P0-7 */
1379 #define   SWFREQ_SHIFT		7
1380 #define   TARVID_MASK		0x001f
1381 #define MEMSTAT_CTG		0x111a0
1382 #define RCBMINAVG		0x111a0
1383 #define RCUPEI			0x111b0
1384 #define RCDNEI			0x111b4
1385 #define RSTDBYCTL		0x111b8
1386 #define   RS1EN			(1<<31)
1387 #define   RS2EN			(1<<30)
1388 #define   RS3EN			(1<<29)
1389 #define   D3RS3EN		(1<<28) /* Display D3 imlies RS3 */
1390 #define   SWPROMORSX		(1<<27) /* RSx promotion timers ignored */
1391 #define   RCWAKERW		(1<<26) /* Resetwarn from PCH causes wakeup */
1392 #define   DPRSLPVREN		(1<<25) /* Fast voltage ramp enable */
1393 #define   GFXTGHYST		(1<<24) /* Hysteresis to allow trunk gating */
1394 #define   RCX_SW_EXIT		(1<<23) /* Leave RSx and prevent re-entry */
1395 #define   RSX_STATUS_MASK	(7<<20)
1396 #define   RSX_STATUS_ON		(0<<20)
1397 #define   RSX_STATUS_RC1	(1<<20)
1398 #define   RSX_STATUS_RC1E	(2<<20)
1399 #define   RSX_STATUS_RS1	(3<<20)
1400 #define   RSX_STATUS_RS2	(4<<20) /* aka rc6 */
1401 #define   RSX_STATUS_RSVD	(5<<20) /* deep rc6 unsupported on ilk */
1402 #define   RSX_STATUS_RS3	(6<<20) /* rs3 unsupported on ilk */
1403 #define   RSX_STATUS_RSVD2	(7<<20)
1404 #define   UWRCRSXE		(1<<19) /* wake counter limit prevents rsx */
1405 #define   RSCRP			(1<<18) /* rs requests control on rs1/2 reqs */
1406 #define   JRSC			(1<<17) /* rsx coupled to cpu c-state */
1407 #define   RS2INC0		(1<<16) /* allow rs2 in cpu c0 */
1408 #define   RS1CONTSAV_MASK	(3<<14)
1409 #define   RS1CONTSAV_NO_RS1	(0<<14) /* rs1 doesn't save/restore context */
1410 #define   RS1CONTSAV_RSVD	(1<<14)
1411 #define   RS1CONTSAV_SAVE_RS1	(2<<14) /* rs1 saves context */
1412 #define   RS1CONTSAV_FULL_RS1	(3<<14) /* rs1 saves and restores context */
1413 #define   NORMSLEXLAT_MASK	(3<<12)
1414 #define   SLOW_RS123		(0<<12)
1415 #define   SLOW_RS23		(1<<12)
1416 #define   SLOW_RS3		(2<<12)
1417 #define   NORMAL_RS123		(3<<12)
1418 #define   RCMODE_TIMEOUT	(1<<11) /* 0 is eval interval method */
1419 #define   IMPROMOEN		(1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
1420 #define   RCENTSYNC		(1<<9) /* rs coupled to cpu c-state (3/6/7) */
1421 #define   STATELOCK		(1<<7) /* locked to rs_cstate if 0 */
1422 #define   RS_CSTATE_MASK	(3<<4)
1423 #define   RS_CSTATE_C367_RS1	(0<<4)
1424 #define   RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
1425 #define   RS_CSTATE_RSVD	(2<<4)
1426 #define   RS_CSTATE_C367_RS2	(3<<4)
1427 #define   REDSAVES		(1<<3) /* no context save if was idle during rs0 */
1428 #define   REDRESTORES		(1<<2) /* no restore if was idle during rs0 */
1429 #define VIDCTL			0x111c0
1430 #define VIDSTS			0x111c8
1431 #define VIDSTART		0x111cc /* 8 bits */
1432 #define MEMSTAT_ILK			0x111f8
1433 #define   MEMSTAT_VID_MASK	0x7f00
1434 #define   MEMSTAT_VID_SHIFT	8
1435 #define   MEMSTAT_PSTATE_MASK	0x00f8
1436 #define   MEMSTAT_PSTATE_SHIFT  3
1437 #define   MEMSTAT_MON_ACTV	(1<<2)
1438 #define   MEMSTAT_SRC_CTL_MASK	0x0003
1439 #define   MEMSTAT_SRC_CTL_CORE	0
1440 #define   MEMSTAT_SRC_CTL_TRB	1
1441 #define   MEMSTAT_SRC_CTL_THM	2
1442 #define   MEMSTAT_SRC_CTL_STDBY 3
1443 #define RCPREVBSYTUPAVG		0x113b8
1444 #define RCPREVBSYTDNAVG		0x113bc
1445 #define PMMISC			0x11214
1446 #define   MCPPCE_EN		(1<<0) /* enable PM_MSG from PCH->MPC */
1447 #define SDEW			0x1124c
1448 #define CSIEW0			0x11250
1449 #define CSIEW1			0x11254
1450 #define CSIEW2			0x11258
1451 #define PEW			0x1125c
1452 #define DEW			0x11270
1453 #define MCHAFE			0x112c0
1454 #define CSIEC			0x112e0
1455 #define DMIEC			0x112e4
1456 #define DDREC			0x112e8
1457 #define PEG0EC			0x112ec
1458 #define PEG1EC			0x112f0
1459 #define GFXEC			0x112f4
1460 #define RPPREVBSYTUPAVG		0x113b8
1461 #define RPPREVBSYTDNAVG		0x113bc
1462 #define ECR			0x11600
1463 #define   ECR_GPFE		(1<<31)
1464 #define   ECR_IMONE		(1<<30)
1465 #define   ECR_CAP_MASK		0x0000001f /* Event range, 0-31 */
1466 #define OGW0			0x11608
1467 #define OGW1			0x1160c
1468 #define EG0			0x11610
1469 #define EG1			0x11614
1470 #define EG2			0x11618
1471 #define EG3			0x1161c
1472 #define EG4			0x11620
1473 #define EG5			0x11624
1474 #define EG6			0x11628
1475 #define EG7			0x1162c
1476 #define PXW			0x11664
1477 #define PXWL			0x11680
1478 #define LCFUSE02		0x116c0
1479 #define   LCFUSE_HIV_MASK	0x000000ff
1480 #define CSIPLL0			0x12c10
1481 #define DDRMPLL1		0X12c20
1482 #define PEG_BAND_GAP_DATA	0x14d68
1483 
1484 #define GEN6_GT_THREAD_STATUS_REG 0x13805c
1485 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
1486 #define GEN6_GT_THREAD_STATUS_CORE_MASK_HSW (0x7 | (0x07 << 16))
1487 
1488 #define GEN6_GT_PERF_STATUS	0x145948
1489 #define GEN6_RP_STATE_LIMITS	0x145994
1490 #define GEN6_RP_STATE_CAP	0x145998
1491 
1492 /*
1493  * Logical Context regs
1494  */
1495 #define CCID			0x2180
1496 #define   CCID_EN		(1<<0)
1497 #define CXT_SIZE		0x21a0
1498 #define GEN6_CXT_POWER_SIZE(cxt_reg)	((cxt_reg >> 24) & 0x3f)
1499 #define GEN6_CXT_RING_SIZE(cxt_reg)	((cxt_reg >> 18) & 0x3f)
1500 #define GEN6_CXT_RENDER_SIZE(cxt_reg)	((cxt_reg >> 12) & 0x3f)
1501 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg)	((cxt_reg >> 6) & 0x3f)
1502 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg)	((cxt_reg >> 0) & 0x3f)
1503 #define GEN6_CXT_TOTAL_SIZE(cxt_reg)	(GEN6_CXT_POWER_SIZE(cxt_reg) + \
1504 					GEN6_CXT_RING_SIZE(cxt_reg) + \
1505 					GEN6_CXT_RENDER_SIZE(cxt_reg) + \
1506 					GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
1507 					GEN6_CXT_PIPELINE_SIZE(cxt_reg))
1508 #define GEN7_CXT_SIZE		0x21a8
1509 #define GEN7_CXT_POWER_SIZE(ctx_reg)	((ctx_reg >> 25) & 0x7f)
1510 #define GEN7_CXT_RING_SIZE(ctx_reg)	((ctx_reg >> 22) & 0x7)
1511 #define GEN7_CXT_RENDER_SIZE(ctx_reg)	((ctx_reg >> 16) & 0x3f)
1512 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg)	((ctx_reg >> 9) & 0x7f)
1513 #define GEN7_CXT_GT1_SIZE(ctx_reg)	((ctx_reg >> 6) & 0x7)
1514 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg)	((ctx_reg >> 0) & 0x3f)
1515 #define GEN7_CXT_TOTAL_SIZE(ctx_reg)	(GEN7_CXT_POWER_SIZE(ctx_reg) + \
1516 					 GEN7_CXT_RING_SIZE(ctx_reg) + \
1517 					 GEN7_CXT_RENDER_SIZE(ctx_reg) + \
1518 					 GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
1519 					 GEN7_CXT_GT1_SIZE(ctx_reg) + \
1520 					 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
1521 #define HSW_CXT_POWER_SIZE(ctx_reg)	((ctx_reg >> 26) & 0x3f)
1522 #define HSW_CXT_RING_SIZE(ctx_reg)	((ctx_reg >> 23) & 0x7)
1523 #define HSW_CXT_RENDER_SIZE(ctx_reg)	((ctx_reg >> 15) & 0xff)
1524 #define HSW_CXT_TOTAL_SIZE(ctx_reg)	(HSW_CXT_POWER_SIZE(ctx_reg) + \
1525 					 HSW_CXT_RING_SIZE(ctx_reg) + \
1526 					 HSW_CXT_RENDER_SIZE(ctx_reg) + \
1527 					 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
1528 
1529 
1530 /*
1531  * Overlay regs
1532  */
1533 
1534 #define OVADD			0x30000
1535 #define DOVSTA			0x30008
1536 #define OC_BUF			(0x3<<20)
1537 #define OGAMC5			0x30010
1538 #define OGAMC4			0x30014
1539 #define OGAMC3			0x30018
1540 #define OGAMC2			0x3001c
1541 #define OGAMC1			0x30020
1542 #define OGAMC0			0x30024
1543 
1544 /*
1545  * Display engine regs
1546  */
1547 
1548 /* Pipe A timing regs */
1549 #define _HTOTAL_A	0x60000
1550 #define _HBLANK_A	0x60004
1551 #define _HSYNC_A		0x60008
1552 #define _VTOTAL_A	0x6000c
1553 #define _VBLANK_A	0x60010
1554 #define _VSYNC_A		0x60014
1555 #define _PIPEASRC	0x6001c
1556 #define _BCLRPAT_A	0x60020
1557 #define _VSYNCSHIFT_A	0x60028
1558 
1559 /* Pipe B timing regs */
1560 #define _HTOTAL_B	0x61000
1561 #define _HBLANK_B	0x61004
1562 #define _HSYNC_B		0x61008
1563 #define _VTOTAL_B	0x6100c
1564 #define _VBLANK_B	0x61010
1565 #define _VSYNC_B		0x61014
1566 #define _PIPEBSRC	0x6101c
1567 #define _BCLRPAT_B	0x61020
1568 #define _VSYNCSHIFT_B	0x61028
1569 
1570 
1571 #define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B)
1572 #define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B)
1573 #define HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B)
1574 #define VTOTAL(trans) _TRANSCODER(trans, _VTOTAL_A, _VTOTAL_B)
1575 #define VBLANK(trans) _TRANSCODER(trans, _VBLANK_A, _VBLANK_B)
1576 #define VSYNC(trans) _TRANSCODER(trans, _VSYNC_A, _VSYNC_B)
1577 #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
1578 #define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
1579 
1580 /* VGA port control */
1581 #define ADPA			0x61100
1582 #define PCH_ADPA                0xe1100
1583 #define VLV_ADPA		(VLV_DISPLAY_BASE + ADPA)
1584 
1585 #define   ADPA_DAC_ENABLE	(1<<31)
1586 #define   ADPA_DAC_DISABLE	0
1587 #define   ADPA_PIPE_SELECT_MASK	(1<<30)
1588 #define   ADPA_PIPE_A_SELECT	0
1589 #define   ADPA_PIPE_B_SELECT	(1<<30)
1590 #define   ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
1591 /* CPT uses bits 29:30 for pch transcoder select */
1592 #define   ADPA_CRT_HOTPLUG_MASK  0x03ff0000 /* bit 25-16 */
1593 #define   ADPA_CRT_HOTPLUG_MONITOR_NONE  (0<<24)
1594 #define   ADPA_CRT_HOTPLUG_MONITOR_MASK  (3<<24)
1595 #define   ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
1596 #define   ADPA_CRT_HOTPLUG_MONITOR_MONO  (2<<24)
1597 #define   ADPA_CRT_HOTPLUG_ENABLE        (1<<23)
1598 #define   ADPA_CRT_HOTPLUG_PERIOD_64     (0<<22)
1599 #define   ADPA_CRT_HOTPLUG_PERIOD_128    (1<<22)
1600 #define   ADPA_CRT_HOTPLUG_WARMUP_5MS    (0<<21)
1601 #define   ADPA_CRT_HOTPLUG_WARMUP_10MS   (1<<21)
1602 #define   ADPA_CRT_HOTPLUG_SAMPLE_2S     (0<<20)
1603 #define   ADPA_CRT_HOTPLUG_SAMPLE_4S     (1<<20)
1604 #define   ADPA_CRT_HOTPLUG_VOLTAGE_40    (0<<18)
1605 #define   ADPA_CRT_HOTPLUG_VOLTAGE_50    (1<<18)
1606 #define   ADPA_CRT_HOTPLUG_VOLTAGE_60    (2<<18)
1607 #define   ADPA_CRT_HOTPLUG_VOLTAGE_70    (3<<18)
1608 #define   ADPA_CRT_HOTPLUG_VOLREF_325MV  (0<<17)
1609 #define   ADPA_CRT_HOTPLUG_VOLREF_475MV  (1<<17)
1610 #define   ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
1611 #define   ADPA_USE_VGA_HVPOLARITY (1<<15)
1612 #define   ADPA_SETS_HVPOLARITY	0
1613 #define   ADPA_VSYNC_CNTL_DISABLE (1<<11)
1614 #define   ADPA_VSYNC_CNTL_ENABLE 0
1615 #define   ADPA_HSYNC_CNTL_DISABLE (1<<10)
1616 #define   ADPA_HSYNC_CNTL_ENABLE 0
1617 #define   ADPA_VSYNC_ACTIVE_HIGH (1<<4)
1618 #define   ADPA_VSYNC_ACTIVE_LOW	0
1619 #define   ADPA_HSYNC_ACTIVE_HIGH (1<<3)
1620 #define   ADPA_HSYNC_ACTIVE_LOW	0
1621 #define   ADPA_DPMS_MASK	(~(3<<10))
1622 #define   ADPA_DPMS_ON		(0<<10)
1623 #define   ADPA_DPMS_SUSPEND	(1<<10)
1624 #define   ADPA_DPMS_STANDBY	(2<<10)
1625 #define   ADPA_DPMS_OFF		(3<<10)
1626 
1627 
1628 /* Hotplug control (945+ only) */
1629 #define PORT_HOTPLUG_EN		0x61110
1630 #define   HDMIB_HOTPLUG_INT_EN			(1 << 29)
1631 #define   DPB_HOTPLUG_INT_EN			(1 << 29)
1632 #define   HDMIC_HOTPLUG_INT_EN			(1 << 28)
1633 #define   DPC_HOTPLUG_INT_EN			(1 << 28)
1634 #define   HDMID_HOTPLUG_INT_EN			(1 << 27)
1635 #define   DPD_HOTPLUG_INT_EN			(1 << 27)
1636 #define   SDVOB_HOTPLUG_INT_EN			(1 << 26)
1637 #define   SDVOC_HOTPLUG_INT_EN			(1 << 25)
1638 #define   TV_HOTPLUG_INT_EN			(1 << 18)
1639 #define   CRT_HOTPLUG_INT_EN			(1 << 9)
1640 #define   CRT_HOTPLUG_FORCE_DETECT		(1 << 3)
1641 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32	(0 << 8)
1642 /* must use period 64 on GM45 according to docs */
1643 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64	(1 << 8)
1644 #define CRT_HOTPLUG_DAC_ON_TIME_2M		(0 << 7)
1645 #define CRT_HOTPLUG_DAC_ON_TIME_4M		(1 << 7)
1646 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40		(0 << 5)
1647 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50		(1 << 5)
1648 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60		(2 << 5)
1649 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70		(3 << 5)
1650 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK	(3 << 5)
1651 #define CRT_HOTPLUG_DETECT_DELAY_1G		(0 << 4)
1652 #define CRT_HOTPLUG_DETECT_DELAY_2G		(1 << 4)
1653 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV	(0 << 2)
1654 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV	(1 << 2)
1655 
1656 #define PORT_HOTPLUG_STAT	0x61114
1657 /* HDMI/DP bits are gen4+ */
1658 #define   DPB_HOTPLUG_LIVE_STATUS               (1 << 29)
1659 #define   DPC_HOTPLUG_LIVE_STATUS               (1 << 28)
1660 #define   DPD_HOTPLUG_LIVE_STATUS               (1 << 27)
1661 #define   DPD_HOTPLUG_INT_STATUS		(3 << 21)
1662 #define   DPC_HOTPLUG_INT_STATUS		(3 << 19)
1663 #define   DPB_HOTPLUG_INT_STATUS		(3 << 17)
1664 /* HDMI bits are shared with the DP bits */
1665 #define   HDMIB_HOTPLUG_LIVE_STATUS             (1 << 29)
1666 #define   HDMIC_HOTPLUG_LIVE_STATUS             (1 << 28)
1667 #define   HDMID_HOTPLUG_LIVE_STATUS             (1 << 27)
1668 #define   HDMID_HOTPLUG_INT_STATUS		(3 << 21)
1669 #define   HDMIC_HOTPLUG_INT_STATUS		(3 << 19)
1670 #define   HDMIB_HOTPLUG_INT_STATUS		(3 << 17)
1671 /* CRT/TV common between gen3+ */
1672 #define   CRT_HOTPLUG_INT_STATUS		(1 << 11)
1673 #define   TV_HOTPLUG_INT_STATUS			(1 << 10)
1674 #define   CRT_HOTPLUG_MONITOR_MASK		(3 << 8)
1675 #define   CRT_HOTPLUG_MONITOR_COLOR		(3 << 8)
1676 #define   CRT_HOTPLUG_MONITOR_MONO		(2 << 8)
1677 #define   CRT_HOTPLUG_MONITOR_NONE		(0 << 8)
1678 /* SDVO is different across gen3/4 */
1679 #define   SDVOC_HOTPLUG_INT_STATUS_G4X		(1 << 3)
1680 #define   SDVOB_HOTPLUG_INT_STATUS_G4X		(1 << 2)
1681 #define   SDVOC_HOTPLUG_INT_STATUS_I965		(3 << 4)
1682 #define   SDVOB_HOTPLUG_INT_STATUS_I965		(3 << 2)
1683 #define   SDVOC_HOTPLUG_INT_STATUS_I915		(1 << 7)
1684 #define   SDVOB_HOTPLUG_INT_STATUS_I915		(1 << 6)
1685 
1686 /* SDVO port control */
1687 #define SDVOB			0x61140
1688 #define SDVOC			0x61160
1689 #define   SDVO_ENABLE		(1 << 31)
1690 #define   SDVO_PIPE_B_SELECT	(1 << 30)
1691 #define   SDVO_STALL_SELECT	(1 << 29)
1692 #define   SDVO_INTERRUPT_ENABLE	(1 << 26)
1693 /**
1694  * 915G/GM SDVO pixel multiplier.
1695  *
1696  * Programmed value is multiplier - 1, up to 5x.
1697  *
1698  * \sa DPLL_MD_UDI_MULTIPLIER_MASK
1699  */
1700 #define   SDVO_PORT_MULTIPLY_MASK	(7 << 23)
1701 #define   SDVO_PORT_MULTIPLY_SHIFT		23
1702 #define   SDVO_PHASE_SELECT_MASK	(15 << 19)
1703 #define   SDVO_PHASE_SELECT_DEFAULT	(6 << 19)
1704 #define   SDVO_CLOCK_OUTPUT_INVERT	(1 << 18)
1705 #define   SDVOC_GANG_MODE		(1 << 16)
1706 #define   SDVO_ENCODING_SDVO		(0x0 << 10)
1707 #define   SDVO_ENCODING_HDMI		(0x2 << 10)
1708 /** Requird for HDMI operation */
1709 #define   SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9)
1710 #define   SDVO_COLOR_RANGE_16_235	(1 << 8)
1711 #define   SDVO_BORDER_ENABLE		(1 << 7)
1712 #define   SDVO_AUDIO_ENABLE		(1 << 6)
1713 /** New with 965, default is to be set */
1714 #define   SDVO_VSYNC_ACTIVE_HIGH	(1 << 4)
1715 /** New with 965, default is to be set */
1716 #define   SDVO_HSYNC_ACTIVE_HIGH	(1 << 3)
1717 #define   SDVOB_PCIE_CONCURRENCY	(1 << 3)
1718 #define   SDVO_DETECTED			(1 << 2)
1719 /* Bits to be preserved when writing */
1720 #define   SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))
1721 #define   SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
1722 
1723 /* DVO port control */
1724 #define DVOA			0x61120
1725 #define DVOB			0x61140
1726 #define DVOC			0x61160
1727 #define   DVO_ENABLE			(1 << 31)
1728 #define   DVO_PIPE_B_SELECT		(1 << 30)
1729 #define   DVO_PIPE_STALL_UNUSED		(0 << 28)
1730 #define   DVO_PIPE_STALL		(1 << 28)
1731 #define   DVO_PIPE_STALL_TV		(2 << 28)
1732 #define   DVO_PIPE_STALL_MASK		(3 << 28)
1733 #define   DVO_USE_VGA_SYNC		(1 << 15)
1734 #define   DVO_DATA_ORDER_I740		(0 << 14)
1735 #define   DVO_DATA_ORDER_FP		(1 << 14)
1736 #define   DVO_VSYNC_DISABLE		(1 << 11)
1737 #define   DVO_HSYNC_DISABLE		(1 << 10)
1738 #define   DVO_VSYNC_TRISTATE		(1 << 9)
1739 #define   DVO_HSYNC_TRISTATE		(1 << 8)
1740 #define   DVO_BORDER_ENABLE		(1 << 7)
1741 #define   DVO_DATA_ORDER_GBRG		(1 << 6)
1742 #define   DVO_DATA_ORDER_RGGB		(0 << 6)
1743 #define   DVO_DATA_ORDER_GBRG_ERRATA	(0 << 6)
1744 #define   DVO_DATA_ORDER_RGGB_ERRATA	(1 << 6)
1745 #define   DVO_VSYNC_ACTIVE_HIGH		(1 << 4)
1746 #define   DVO_HSYNC_ACTIVE_HIGH		(1 << 3)
1747 #define   DVO_BLANK_ACTIVE_HIGH		(1 << 2)
1748 #define   DVO_OUTPUT_CSTATE_PIXELS	(1 << 1)	/* SDG only */
1749 #define   DVO_OUTPUT_SOURCE_SIZE_PIXELS	(1 << 0)	/* SDG only */
1750 #define   DVO_PRESERVE_MASK		(0x7<<24)
1751 #define DVOA_SRCDIM		0x61124
1752 #define DVOB_SRCDIM		0x61144
1753 #define DVOC_SRCDIM		0x61164
1754 #define   DVO_SRCDIM_HORIZONTAL_SHIFT	12
1755 #define   DVO_SRCDIM_VERTICAL_SHIFT	0
1756 
1757 /* LVDS port control */
1758 #define LVDS			0x61180
1759 /*
1760  * Enables the LVDS port.  This bit must be set before DPLLs are enabled, as
1761  * the DPLL semantics change when the LVDS is assigned to that pipe.
1762  */
1763 #define   LVDS_PORT_EN			(1 << 31)
1764 /* Selects pipe B for LVDS data.  Must be set on pre-965. */
1765 #define   LVDS_PIPEB_SELECT		(1 << 30)
1766 #define   LVDS_PIPE_MASK		(1 << 30)
1767 #define   LVDS_PIPE(pipe)		((pipe) << 30)
1768 /* LVDS dithering flag on 965/g4x platform */
1769 #define   LVDS_ENABLE_DITHER		(1 << 25)
1770 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
1771 #define   LVDS_VSYNC_POLARITY		(1 << 21)
1772 #define   LVDS_HSYNC_POLARITY		(1 << 20)
1773 
1774 /* Enable border for unscaled (or aspect-scaled) display */
1775 #define   LVDS_BORDER_ENABLE		(1 << 15)
1776 /*
1777  * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
1778  * pixel.
1779  */
1780 #define   LVDS_A0A2_CLKA_POWER_MASK	(3 << 8)
1781 #define   LVDS_A0A2_CLKA_POWER_DOWN	(0 << 8)
1782 #define   LVDS_A0A2_CLKA_POWER_UP	(3 << 8)
1783 /*
1784  * Controls the A3 data pair, which contains the additional LSBs for 24 bit
1785  * mode.  Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
1786  * on.
1787  */
1788 #define   LVDS_A3_POWER_MASK		(3 << 6)
1789 #define   LVDS_A3_POWER_DOWN		(0 << 6)
1790 #define   LVDS_A3_POWER_UP		(3 << 6)
1791 /*
1792  * Controls the CLKB pair.  This should only be set when LVDS_B0B3_POWER_UP
1793  * is set.
1794  */
1795 #define   LVDS_CLKB_POWER_MASK		(3 << 4)
1796 #define   LVDS_CLKB_POWER_DOWN		(0 << 4)
1797 #define   LVDS_CLKB_POWER_UP		(3 << 4)
1798 /*
1799  * Controls the B0-B3 data pairs.  This must be set to match the DPLL p2
1800  * setting for whether we are in dual-channel mode.  The B3 pair will
1801  * additionally only be powered up when LVDS_A3_POWER_UP is set.
1802  */
1803 #define   LVDS_B0B3_POWER_MASK		(3 << 2)
1804 #define   LVDS_B0B3_POWER_DOWN		(0 << 2)
1805 #define   LVDS_B0B3_POWER_UP		(3 << 2)
1806 
1807 /* Video Data Island Packet control */
1808 #define VIDEO_DIP_DATA		0x61178
1809 /* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC
1810  * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
1811  * of the infoframe structure specified by CEA-861. */
1812 #define   VIDEO_DIP_DATA_SIZE	32
1813 #define VIDEO_DIP_CTL		0x61170
1814 /* Pre HSW: */
1815 #define   VIDEO_DIP_ENABLE		(1 << 31)
1816 #define   VIDEO_DIP_PORT_B		(1 << 29)
1817 #define   VIDEO_DIP_PORT_C		(2 << 29)
1818 #define   VIDEO_DIP_PORT_D		(3 << 29)
1819 #define   VIDEO_DIP_PORT_MASK		(3 << 29)
1820 #define   VIDEO_DIP_ENABLE_GCP		(1 << 25)
1821 #define   VIDEO_DIP_ENABLE_AVI		(1 << 21)
1822 #define   VIDEO_DIP_ENABLE_VENDOR	(2 << 21)
1823 #define   VIDEO_DIP_ENABLE_GAMUT	(4 << 21)
1824 #define   VIDEO_DIP_ENABLE_SPD		(8 << 21)
1825 #define   VIDEO_DIP_SELECT_AVI		(0 << 19)
1826 #define   VIDEO_DIP_SELECT_VENDOR	(1 << 19)
1827 #define   VIDEO_DIP_SELECT_SPD		(3 << 19)
1828 #define   VIDEO_DIP_SELECT_MASK		(3 << 19)
1829 #define   VIDEO_DIP_FREQ_ONCE		(0 << 16)
1830 #define   VIDEO_DIP_FREQ_VSYNC		(1 << 16)
1831 #define   VIDEO_DIP_FREQ_2VSYNC		(2 << 16)
1832 #define   VIDEO_DIP_FREQ_MASK		(3 << 16)
1833 /* HSW and later: */
1834 #define   VIDEO_DIP_ENABLE_VSC_HSW	(1 << 20)
1835 #define   VIDEO_DIP_ENABLE_GCP_HSW	(1 << 16)
1836 #define   VIDEO_DIP_ENABLE_AVI_HSW	(1 << 12)
1837 #define   VIDEO_DIP_ENABLE_VS_HSW	(1 << 8)
1838 #define   VIDEO_DIP_ENABLE_GMP_HSW	(1 << 4)
1839 #define   VIDEO_DIP_ENABLE_SPD_HSW	(1 << 0)
1840 
1841 /* Panel power sequencing */
1842 #define PP_STATUS	0x61200
1843 #define   PP_ON		(1 << 31)
1844 /*
1845  * Indicates that all dependencies of the panel are on:
1846  *
1847  * - PLL enabled
1848  * - pipe enabled
1849  * - LVDS/DVOB/DVOC on
1850  */
1851 #define   PP_READY		(1 << 30)
1852 #define   PP_SEQUENCE_NONE	(0 << 28)
1853 #define   PP_SEQUENCE_POWER_UP	(1 << 28)
1854 #define   PP_SEQUENCE_POWER_DOWN (2 << 28)
1855 #define   PP_SEQUENCE_MASK	(3 << 28)
1856 #define   PP_SEQUENCE_SHIFT	28
1857 #define   PP_CYCLE_DELAY_ACTIVE	(1 << 27)
1858 #define   PP_SEQUENCE_STATE_MASK 0x0000000f
1859 #define   PP_SEQUENCE_STATE_OFF_IDLE	(0x0 << 0)
1860 #define   PP_SEQUENCE_STATE_OFF_S0_1	(0x1 << 0)
1861 #define   PP_SEQUENCE_STATE_OFF_S0_2	(0x2 << 0)
1862 #define   PP_SEQUENCE_STATE_OFF_S0_3	(0x3 << 0)
1863 #define   PP_SEQUENCE_STATE_ON_IDLE	(0x8 << 0)
1864 #define   PP_SEQUENCE_STATE_ON_S1_0	(0x9 << 0)
1865 #define   PP_SEQUENCE_STATE_ON_S1_2	(0xa << 0)
1866 #define   PP_SEQUENCE_STATE_ON_S1_3	(0xb << 0)
1867 #define   PP_SEQUENCE_STATE_RESET	(0xf << 0)
1868 #define PP_CONTROL	0x61204
1869 #define   POWER_TARGET_ON	(1 << 0)
1870 #define PP_ON_DELAYS	0x61208
1871 #define PP_OFF_DELAYS	0x6120c
1872 #define PP_DIVISOR	0x61210
1873 
1874 /* Panel fitting */
1875 #define PFIT_CONTROL	0x61230
1876 #define   PFIT_ENABLE		(1 << 31)
1877 #define   PFIT_PIPE_MASK	(3 << 29)
1878 #define   PFIT_PIPE_SHIFT	29
1879 #define   VERT_INTERP_DISABLE	(0 << 10)
1880 #define   VERT_INTERP_BILINEAR	(1 << 10)
1881 #define   VERT_INTERP_MASK	(3 << 10)
1882 #define   VERT_AUTO_SCALE	(1 << 9)
1883 #define   HORIZ_INTERP_DISABLE	(0 << 6)
1884 #define   HORIZ_INTERP_BILINEAR	(1 << 6)
1885 #define   HORIZ_INTERP_MASK	(3 << 6)
1886 #define   HORIZ_AUTO_SCALE	(1 << 5)
1887 #define   PANEL_8TO6_DITHER_ENABLE (1 << 3)
1888 #define   PFIT_FILTER_FUZZY	(0 << 24)
1889 #define   PFIT_SCALING_AUTO	(0 << 26)
1890 #define   PFIT_SCALING_PROGRAMMED (1 << 26)
1891 #define   PFIT_SCALING_PILLAR	(2 << 26)
1892 #define   PFIT_SCALING_LETTER	(3 << 26)
1893 #define PFIT_PGM_RATIOS	0x61234
1894 #define   PFIT_VERT_SCALE_MASK			0xfff00000
1895 #define   PFIT_HORIZ_SCALE_MASK			0x0000fff0
1896 /* Pre-965 */
1897 #define		PFIT_VERT_SCALE_SHIFT		20
1898 #define		PFIT_VERT_SCALE_MASK		0xfff00000
1899 #define		PFIT_HORIZ_SCALE_SHIFT		4
1900 #define		PFIT_HORIZ_SCALE_MASK		0x0000fff0
1901 /* 965+ */
1902 #define		PFIT_VERT_SCALE_SHIFT_965	16
1903 #define		PFIT_VERT_SCALE_MASK_965	0x1fff0000
1904 #define		PFIT_HORIZ_SCALE_SHIFT_965	0
1905 #define		PFIT_HORIZ_SCALE_MASK_965	0x00001fff
1906 
1907 #define PFIT_AUTO_RATIOS 0x61238
1908 
1909 /* Backlight control */
1910 #define BLC_PWM_CTL2		0x61250 /* 965+ only */
1911 #define   BLM_PWM_ENABLE		(1 << 31)
1912 #define   BLM_COMBINATION_MODE		(1 << 30) /* gen4 only */
1913 #define   BLM_PIPE_SELECT		(1 << 29)
1914 #define   BLM_PIPE_SELECT_IVB		(3 << 29)
1915 #define   BLM_PIPE_A			(0 << 29)
1916 #define   BLM_PIPE_B			(1 << 29)
1917 #define   BLM_PIPE_C			(2 << 29) /* ivb + */
1918 #define   BLM_PIPE(pipe)		((pipe) << 29)
1919 #define   BLM_POLARITY_I965		(1 << 28) /* gen4 only */
1920 #define   BLM_PHASE_IN_INTERUPT_STATUS	(1 << 26)
1921 #define   BLM_PHASE_IN_ENABLE		(1 << 25)
1922 #define   BLM_PHASE_IN_INTERUPT_ENABL	(1 << 24)
1923 #define   BLM_PHASE_IN_TIME_BASE_SHIFT	(16)
1924 #define   BLM_PHASE_IN_TIME_BASE_MASK	(0xff << 16)
1925 #define   BLM_PHASE_IN_COUNT_SHIFT	(8)
1926 #define   BLM_PHASE_IN_COUNT_MASK	(0xff << 8)
1927 #define   BLM_PHASE_IN_INCR_SHIFT	(0)
1928 #define   BLM_PHASE_IN_INCR_MASK	(0xff << 0)
1929 #define BLC_PWM_CTL		0x61254
1930 /*
1931  * This is the most significant 15 bits of the number of backlight cycles in a
1932  * complete cycle of the modulated backlight control.
1933  *
1934  * The actual value is this field multiplied by two.
1935  */
1936 #define   BACKLIGHT_MODULATION_FREQ_SHIFT	(17)
1937 #define   BACKLIGHT_MODULATION_FREQ_MASK	(0x7fff << 17)
1938 #define   BLM_LEGACY_MODE			(1 << 16) /* gen2 only */
1939 /*
1940  * This is the number of cycles out of the backlight modulation cycle for which
1941  * the backlight is on.
1942  *
1943  * This field must be no greater than the number of cycles in the complete
1944  * backlight modulation cycle.
1945  */
1946 #define   BACKLIGHT_DUTY_CYCLE_SHIFT		(0)
1947 #define   BACKLIGHT_DUTY_CYCLE_MASK		(0xffff)
1948 #define   BACKLIGHT_DUTY_CYCLE_MASK_PNV		(0xfffe)
1949 #define   BLM_POLARITY_PNV			(1 << 0) /* pnv only */
1950 
1951 #define BLC_HIST_CTL		0x61260
1952 
1953 /* New registers for PCH-split platforms. Safe where new bits show up, the
1954  * register layout machtes with gen4 BLC_PWM_CTL[12]. */
1955 #define BLC_PWM_CPU_CTL2	0x48250
1956 #define BLC_PWM_CPU_CTL		0x48254
1957 
1958 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
1959  * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
1960 #define BLC_PWM_PCH_CTL1	0xc8250
1961 #define   BLM_PCH_PWM_ENABLE			(1 << 31)
1962 #define   BLM_PCH_OVERRIDE_ENABLE		(1 << 30)
1963 #define   BLM_PCH_POLARITY			(1 << 29)
1964 #define BLC_PWM_PCH_CTL2	0xc8254
1965 
1966 /* TV port control */
1967 #define TV_CTL			0x68000
1968 /** Enables the TV encoder */
1969 # define TV_ENC_ENABLE			(1 << 31)
1970 /** Sources the TV encoder input from pipe B instead of A. */
1971 # define TV_ENC_PIPEB_SELECT		(1 << 30)
1972 /** Outputs composite video (DAC A only) */
1973 # define TV_ENC_OUTPUT_COMPOSITE	(0 << 28)
1974 /** Outputs SVideo video (DAC B/C) */
1975 # define TV_ENC_OUTPUT_SVIDEO		(1 << 28)
1976 /** Outputs Component video (DAC A/B/C) */
1977 # define TV_ENC_OUTPUT_COMPONENT	(2 << 28)
1978 /** Outputs Composite and SVideo (DAC A/B/C) */
1979 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE	(3 << 28)
1980 # define TV_TRILEVEL_SYNC		(1 << 21)
1981 /** Enables slow sync generation (945GM only) */
1982 # define TV_SLOW_SYNC			(1 << 20)
1983 /** Selects 4x oversampling for 480i and 576p */
1984 # define TV_OVERSAMPLE_4X		(0 << 18)
1985 /** Selects 2x oversampling for 720p and 1080i */
1986 # define TV_OVERSAMPLE_2X		(1 << 18)
1987 /** Selects no oversampling for 1080p */
1988 # define TV_OVERSAMPLE_NONE		(2 << 18)
1989 /** Selects 8x oversampling */
1990 # define TV_OVERSAMPLE_8X		(3 << 18)
1991 /** Selects progressive mode rather than interlaced */
1992 # define TV_PROGRESSIVE			(1 << 17)
1993 /** Sets the colorburst to PAL mode.  Required for non-M PAL modes. */
1994 # define TV_PAL_BURST			(1 << 16)
1995 /** Field for setting delay of Y compared to C */
1996 # define TV_YC_SKEW_MASK		(7 << 12)
1997 /** Enables a fix for 480p/576p standard definition modes on the 915GM only */
1998 # define TV_ENC_SDP_FIX			(1 << 11)
1999 /**
2000  * Enables a fix for the 915GM only.
2001  *
2002  * Not sure what it does.
2003  */
2004 # define TV_ENC_C0_FIX			(1 << 10)
2005 /** Bits that must be preserved by software */
2006 # define TV_CTL_SAVE			((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
2007 # define TV_FUSE_STATE_MASK		(3 << 4)
2008 /** Read-only state that reports all features enabled */
2009 # define TV_FUSE_STATE_ENABLED		(0 << 4)
2010 /** Read-only state that reports that Macrovision is disabled in hardware*/
2011 # define TV_FUSE_STATE_NO_MACROVISION	(1 << 4)
2012 /** Read-only state that reports that TV-out is disabled in hardware. */
2013 # define TV_FUSE_STATE_DISABLED		(2 << 4)
2014 /** Normal operation */
2015 # define TV_TEST_MODE_NORMAL		(0 << 0)
2016 /** Encoder test pattern 1 - combo pattern */
2017 # define TV_TEST_MODE_PATTERN_1		(1 << 0)
2018 /** Encoder test pattern 2 - full screen vertical 75% color bars */
2019 # define TV_TEST_MODE_PATTERN_2		(2 << 0)
2020 /** Encoder test pattern 3 - full screen horizontal 75% color bars */
2021 # define TV_TEST_MODE_PATTERN_3		(3 << 0)
2022 /** Encoder test pattern 4 - random noise */
2023 # define TV_TEST_MODE_PATTERN_4		(4 << 0)
2024 /** Encoder test pattern 5 - linear color ramps */
2025 # define TV_TEST_MODE_PATTERN_5		(5 << 0)
2026 /**
2027  * This test mode forces the DACs to 50% of full output.
2028  *
2029  * This is used for load detection in combination with TVDAC_SENSE_MASK
2030  */
2031 # define TV_TEST_MODE_MONITOR_DETECT	(7 << 0)
2032 # define TV_TEST_MODE_MASK		(7 << 0)
2033 
2034 #define TV_DAC			0x68004
2035 # define TV_DAC_SAVE		0x00ffff00
2036 /**
2037  * Reports that DAC state change logic has reported change (RO).
2038  *
2039  * This gets cleared when TV_DAC_STATE_EN is cleared
2040 */
2041 # define TVDAC_STATE_CHG		(1 << 31)
2042 # define TVDAC_SENSE_MASK		(7 << 28)
2043 /** Reports that DAC A voltage is above the detect threshold */
2044 # define TVDAC_A_SENSE			(1 << 30)
2045 /** Reports that DAC B voltage is above the detect threshold */
2046 # define TVDAC_B_SENSE			(1 << 29)
2047 /** Reports that DAC C voltage is above the detect threshold */
2048 # define TVDAC_C_SENSE			(1 << 28)
2049 /**
2050  * Enables DAC state detection logic, for load-based TV detection.
2051  *
2052  * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
2053  * to off, for load detection to work.
2054  */
2055 # define TVDAC_STATE_CHG_EN		(1 << 27)
2056 /** Sets the DAC A sense value to high */
2057 # define TVDAC_A_SENSE_CTL		(1 << 26)
2058 /** Sets the DAC B sense value to high */
2059 # define TVDAC_B_SENSE_CTL		(1 << 25)
2060 /** Sets the DAC C sense value to high */
2061 # define TVDAC_C_SENSE_CTL		(1 << 24)
2062 /** Overrides the ENC_ENABLE and DAC voltage levels */
2063 # define DAC_CTL_OVERRIDE		(1 << 7)
2064 /** Sets the slew rate.  Must be preserved in software */
2065 # define ENC_TVDAC_SLEW_FAST		(1 << 6)
2066 # define DAC_A_1_3_V			(0 << 4)
2067 # define DAC_A_1_1_V			(1 << 4)
2068 # define DAC_A_0_7_V			(2 << 4)
2069 # define DAC_A_MASK			(3 << 4)
2070 # define DAC_B_1_3_V			(0 << 2)
2071 # define DAC_B_1_1_V			(1 << 2)
2072 # define DAC_B_0_7_V			(2 << 2)
2073 # define DAC_B_MASK			(3 << 2)
2074 # define DAC_C_1_3_V			(0 << 0)
2075 # define DAC_C_1_1_V			(1 << 0)
2076 # define DAC_C_0_7_V			(2 << 0)
2077 # define DAC_C_MASK			(3 << 0)
2078 
2079 /**
2080  * CSC coefficients are stored in a floating point format with 9 bits of
2081  * mantissa and 2 or 3 bits of exponent.  The exponent is represented as 2**-n,
2082  * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
2083  * -1 (0x3) being the only legal negative value.
2084  */
2085 #define TV_CSC_Y		0x68010
2086 # define TV_RY_MASK			0x07ff0000
2087 # define TV_RY_SHIFT			16
2088 # define TV_GY_MASK			0x00000fff
2089 # define TV_GY_SHIFT			0
2090 
2091 #define TV_CSC_Y2		0x68014
2092 # define TV_BY_MASK			0x07ff0000
2093 # define TV_BY_SHIFT			16
2094 /**
2095  * Y attenuation for component video.
2096  *
2097  * Stored in 1.9 fixed point.
2098  */
2099 # define TV_AY_MASK			0x000003ff
2100 # define TV_AY_SHIFT			0
2101 
2102 #define TV_CSC_U		0x68018
2103 # define TV_RU_MASK			0x07ff0000
2104 # define TV_RU_SHIFT			16
2105 # define TV_GU_MASK			0x000007ff
2106 # define TV_GU_SHIFT			0
2107 
2108 #define TV_CSC_U2		0x6801c
2109 # define TV_BU_MASK			0x07ff0000
2110 # define TV_BU_SHIFT			16
2111 /**
2112  * U attenuation for component video.
2113  *
2114  * Stored in 1.9 fixed point.
2115  */
2116 # define TV_AU_MASK			0x000003ff
2117 # define TV_AU_SHIFT			0
2118 
2119 #define TV_CSC_V		0x68020
2120 # define TV_RV_MASK			0x0fff0000
2121 # define TV_RV_SHIFT			16
2122 # define TV_GV_MASK			0x000007ff
2123 # define TV_GV_SHIFT			0
2124 
2125 #define TV_CSC_V2		0x68024
2126 # define TV_BV_MASK			0x07ff0000
2127 # define TV_BV_SHIFT			16
2128 /**
2129  * V attenuation for component video.
2130  *
2131  * Stored in 1.9 fixed point.
2132  */
2133 # define TV_AV_MASK			0x000007ff
2134 # define TV_AV_SHIFT			0
2135 
2136 #define TV_CLR_KNOBS		0x68028
2137 /** 2s-complement brightness adjustment */
2138 # define TV_BRIGHTNESS_MASK		0xff000000
2139 # define TV_BRIGHTNESS_SHIFT		24
2140 /** Contrast adjustment, as a 2.6 unsigned floating point number */
2141 # define TV_CONTRAST_MASK		0x00ff0000
2142 # define TV_CONTRAST_SHIFT		16
2143 /** Saturation adjustment, as a 2.6 unsigned floating point number */
2144 # define TV_SATURATION_MASK		0x0000ff00
2145 # define TV_SATURATION_SHIFT		8
2146 /** Hue adjustment, as an integer phase angle in degrees */
2147 # define TV_HUE_MASK			0x000000ff
2148 # define TV_HUE_SHIFT			0
2149 
2150 #define TV_CLR_LEVEL		0x6802c
2151 /** Controls the DAC level for black */
2152 # define TV_BLACK_LEVEL_MASK		0x01ff0000
2153 # define TV_BLACK_LEVEL_SHIFT		16
2154 /** Controls the DAC level for blanking */
2155 # define TV_BLANK_LEVEL_MASK		0x000001ff
2156 # define TV_BLANK_LEVEL_SHIFT		0
2157 
2158 #define TV_H_CTL_1		0x68030
2159 /** Number of pixels in the hsync. */
2160 # define TV_HSYNC_END_MASK		0x1fff0000
2161 # define TV_HSYNC_END_SHIFT		16
2162 /** Total number of pixels minus one in the line (display and blanking). */
2163 # define TV_HTOTAL_MASK			0x00001fff
2164 # define TV_HTOTAL_SHIFT		0
2165 
2166 #define TV_H_CTL_2		0x68034
2167 /** Enables the colorburst (needed for non-component color) */
2168 # define TV_BURST_ENA			(1 << 31)
2169 /** Offset of the colorburst from the start of hsync, in pixels minus one. */
2170 # define TV_HBURST_START_SHIFT		16
2171 # define TV_HBURST_START_MASK		0x1fff0000
2172 /** Length of the colorburst */
2173 # define TV_HBURST_LEN_SHIFT		0
2174 # define TV_HBURST_LEN_MASK		0x0001fff
2175 
2176 #define TV_H_CTL_3		0x68038
2177 /** End of hblank, measured in pixels minus one from start of hsync */
2178 # define TV_HBLANK_END_SHIFT		16
2179 # define TV_HBLANK_END_MASK		0x1fff0000
2180 /** Start of hblank, measured in pixels minus one from start of hsync */
2181 # define TV_HBLANK_START_SHIFT		0
2182 # define TV_HBLANK_START_MASK		0x0001fff
2183 
2184 #define TV_V_CTL_1		0x6803c
2185 /** XXX */
2186 # define TV_NBR_END_SHIFT		16
2187 # define TV_NBR_END_MASK		0x07ff0000
2188 /** XXX */
2189 # define TV_VI_END_F1_SHIFT		8
2190 # define TV_VI_END_F1_MASK		0x00003f00
2191 /** XXX */
2192 # define TV_VI_END_F2_SHIFT		0
2193 # define TV_VI_END_F2_MASK		0x0000003f
2194 
2195 #define TV_V_CTL_2		0x68040
2196 /** Length of vsync, in half lines */
2197 # define TV_VSYNC_LEN_MASK		0x07ff0000
2198 # define TV_VSYNC_LEN_SHIFT		16
2199 /** Offset of the start of vsync in field 1, measured in one less than the
2200  * number of half lines.
2201  */
2202 # define TV_VSYNC_START_F1_MASK		0x00007f00
2203 # define TV_VSYNC_START_F1_SHIFT	8
2204 /**
2205  * Offset of the start of vsync in field 2, measured in one less than the
2206  * number of half lines.
2207  */
2208 # define TV_VSYNC_START_F2_MASK		0x0000007f
2209 # define TV_VSYNC_START_F2_SHIFT	0
2210 
2211 #define TV_V_CTL_3		0x68044
2212 /** Enables generation of the equalization signal */
2213 # define TV_EQUAL_ENA			(1 << 31)
2214 /** Length of vsync, in half lines */
2215 # define TV_VEQ_LEN_MASK		0x007f0000
2216 # define TV_VEQ_LEN_SHIFT		16
2217 /** Offset of the start of equalization in field 1, measured in one less than
2218  * the number of half lines.
2219  */
2220 # define TV_VEQ_START_F1_MASK		0x0007f00
2221 # define TV_VEQ_START_F1_SHIFT		8
2222 /**
2223  * Offset of the start of equalization in field 2, measured in one less than
2224  * the number of half lines.
2225  */
2226 # define TV_VEQ_START_F2_MASK		0x000007f
2227 # define TV_VEQ_START_F2_SHIFT		0
2228 
2229 #define TV_V_CTL_4		0x68048
2230 /**
2231  * Offset to start of vertical colorburst, measured in one less than the
2232  * number of lines from vertical start.
2233  */
2234 # define TV_VBURST_START_F1_MASK	0x003f0000
2235 # define TV_VBURST_START_F1_SHIFT	16
2236 /**
2237  * Offset to the end of vertical colorburst, measured in one less than the
2238  * number of lines from the start of NBR.
2239  */
2240 # define TV_VBURST_END_F1_MASK		0x000000ff
2241 # define TV_VBURST_END_F1_SHIFT		0
2242 
2243 #define TV_V_CTL_5		0x6804c
2244 /**
2245  * Offset to start of vertical colorburst, measured in one less than the
2246  * number of lines from vertical start.
2247  */
2248 # define TV_VBURST_START_F2_MASK	0x003f0000
2249 # define TV_VBURST_START_F2_SHIFT	16
2250 /**
2251  * Offset to the end of vertical colorburst, measured in one less than the
2252  * number of lines from the start of NBR.
2253  */
2254 # define TV_VBURST_END_F2_MASK		0x000000ff
2255 # define TV_VBURST_END_F2_SHIFT		0
2256 
2257 #define TV_V_CTL_6		0x68050
2258 /**
2259  * Offset to start of vertical colorburst, measured in one less than the
2260  * number of lines from vertical start.
2261  */
2262 # define TV_VBURST_START_F3_MASK	0x003f0000
2263 # define TV_VBURST_START_F3_SHIFT	16
2264 /**
2265  * Offset to the end of vertical colorburst, measured in one less than the
2266  * number of lines from the start of NBR.
2267  */
2268 # define TV_VBURST_END_F3_MASK		0x000000ff
2269 # define TV_VBURST_END_F3_SHIFT		0
2270 
2271 #define TV_V_CTL_7		0x68054
2272 /**
2273  * Offset to start of vertical colorburst, measured in one less than the
2274  * number of lines from vertical start.
2275  */
2276 # define TV_VBURST_START_F4_MASK	0x003f0000
2277 # define TV_VBURST_START_F4_SHIFT	16
2278 /**
2279  * Offset to the end of vertical colorburst, measured in one less than the
2280  * number of lines from the start of NBR.
2281  */
2282 # define TV_VBURST_END_F4_MASK		0x000000ff
2283 # define TV_VBURST_END_F4_SHIFT		0
2284 
2285 #define TV_SC_CTL_1		0x68060
2286 /** Turns on the first subcarrier phase generation DDA */
2287 # define TV_SC_DDA1_EN			(1 << 31)
2288 /** Turns on the first subcarrier phase generation DDA */
2289 # define TV_SC_DDA2_EN			(1 << 30)
2290 /** Turns on the first subcarrier phase generation DDA */
2291 # define TV_SC_DDA3_EN			(1 << 29)
2292 /** Sets the subcarrier DDA to reset frequency every other field */
2293 # define TV_SC_RESET_EVERY_2		(0 << 24)
2294 /** Sets the subcarrier DDA to reset frequency every fourth field */
2295 # define TV_SC_RESET_EVERY_4		(1 << 24)
2296 /** Sets the subcarrier DDA to reset frequency every eighth field */
2297 # define TV_SC_RESET_EVERY_8		(2 << 24)
2298 /** Sets the subcarrier DDA to never reset the frequency */
2299 # define TV_SC_RESET_NEVER		(3 << 24)
2300 /** Sets the peak amplitude of the colorburst.*/
2301 # define TV_BURST_LEVEL_MASK		0x00ff0000
2302 # define TV_BURST_LEVEL_SHIFT		16
2303 /** Sets the increment of the first subcarrier phase generation DDA */
2304 # define TV_SCDDA1_INC_MASK		0x00000fff
2305 # define TV_SCDDA1_INC_SHIFT		0
2306 
2307 #define TV_SC_CTL_2		0x68064
2308 /** Sets the rollover for the second subcarrier phase generation DDA */
2309 # define TV_SCDDA2_SIZE_MASK		0x7fff0000
2310 # define TV_SCDDA2_SIZE_SHIFT		16
2311 /** Sets the increent of the second subcarrier phase generation DDA */
2312 # define TV_SCDDA2_INC_MASK		0x00007fff
2313 # define TV_SCDDA2_INC_SHIFT		0
2314 
2315 #define TV_SC_CTL_3		0x68068
2316 /** Sets the rollover for the third subcarrier phase generation DDA */
2317 # define TV_SCDDA3_SIZE_MASK		0x7fff0000
2318 # define TV_SCDDA3_SIZE_SHIFT		16
2319 /** Sets the increent of the third subcarrier phase generation DDA */
2320 # define TV_SCDDA3_INC_MASK		0x00007fff
2321 # define TV_SCDDA3_INC_SHIFT		0
2322 
2323 #define TV_WIN_POS		0x68070
2324 /** X coordinate of the display from the start of horizontal active */
2325 # define TV_XPOS_MASK			0x1fff0000
2326 # define TV_XPOS_SHIFT			16
2327 /** Y coordinate of the display from the start of vertical active (NBR) */
2328 # define TV_YPOS_MASK			0x00000fff
2329 # define TV_YPOS_SHIFT			0
2330 
2331 #define TV_WIN_SIZE		0x68074
2332 /** Horizontal size of the display window, measured in pixels*/
2333 # define TV_XSIZE_MASK			0x1fff0000
2334 # define TV_XSIZE_SHIFT			16
2335 /**
2336  * Vertical size of the display window, measured in pixels.
2337  *
2338  * Must be even for interlaced modes.
2339  */
2340 # define TV_YSIZE_MASK			0x00000fff
2341 # define TV_YSIZE_SHIFT			0
2342 
2343 #define TV_FILTER_CTL_1		0x68080
2344 /**
2345  * Enables automatic scaling calculation.
2346  *
2347  * If set, the rest of the registers are ignored, and the calculated values can
2348  * be read back from the register.
2349  */
2350 # define TV_AUTO_SCALE			(1 << 31)
2351 /**
2352  * Disables the vertical filter.
2353  *
2354  * This is required on modes more than 1024 pixels wide */
2355 # define TV_V_FILTER_BYPASS		(1 << 29)
2356 /** Enables adaptive vertical filtering */
2357 # define TV_VADAPT			(1 << 28)
2358 # define TV_VADAPT_MODE_MASK		(3 << 26)
2359 /** Selects the least adaptive vertical filtering mode */
2360 # define TV_VADAPT_MODE_LEAST		(0 << 26)
2361 /** Selects the moderately adaptive vertical filtering mode */
2362 # define TV_VADAPT_MODE_MODERATE	(1 << 26)
2363 /** Selects the most adaptive vertical filtering mode */
2364 # define TV_VADAPT_MODE_MOST		(3 << 26)
2365 /**
2366  * Sets the horizontal scaling factor.
2367  *
2368  * This should be the fractional part of the horizontal scaling factor divided
2369  * by the oversampling rate.  TV_HSCALE should be less than 1, and set to:
2370  *
2371  * (src width - 1) / ((oversample * dest width) - 1)
2372  */
2373 # define TV_HSCALE_FRAC_MASK		0x00003fff
2374 # define TV_HSCALE_FRAC_SHIFT		0
2375 
2376 #define TV_FILTER_CTL_2		0x68084
2377 /**
2378  * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2379  *
2380  * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
2381  */
2382 # define TV_VSCALE_INT_MASK		0x00038000
2383 # define TV_VSCALE_INT_SHIFT		15
2384 /**
2385  * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2386  *
2387  * \sa TV_VSCALE_INT_MASK
2388  */
2389 # define TV_VSCALE_FRAC_MASK		0x00007fff
2390 # define TV_VSCALE_FRAC_SHIFT		0
2391 
2392 #define TV_FILTER_CTL_3		0x68088
2393 /**
2394  * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2395  *
2396  * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
2397  *
2398  * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2399  */
2400 # define TV_VSCALE_IP_INT_MASK		0x00038000
2401 # define TV_VSCALE_IP_INT_SHIFT		15
2402 /**
2403  * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2404  *
2405  * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2406  *
2407  * \sa TV_VSCALE_IP_INT_MASK
2408  */
2409 # define TV_VSCALE_IP_FRAC_MASK		0x00007fff
2410 # define TV_VSCALE_IP_FRAC_SHIFT		0
2411 
2412 #define TV_CC_CONTROL		0x68090
2413 # define TV_CC_ENABLE			(1 << 31)
2414 /**
2415  * Specifies which field to send the CC data in.
2416  *
2417  * CC data is usually sent in field 0.
2418  */
2419 # define TV_CC_FID_MASK			(1 << 27)
2420 # define TV_CC_FID_SHIFT		27
2421 /** Sets the horizontal position of the CC data.  Usually 135. */
2422 # define TV_CC_HOFF_MASK		0x03ff0000
2423 # define TV_CC_HOFF_SHIFT		16
2424 /** Sets the vertical position of the CC data.  Usually 21 */
2425 # define TV_CC_LINE_MASK		0x0000003f
2426 # define TV_CC_LINE_SHIFT		0
2427 
2428 #define TV_CC_DATA		0x68094
2429 # define TV_CC_RDY			(1 << 31)
2430 /** Second word of CC data to be transmitted. */
2431 # define TV_CC_DATA_2_MASK		0x007f0000
2432 # define TV_CC_DATA_2_SHIFT		16
2433 /** First word of CC data to be transmitted. */
2434 # define TV_CC_DATA_1_MASK		0x0000007f
2435 # define TV_CC_DATA_1_SHIFT		0
2436 
2437 #define TV_H_LUMA_0		0x68100
2438 #define TV_H_LUMA_59		0x681ec
2439 #define TV_H_CHROMA_0		0x68200
2440 #define TV_H_CHROMA_59		0x682ec
2441 #define TV_V_LUMA_0		0x68300
2442 #define TV_V_LUMA_42		0x683a8
2443 #define TV_V_CHROMA_0		0x68400
2444 #define TV_V_CHROMA_42		0x684a8
2445 
2446 /* Display Port */
2447 #define DP_A				0x64000 /* eDP */
2448 #define DP_B				0x64100
2449 #define DP_C				0x64200
2450 #define DP_D				0x64300
2451 
2452 #define   DP_PORT_EN			(1 << 31)
2453 #define   DP_PIPEB_SELECT		(1 << 30)
2454 #define   DP_PIPE_MASK			(1 << 30)
2455 
2456 /* Link training mode - select a suitable mode for each stage */
2457 #define   DP_LINK_TRAIN_PAT_1		(0 << 28)
2458 #define   DP_LINK_TRAIN_PAT_2		(1 << 28)
2459 #define   DP_LINK_TRAIN_PAT_IDLE	(2 << 28)
2460 #define   DP_LINK_TRAIN_OFF		(3 << 28)
2461 #define   DP_LINK_TRAIN_MASK		(3 << 28)
2462 #define   DP_LINK_TRAIN_SHIFT		28
2463 
2464 /* CPT Link training mode */
2465 #define   DP_LINK_TRAIN_PAT_1_CPT	(0 << 8)
2466 #define   DP_LINK_TRAIN_PAT_2_CPT	(1 << 8)
2467 #define   DP_LINK_TRAIN_PAT_IDLE_CPT	(2 << 8)
2468 #define   DP_LINK_TRAIN_OFF_CPT		(3 << 8)
2469 #define   DP_LINK_TRAIN_MASK_CPT	(7 << 8)
2470 #define   DP_LINK_TRAIN_SHIFT_CPT	8
2471 
2472 /* Signal voltages. These are mostly controlled by the other end */
2473 #define   DP_VOLTAGE_0_4		(0 << 25)
2474 #define   DP_VOLTAGE_0_6		(1 << 25)
2475 #define   DP_VOLTAGE_0_8		(2 << 25)
2476 #define   DP_VOLTAGE_1_2		(3 << 25)
2477 #define   DP_VOLTAGE_MASK		(7 << 25)
2478 #define   DP_VOLTAGE_SHIFT		25
2479 
2480 /* Signal pre-emphasis levels, like voltages, the other end tells us what
2481  * they want
2482  */
2483 #define   DP_PRE_EMPHASIS_0		(0 << 22)
2484 #define   DP_PRE_EMPHASIS_3_5		(1 << 22)
2485 #define   DP_PRE_EMPHASIS_6		(2 << 22)
2486 #define   DP_PRE_EMPHASIS_9_5		(3 << 22)
2487 #define   DP_PRE_EMPHASIS_MASK		(7 << 22)
2488 #define   DP_PRE_EMPHASIS_SHIFT		22
2489 
2490 /* How many wires to use. I guess 3 was too hard */
2491 #define   DP_PORT_WIDTH_1		(0 << 19)
2492 #define   DP_PORT_WIDTH_2		(1 << 19)
2493 #define   DP_PORT_WIDTH_4		(3 << 19)
2494 #define   DP_PORT_WIDTH_MASK		(7 << 19)
2495 
2496 /* Mystic DPCD version 1.1 special mode */
2497 #define   DP_ENHANCED_FRAMING		(1 << 18)
2498 
2499 /* eDP */
2500 #define   DP_PLL_FREQ_270MHZ		(0 << 16)
2501 #define   DP_PLL_FREQ_160MHZ		(1 << 16)
2502 #define   DP_PLL_FREQ_MASK		(3 << 16)
2503 
2504 /** locked once port is enabled */
2505 #define   DP_PORT_REVERSAL		(1 << 15)
2506 
2507 /* eDP */
2508 #define   DP_PLL_ENABLE			(1 << 14)
2509 
2510 /** sends the clock on lane 15 of the PEG for debug */
2511 #define   DP_CLOCK_OUTPUT_ENABLE	(1 << 13)
2512 
2513 #define   DP_SCRAMBLING_DISABLE		(1 << 12)
2514 #define   DP_SCRAMBLING_DISABLE_IRONLAKE	(1 << 7)
2515 
2516 /** limit RGB values to avoid confusing TVs */
2517 #define   DP_COLOR_RANGE_16_235		(1 << 8)
2518 
2519 /** Turn on the audio link */
2520 #define   DP_AUDIO_OUTPUT_ENABLE	(1 << 6)
2521 
2522 /** vs and hs sync polarity */
2523 #define   DP_SYNC_VS_HIGH		(1 << 4)
2524 #define   DP_SYNC_HS_HIGH		(1 << 3)
2525 
2526 /** A fantasy */
2527 #define   DP_DETECTED			(1 << 2)
2528 
2529 /** The aux channel provides a way to talk to the
2530  * signal sink for DDC etc. Max packet size supported
2531  * is 20 bytes in each direction, hence the 5 fixed
2532  * data registers
2533  */
2534 #define DPA_AUX_CH_CTL			0x64010
2535 #define DPA_AUX_CH_DATA1		0x64014
2536 #define DPA_AUX_CH_DATA2		0x64018
2537 #define DPA_AUX_CH_DATA3		0x6401c
2538 #define DPA_AUX_CH_DATA4		0x64020
2539 #define DPA_AUX_CH_DATA5		0x64024
2540 
2541 #define DPB_AUX_CH_CTL			0x64110
2542 #define DPB_AUX_CH_DATA1		0x64114
2543 #define DPB_AUX_CH_DATA2		0x64118
2544 #define DPB_AUX_CH_DATA3		0x6411c
2545 #define DPB_AUX_CH_DATA4		0x64120
2546 #define DPB_AUX_CH_DATA5		0x64124
2547 
2548 #define DPC_AUX_CH_CTL			0x64210
2549 #define DPC_AUX_CH_DATA1		0x64214
2550 #define DPC_AUX_CH_DATA2		0x64218
2551 #define DPC_AUX_CH_DATA3		0x6421c
2552 #define DPC_AUX_CH_DATA4		0x64220
2553 #define DPC_AUX_CH_DATA5		0x64224
2554 
2555 #define DPD_AUX_CH_CTL			0x64310
2556 #define DPD_AUX_CH_DATA1		0x64314
2557 #define DPD_AUX_CH_DATA2		0x64318
2558 #define DPD_AUX_CH_DATA3		0x6431c
2559 #define DPD_AUX_CH_DATA4		0x64320
2560 #define DPD_AUX_CH_DATA5		0x64324
2561 
2562 #define   DP_AUX_CH_CTL_SEND_BUSY	    (1 << 31)
2563 #define   DP_AUX_CH_CTL_DONE		    (1 << 30)
2564 #define   DP_AUX_CH_CTL_INTERRUPT	    (1 << 29)
2565 #define   DP_AUX_CH_CTL_TIME_OUT_ERROR	    (1 << 28)
2566 #define   DP_AUX_CH_CTL_TIME_OUT_400us	    (0 << 26)
2567 #define   DP_AUX_CH_CTL_TIME_OUT_600us	    (1 << 26)
2568 #define   DP_AUX_CH_CTL_TIME_OUT_800us	    (2 << 26)
2569 #define   DP_AUX_CH_CTL_TIME_OUT_1600us	    (3 << 26)
2570 #define   DP_AUX_CH_CTL_TIME_OUT_MASK	    (3 << 26)
2571 #define   DP_AUX_CH_CTL_RECEIVE_ERROR	    (1 << 25)
2572 #define   DP_AUX_CH_CTL_MESSAGE_SIZE_MASK    (0x1f << 20)
2573 #define   DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT   20
2574 #define   DP_AUX_CH_CTL_PRECHARGE_2US_MASK   (0xf << 16)
2575 #define   DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT  16
2576 #define   DP_AUX_CH_CTL_AUX_AKSV_SELECT	    (1 << 15)
2577 #define   DP_AUX_CH_CTL_MANCHESTER_TEST	    (1 << 14)
2578 #define   DP_AUX_CH_CTL_SYNC_TEST	    (1 << 13)
2579 #define   DP_AUX_CH_CTL_DEGLITCH_TEST	    (1 << 12)
2580 #define   DP_AUX_CH_CTL_PRECHARGE_TEST	    (1 << 11)
2581 #define   DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK    (0x7ff)
2582 #define   DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT   0
2583 
2584 /*
2585  * Computing GMCH M and N values for the Display Port link
2586  *
2587  * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
2588  *
2589  * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
2590  *
2591  * The GMCH value is used internally
2592  *
2593  * bytes_per_pixel is the number of bytes coming out of the plane,
2594  * which is after the LUTs, so we want the bytes for our color format.
2595  * For our current usage, this is always 3, one byte for R, G and B.
2596  */
2597 #define _PIPEA_GMCH_DATA_M			0x70050
2598 #define _PIPEB_GMCH_DATA_M			0x71050
2599 
2600 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
2601 #define   PIPE_GMCH_DATA_M_TU_SIZE_MASK		(0x3f << 25)
2602 #define   PIPE_GMCH_DATA_M_TU_SIZE_SHIFT	25
2603 
2604 #define   PIPE_GMCH_DATA_M_MASK			(0xffffff)
2605 
2606 #define _PIPEA_GMCH_DATA_N			0x70054
2607 #define _PIPEB_GMCH_DATA_N			0x71054
2608 #define   PIPE_GMCH_DATA_N_MASK			(0xffffff)
2609 
2610 /*
2611  * Computing Link M and N values for the Display Port link
2612  *
2613  * Link M / N = pixel_clock / ls_clk
2614  *
2615  * (the DP spec calls pixel_clock the 'strm_clk')
2616  *
2617  * The Link value is transmitted in the Main Stream
2618  * Attributes and VB-ID.
2619  */
2620 
2621 #define _PIPEA_DP_LINK_M				0x70060
2622 #define _PIPEB_DP_LINK_M				0x71060
2623 #define   PIPEA_DP_LINK_M_MASK			(0xffffff)
2624 
2625 #define _PIPEA_DP_LINK_N				0x70064
2626 #define _PIPEB_DP_LINK_N				0x71064
2627 #define   PIPEA_DP_LINK_N_MASK			(0xffffff)
2628 
2629 #define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M)
2630 #define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N)
2631 #define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M)
2632 #define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N)
2633 
2634 /* Display & cursor control */
2635 
2636 /* Pipe A */
2637 #define _PIPEADSL		0x70000
2638 #define   DSL_LINEMASK_GEN2	0x00000fff
2639 #define   DSL_LINEMASK_GEN3	0x00001fff
2640 #define _PIPEACONF		0x70008
2641 #define   PIPECONF_ENABLE	(1<<31)
2642 #define   PIPECONF_DISABLE	0
2643 #define   PIPECONF_DOUBLE_WIDE	(1<<30)
2644 #define   I965_PIPECONF_ACTIVE	(1<<30)
2645 #define   PIPECONF_FRAME_START_DELAY_MASK (3<<27)
2646 #define   PIPECONF_SINGLE_WIDE	0
2647 #define   PIPECONF_PIPE_UNLOCKED 0
2648 #define   PIPECONF_PIPE_LOCKED	(1<<25)
2649 #define   PIPECONF_PALETTE	0
2650 #define   PIPECONF_GAMMA		(1<<24)
2651 #define   PIPECONF_FORCE_BORDER	(1<<25)
2652 #define   PIPECONF_INTERLACE_MASK	(7 << 21)
2653 #define   PIPECONF_INTERLACE_MASK_HSW	(3 << 21)
2654 /* Note that pre-gen3 does not support interlaced display directly. Panel
2655  * fitting must be disabled on pre-ilk for interlaced. */
2656 #define   PIPECONF_PROGRESSIVE			(0 << 21)
2657 #define   PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL	(4 << 21) /* gen4 only */
2658 #define   PIPECONF_INTERLACE_W_SYNC_SHIFT	(5 << 21) /* gen4 only */
2659 #define   PIPECONF_INTERLACE_W_FIELD_INDICATION	(6 << 21)
2660 #define   PIPECONF_INTERLACE_FIELD_0_ONLY	(7 << 21) /* gen3 only */
2661 /* Ironlake and later have a complete new set of values for interlaced. PFIT
2662  * means panel fitter required, PF means progressive fetch, DBL means power
2663  * saving pixel doubling. */
2664 #define   PIPECONF_PFIT_PF_INTERLACED_ILK	(1 << 21)
2665 #define   PIPECONF_INTERLACED_ILK		(3 << 21)
2666 #define   PIPECONF_INTERLACED_DBL_ILK		(4 << 21) /* ilk/snb only */
2667 #define   PIPECONF_PFIT_PF_INTERLACED_DBL_ILK	(5 << 21) /* ilk/snb only */
2668 #define   PIPECONF_CXSR_DOWNCLOCK	(1<<16)
2669 #define   PIPECONF_BPP_MASK	(0x000000e0)
2670 #define   PIPECONF_BPP_8	(0<<5)
2671 #define   PIPECONF_BPP_10	(1<<5)
2672 #define   PIPECONF_BPP_6	(2<<5)
2673 #define   PIPECONF_BPP_12	(3<<5)
2674 #define   PIPECONF_DITHER_EN	(1<<4)
2675 #define   PIPECONF_DITHER_TYPE_MASK (0x0000000c)
2676 #define   PIPECONF_DITHER_TYPE_SP (0<<2)
2677 #define   PIPECONF_DITHER_TYPE_ST1 (1<<2)
2678 #define   PIPECONF_DITHER_TYPE_ST2 (2<<2)
2679 #define   PIPECONF_DITHER_TYPE_TEMP (3<<2)
2680 #define _PIPEASTAT		0x70024
2681 #define   PIPE_FIFO_UNDERRUN_STATUS		(1UL<<31)
2682 #define   SPRITE1_FLIPDONE_INT_EN_VLV		(1UL<<30)
2683 #define   PIPE_CRC_ERROR_ENABLE			(1UL<<29)
2684 #define   PIPE_CRC_DONE_ENABLE			(1UL<<28)
2685 #define   PIPE_GMBUS_EVENT_ENABLE		(1UL<<27)
2686 #define   PLANE_FLIP_DONE_INT_EN_VLV		(1UL<<26)
2687 #define   PIPE_HOTPLUG_INTERRUPT_ENABLE		(1UL<<26)
2688 #define   PIPE_VSYNC_INTERRUPT_ENABLE		(1UL<<25)
2689 #define   PIPE_DISPLAY_LINE_COMPARE_ENABLE	(1UL<<24)
2690 #define   PIPE_DPST_EVENT_ENABLE		(1UL<<23)
2691 #define   SPRITE0_FLIP_DONE_INT_EN_VLV		(1UL<<26)
2692 #define   PIPE_LEGACY_BLC_EVENT_ENABLE		(1UL<<22)
2693 #define   PIPE_ODD_FIELD_INTERRUPT_ENABLE	(1UL<<21)
2694 #define   PIPE_EVEN_FIELD_INTERRUPT_ENABLE	(1UL<<20)
2695 #define   PIPE_HOTPLUG_TV_INTERRUPT_ENABLE	(1UL<<18) /* pre-965 */
2696 #define   PIPE_START_VBLANK_INTERRUPT_ENABLE	(1UL<<18) /* 965 or later */
2697 #define   PIPE_VBLANK_INTERRUPT_ENABLE		(1UL<<17)
2698 #define   PIPEA_HBLANK_INT_EN_VLV		(1UL<<16)
2699 #define   PIPE_OVERLAY_UPDATED_ENABLE		(1UL<<16)
2700 #define   SPRITE1_FLIPDONE_INT_STATUS_VLV	(1UL<<15)
2701 #define   SPRITE0_FLIPDONE_INT_STATUS_VLV	(1UL<<15)
2702 #define   PIPE_CRC_ERROR_INTERRUPT_STATUS	(1UL<<13)
2703 #define   PIPE_CRC_DONE_INTERRUPT_STATUS	(1UL<<12)
2704 #define   PIPE_GMBUS_INTERRUPT_STATUS		(1UL<<11)
2705 #define   PLANE_FLIPDONE_INT_STATUS_VLV		(1UL<<10)
2706 #define   PIPE_HOTPLUG_INTERRUPT_STATUS		(1UL<<10)
2707 #define   PIPE_VSYNC_INTERRUPT_STATUS		(1UL<<9)
2708 #define   PIPE_DISPLAY_LINE_COMPARE_STATUS	(1UL<<8)
2709 #define   PIPE_DPST_EVENT_STATUS		(1UL<<7)
2710 #define   PIPE_LEGACY_BLC_EVENT_STATUS		(1UL<<6)
2711 #define   PIPE_ODD_FIELD_INTERRUPT_STATUS	(1UL<<5)
2712 #define   PIPE_EVEN_FIELD_INTERRUPT_STATUS	(1UL<<4)
2713 #define   PIPE_HOTPLUG_TV_INTERRUPT_STATUS	(1UL<<2) /* pre-965 */
2714 #define   PIPE_START_VBLANK_INTERRUPT_STATUS	(1UL<<2) /* 965 or later */
2715 #define   PIPE_VBLANK_INTERRUPT_STATUS		(1UL<<1)
2716 #define   PIPE_OVERLAY_UPDATED_STATUS		(1UL<<0)
2717 #define   PIPE_BPC_MASK				(7 << 5) /* Ironlake */
2718 #define   PIPE_8BPC				(0 << 5)
2719 #define   PIPE_10BPC				(1 << 5)
2720 #define   PIPE_6BPC				(2 << 5)
2721 #define   PIPE_12BPC				(3 << 5)
2722 
2723 #define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)
2724 #define PIPECONF(tran) _TRANSCODER(tran, _PIPEACONF, _PIPEBCONF)
2725 #define PIPEDSL(pipe)  _PIPE(pipe, _PIPEADSL, _PIPEBDSL)
2726 #define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH)
2727 #define PIPEFRAMEPIXEL(pipe)  _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
2728 #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
2729 
2730 #define VLV_DPFLIPSTAT				0x70028
2731 #define   PIPEB_LINE_COMPARE_INT_EN		(1<<29)
2732 #define   PIPEB_HLINE_INT_EN			(1<<28)
2733 #define   PIPEB_VBLANK_INT_EN			(1<<27)
2734 #define   SPRITED_FLIPDONE_INT_EN		(1<<26)
2735 #define   SPRITEC_FLIPDONE_INT_EN		(1<<25)
2736 #define   PLANEB_FLIPDONE_INT_EN		(1<<24)
2737 #define   PIPEA_LINE_COMPARE_INT_EN		(1<<21)
2738 #define   PIPEA_HLINE_INT_EN			(1<<20)
2739 #define   PIPEA_VBLANK_INT_EN			(1<<19)
2740 #define   SPRITEB_FLIPDONE_INT_EN		(1<<18)
2741 #define   SPRITEA_FLIPDONE_INT_EN		(1<<17)
2742 #define   PLANEA_FLIPDONE_INT_EN		(1<<16)
2743 
2744 #define DPINVGTT				0x7002c /* VLV only */
2745 #define   CURSORB_INVALID_GTT_INT_EN		(1<<23)
2746 #define   CURSORA_INVALID_GTT_INT_EN		(1<<22)
2747 #define   SPRITED_INVALID_GTT_INT_EN		(1<<21)
2748 #define   SPRITEC_INVALID_GTT_INT_EN		(1<<20)
2749 #define   PLANEB_INVALID_GTT_INT_EN		(1<<19)
2750 #define   SPRITEB_INVALID_GTT_INT_EN		(1<<18)
2751 #define   SPRITEA_INVALID_GTT_INT_EN		(1<<17)
2752 #define   PLANEA_INVALID_GTT_INT_EN		(1<<16)
2753 #define   DPINVGTT_EN_MASK			0xff0000
2754 #define   CURSORB_INVALID_GTT_STATUS		(1<<7)
2755 #define   CURSORA_INVALID_GTT_STATUS		(1<<6)
2756 #define   SPRITED_INVALID_GTT_STATUS		(1<<5)
2757 #define   SPRITEC_INVALID_GTT_STATUS		(1<<4)
2758 #define   PLANEB_INVALID_GTT_STATUS		(1<<3)
2759 #define   SPRITEB_INVALID_GTT_STATUS		(1<<2)
2760 #define   SPRITEA_INVALID_GTT_STATUS		(1<<1)
2761 #define   PLANEA_INVALID_GTT_STATUS		(1<<0)
2762 #define   DPINVGTT_STATUS_MASK			0xff
2763 
2764 #define DSPARB			0x70030
2765 #define   DSPARB_CSTART_MASK	(0x7f << 7)
2766 #define   DSPARB_CSTART_SHIFT	7
2767 #define   DSPARB_BSTART_MASK	(0x7f)
2768 #define   DSPARB_BSTART_SHIFT	0
2769 #define   DSPARB_BEND_SHIFT	9 /* on 855 */
2770 #define   DSPARB_AEND_SHIFT	0
2771 
2772 #define DSPFW1			0x70034
2773 #define   DSPFW_SR_SHIFT	23
2774 #define   DSPFW_SR_MASK		(0x1ff<<23)
2775 #define   DSPFW_CURSORB_SHIFT	16
2776 #define   DSPFW_CURSORB_MASK	(0x3f<<16)
2777 #define   DSPFW_PLANEB_SHIFT	8
2778 #define   DSPFW_PLANEB_MASK	(0x7f<<8)
2779 #define   DSPFW_PLANEA_MASK	(0x7f)
2780 #define DSPFW2			0x70038
2781 #define   DSPFW_CURSORA_MASK	0x00003f00
2782 #define   DSPFW_CURSORA_SHIFT	8
2783 #define   DSPFW_PLANEC_MASK	(0x7f)
2784 #define DSPFW3			0x7003c
2785 #define   DSPFW_HPLL_SR_EN	(1<<31)
2786 #define   DSPFW_CURSOR_SR_SHIFT	24
2787 #define   PINEVIEW_SELF_REFRESH_EN	(1<<30)
2788 #define   DSPFW_CURSOR_SR_MASK		(0x3f<<24)
2789 #define   DSPFW_HPLL_CURSOR_SHIFT	16
2790 #define   DSPFW_HPLL_CURSOR_MASK	(0x3f<<16)
2791 #define   DSPFW_HPLL_SR_MASK		(0x1ff)
2792 
2793 /* drain latency register values*/
2794 #define DRAIN_LATENCY_PRECISION_32	32
2795 #define DRAIN_LATENCY_PRECISION_16	16
2796 #define VLV_DDL1			0x70050
2797 #define DDL_CURSORA_PRECISION_32	(1<<31)
2798 #define DDL_CURSORA_PRECISION_16	(0<<31)
2799 #define DDL_CURSORA_SHIFT		24
2800 #define DDL_PLANEA_PRECISION_32		(1<<7)
2801 #define DDL_PLANEA_PRECISION_16		(0<<7)
2802 #define VLV_DDL2			0x70054
2803 #define DDL_CURSORB_PRECISION_32	(1<<31)
2804 #define DDL_CURSORB_PRECISION_16	(0<<31)
2805 #define DDL_CURSORB_SHIFT		24
2806 #define DDL_PLANEB_PRECISION_32		(1<<7)
2807 #define DDL_PLANEB_PRECISION_16		(0<<7)
2808 
2809 /* FIFO watermark sizes etc */
2810 #define G4X_FIFO_LINE_SIZE	64
2811 #define I915_FIFO_LINE_SIZE	64
2812 #define I830_FIFO_LINE_SIZE	32
2813 
2814 #define VALLEYVIEW_FIFO_SIZE	255
2815 #define G4X_FIFO_SIZE		127
2816 #define I965_FIFO_SIZE		512
2817 #define I945_FIFO_SIZE		127
2818 #define I915_FIFO_SIZE		95
2819 #define I855GM_FIFO_SIZE	127 /* In cachelines */
2820 #define I830_FIFO_SIZE		95
2821 
2822 #define VALLEYVIEW_MAX_WM	0xff
2823 #define G4X_MAX_WM		0x3f
2824 #define I915_MAX_WM		0x3f
2825 
2826 #define PINEVIEW_DISPLAY_FIFO	512 /* in 64byte unit */
2827 #define PINEVIEW_FIFO_LINE_SIZE	64
2828 #define PINEVIEW_MAX_WM		0x1ff
2829 #define PINEVIEW_DFT_WM		0x3f
2830 #define PINEVIEW_DFT_HPLLOFF_WM	0
2831 #define PINEVIEW_GUARD_WM		10
2832 #define PINEVIEW_CURSOR_FIFO		64
2833 #define PINEVIEW_CURSOR_MAX_WM	0x3f
2834 #define PINEVIEW_CURSOR_DFT_WM	0
2835 #define PINEVIEW_CURSOR_GUARD_WM	5
2836 
2837 #define VALLEYVIEW_CURSOR_MAX_WM 64
2838 #define I965_CURSOR_FIFO	64
2839 #define I965_CURSOR_MAX_WM	32
2840 #define I965_CURSOR_DFT_WM	8
2841 
2842 /* define the Watermark register on Ironlake */
2843 #define WM0_PIPEA_ILK		0x45100
2844 #define  WM0_PIPE_PLANE_MASK	(0x7f<<16)
2845 #define  WM0_PIPE_PLANE_SHIFT	16
2846 #define  WM0_PIPE_SPRITE_MASK	(0x3f<<8)
2847 #define  WM0_PIPE_SPRITE_SHIFT	8
2848 #define  WM0_PIPE_CURSOR_MASK	(0x1f)
2849 
2850 #define WM0_PIPEB_ILK		0x45104
2851 #define WM0_PIPEC_IVB		0x45200
2852 #define WM1_LP_ILK		0x45108
2853 #define  WM1_LP_SR_EN		(1<<31)
2854 #define  WM1_LP_LATENCY_SHIFT	24
2855 #define  WM1_LP_LATENCY_MASK	(0x7f<<24)
2856 #define  WM1_LP_FBC_MASK	(0xf<<20)
2857 #define  WM1_LP_FBC_SHIFT	20
2858 #define  WM1_LP_SR_MASK		(0x1ff<<8)
2859 #define  WM1_LP_SR_SHIFT	8
2860 #define  WM1_LP_CURSOR_MASK	(0x3f)
2861 #define WM2_LP_ILK		0x4510c
2862 #define  WM2_LP_EN		(1<<31)
2863 #define WM3_LP_ILK		0x45110
2864 #define  WM3_LP_EN		(1<<31)
2865 #define WM1S_LP_ILK		0x45120
2866 #define WM2S_LP_IVB		0x45124
2867 #define WM3S_LP_IVB		0x45128
2868 #define  WM1S_LP_EN		(1<<31)
2869 
2870 /* Memory latency timer register */
2871 #define MLTR_ILK		0x11222
2872 #define  MLTR_WM1_SHIFT		0
2873 #define  MLTR_WM2_SHIFT		8
2874 /* the unit of memory self-refresh latency time is 0.5us */
2875 #define  ILK_SRLT_MASK		0x3f
2876 #define ILK_LATENCY(shift)	(I915_READ(MLTR_ILK) >> (shift) & ILK_SRLT_MASK)
2877 #define ILK_READ_WM1_LATENCY()	ILK_LATENCY(MLTR_WM1_SHIFT)
2878 #define ILK_READ_WM2_LATENCY()	ILK_LATENCY(MLTR_WM2_SHIFT)
2879 
2880 /* define the fifo size on Ironlake */
2881 #define ILK_DISPLAY_FIFO	128
2882 #define ILK_DISPLAY_MAXWM	64
2883 #define ILK_DISPLAY_DFTWM	8
2884 #define ILK_CURSOR_FIFO		32
2885 #define ILK_CURSOR_MAXWM	16
2886 #define ILK_CURSOR_DFTWM	8
2887 
2888 #define ILK_DISPLAY_SR_FIFO	512
2889 #define ILK_DISPLAY_MAX_SRWM	0x1ff
2890 #define ILK_DISPLAY_DFT_SRWM	0x3f
2891 #define ILK_CURSOR_SR_FIFO	64
2892 #define ILK_CURSOR_MAX_SRWM	0x3f
2893 #define ILK_CURSOR_DFT_SRWM	8
2894 
2895 #define ILK_FIFO_LINE_SIZE	64
2896 
2897 /* define the WM info on Sandybridge */
2898 #define SNB_DISPLAY_FIFO	128
2899 #define SNB_DISPLAY_MAXWM	0x7f	/* bit 16:22 */
2900 #define SNB_DISPLAY_DFTWM	8
2901 #define SNB_CURSOR_FIFO		32
2902 #define SNB_CURSOR_MAXWM	0x1f	/* bit 4:0 */
2903 #define SNB_CURSOR_DFTWM	8
2904 
2905 #define SNB_DISPLAY_SR_FIFO	512
2906 #define SNB_DISPLAY_MAX_SRWM	0x1ff	/* bit 16:8 */
2907 #define SNB_DISPLAY_DFT_SRWM	0x3f
2908 #define SNB_CURSOR_SR_FIFO	64
2909 #define SNB_CURSOR_MAX_SRWM	0x3f	/* bit 5:0 */
2910 #define SNB_CURSOR_DFT_SRWM	8
2911 
2912 #define SNB_FBC_MAX_SRWM	0xf	/* bit 23:20 */
2913 
2914 #define SNB_FIFO_LINE_SIZE	64
2915 
2916 
2917 /* the address where we get all kinds of latency value */
2918 #define SSKPD			0x5d10
2919 #define SSKPD_WM_MASK		0x3f
2920 #define SSKPD_WM0_SHIFT		0
2921 #define SSKPD_WM1_SHIFT		8
2922 #define SSKPD_WM2_SHIFT		16
2923 #define SSKPD_WM3_SHIFT		24
2924 
2925 #define SNB_LATENCY(shift)	(I915_READ(MCHBAR_MIRROR_BASE_SNB + SSKPD) >> (shift) & SSKPD_WM_MASK)
2926 #define SNB_READ_WM0_LATENCY()		SNB_LATENCY(SSKPD_WM0_SHIFT)
2927 #define SNB_READ_WM1_LATENCY()		SNB_LATENCY(SSKPD_WM1_SHIFT)
2928 #define SNB_READ_WM2_LATENCY()		SNB_LATENCY(SSKPD_WM2_SHIFT)
2929 #define SNB_READ_WM3_LATENCY()		SNB_LATENCY(SSKPD_WM3_SHIFT)
2930 
2931 /*
2932  * The two pipe frame counter registers are not synchronized, so
2933  * reading a stable value is somewhat tricky. The following code
2934  * should work:
2935  *
2936  *  do {
2937  *    high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2938  *             PIPE_FRAME_HIGH_SHIFT;
2939  *    low1 =  ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
2940  *             PIPE_FRAME_LOW_SHIFT);
2941  *    high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2942  *             PIPE_FRAME_HIGH_SHIFT);
2943  *  } while (high1 != high2);
2944  *  frame = (high1 << 8) | low1;
2945  */
2946 #define _PIPEAFRAMEHIGH          0x70040
2947 #define   PIPE_FRAME_HIGH_MASK    0x0000ffff
2948 #define   PIPE_FRAME_HIGH_SHIFT   0
2949 #define _PIPEAFRAMEPIXEL         0x70044
2950 #define   PIPE_FRAME_LOW_MASK     0xff000000
2951 #define   PIPE_FRAME_LOW_SHIFT    24
2952 #define   PIPE_PIXEL_MASK         0x00ffffff
2953 #define   PIPE_PIXEL_SHIFT        0
2954 /* GM45+ just has to be different */
2955 #define _PIPEA_FRMCOUNT_GM45	0x70040
2956 #define _PIPEA_FLIPCOUNT_GM45	0x70044
2957 #define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
2958 
2959 /* Cursor A & B regs */
2960 #define _CURACNTR		0x70080
2961 /* Old style CUR*CNTR flags (desktop 8xx) */
2962 #define   CURSOR_ENABLE		0x80000000
2963 #define   CURSOR_GAMMA_ENABLE	0x40000000
2964 #define   CURSOR_STRIDE_MASK	0x30000000
2965 #define   CURSOR_FORMAT_SHIFT	24
2966 #define   CURSOR_FORMAT_MASK	(0x07 << CURSOR_FORMAT_SHIFT)
2967 #define   CURSOR_FORMAT_2C	(0x00 << CURSOR_FORMAT_SHIFT)
2968 #define   CURSOR_FORMAT_3C	(0x01 << CURSOR_FORMAT_SHIFT)
2969 #define   CURSOR_FORMAT_4C	(0x02 << CURSOR_FORMAT_SHIFT)
2970 #define   CURSOR_FORMAT_ARGB	(0x04 << CURSOR_FORMAT_SHIFT)
2971 #define   CURSOR_FORMAT_XRGB	(0x05 << CURSOR_FORMAT_SHIFT)
2972 /* New style CUR*CNTR flags */
2973 #define   CURSOR_MODE		0x27
2974 #define   CURSOR_MODE_DISABLE   0x00
2975 #define   CURSOR_MODE_64_32B_AX 0x07
2976 #define   CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
2977 #define   MCURSOR_PIPE_SELECT	(1 << 28)
2978 #define   MCURSOR_PIPE_A	0x00
2979 #define   MCURSOR_PIPE_B	(1 << 28)
2980 #define   MCURSOR_GAMMA_ENABLE  (1 << 26)
2981 #define _CURABASE		0x70084
2982 #define _CURAPOS			0x70088
2983 #define   CURSOR_POS_MASK       0x007FF
2984 #define   CURSOR_POS_SIGN       0x8000
2985 #define   CURSOR_X_SHIFT        0
2986 #define   CURSOR_Y_SHIFT        16
2987 #define CURSIZE			0x700a0
2988 #define _CURBCNTR		0x700c0
2989 #define _CURBBASE		0x700c4
2990 #define _CURBPOS			0x700c8
2991 
2992 #define _CURBCNTR_IVB		0x71080
2993 #define _CURBBASE_IVB		0x71084
2994 #define _CURBPOS_IVB		0x71088
2995 
2996 #define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR)
2997 #define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE)
2998 #define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS)
2999 
3000 #define CURCNTR_IVB(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR_IVB)
3001 #define CURBASE_IVB(pipe) _PIPE(pipe, _CURABASE, _CURBBASE_IVB)
3002 #define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB)
3003 
3004 /* Display A control */
3005 #define _DSPACNTR                0x70180
3006 #define   DISPLAY_PLANE_ENABLE			(1<<31)
3007 #define   DISPLAY_PLANE_DISABLE			0
3008 #define   DISPPLANE_GAMMA_ENABLE		(1<<30)
3009 #define   DISPPLANE_GAMMA_DISABLE		0
3010 #define   DISPPLANE_PIXFORMAT_MASK		(0xf<<26)
3011 #define   DISPPLANE_YUV422			(0x0<<26)
3012 #define   DISPPLANE_8BPP			(0x2<<26)
3013 #define   DISPPLANE_BGRA555			(0x3<<26)
3014 #define   DISPPLANE_BGRX555			(0x4<<26)
3015 #define   DISPPLANE_BGRX565			(0x5<<26)
3016 #define   DISPPLANE_BGRX888			(0x6<<26)
3017 #define   DISPPLANE_BGRA888			(0x7<<26)
3018 #define   DISPPLANE_RGBX101010			(0x8<<26)
3019 #define   DISPPLANE_RGBA101010			(0x9<<26)
3020 #define   DISPPLANE_BGRX101010			(0xa<<26)
3021 #define   DISPPLANE_RGBX161616			(0xc<<26)
3022 #define   DISPPLANE_RGBX888			(0xe<<26)
3023 #define   DISPPLANE_RGBA888			(0xf<<26)
3024 #define   DISPPLANE_STEREO_ENABLE		(1<<25)
3025 #define   DISPPLANE_STEREO_DISABLE		0
3026 #define   DISPPLANE_SEL_PIPE_SHIFT		24
3027 #define   DISPPLANE_SEL_PIPE_MASK		(3<<DISPPLANE_SEL_PIPE_SHIFT)
3028 #define   DISPPLANE_SEL_PIPE_A			0
3029 #define   DISPPLANE_SEL_PIPE_B			(1<<DISPPLANE_SEL_PIPE_SHIFT)
3030 #define   DISPPLANE_SRC_KEY_ENABLE		(1<<22)
3031 #define   DISPPLANE_SRC_KEY_DISABLE		0
3032 #define   DISPPLANE_LINE_DOUBLE			(1<<20)
3033 #define   DISPPLANE_NO_LINE_DOUBLE		0
3034 #define   DISPPLANE_STEREO_POLARITY_FIRST	0
3035 #define   DISPPLANE_STEREO_POLARITY_SECOND	(1<<18)
3036 #define   DISPPLANE_TRICKLE_FEED_DISABLE	(1<<14) /* Ironlake */
3037 #define   DISPPLANE_TILED			(1<<10)
3038 #define _DSPAADDR		0x70184
3039 #define _DSPASTRIDE		0x70188
3040 #define _DSPAPOS			0x7018C /* reserved */
3041 #define _DSPASIZE		0x70190
3042 #define _DSPASURF		0x7019C /* 965+ only */
3043 #define _DSPATILEOFF		0x701A4 /* 965+ only */
3044 #define _DSPAOFFSET		0x701A4 /* HSW */
3045 #define _DSPASURFLIVE		0x701AC
3046 
3047 #define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR)
3048 #define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR)
3049 #define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE)
3050 #define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS)
3051 #define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE)
3052 #define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF)
3053 #define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF)
3054 #define DSPLINOFF(plane) DSPADDR(plane)
3055 #define DSPOFFSET(plane) _PIPE(plane, _DSPAOFFSET, _DSPBOFFSET)
3056 #define DSPSURFLIVE(plane) _PIPE(plane, _DSPASURFLIVE, _DSPBSURFLIVE)
3057 
3058 /* Display/Sprite base address macros */
3059 #define DISP_BASEADDR_MASK	(0xfffff000)
3060 #define I915_LO_DISPBASE(val)	(val & ~DISP_BASEADDR_MASK)
3061 #define I915_HI_DISPBASE(val)	(val & DISP_BASEADDR_MASK)
3062 #define I915_MODIFY_DISPBASE(reg, gfx_addr) \
3063 		(I915_WRITE((reg), (gfx_addr) | I915_LO_DISPBASE(I915_READ(reg))))
3064 
3065 /* VBIOS flags */
3066 #define SWF00			0x71410
3067 #define SWF01			0x71414
3068 #define SWF02			0x71418
3069 #define SWF03			0x7141c
3070 #define SWF04			0x71420
3071 #define SWF05			0x71424
3072 #define SWF06			0x71428
3073 #define SWF10			0x70410
3074 #define SWF11			0x70414
3075 #define SWF14			0x71420
3076 #define SWF30			0x72414
3077 #define SWF31			0x72418
3078 #define SWF32			0x7241c
3079 
3080 /* Pipe B */
3081 #define _PIPEBDSL		0x71000
3082 #define _PIPEBCONF		0x71008
3083 #define _PIPEBSTAT		0x71024
3084 #define _PIPEBFRAMEHIGH		0x71040
3085 #define _PIPEBFRAMEPIXEL		0x71044
3086 #define _PIPEB_FRMCOUNT_GM45	0x71040
3087 #define _PIPEB_FLIPCOUNT_GM45	0x71044
3088 
3089 
3090 /* Display B control */
3091 #define _DSPBCNTR		0x71180
3092 #define   DISPPLANE_ALPHA_TRANS_ENABLE		(1<<15)
3093 #define   DISPPLANE_ALPHA_TRANS_DISABLE		0
3094 #define   DISPPLANE_SPRITE_ABOVE_DISPLAY	0
3095 #define   DISPPLANE_SPRITE_ABOVE_OVERLAY	(1)
3096 #define _DSPBADDR		0x71184
3097 #define _DSPBSTRIDE		0x71188
3098 #define _DSPBPOS			0x7118C
3099 #define _DSPBSIZE		0x71190
3100 #define _DSPBSURF		0x7119C
3101 #define _DSPBTILEOFF		0x711A4
3102 #define _DSPBOFFSET		0x711A4
3103 #define _DSPBSURFLIVE		0x711AC
3104 
3105 /* Sprite A control */
3106 #define _DVSACNTR		0x72180
3107 #define   DVS_ENABLE		(1<<31)
3108 #define   DVS_GAMMA_ENABLE	(1<<30)
3109 #define   DVS_PIXFORMAT_MASK	(3<<25)
3110 #define   DVS_FORMAT_YUV422	(0<<25)
3111 #define   DVS_FORMAT_RGBX101010	(1<<25)
3112 #define   DVS_FORMAT_RGBX888	(2<<25)
3113 #define   DVS_FORMAT_RGBX161616	(3<<25)
3114 #define   DVS_SOURCE_KEY	(1<<22)
3115 #define   DVS_RGB_ORDER_XBGR	(1<<20)
3116 #define   DVS_YUV_BYTE_ORDER_MASK (3<<16)
3117 #define   DVS_YUV_ORDER_YUYV	(0<<16)
3118 #define   DVS_YUV_ORDER_UYVY	(1<<16)
3119 #define   DVS_YUV_ORDER_YVYU	(2<<16)
3120 #define   DVS_YUV_ORDER_VYUY	(3<<16)
3121 #define   DVS_DEST_KEY		(1<<2)
3122 #define   DVS_TRICKLE_FEED_DISABLE (1<<14)
3123 #define   DVS_TILED		(1<<10)
3124 #define _DVSALINOFF		0x72184
3125 #define _DVSASTRIDE		0x72188
3126 #define _DVSAPOS		0x7218c
3127 #define _DVSASIZE		0x72190
3128 #define _DVSAKEYVAL		0x72194
3129 #define _DVSAKEYMSK		0x72198
3130 #define _DVSASURF		0x7219c
3131 #define _DVSAKEYMAXVAL		0x721a0
3132 #define _DVSATILEOFF		0x721a4
3133 #define _DVSASURFLIVE		0x721ac
3134 #define _DVSASCALE		0x72204
3135 #define   DVS_SCALE_ENABLE	(1<<31)
3136 #define   DVS_FILTER_MASK	(3<<29)
3137 #define   DVS_FILTER_MEDIUM	(0<<29)
3138 #define   DVS_FILTER_ENHANCING	(1<<29)
3139 #define   DVS_FILTER_SOFTENING	(2<<29)
3140 #define   DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
3141 #define   DVS_VERTICAL_OFFSET_ENABLE (1<<27)
3142 #define _DVSAGAMC		0x72300
3143 
3144 #define _DVSBCNTR		0x73180
3145 #define _DVSBLINOFF		0x73184
3146 #define _DVSBSTRIDE		0x73188
3147 #define _DVSBPOS		0x7318c
3148 #define _DVSBSIZE		0x73190
3149 #define _DVSBKEYVAL		0x73194
3150 #define _DVSBKEYMSK		0x73198
3151 #define _DVSBSURF		0x7319c
3152 #define _DVSBKEYMAXVAL		0x731a0
3153 #define _DVSBTILEOFF		0x731a4
3154 #define _DVSBSURFLIVE		0x731ac
3155 #define _DVSBSCALE		0x73204
3156 #define _DVSBGAMC		0x73300
3157 
3158 #define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR)
3159 #define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
3160 #define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
3161 #define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS)
3162 #define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF)
3163 #define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
3164 #define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)
3165 #define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)
3166 #define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
3167 #define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
3168 #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
3169 #define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
3170 
3171 #define _SPRA_CTL		0x70280
3172 #define   SPRITE_ENABLE			(1<<31)
3173 #define   SPRITE_GAMMA_ENABLE		(1<<30)
3174 #define   SPRITE_PIXFORMAT_MASK		(7<<25)
3175 #define   SPRITE_FORMAT_YUV422		(0<<25)
3176 #define   SPRITE_FORMAT_RGBX101010	(1<<25)
3177 #define   SPRITE_FORMAT_RGBX888		(2<<25)
3178 #define   SPRITE_FORMAT_RGBX161616	(3<<25)
3179 #define   SPRITE_FORMAT_YUV444		(4<<25)
3180 #define   SPRITE_FORMAT_XR_BGR101010	(5<<25) /* Extended range */
3181 #define   SPRITE_CSC_ENABLE		(1<<24)
3182 #define   SPRITE_SOURCE_KEY		(1<<22)
3183 #define   SPRITE_RGB_ORDER_RGBX		(1<<20) /* only for 888 and 161616 */
3184 #define   SPRITE_YUV_TO_RGB_CSC_DISABLE	(1<<19)
3185 #define   SPRITE_YUV_CSC_FORMAT_BT709	(1<<18) /* 0 is BT601 */
3186 #define   SPRITE_YUV_BYTE_ORDER_MASK	(3<<16)
3187 #define   SPRITE_YUV_ORDER_YUYV		(0<<16)
3188 #define   SPRITE_YUV_ORDER_UYVY		(1<<16)
3189 #define   SPRITE_YUV_ORDER_YVYU		(2<<16)
3190 #define   SPRITE_YUV_ORDER_VYUY		(3<<16)
3191 #define   SPRITE_TRICKLE_FEED_DISABLE	(1<<14)
3192 #define   SPRITE_INT_GAMMA_ENABLE	(1<<13)
3193 #define   SPRITE_TILED			(1<<10)
3194 #define   SPRITE_DEST_KEY		(1<<2)
3195 #define _SPRA_LINOFF		0x70284
3196 #define _SPRA_STRIDE		0x70288
3197 #define _SPRA_POS		0x7028c
3198 #define _SPRA_SIZE		0x70290
3199 #define _SPRA_KEYVAL		0x70294
3200 #define _SPRA_KEYMSK		0x70298
3201 #define _SPRA_SURF		0x7029c
3202 #define _SPRA_KEYMAX		0x702a0
3203 #define _SPRA_TILEOFF		0x702a4
3204 #define _SPRA_OFFSET		0x702a4
3205 #define _SPRA_SURFLIVE		0x702ac
3206 #define _SPRA_SCALE		0x70304
3207 #define   SPRITE_SCALE_ENABLE	(1<<31)
3208 #define   SPRITE_FILTER_MASK	(3<<29)
3209 #define   SPRITE_FILTER_MEDIUM	(0<<29)
3210 #define   SPRITE_FILTER_ENHANCING	(1<<29)
3211 #define   SPRITE_FILTER_SOFTENING	(2<<29)
3212 #define   SPRITE_VERTICAL_OFFSET_HALF	(1<<28) /* must be enabled below */
3213 #define   SPRITE_VERTICAL_OFFSET_ENABLE	(1<<27)
3214 #define _SPRA_GAMC		0x70400
3215 
3216 #define _SPRB_CTL		0x71280
3217 #define _SPRB_LINOFF		0x71284
3218 #define _SPRB_STRIDE		0x71288
3219 #define _SPRB_POS		0x7128c
3220 #define _SPRB_SIZE		0x71290
3221 #define _SPRB_KEYVAL		0x71294
3222 #define _SPRB_KEYMSK		0x71298
3223 #define _SPRB_SURF		0x7129c
3224 #define _SPRB_KEYMAX		0x712a0
3225 #define _SPRB_TILEOFF		0x712a4
3226 #define _SPRB_OFFSET		0x712a4
3227 #define _SPRB_SURFLIVE		0x712ac
3228 #define _SPRB_SCALE		0x71304
3229 #define _SPRB_GAMC		0x71400
3230 
3231 #define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
3232 #define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
3233 #define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
3234 #define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS)
3235 #define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
3236 #define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
3237 #define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
3238 #define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
3239 #define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
3240 #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
3241 #define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
3242 #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
3243 #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
3244 #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
3245 
3246 /* VBIOS regs */
3247 #define VGACNTRL		0x71400
3248 # define VGA_DISP_DISABLE			(1 << 31)
3249 # define VGA_2X_MODE				(1 << 30)
3250 # define VGA_PIPE_B_SELECT			(1 << 29)
3251 
3252 /* Ironlake */
3253 
3254 #define CPU_VGACNTRL	0x41000
3255 
3256 #define DIGITAL_PORT_HOTPLUG_CNTRL      0x44030
3257 #define  DIGITAL_PORTA_HOTPLUG_ENABLE           (1 << 4)
3258 #define  DIGITAL_PORTA_SHORT_PULSE_2MS          (0 << 2)
3259 #define  DIGITAL_PORTA_SHORT_PULSE_4_5MS        (1 << 2)
3260 #define  DIGITAL_PORTA_SHORT_PULSE_6MS          (2 << 2)
3261 #define  DIGITAL_PORTA_SHORT_PULSE_100MS        (3 << 2)
3262 #define  DIGITAL_PORTA_NO_DETECT                (0 << 0)
3263 #define  DIGITAL_PORTA_LONG_PULSE_DETECT_MASK   (1 << 1)
3264 #define  DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK  (1 << 0)
3265 
3266 /* refresh rate hardware control */
3267 #define RR_HW_CTL       0x45300
3268 #define  RR_HW_LOW_POWER_FRAMES_MASK    0xff
3269 #define  RR_HW_HIGH_POWER_FRAMES_MASK   0xff00
3270 
3271 #define FDI_PLL_BIOS_0  0x46000
3272 #define  FDI_PLL_FB_CLOCK_MASK  0xff
3273 #define FDI_PLL_BIOS_1  0x46004
3274 #define FDI_PLL_BIOS_2  0x46008
3275 #define DISPLAY_PORT_PLL_BIOS_0         0x4600c
3276 #define DISPLAY_PORT_PLL_BIOS_1         0x46010
3277 #define DISPLAY_PORT_PLL_BIOS_2         0x46014
3278 
3279 #define PCH_3DCGDIS0		0x46020
3280 # define MARIUNIT_CLOCK_GATE_DISABLE		(1 << 18)
3281 # define SVSMUNIT_CLOCK_GATE_DISABLE		(1 << 1)
3282 
3283 #define PCH_3DCGDIS1		0x46024
3284 # define VFMUNIT_CLOCK_GATE_DISABLE		(1 << 11)
3285 
3286 #define FDI_PLL_FREQ_CTL        0x46030
3287 #define  FDI_PLL_FREQ_CHANGE_REQUEST    (1<<24)
3288 #define  FDI_PLL_FREQ_LOCK_LIMIT_MASK   0xfff00
3289 #define  FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK  0xff
3290 
3291 
3292 #define _PIPEA_DATA_M1           0x60030
3293 #define  TU_SIZE(x)             (((x)-1) << 25) /* default size 64 */
3294 #define  TU_SIZE_MASK           0x7e000000
3295 #define  PIPE_DATA_M1_OFFSET    0
3296 #define _PIPEA_DATA_N1           0x60034
3297 #define  PIPE_DATA_N1_OFFSET    0
3298 
3299 #define _PIPEA_DATA_M2           0x60038
3300 #define  PIPE_DATA_M2_OFFSET    0
3301 #define _PIPEA_DATA_N2           0x6003c
3302 #define  PIPE_DATA_N2_OFFSET    0
3303 
3304 #define _PIPEA_LINK_M1           0x60040
3305 #define  PIPE_LINK_M1_OFFSET    0
3306 #define _PIPEA_LINK_N1           0x60044
3307 #define  PIPE_LINK_N1_OFFSET    0
3308 
3309 #define _PIPEA_LINK_M2           0x60048
3310 #define  PIPE_LINK_M2_OFFSET    0
3311 #define _PIPEA_LINK_N2           0x6004c
3312 #define  PIPE_LINK_N2_OFFSET    0
3313 
3314 /* PIPEB timing regs are same start from 0x61000 */
3315 
3316 #define _PIPEB_DATA_M1           0x61030
3317 #define _PIPEB_DATA_N1           0x61034
3318 
3319 #define _PIPEB_DATA_M2           0x61038
3320 #define _PIPEB_DATA_N2           0x6103c
3321 
3322 #define _PIPEB_LINK_M1           0x61040
3323 #define _PIPEB_LINK_N1           0x61044
3324 
3325 #define _PIPEB_LINK_M2           0x61048
3326 #define _PIPEB_LINK_N2           0x6104c
3327 
3328 #define PIPE_DATA_M1(tran) _TRANSCODER(tran, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
3329 #define PIPE_DATA_N1(tran) _TRANSCODER(tran, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
3330 #define PIPE_DATA_M2(tran) _TRANSCODER(tran, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
3331 #define PIPE_DATA_N2(tran) _TRANSCODER(tran, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
3332 #define PIPE_LINK_M1(tran) _TRANSCODER(tran, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
3333 #define PIPE_LINK_N1(tran) _TRANSCODER(tran, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
3334 #define PIPE_LINK_M2(tran) _TRANSCODER(tran, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
3335 #define PIPE_LINK_N2(tran) _TRANSCODER(tran, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
3336 
3337 /* CPU panel fitter */
3338 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
3339 #define _PFA_CTL_1               0x68080
3340 #define _PFB_CTL_1               0x68880
3341 #define  PF_ENABLE              (1<<31)
3342 #define  PF_PIPE_SEL_MASK_IVB	(3<<29)
3343 #define  PF_PIPE_SEL_IVB(pipe)	((pipe)<<29)
3344 #define  PF_FILTER_MASK		(3<<23)
3345 #define  PF_FILTER_PROGRAMMED	(0<<23)
3346 #define  PF_FILTER_MED_3x3	(1<<23)
3347 #define  PF_FILTER_EDGE_ENHANCE	(2<<23)
3348 #define  PF_FILTER_EDGE_SOFTEN	(3<<23)
3349 #define _PFA_WIN_SZ		0x68074
3350 #define _PFB_WIN_SZ		0x68874
3351 #define _PFA_WIN_POS		0x68070
3352 #define _PFB_WIN_POS		0x68870
3353 #define _PFA_VSCALE		0x68084
3354 #define _PFB_VSCALE		0x68884
3355 #define _PFA_HSCALE		0x68090
3356 #define _PFB_HSCALE		0x68890
3357 
3358 #define PF_CTL(pipe)		_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
3359 #define PF_WIN_SZ(pipe)		_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
3360 #define PF_WIN_POS(pipe)	_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
3361 #define PF_VSCALE(pipe)		_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
3362 #define PF_HSCALE(pipe)		_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
3363 
3364 /* legacy palette */
3365 #define _LGC_PALETTE_A           0x4a000
3366 #define _LGC_PALETTE_B           0x4a800
3367 #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
3368 
3369 /* interrupts */
3370 #define DE_MASTER_IRQ_CONTROL   (1 << 31)
3371 #define DE_SPRITEB_FLIP_DONE    (1 << 29)
3372 #define DE_SPRITEA_FLIP_DONE    (1 << 28)
3373 #define DE_PLANEB_FLIP_DONE     (1 << 27)
3374 #define DE_PLANEA_FLIP_DONE     (1 << 26)
3375 #define DE_PCU_EVENT            (1 << 25)
3376 #define DE_GTT_FAULT            (1 << 24)
3377 #define DE_POISON               (1 << 23)
3378 #define DE_PERFORM_COUNTER      (1 << 22)
3379 #define DE_PCH_EVENT            (1 << 21)
3380 #define DE_AUX_CHANNEL_A        (1 << 20)
3381 #define DE_DP_A_HOTPLUG         (1 << 19)
3382 #define DE_GSE                  (1 << 18)
3383 #define DE_PIPEB_VBLANK         (1 << 15)
3384 #define DE_PIPEB_EVEN_FIELD     (1 << 14)
3385 #define DE_PIPEB_ODD_FIELD      (1 << 13)
3386 #define DE_PIPEB_LINE_COMPARE   (1 << 12)
3387 #define DE_PIPEB_VSYNC          (1 << 11)
3388 #define DE_PIPEB_FIFO_UNDERRUN  (1 << 8)
3389 #define DE_PIPEA_VBLANK         (1 << 7)
3390 #define DE_PIPEA_EVEN_FIELD     (1 << 6)
3391 #define DE_PIPEA_ODD_FIELD      (1 << 5)
3392 #define DE_PIPEA_LINE_COMPARE   (1 << 4)
3393 #define DE_PIPEA_VSYNC          (1 << 3)
3394 #define DE_PIPEA_FIFO_UNDERRUN  (1 << 0)
3395 
3396 /* More Ivybridge lolz */
3397 #define DE_ERR_DEBUG_IVB		(1<<30)
3398 #define DE_GSE_IVB			(1<<29)
3399 #define DE_PCH_EVENT_IVB		(1<<28)
3400 #define DE_DP_A_HOTPLUG_IVB		(1<<27)
3401 #define DE_AUX_CHANNEL_A_IVB		(1<<26)
3402 #define DE_SPRITEC_FLIP_DONE_IVB	(1<<14)
3403 #define DE_PLANEC_FLIP_DONE_IVB		(1<<13)
3404 #define DE_PIPEC_VBLANK_IVB		(1<<10)
3405 #define DE_SPRITEB_FLIP_DONE_IVB	(1<<9)
3406 #define DE_PLANEB_FLIP_DONE_IVB		(1<<8)
3407 #define DE_PIPEB_VBLANK_IVB		(1<<5)
3408 #define DE_SPRITEA_FLIP_DONE_IVB	(1<<4)
3409 #define DE_PLANEA_FLIP_DONE_IVB		(1<<3)
3410 #define DE_PIPEA_VBLANK_IVB		(1<<0)
3411 
3412 #define VLV_MASTER_IER			0x4400c /* Gunit master IER */
3413 #define   MASTER_INTERRUPT_ENABLE	(1<<31)
3414 
3415 #define DEISR   0x44000
3416 #define DEIMR   0x44004
3417 #define DEIIR   0x44008
3418 #define DEIER   0x4400c
3419 
3420 /* GT interrupt.
3421  * Note that for gen6+ the ring-specific interrupt bits do alias with the
3422  * corresponding bits in the per-ring interrupt control registers. */
3423 #define GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT	(1 << 26)
3424 #define GT_GEN6_BLT_CS_ERROR_INTERRUPT		(1 << 25)
3425 #define GT_GEN6_BLT_USER_INTERRUPT		(1 << 22)
3426 #define GT_GEN6_BSD_CS_ERROR_INTERRUPT		(1 << 15)
3427 #define GT_GEN6_BSD_USER_INTERRUPT		(1 << 12)
3428 #define GT_BSD_USER_INTERRUPT			(1 << 5) /* ilk only */
3429 #define GT_GEN7_L3_PARITY_ERROR_INTERRUPT	(1 << 5)
3430 #define GT_PIPE_NOTIFY				(1 << 4)
3431 #define GT_RENDER_CS_ERROR_INTERRUPT		(1 << 3)
3432 #define GT_SYNC_STATUS				(1 << 2)
3433 #define GT_USER_INTERRUPT			(1 << 0)
3434 
3435 #define GTISR   0x44010
3436 #define GTIMR   0x44014
3437 #define GTIIR   0x44018
3438 #define GTIER   0x4401c
3439 
3440 #define ILK_DISPLAY_CHICKEN2	0x42004
3441 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
3442 #define  ILK_ELPIN_409_SELECT	(1 << 25)
3443 #define  ILK_DPARB_GATE	(1<<22)
3444 #define  ILK_VSDPFD_FULL	(1<<21)
3445 #define ILK_DISPLAY_CHICKEN_FUSES	0x42014
3446 #define  ILK_INTERNAL_GRAPHICS_DISABLE	(1<<31)
3447 #define  ILK_INTERNAL_DISPLAY_DISABLE	(1<<30)
3448 #define  ILK_DISPLAY_DEBUG_DISABLE	(1<<29)
3449 #define  ILK_HDCP_DISABLE		(1<<25)
3450 #define  ILK_eDP_A_DISABLE		(1<<24)
3451 #define  ILK_DESKTOP			(1<<23)
3452 
3453 #define ILK_DSPCLK_GATE_D			0x42020
3454 #define   ILK_VRHUNIT_CLOCK_GATE_DISABLE	(1 << 28)
3455 #define   ILK_DPFCUNIT_CLOCK_GATE_DISABLE	(1 << 9)
3456 #define   ILK_DPFCRUNIT_CLOCK_GATE_DISABLE	(1 << 8)
3457 #define   ILK_DPFDUNIT_CLOCK_GATE_ENABLE	(1 << 7)
3458 #define   ILK_DPARBUNIT_CLOCK_GATE_ENABLE	(1 << 5)
3459 
3460 #define IVB_CHICKEN3	0x4200c
3461 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE	(1 << 5)
3462 # define CHICKEN3_DGMG_DONE_FIX_DISABLE		(1 << 2)
3463 
3464 #define DISP_ARB_CTL	0x45000
3465 #define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)
3466 #define  DISP_FBC_WM_DIS		(1<<15)
3467 
3468 /* GEN7 chicken */
3469 #define GEN7_COMMON_SLICE_CHICKEN1		0x7010
3470 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	((1<<10) | (1<<26))
3471 
3472 #define GEN7_L3CNTLREG1				0xB01C
3473 #define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C4FFF8C
3474 #define  GEN7_L3AGDIS				(1<<19)
3475 
3476 #define GEN7_L3_CHICKEN_MODE_REGISTER		0xB030
3477 #define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
3478 
3479 #define GEN7_L3SQCREG4				0xb034
3480 #define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
3481 
3482 /* WaCatErrorRejectionIssue */
3483 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
3484 #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
3485 
3486 #define HSW_FUSE_STRAP		0x42014
3487 #define  HSW_CDCLK_LIMIT	(1 << 24)
3488 
3489 /* PCH */
3490 
3491 /* south display engine interrupt: IBX */
3492 #define SDE_AUDIO_POWER_D	(1 << 27)
3493 #define SDE_AUDIO_POWER_C	(1 << 26)
3494 #define SDE_AUDIO_POWER_B	(1 << 25)
3495 #define SDE_AUDIO_POWER_SHIFT	(25)
3496 #define SDE_AUDIO_POWER_MASK	(7 << SDE_AUDIO_POWER_SHIFT)
3497 #define SDE_GMBUS		(1 << 24)
3498 #define SDE_AUDIO_HDCP_TRANSB	(1 << 23)
3499 #define SDE_AUDIO_HDCP_TRANSA	(1 << 22)
3500 #define SDE_AUDIO_HDCP_MASK	(3 << 22)
3501 #define SDE_AUDIO_TRANSB	(1 << 21)
3502 #define SDE_AUDIO_TRANSA	(1 << 20)
3503 #define SDE_AUDIO_TRANS_MASK	(3 << 20)
3504 #define SDE_POISON		(1 << 19)
3505 /* 18 reserved */
3506 #define SDE_FDI_RXB		(1 << 17)
3507 #define SDE_FDI_RXA		(1 << 16)
3508 #define SDE_FDI_MASK		(3 << 16)
3509 #define SDE_AUXD		(1 << 15)
3510 #define SDE_AUXC		(1 << 14)
3511 #define SDE_AUXB		(1 << 13)
3512 #define SDE_AUX_MASK		(7 << 13)
3513 /* 12 reserved */
3514 #define SDE_CRT_HOTPLUG         (1 << 11)
3515 #define SDE_PORTD_HOTPLUG       (1 << 10)
3516 #define SDE_PORTC_HOTPLUG       (1 << 9)
3517 #define SDE_PORTB_HOTPLUG       (1 << 8)
3518 #define SDE_SDVOB_HOTPLUG       (1 << 6)
3519 #define SDE_HOTPLUG_MASK	(0xf << 8)
3520 #define SDE_TRANSB_CRC_DONE	(1 << 5)
3521 #define SDE_TRANSB_CRC_ERR	(1 << 4)
3522 #define SDE_TRANSB_FIFO_UNDER	(1 << 3)
3523 #define SDE_TRANSA_CRC_DONE	(1 << 2)
3524 #define SDE_TRANSA_CRC_ERR	(1 << 1)
3525 #define SDE_TRANSA_FIFO_UNDER	(1 << 0)
3526 #define SDE_TRANS_MASK		(0x3f)
3527 
3528 /* south display engine interrupt: CPT/PPT */
3529 #define SDE_AUDIO_POWER_D_CPT	(1 << 31)
3530 #define SDE_AUDIO_POWER_C_CPT	(1 << 30)
3531 #define SDE_AUDIO_POWER_B_CPT	(1 << 29)
3532 #define SDE_AUDIO_POWER_SHIFT_CPT   29
3533 #define SDE_AUDIO_POWER_MASK_CPT    (7 << 29)
3534 #define SDE_AUXD_CPT		(1 << 27)
3535 #define SDE_AUXC_CPT		(1 << 26)
3536 #define SDE_AUXB_CPT		(1 << 25)
3537 #define SDE_AUX_MASK_CPT	(7 << 25)
3538 #define SDE_PORTD_HOTPLUG_CPT	(1 << 23)
3539 #define SDE_PORTC_HOTPLUG_CPT	(1 << 22)
3540 #define SDE_PORTB_HOTPLUG_CPT	(1 << 21)
3541 #define SDE_CRT_HOTPLUG_CPT	(1 << 19)
3542 #define SDE_HOTPLUG_MASK_CPT	(SDE_CRT_HOTPLUG_CPT |		\
3543 				 SDE_PORTD_HOTPLUG_CPT |	\
3544 				 SDE_PORTC_HOTPLUG_CPT |	\
3545 				 SDE_PORTB_HOTPLUG_CPT)
3546 #define SDE_GMBUS_CPT		(1 << 17)
3547 #define SDE_AUDIO_CP_REQ_C_CPT	(1 << 10)
3548 #define SDE_AUDIO_CP_CHG_C_CPT	(1 << 9)
3549 #define SDE_FDI_RXC_CPT		(1 << 8)
3550 #define SDE_AUDIO_CP_REQ_B_CPT	(1 << 6)
3551 #define SDE_AUDIO_CP_CHG_B_CPT	(1 << 5)
3552 #define SDE_FDI_RXB_CPT		(1 << 4)
3553 #define SDE_AUDIO_CP_REQ_A_CPT	(1 << 2)
3554 #define SDE_AUDIO_CP_CHG_A_CPT	(1 << 1)
3555 #define SDE_FDI_RXA_CPT		(1 << 0)
3556 #define SDE_AUDIO_CP_REQ_CPT	(SDE_AUDIO_CP_REQ_C_CPT | \
3557 				 SDE_AUDIO_CP_REQ_B_CPT | \
3558 				 SDE_AUDIO_CP_REQ_A_CPT)
3559 #define SDE_AUDIO_CP_CHG_CPT	(SDE_AUDIO_CP_CHG_C_CPT | \
3560 				 SDE_AUDIO_CP_CHG_B_CPT | \
3561 				 SDE_AUDIO_CP_CHG_A_CPT)
3562 #define SDE_FDI_MASK_CPT	(SDE_FDI_RXC_CPT | \
3563 				 SDE_FDI_RXB_CPT | \
3564 				 SDE_FDI_RXA_CPT)
3565 
3566 #define SDEISR  0xc4000
3567 #define SDEIMR  0xc4004
3568 #define SDEIIR  0xc4008
3569 #define SDEIER  0xc400c
3570 
3571 /* digital port hotplug */
3572 #define PCH_PORT_HOTPLUG        0xc4030		/* SHOTPLUG_CTL */
3573 #define PORTD_HOTPLUG_ENABLE            (1 << 20)
3574 #define PORTD_PULSE_DURATION_2ms        (0)
3575 #define PORTD_PULSE_DURATION_4_5ms      (1 << 18)
3576 #define PORTD_PULSE_DURATION_6ms        (2 << 18)
3577 #define PORTD_PULSE_DURATION_100ms      (3 << 18)
3578 #define PORTD_PULSE_DURATION_MASK	(3 << 18)
3579 #define PORTD_HOTPLUG_NO_DETECT         (0)
3580 #define PORTD_HOTPLUG_SHORT_DETECT      (1 << 16)
3581 #define PORTD_HOTPLUG_LONG_DETECT       (1 << 17)
3582 #define PORTC_HOTPLUG_ENABLE            (1 << 12)
3583 #define PORTC_PULSE_DURATION_2ms        (0)
3584 #define PORTC_PULSE_DURATION_4_5ms      (1 << 10)
3585 #define PORTC_PULSE_DURATION_6ms        (2 << 10)
3586 #define PORTC_PULSE_DURATION_100ms      (3 << 10)
3587 #define PORTC_PULSE_DURATION_MASK	(3 << 10)
3588 #define PORTC_HOTPLUG_NO_DETECT         (0)
3589 #define PORTC_HOTPLUG_SHORT_DETECT      (1 << 8)
3590 #define PORTC_HOTPLUG_LONG_DETECT       (1 << 9)
3591 #define PORTB_HOTPLUG_ENABLE            (1 << 4)
3592 #define PORTB_PULSE_DURATION_2ms        (0)
3593 #define PORTB_PULSE_DURATION_4_5ms      (1 << 2)
3594 #define PORTB_PULSE_DURATION_6ms        (2 << 2)
3595 #define PORTB_PULSE_DURATION_100ms      (3 << 2)
3596 #define PORTB_PULSE_DURATION_MASK	(3 << 2)
3597 #define PORTB_HOTPLUG_NO_DETECT         (0)
3598 #define PORTB_HOTPLUG_SHORT_DETECT      (1 << 0)
3599 #define PORTB_HOTPLUG_LONG_DETECT       (1 << 1)
3600 
3601 #define PCH_GPIOA               0xc5010
3602 #define PCH_GPIOB               0xc5014
3603 #define PCH_GPIOC               0xc5018
3604 #define PCH_GPIOD               0xc501c
3605 #define PCH_GPIOE               0xc5020
3606 #define PCH_GPIOF               0xc5024
3607 
3608 #define PCH_GMBUS0		0xc5100
3609 #define PCH_GMBUS1		0xc5104
3610 #define PCH_GMBUS2		0xc5108
3611 #define PCH_GMBUS3		0xc510c
3612 #define PCH_GMBUS4		0xc5110
3613 #define PCH_GMBUS5		0xc5120
3614 
3615 #define _PCH_DPLL_A              0xc6014
3616 #define _PCH_DPLL_B              0xc6018
3617 #define _PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
3618 
3619 #define _PCH_FPA0                0xc6040
3620 #define  FP_CB_TUNE		(0x3<<22)
3621 #define _PCH_FPA1                0xc6044
3622 #define _PCH_FPB0                0xc6048
3623 #define _PCH_FPB1                0xc604c
3624 #define _PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
3625 #define _PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
3626 
3627 #define PCH_DPLL_TEST           0xc606c
3628 
3629 #define PCH_DREF_CONTROL        0xC6200
3630 #define  DREF_CONTROL_MASK      0x7fc3
3631 #define  DREF_CPU_SOURCE_OUTPUT_DISABLE         (0<<13)
3632 #define  DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD      (2<<13)
3633 #define  DREF_CPU_SOURCE_OUTPUT_NONSPREAD       (3<<13)
3634 #define  DREF_CPU_SOURCE_OUTPUT_MASK		(3<<13)
3635 #define  DREF_SSC_SOURCE_DISABLE                (0<<11)
3636 #define  DREF_SSC_SOURCE_ENABLE                 (2<<11)
3637 #define  DREF_SSC_SOURCE_MASK			(3<<11)
3638 #define  DREF_NONSPREAD_SOURCE_DISABLE          (0<<9)
3639 #define  DREF_NONSPREAD_CK505_ENABLE		(1<<9)
3640 #define  DREF_NONSPREAD_SOURCE_ENABLE           (2<<9)
3641 #define  DREF_NONSPREAD_SOURCE_MASK		(3<<9)
3642 #define  DREF_SUPERSPREAD_SOURCE_DISABLE        (0<<7)
3643 #define  DREF_SUPERSPREAD_SOURCE_ENABLE         (2<<7)
3644 #define  DREF_SUPERSPREAD_SOURCE_MASK		(3<<7)
3645 #define  DREF_SSC4_DOWNSPREAD                   (0<<6)
3646 #define  DREF_SSC4_CENTERSPREAD                 (1<<6)
3647 #define  DREF_SSC1_DISABLE                      (0<<1)
3648 #define  DREF_SSC1_ENABLE                       (1<<1)
3649 #define  DREF_SSC4_DISABLE                      (0)
3650 #define  DREF_SSC4_ENABLE                       (1)
3651 
3652 #define PCH_RAWCLK_FREQ         0xc6204
3653 #define  FDL_TP1_TIMER_SHIFT    12
3654 #define  FDL_TP1_TIMER_MASK     (3<<12)
3655 #define  FDL_TP2_TIMER_SHIFT    10
3656 #define  FDL_TP2_TIMER_MASK     (3<<10)
3657 #define  RAWCLK_FREQ_MASK       0x3ff
3658 
3659 #define PCH_DPLL_TMR_CFG        0xc6208
3660 
3661 #define PCH_SSC4_PARMS          0xc6210
3662 #define PCH_SSC4_AUX_PARMS      0xc6214
3663 
3664 #define PCH_DPLL_SEL		0xc7000
3665 #define  TRANSA_DPLL_ENABLE	(1<<3)
3666 #define	 TRANSA_DPLLB_SEL	(1<<0)
3667 #define	 TRANSA_DPLLA_SEL	0
3668 #define  TRANSB_DPLL_ENABLE	(1<<7)
3669 #define	 TRANSB_DPLLB_SEL	(1<<4)
3670 #define	 TRANSB_DPLLA_SEL	(0)
3671 #define  TRANSC_DPLL_ENABLE	(1<<11)
3672 #define	 TRANSC_DPLLB_SEL	(1<<8)
3673 #define	 TRANSC_DPLLA_SEL	(0)
3674 
3675 /* transcoder */
3676 
3677 #define _TRANS_HTOTAL_A          0xe0000
3678 #define  TRANS_HTOTAL_SHIFT     16
3679 #define  TRANS_HACTIVE_SHIFT    0
3680 #define _TRANS_HBLANK_A          0xe0004
3681 #define  TRANS_HBLANK_END_SHIFT 16
3682 #define  TRANS_HBLANK_START_SHIFT 0
3683 #define _TRANS_HSYNC_A           0xe0008
3684 #define  TRANS_HSYNC_END_SHIFT  16
3685 #define  TRANS_HSYNC_START_SHIFT 0
3686 #define _TRANS_VTOTAL_A          0xe000c
3687 #define  TRANS_VTOTAL_SHIFT     16
3688 #define  TRANS_VACTIVE_SHIFT    0
3689 #define _TRANS_VBLANK_A          0xe0010
3690 #define  TRANS_VBLANK_END_SHIFT 16
3691 #define  TRANS_VBLANK_START_SHIFT 0
3692 #define _TRANS_VSYNC_A           0xe0014
3693 #define  TRANS_VSYNC_END_SHIFT  16
3694 #define  TRANS_VSYNC_START_SHIFT 0
3695 #define _TRANS_VSYNCSHIFT_A	0xe0028
3696 
3697 #define _TRANSA_DATA_M1          0xe0030
3698 #define _TRANSA_DATA_N1          0xe0034
3699 #define _TRANSA_DATA_M2          0xe0038
3700 #define _TRANSA_DATA_N2          0xe003c
3701 #define _TRANSA_DP_LINK_M1       0xe0040
3702 #define _TRANSA_DP_LINK_N1       0xe0044
3703 #define _TRANSA_DP_LINK_M2       0xe0048
3704 #define _TRANSA_DP_LINK_N2       0xe004c
3705 
3706 /* Per-transcoder DIP controls */
3707 
3708 #define _VIDEO_DIP_CTL_A         0xe0200
3709 #define _VIDEO_DIP_DATA_A        0xe0208
3710 #define _VIDEO_DIP_GCP_A         0xe0210
3711 
3712 #define _VIDEO_DIP_CTL_B         0xe1200
3713 #define _VIDEO_DIP_DATA_B        0xe1208
3714 #define _VIDEO_DIP_GCP_B         0xe1210
3715 
3716 #define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
3717 #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
3718 #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
3719 
3720 #define VLV_VIDEO_DIP_CTL_A		0x60200
3721 #define VLV_VIDEO_DIP_DATA_A		0x60208
3722 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A	0x60210
3723 
3724 #define VLV_VIDEO_DIP_CTL_B		0x61170
3725 #define VLV_VIDEO_DIP_DATA_B		0x61174
3726 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_B	0x61178
3727 
3728 #define VLV_TVIDEO_DIP_CTL(pipe) \
3729 	 _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B)
3730 #define VLV_TVIDEO_DIP_DATA(pipe) \
3731 	 _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B)
3732 #define VLV_TVIDEO_DIP_GCP(pipe) \
3733 	_PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
3734 
3735 /* Haswell DIP controls */
3736 #define HSW_VIDEO_DIP_CTL_A		0x60200
3737 #define HSW_VIDEO_DIP_AVI_DATA_A	0x60220
3738 #define HSW_VIDEO_DIP_VS_DATA_A		0x60260
3739 #define HSW_VIDEO_DIP_SPD_DATA_A	0x602A0
3740 #define HSW_VIDEO_DIP_GMP_DATA_A	0x602E0
3741 #define HSW_VIDEO_DIP_VSC_DATA_A	0x60320
3742 #define HSW_VIDEO_DIP_AVI_ECC_A		0x60240
3743 #define HSW_VIDEO_DIP_VS_ECC_A		0x60280
3744 #define HSW_VIDEO_DIP_SPD_ECC_A		0x602C0
3745 #define HSW_VIDEO_DIP_GMP_ECC_A		0x60300
3746 #define HSW_VIDEO_DIP_VSC_ECC_A		0x60344
3747 #define HSW_VIDEO_DIP_GCP_A		0x60210
3748 
3749 #define HSW_VIDEO_DIP_CTL_B		0x61200
3750 #define HSW_VIDEO_DIP_AVI_DATA_B	0x61220
3751 #define HSW_VIDEO_DIP_VS_DATA_B		0x61260
3752 #define HSW_VIDEO_DIP_SPD_DATA_B	0x612A0
3753 #define HSW_VIDEO_DIP_GMP_DATA_B	0x612E0
3754 #define HSW_VIDEO_DIP_VSC_DATA_B	0x61320
3755 #define HSW_VIDEO_DIP_BVI_ECC_B		0x61240
3756 #define HSW_VIDEO_DIP_VS_ECC_B		0x61280
3757 #define HSW_VIDEO_DIP_SPD_ECC_B		0x612C0
3758 #define HSW_VIDEO_DIP_GMP_ECC_B		0x61300
3759 #define HSW_VIDEO_DIP_VSC_ECC_B		0x61344
3760 #define HSW_VIDEO_DIP_GCP_B		0x61210
3761 
3762 #define HSW_TVIDEO_DIP_CTL(pipe) \
3763 	 _PIPE(pipe, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B)
3764 #define HSW_TVIDEO_DIP_AVI_DATA(pipe) \
3765 	 _PIPE(pipe, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B)
3766 #define HSW_TVIDEO_DIP_SPD_DATA(pipe) \
3767 	 _PIPE(pipe, HSW_VIDEO_DIP_SPD_DATA_A, HSW_VIDEO_DIP_SPD_DATA_B)
3768 #define HSW_TVIDEO_DIP_GCP(pipe) \
3769 	_PIPE(pipe, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B)
3770 
3771 #define _TRANS_HTOTAL_B          0xe1000
3772 #define _TRANS_HBLANK_B          0xe1004
3773 #define _TRANS_HSYNC_B           0xe1008
3774 #define _TRANS_VTOTAL_B          0xe100c
3775 #define _TRANS_VBLANK_B          0xe1010
3776 #define _TRANS_VSYNC_B           0xe1014
3777 #define _TRANS_VSYNCSHIFT_B	 0xe1028
3778 
3779 #define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B)
3780 #define TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B)
3781 #define TRANS_HSYNC(pipe) _PIPE(pipe, _TRANS_HSYNC_A, _TRANS_HSYNC_B)
3782 #define TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B)
3783 #define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B)
3784 #define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B)
3785 #define TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _TRANS_VSYNCSHIFT_A, \
3786 				     _TRANS_VSYNCSHIFT_B)
3787 
3788 #define _TRANSB_DATA_M1          0xe1030
3789 #define _TRANSB_DATA_N1          0xe1034
3790 #define _TRANSB_DATA_M2          0xe1038
3791 #define _TRANSB_DATA_N2          0xe103c
3792 #define _TRANSB_DP_LINK_M1       0xe1040
3793 #define _TRANSB_DP_LINK_N1       0xe1044
3794 #define _TRANSB_DP_LINK_M2       0xe1048
3795 #define _TRANSB_DP_LINK_N2       0xe104c
3796 
3797 #define TRANSDATA_M1(pipe) _PIPE(pipe, _TRANSA_DATA_M1, _TRANSB_DATA_M1)
3798 #define TRANSDATA_N1(pipe) _PIPE(pipe, _TRANSA_DATA_N1, _TRANSB_DATA_N1)
3799 #define TRANSDATA_M2(pipe) _PIPE(pipe, _TRANSA_DATA_M2, _TRANSB_DATA_M2)
3800 #define TRANSDATA_N2(pipe) _PIPE(pipe, _TRANSA_DATA_N2, _TRANSB_DATA_N2)
3801 #define TRANSDPLINK_M1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M1, _TRANSB_DP_LINK_M1)
3802 #define TRANSDPLINK_N1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N1, _TRANSB_DP_LINK_N1)
3803 #define TRANSDPLINK_M2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M2, _TRANSB_DP_LINK_M2)
3804 #define TRANSDPLINK_N2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N2, _TRANSB_DP_LINK_N2)
3805 
3806 #define _TRANSACONF              0xf0008
3807 #define _TRANSBCONF              0xf1008
3808 #define TRANSCONF(plane) _PIPE(plane, _TRANSACONF, _TRANSBCONF)
3809 #define  TRANS_DISABLE          (0<<31)
3810 #define  TRANS_ENABLE           (1<<31)
3811 #define  TRANS_STATE_MASK       (1<<30)
3812 #define  TRANS_STATE_DISABLE    (0<<30)
3813 #define  TRANS_STATE_ENABLE     (1<<30)
3814 #define  TRANS_FSYNC_DELAY_HB1  (0<<27)
3815 #define  TRANS_FSYNC_DELAY_HB2  (1<<27)
3816 #define  TRANS_FSYNC_DELAY_HB3  (2<<27)
3817 #define  TRANS_FSYNC_DELAY_HB4  (3<<27)
3818 #define  TRANS_DP_AUDIO_ONLY    (1<<26)
3819 #define  TRANS_DP_VIDEO_AUDIO   (0<<26)
3820 #define  TRANS_INTERLACE_MASK   (7<<21)
3821 #define  TRANS_PROGRESSIVE      (0<<21)
3822 #define  TRANS_INTERLACED       (3<<21)
3823 #define  TRANS_LEGACY_INTERLACED_ILK (2<<21)
3824 #define  TRANS_8BPC             (0<<5)
3825 #define  TRANS_10BPC            (1<<5)
3826 #define  TRANS_6BPC             (2<<5)
3827 #define  TRANS_12BPC            (3<<5)
3828 
3829 #define _TRANSA_CHICKEN1	 0xf0060
3830 #define _TRANSB_CHICKEN1	 0xf1060
3831 #define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
3832 #define  TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	(1<<4)
3833 #define _TRANSA_CHICKEN2	 0xf0064
3834 #define _TRANSB_CHICKEN2	 0xf1064
3835 #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
3836 #define  TRANS_CHICKEN2_TIMING_OVERRIDE		(1<<31)
3837 
3838 
3839 #define SOUTH_CHICKEN1		0xc2000
3840 #define  FDIA_PHASE_SYNC_SHIFT_OVR	19
3841 #define  FDIA_PHASE_SYNC_SHIFT_EN	18
3842 #define  FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
3843 #define  FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
3844 #define  FDI_BC_BIFURCATION_SELECT	(1 << 12)
3845 #define SOUTH_CHICKEN2		0xc2004
3846 #define  FDI_MPHY_IOSFSB_RESET_STATUS	(1<<13)
3847 #define  FDI_MPHY_IOSFSB_RESET_CTL	(1<<12)
3848 #define  DPLS_EDP_PPS_FIX_DIS		(1<<0)
3849 
3850 #define _FDI_RXA_CHICKEN         0xc200c
3851 #define _FDI_RXB_CHICKEN         0xc2010
3852 #define  FDI_RX_PHASE_SYNC_POINTER_OVR	(1<<1)
3853 #define  FDI_RX_PHASE_SYNC_POINTER_EN	(1<<0)
3854 #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
3855 
3856 #define SOUTH_DSPCLK_GATE_D	0xc2020
3857 #define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
3858 #define  PCH_LP_PARTITION_LEVEL_DISABLE  (1<<12)
3859 
3860 /* CPU: FDI_TX */
3861 #define _FDI_TXA_CTL             0x60100
3862 #define _FDI_TXB_CTL             0x61100
3863 #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
3864 #define  FDI_TX_DISABLE         (0<<31)
3865 #define  FDI_TX_ENABLE          (1<<31)
3866 #define  FDI_LINK_TRAIN_PATTERN_1       (0<<28)
3867 #define  FDI_LINK_TRAIN_PATTERN_2       (1<<28)
3868 #define  FDI_LINK_TRAIN_PATTERN_IDLE    (2<<28)
3869 #define  FDI_LINK_TRAIN_NONE            (3<<28)
3870 #define  FDI_LINK_TRAIN_VOLTAGE_0_4V    (0<<25)
3871 #define  FDI_LINK_TRAIN_VOLTAGE_0_6V    (1<<25)
3872 #define  FDI_LINK_TRAIN_VOLTAGE_0_8V    (2<<25)
3873 #define  FDI_LINK_TRAIN_VOLTAGE_1_2V    (3<<25)
3874 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
3875 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
3876 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_2X   (2<<22)
3877 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_3X   (3<<22)
3878 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
3879    SNB has different settings. */
3880 /* SNB A-stepping */
3881 #define  FDI_LINK_TRAIN_400MV_0DB_SNB_A		(0x38<<22)
3882 #define  FDI_LINK_TRAIN_400MV_6DB_SNB_A		(0x02<<22)
3883 #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_A	(0x01<<22)
3884 #define  FDI_LINK_TRAIN_800MV_0DB_SNB_A		(0x0<<22)
3885 /* SNB B-stepping */
3886 #define  FDI_LINK_TRAIN_400MV_0DB_SNB_B		(0x0<<22)
3887 #define  FDI_LINK_TRAIN_400MV_6DB_SNB_B		(0x3a<<22)
3888 #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_B	(0x39<<22)
3889 #define  FDI_LINK_TRAIN_800MV_0DB_SNB_B		(0x38<<22)
3890 #define  FDI_LINK_TRAIN_VOL_EMP_MASK		(0x3f<<22)
3891 #define  FDI_DP_PORT_WIDTH_X1           (0<<19)
3892 #define  FDI_DP_PORT_WIDTH_X2           (1<<19)
3893 #define  FDI_DP_PORT_WIDTH_X3           (2<<19)
3894 #define  FDI_DP_PORT_WIDTH_X4           (3<<19)
3895 #define  FDI_TX_ENHANCE_FRAME_ENABLE    (1<<18)
3896 /* Ironlake: hardwired to 1 */
3897 #define  FDI_TX_PLL_ENABLE              (1<<14)
3898 
3899 /* Ivybridge has different bits for lolz */
3900 #define  FDI_LINK_TRAIN_PATTERN_1_IVB       (0<<8)
3901 #define  FDI_LINK_TRAIN_PATTERN_2_IVB       (1<<8)
3902 #define  FDI_LINK_TRAIN_PATTERN_IDLE_IVB    (2<<8)
3903 #define  FDI_LINK_TRAIN_NONE_IVB            (3<<8)
3904 
3905 /* both Tx and Rx */
3906 #define  FDI_COMPOSITE_SYNC		(1<<11)
3907 #define  FDI_LINK_TRAIN_AUTO		(1<<10)
3908 #define  FDI_SCRAMBLING_ENABLE          (0<<7)
3909 #define  FDI_SCRAMBLING_DISABLE         (1<<7)
3910 
3911 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
3912 #define _FDI_RXA_CTL             0xf000c
3913 #define _FDI_RXB_CTL             0xf100c
3914 #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
3915 #define  FDI_RX_ENABLE          (1<<31)
3916 /* train, dp width same as FDI_TX */
3917 #define  FDI_FS_ERRC_ENABLE		(1<<27)
3918 #define  FDI_FE_ERRC_ENABLE		(1<<26)
3919 #define  FDI_DP_PORT_WIDTH_X8           (7<<19)
3920 #define  FDI_RX_POLARITY_REVERSED_LPT	(1<<16)
3921 #define  FDI_8BPC                       (0<<16)
3922 #define  FDI_10BPC                      (1<<16)
3923 #define  FDI_6BPC                       (2<<16)
3924 #define  FDI_12BPC                      (3<<16)
3925 #define  FDI_LINK_REVERSE_OVERWRITE     (1<<15)
3926 #define  FDI_DMI_LINK_REVERSE_MASK      (1<<14)
3927 #define  FDI_RX_PLL_ENABLE              (1<<13)
3928 #define  FDI_FS_ERR_CORRECT_ENABLE      (1<<11)
3929 #define  FDI_FE_ERR_CORRECT_ENABLE      (1<<10)
3930 #define  FDI_FS_ERR_REPORT_ENABLE       (1<<9)
3931 #define  FDI_FE_ERR_REPORT_ENABLE       (1<<8)
3932 #define  FDI_RX_ENHANCE_FRAME_ENABLE    (1<<6)
3933 #define  FDI_PCDCLK	                (1<<4)
3934 /* CPT */
3935 #define  FDI_AUTO_TRAINING			(1<<10)
3936 #define  FDI_LINK_TRAIN_PATTERN_1_CPT		(0<<8)
3937 #define  FDI_LINK_TRAIN_PATTERN_2_CPT		(1<<8)
3938 #define  FDI_LINK_TRAIN_PATTERN_IDLE_CPT	(2<<8)
3939 #define  FDI_LINK_TRAIN_NORMAL_CPT		(3<<8)
3940 #define  FDI_LINK_TRAIN_PATTERN_MASK_CPT	(3<<8)
3941 /* LPT */
3942 #define  FDI_PORT_WIDTH_2X_LPT			(1<<19)
3943 #define  FDI_PORT_WIDTH_1X_LPT			(0<<19)
3944 
3945 #define _FDI_RXA_MISC			0xf0010
3946 #define _FDI_RXB_MISC			0xf1010
3947 #define  FDI_RX_PWRDN_LANE1_MASK	(3<<26)
3948 #define  FDI_RX_PWRDN_LANE1_VAL(x)	((x)<<26)
3949 #define  FDI_RX_PWRDN_LANE0_MASK	(3<<24)
3950 #define  FDI_RX_PWRDN_LANE0_VAL(x)	((x)<<24)
3951 #define  FDI_RX_TP1_TO_TP2_48		(2<<20)
3952 #define  FDI_RX_TP1_TO_TP2_64		(3<<20)
3953 #define  FDI_RX_FDI_DELAY_90		(0x90<<0)
3954 #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
3955 
3956 #define _FDI_RXA_TUSIZE1         0xf0030
3957 #define _FDI_RXA_TUSIZE2         0xf0038
3958 #define _FDI_RXB_TUSIZE1         0xf1030
3959 #define _FDI_RXB_TUSIZE2         0xf1038
3960 #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
3961 #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
3962 
3963 /* FDI_RX interrupt register format */
3964 #define FDI_RX_INTER_LANE_ALIGN         (1<<10)
3965 #define FDI_RX_SYMBOL_LOCK              (1<<9) /* train 2 */
3966 #define FDI_RX_BIT_LOCK                 (1<<8) /* train 1 */
3967 #define FDI_RX_TRAIN_PATTERN_2_FAIL     (1<<7)
3968 #define FDI_RX_FS_CODE_ERR              (1<<6)
3969 #define FDI_RX_FE_CODE_ERR              (1<<5)
3970 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE    (1<<4)
3971 #define FDI_RX_HDCP_LINK_FAIL           (1<<3)
3972 #define FDI_RX_PIXEL_FIFO_OVERFLOW      (1<<2)
3973 #define FDI_RX_CROSS_CLOCK_OVERFLOW     (1<<1)
3974 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW    (1<<0)
3975 
3976 #define _FDI_RXA_IIR             0xf0014
3977 #define _FDI_RXA_IMR             0xf0018
3978 #define _FDI_RXB_IIR             0xf1014
3979 #define _FDI_RXB_IMR             0xf1018
3980 #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
3981 #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
3982 
3983 #define FDI_PLL_CTL_1           0xfe000
3984 #define FDI_PLL_CTL_2           0xfe004
3985 
3986 /* or SDVOB */
3987 #define HDMIB   0xe1140
3988 #define  PORT_ENABLE    (1 << 31)
3989 #define  TRANSCODER(pipe)       ((pipe) << 30)
3990 #define  TRANSCODER_CPT(pipe)   ((pipe) << 29)
3991 #define  TRANSCODER_MASK        (1 << 30)
3992 #define  TRANSCODER_MASK_CPT    (3 << 29)
3993 #define  COLOR_FORMAT_8bpc      (0)
3994 #define  COLOR_FORMAT_12bpc     (3 << 26)
3995 #define  SDVOB_HOTPLUG_ENABLE   (1 << 23)
3996 #define  SDVO_ENCODING          (0)
3997 #define  TMDS_ENCODING          (2 << 10)
3998 #define  NULL_PACKET_VSYNC_ENABLE       (1 << 9)
3999 /* CPT */
4000 #define  HDMI_MODE_SELECT	(1 << 9)
4001 #define  DVI_MODE_SELECT	(0)
4002 #define  SDVOB_BORDER_ENABLE    (1 << 7)
4003 #define  AUDIO_ENABLE           (1 << 6)
4004 #define  VSYNC_ACTIVE_HIGH      (1 << 4)
4005 #define  HSYNC_ACTIVE_HIGH      (1 << 3)
4006 #define  PORT_DETECTED          (1 << 2)
4007 
4008 /* PCH SDVOB multiplex with HDMIB */
4009 #define PCH_SDVOB	HDMIB
4010 
4011 #define HDMIC   0xe1150
4012 #define HDMID   0xe1160
4013 
4014 #define PCH_LVDS	0xe1180
4015 #define  LVDS_DETECTED	(1 << 1)
4016 
4017 /* vlv has 2 sets of panel control regs. */
4018 #define PIPEA_PP_STATUS         0x61200
4019 #define PIPEA_PP_CONTROL        0x61204
4020 #define PIPEA_PP_ON_DELAYS      0x61208
4021 #define PIPEA_PP_OFF_DELAYS     0x6120c
4022 #define PIPEA_PP_DIVISOR        0x61210
4023 
4024 #define PIPEB_PP_STATUS         0x61300
4025 #define PIPEB_PP_CONTROL        0x61304
4026 #define PIPEB_PP_ON_DELAYS      0x61308
4027 #define PIPEB_PP_OFF_DELAYS     0x6130c
4028 #define PIPEB_PP_DIVISOR        0x61310
4029 
4030 #define PCH_PP_STATUS		0xc7200
4031 #define PCH_PP_CONTROL		0xc7204
4032 #define  PANEL_UNLOCK_REGS	(0xabcd << 16)
4033 #define  PANEL_UNLOCK_MASK	(0xffff << 16)
4034 #define  EDP_FORCE_VDD		(1 << 3)
4035 #define  EDP_BLC_ENABLE		(1 << 2)
4036 #define  PANEL_POWER_RESET	(1 << 1)
4037 #define  PANEL_POWER_OFF	(0 << 0)
4038 #define  PANEL_POWER_ON		(1 << 0)
4039 #define PCH_PP_ON_DELAYS	0xc7208
4040 #define  PANEL_PORT_SELECT_MASK	(3 << 30)
4041 #define  PANEL_PORT_SELECT_LVDS	(0 << 30)
4042 #define  PANEL_PORT_SELECT_DPA	(1 << 30)
4043 #define  EDP_PANEL		(1 << 30)
4044 #define  PANEL_PORT_SELECT_DPC	(2 << 30)
4045 #define  PANEL_PORT_SELECT_DPD	(3 << 30)
4046 #define  PANEL_POWER_UP_DELAY_MASK	(0x1fff0000)
4047 #define  PANEL_POWER_UP_DELAY_SHIFT	16
4048 #define  PANEL_LIGHT_ON_DELAY_MASK	(0x1fff)
4049 #define  PANEL_LIGHT_ON_DELAY_SHIFT	0
4050 
4051 #define PCH_PP_OFF_DELAYS	0xc720c
4052 #define  PANEL_POWER_PORT_SELECT_MASK	(0x3 << 30)
4053 #define  PANEL_POWER_PORT_LVDS		(0 << 30)
4054 #define  PANEL_POWER_PORT_DP_A		(1 << 30)
4055 #define  PANEL_POWER_PORT_DP_C		(2 << 30)
4056 #define  PANEL_POWER_PORT_DP_D		(3 << 30)
4057 #define  PANEL_POWER_DOWN_DELAY_MASK	(0x1fff0000)
4058 #define  PANEL_POWER_DOWN_DELAY_SHIFT	16
4059 #define  PANEL_LIGHT_OFF_DELAY_MASK	(0x1fff)
4060 #define  PANEL_LIGHT_OFF_DELAY_SHIFT	0
4061 
4062 #define PCH_PP_DIVISOR		0xc7210
4063 #define  PP_REFERENCE_DIVIDER_MASK	(0xffffff00)
4064 #define  PP_REFERENCE_DIVIDER_SHIFT	8
4065 #define  PANEL_POWER_CYCLE_DELAY_MASK	(0x1f)
4066 #define  PANEL_POWER_CYCLE_DELAY_SHIFT	0
4067 
4068 #define PCH_DP_B		0xe4100
4069 #define PCH_DPB_AUX_CH_CTL	0xe4110
4070 #define PCH_DPB_AUX_CH_DATA1	0xe4114
4071 #define PCH_DPB_AUX_CH_DATA2	0xe4118
4072 #define PCH_DPB_AUX_CH_DATA3	0xe411c
4073 #define PCH_DPB_AUX_CH_DATA4	0xe4120
4074 #define PCH_DPB_AUX_CH_DATA5	0xe4124
4075 
4076 #define PCH_DP_C		0xe4200
4077 #define PCH_DPC_AUX_CH_CTL	0xe4210
4078 #define PCH_DPC_AUX_CH_DATA1	0xe4214
4079 #define PCH_DPC_AUX_CH_DATA2	0xe4218
4080 #define PCH_DPC_AUX_CH_DATA3	0xe421c
4081 #define PCH_DPC_AUX_CH_DATA4	0xe4220
4082 #define PCH_DPC_AUX_CH_DATA5	0xe4224
4083 
4084 #define PCH_DP_D		0xe4300
4085 #define PCH_DPD_AUX_CH_CTL	0xe4310
4086 #define PCH_DPD_AUX_CH_DATA1	0xe4314
4087 #define PCH_DPD_AUX_CH_DATA2	0xe4318
4088 #define PCH_DPD_AUX_CH_DATA3	0xe431c
4089 #define PCH_DPD_AUX_CH_DATA4	0xe4320
4090 #define PCH_DPD_AUX_CH_DATA5	0xe4324
4091 
4092 /* CPT */
4093 #define  PORT_TRANS_A_SEL_CPT	0
4094 #define  PORT_TRANS_B_SEL_CPT	(1<<29)
4095 #define  PORT_TRANS_C_SEL_CPT	(2<<29)
4096 #define  PORT_TRANS_SEL_MASK	(3<<29)
4097 #define  PORT_TRANS_SEL_CPT(pipe)	((pipe) << 29)
4098 #define  PORT_TO_PIPE(val)	(((val) & (1<<30)) >> 30)
4099 #define  PORT_TO_PIPE_CPT(val)	(((val) & PORT_TRANS_SEL_MASK) >> 29)
4100 
4101 #define TRANS_DP_CTL_A		0xe0300
4102 #define TRANS_DP_CTL_B		0xe1300
4103 #define TRANS_DP_CTL_C		0xe2300
4104 #define TRANS_DP_CTL(pipe)	_PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B)
4105 #define  TRANS_DP_OUTPUT_ENABLE	(1<<31)
4106 #define  TRANS_DP_PORT_SEL_B	(0<<29)
4107 #define  TRANS_DP_PORT_SEL_C	(1<<29)
4108 #define  TRANS_DP_PORT_SEL_D	(2<<29)
4109 #define  TRANS_DP_PORT_SEL_NONE	(3<<29)
4110 #define  TRANS_DP_PORT_SEL_MASK	(3<<29)
4111 #define  TRANS_DP_AUDIO_ONLY	(1<<26)
4112 #define  TRANS_DP_ENH_FRAMING	(1<<18)
4113 #define  TRANS_DP_8BPC		(0<<9)
4114 #define  TRANS_DP_10BPC		(1<<9)
4115 #define  TRANS_DP_6BPC		(2<<9)
4116 #define  TRANS_DP_12BPC		(3<<9)
4117 #define  TRANS_DP_BPC_MASK	(3<<9)
4118 #define  TRANS_DP_VSYNC_ACTIVE_HIGH	(1<<4)
4119 #define  TRANS_DP_VSYNC_ACTIVE_LOW	0
4120 #define  TRANS_DP_HSYNC_ACTIVE_HIGH	(1<<3)
4121 #define  TRANS_DP_HSYNC_ACTIVE_LOW	0
4122 #define  TRANS_DP_SYNC_MASK	(3<<3)
4123 
4124 /* SNB eDP training params */
4125 /* SNB A-stepping */
4126 #define  EDP_LINK_TRAIN_400MV_0DB_SNB_A		(0x38<<22)
4127 #define  EDP_LINK_TRAIN_400MV_6DB_SNB_A		(0x02<<22)
4128 #define  EDP_LINK_TRAIN_600MV_3_5DB_SNB_A	(0x01<<22)
4129 #define  EDP_LINK_TRAIN_800MV_0DB_SNB_A		(0x0<<22)
4130 /* SNB B-stepping */
4131 #define  EDP_LINK_TRAIN_400_600MV_0DB_SNB_B	(0x0<<22)
4132 #define  EDP_LINK_TRAIN_400MV_3_5DB_SNB_B	(0x1<<22)
4133 #define  EDP_LINK_TRAIN_400_600MV_6DB_SNB_B	(0x3a<<22)
4134 #define  EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B	(0x39<<22)
4135 #define  EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B	(0x38<<22)
4136 #define  EDP_LINK_TRAIN_VOL_EMP_MASK_SNB	(0x3f<<22)
4137 
4138 /* IVB */
4139 #define EDP_LINK_TRAIN_400MV_0DB_IVB		(0x24 <<22)
4140 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB		(0x2a <<22)
4141 #define EDP_LINK_TRAIN_400MV_6DB_IVB		(0x2f <<22)
4142 #define EDP_LINK_TRAIN_600MV_0DB_IVB		(0x30 <<22)
4143 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB		(0x36 <<22)
4144 #define EDP_LINK_TRAIN_800MV_0DB_IVB		(0x38 <<22)
4145 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB		(0x33 <<22)
4146 
4147 /* legacy values */
4148 #define EDP_LINK_TRAIN_500MV_0DB_IVB		(0x00 <<22)
4149 #define EDP_LINK_TRAIN_1000MV_0DB_IVB		(0x20 <<22)
4150 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB		(0x02 <<22)
4151 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB		(0x22 <<22)
4152 #define EDP_LINK_TRAIN_1000MV_6DB_IVB		(0x23 <<22)
4153 
4154 #define  EDP_LINK_TRAIN_VOL_EMP_MASK_IVB	(0x3f<<22)
4155 
4156 #define  FORCEWAKE				0xA18C
4157 #define  FORCEWAKE_VLV				0x1300b0
4158 #define  FORCEWAKE_ACK_VLV			0x1300b4
4159 #define  FORCEWAKE_ACK_HSW			0x130044
4160 #define  FORCEWAKE_ACK				0x130090
4161 #define  FORCEWAKE_MT				0xa188 /* multi-threaded */
4162 #define   FORCEWAKE_KERNEL			0x1
4163 #define   FORCEWAKE_USER			0x2
4164 #define  FORCEWAKE_MT_ACK			0x130040
4165 #define  ECOBUS					0xa180
4166 #define    FORCEWAKE_MT_ENABLE			(1<<5)
4167 
4168 #define  GTFIFODBG				0x120000
4169 #define    GT_FIFO_CPU_ERROR_MASK		7
4170 #define    GT_FIFO_OVFERR			(1<<2)
4171 #define    GT_FIFO_IAWRERR			(1<<1)
4172 #define    GT_FIFO_IARDERR			(1<<0)
4173 
4174 #define  GT_FIFO_FREE_ENTRIES			0x120008
4175 #define    GT_FIFO_NUM_RESERVED_ENTRIES		20
4176 
4177 #define GEN6_UCGCTL1				0x9400
4178 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE		(1 << 5)
4179 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE			(1 << 7)
4180 
4181 #define GEN6_UCGCTL2				0x9404
4182 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE		(1 << 30)
4183 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE		(1 << 22)
4184 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE		(1 << 13)
4185 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE		(1 << 12)
4186 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE		(1 << 11)
4187 
4188 #define GEN7_UCGCTL4				0x940c
4189 #define  GEN7_L3BANK2X_CLOCK_GATE_DISABLE	(1<<25)
4190 
4191 #define GEN6_RPNSWREQ				0xA008
4192 #define   GEN6_TURBO_DISABLE			(1<<31)
4193 #define   GEN6_FREQUENCY(x)			((x)<<25)
4194 #define   GEN6_OFFSET(x)			((x)<<19)
4195 #define   GEN6_AGGRESSIVE_TURBO			(0<<15)
4196 #define GEN6_RC_VIDEO_FREQ			0xA00C
4197 #define GEN6_RC_CONTROL				0xA090
4198 #define   GEN6_RC_CTL_RC6pp_ENABLE		(1<<16)
4199 #define   GEN6_RC_CTL_RC6p_ENABLE		(1<<17)
4200 #define   GEN6_RC_CTL_RC6_ENABLE		(1<<18)
4201 #define   GEN6_RC_CTL_RC1e_ENABLE		(1<<20)
4202 #define   GEN6_RC_CTL_RC7_ENABLE		(1<<22)
4203 #define   GEN6_RC_CTL_EI_MODE(x)		((x)<<27)
4204 #define   GEN6_RC_CTL_HW_ENABLE			(1<<31)
4205 #define GEN6_RP_DOWN_TIMEOUT			0xA010
4206 #define GEN6_RP_INTERRUPT_LIMITS		0xA014
4207 #define GEN6_RPSTAT1				0xA01C
4208 #define   GEN6_CAGF_SHIFT			8
4209 #define   GEN6_CAGF_MASK			(0x7f << GEN6_CAGF_SHIFT)
4210 #define GEN6_RP_CONTROL				0xA024
4211 #define   GEN6_RP_MEDIA_TURBO			(1<<11)
4212 #define   GEN6_RP_MEDIA_MODE_MASK		(3<<9)
4213 #define   GEN6_RP_MEDIA_HW_TURBO_MODE		(3<<9)
4214 #define   GEN6_RP_MEDIA_HW_NORMAL_MODE		(2<<9)
4215 #define   GEN6_RP_MEDIA_HW_MODE			(1<<9)
4216 #define   GEN6_RP_MEDIA_SW_MODE			(0<<9)
4217 #define   GEN6_RP_MEDIA_IS_GFX			(1<<8)
4218 #define   GEN6_RP_ENABLE			(1<<7)
4219 #define   GEN6_RP_UP_IDLE_MIN			(0x1<<3)
4220 #define   GEN6_RP_UP_BUSY_AVG			(0x2<<3)
4221 #define   GEN6_RP_UP_BUSY_CONT			(0x4<<3)
4222 #define   GEN7_RP_DOWN_IDLE_AVG			(0x2<<0)
4223 #define   GEN6_RP_DOWN_IDLE_CONT		(0x1<<0)
4224 #define GEN6_RP_UP_THRESHOLD			0xA02C
4225 #define GEN6_RP_DOWN_THRESHOLD			0xA030
4226 #define GEN6_RP_CUR_UP_EI			0xA050
4227 #define   GEN6_CURICONT_MASK			0xffffff
4228 #define GEN6_RP_CUR_UP				0xA054
4229 #define   GEN6_CURBSYTAVG_MASK			0xffffff
4230 #define GEN6_RP_PREV_UP				0xA058
4231 #define GEN6_RP_CUR_DOWN_EI			0xA05C
4232 #define   GEN6_CURIAVG_MASK			0xffffff
4233 #define GEN6_RP_CUR_DOWN			0xA060
4234 #define GEN6_RP_PREV_DOWN			0xA064
4235 #define GEN6_RP_UP_EI				0xA068
4236 #define GEN6_RP_DOWN_EI				0xA06C
4237 #define GEN6_RP_IDLE_HYSTERSIS			0xA070
4238 #define GEN6_RC_STATE				0xA094
4239 #define GEN6_RC1_WAKE_RATE_LIMIT		0xA098
4240 #define GEN6_RC6_WAKE_RATE_LIMIT		0xA09C
4241 #define GEN6_RC6pp_WAKE_RATE_LIMIT		0xA0A0
4242 #define GEN6_RC_EVALUATION_INTERVAL		0xA0A8
4243 #define GEN6_RC_IDLE_HYSTERSIS			0xA0AC
4244 #define GEN6_RC_SLEEP				0xA0B0
4245 #define GEN6_RC1e_THRESHOLD			0xA0B4
4246 #define GEN6_RC6_THRESHOLD			0xA0B8
4247 #define GEN6_RC6p_THRESHOLD			0xA0BC
4248 #define GEN6_RC6pp_THRESHOLD			0xA0C0
4249 #define GEN6_PMINTRMSK				0xA168
4250 
4251 #define GEN6_PMISR				0x44020
4252 #define GEN6_PMIMR				0x44024 /* rps_lock */
4253 #define GEN6_PMIIR				0x44028
4254 #define GEN6_PMIER				0x4402C
4255 #define  GEN6_PM_MBOX_EVENT			(1<<25)
4256 #define  GEN6_PM_THERMAL_EVENT			(1<<24)
4257 #define  GEN6_PM_RP_DOWN_TIMEOUT		(1<<6)
4258 #define  GEN6_PM_RP_UP_THRESHOLD		(1<<5)
4259 #define  GEN6_PM_RP_DOWN_THRESHOLD		(1<<4)
4260 #define  GEN6_PM_RP_UP_EI_EXPIRED		(1<<2)
4261 #define  GEN6_PM_RP_DOWN_EI_EXPIRED		(1<<1)
4262 #define  GEN6_PM_DEFERRED_EVENTS		(GEN6_PM_RP_UP_THRESHOLD | \
4263 						 GEN6_PM_RP_DOWN_THRESHOLD | \
4264 						 GEN6_PM_RP_DOWN_TIMEOUT)
4265 
4266 #define GEN6_GT_GFX_RC6_LOCKED			0x138104
4267 #define GEN6_GT_GFX_RC6				0x138108
4268 #define GEN6_GT_GFX_RC6p			0x13810C
4269 #define GEN6_GT_GFX_RC6pp			0x138110
4270 
4271 #define GEN6_PCODE_MAILBOX			0x138124
4272 #define   GEN6_PCODE_READY			(1<<31)
4273 #define   GEN6_READ_OC_PARAMS			0xc
4274 #define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE	0x8
4275 #define   GEN6_PCODE_READ_MIN_FREQ_TABLE	0x9
4276 #define	  GEN6_PCODE_WRITE_RC6VIDS		0x4
4277 #define	  GEN6_PCODE_READ_RC6VIDS		0x5
4278 #define   GEN6_ENCODE_RC6_VID(mv)		(((mv) / 5) - 245) < 0 ?: 0
4279 #define   GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) > 0 ? ((vids) * 5) + 245 : 0)
4280 #define GEN6_PCODE_DATA				0x138128
4281 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
4282 
4283 #define GEN6_GT_CORE_STATUS		0x138060
4284 #define   GEN6_CORE_CPD_STATE_MASK	(7<<4)
4285 #define   GEN6_RCn_MASK			7
4286 #define   GEN6_RC0			0
4287 #define   GEN6_RC3			2
4288 #define   GEN6_RC6			3
4289 #define   GEN6_RC7			4
4290 
4291 #define GEN7_MISCCPCTL			(0x9424)
4292 #define   GEN7_DOP_CLOCK_GATE_ENABLE	(1<<0)
4293 
4294 /* IVYBRIDGE DPF */
4295 #define GEN7_L3CDERRST1			0xB008 /* L3CD Error Status 1 */
4296 #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
4297 #define   GEN7_PARITY_ERROR_VALID	(1<<13)
4298 #define   GEN7_L3CDERRST1_BANK_MASK	(3<<11)
4299 #define   GEN7_L3CDERRST1_SUBBANK_MASK	(7<<8)
4300 #define GEN7_PARITY_ERROR_ROW(reg) \
4301 		((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14)
4302 #define GEN7_PARITY_ERROR_BANK(reg) \
4303 		((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11)
4304 #define GEN7_PARITY_ERROR_SUBBANK(reg) \
4305 		((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
4306 #define   GEN7_L3CDERRST1_ENABLE	(1<<7)
4307 
4308 #define GEN7_L3LOG_BASE			0xB070
4309 #define GEN7_L3LOG_SIZE			0x80
4310 
4311 #define GEN7_HALF_SLICE_CHICKEN1	0xe100 /* IVB GT1 + VLV */
4312 #define GEN7_HALF_SLICE_CHICKEN1_GT2	0xf100
4313 #define   GEN7_MAX_PS_THREAD_DEP		(8<<12)
4314 #define   GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE	(1<<3)
4315 
4316 #define GEN7_ROW_CHICKEN2		0xe4f4
4317 #define GEN7_ROW_CHICKEN2_GT2		0xf4f4
4318 #define   DOP_CLOCK_GATING_DISABLE	(1<<0)
4319 
4320 #define G4X_AUD_VID_DID			0x62020
4321 #define INTEL_AUDIO_DEVCL		0x808629FB
4322 #define INTEL_AUDIO_DEVBLC		0x80862801
4323 #define INTEL_AUDIO_DEVCTG		0x80862802
4324 
4325 #define G4X_AUD_CNTL_ST			0x620B4
4326 #define G4X_ELDV_DEVCL_DEVBLC		(1 << 13)
4327 #define G4X_ELDV_DEVCTG			(1 << 14)
4328 #define G4X_ELD_ADDR			(0xf << 5)
4329 #define G4X_ELD_ACK			(1 << 4)
4330 #define G4X_HDMIW_HDMIEDID		0x6210C
4331 
4332 #define IBX_HDMIW_HDMIEDID_A		0xE2050
4333 #define IBX_HDMIW_HDMIEDID_B		0xE2150
4334 #define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
4335 					IBX_HDMIW_HDMIEDID_A, \
4336 					IBX_HDMIW_HDMIEDID_B)
4337 #define IBX_AUD_CNTL_ST_A		0xE20B4
4338 #define IBX_AUD_CNTL_ST_B		0xE21B4
4339 #define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \
4340 					IBX_AUD_CNTL_ST_A, \
4341 					IBX_AUD_CNTL_ST_B)
4342 #define IBX_ELD_BUFFER_SIZE		(0x1f << 10)
4343 #define IBX_ELD_ADDRESS			(0x1f << 5)
4344 #define IBX_ELD_ACK			(1 << 4)
4345 #define IBX_AUD_CNTL_ST2		0xE20C0
4346 #define IBX_ELD_VALIDB			(1 << 0)
4347 #define IBX_CP_READYB			(1 << 1)
4348 
4349 #define CPT_HDMIW_HDMIEDID_A		0xE5050
4350 #define CPT_HDMIW_HDMIEDID_B		0xE5150
4351 #define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
4352 					CPT_HDMIW_HDMIEDID_A, \
4353 					CPT_HDMIW_HDMIEDID_B)
4354 #define CPT_AUD_CNTL_ST_A		0xE50B4
4355 #define CPT_AUD_CNTL_ST_B		0xE51B4
4356 #define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \
4357 					CPT_AUD_CNTL_ST_A, \
4358 					CPT_AUD_CNTL_ST_B)
4359 #define CPT_AUD_CNTRL_ST2		0xE50C0
4360 
4361 /* These are the 4 32-bit write offset registers for each stream
4362  * output buffer.  It determines the offset from the
4363  * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
4364  */
4365 #define GEN7_SO_WRITE_OFFSET(n)		(0x5280 + (n) * 4)
4366 
4367 #define IBX_AUD_CONFIG_A			0xe2000
4368 #define IBX_AUD_CONFIG_B			0xe2100
4369 #define IBX_AUD_CFG(pipe) _PIPE(pipe, \
4370 					IBX_AUD_CONFIG_A, \
4371 					IBX_AUD_CONFIG_B)
4372 #define CPT_AUD_CONFIG_A			0xe5000
4373 #define CPT_AUD_CONFIG_B			0xe5100
4374 #define CPT_AUD_CFG(pipe) _PIPE(pipe, \
4375 					CPT_AUD_CONFIG_A, \
4376 					CPT_AUD_CONFIG_B)
4377 #define   AUD_CONFIG_N_VALUE_INDEX		(1 << 29)
4378 #define   AUD_CONFIG_N_PROG_ENABLE		(1 << 28)
4379 #define   AUD_CONFIG_UPPER_N_SHIFT		20
4380 #define   AUD_CONFIG_UPPER_N_VALUE		(0xff << 20)
4381 #define   AUD_CONFIG_LOWER_N_SHIFT		4
4382 #define   AUD_CONFIG_LOWER_N_VALUE		(0xfff << 4)
4383 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT	16
4384 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI		(0xf << 16)
4385 #define   AUD_CONFIG_DISABLE_NCTS		(1 << 3)
4386 
4387 /* HSW Audio */
4388 #define   HSW_AUD_CONFIG_A		0x65000 /* Audio Configuration Transcoder A */
4389 #define   HSW_AUD_CONFIG_B		0x65100 /* Audio Configuration Transcoder B */
4390 #define   HSW_AUD_CFG(pipe) _PIPE(pipe, \
4391 					HSW_AUD_CONFIG_A, \
4392 					HSW_AUD_CONFIG_B)
4393 
4394 #define   HSW_AUD_MISC_CTRL_A		0x65010 /* Audio Misc Control Convert 1 */
4395 #define   HSW_AUD_MISC_CTRL_B		0x65110 /* Audio Misc Control Convert 2 */
4396 #define   HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \
4397 					HSW_AUD_MISC_CTRL_A, \
4398 					HSW_AUD_MISC_CTRL_B)
4399 
4400 #define   HSW_AUD_DIP_ELD_CTRL_ST_A	0x650b4 /* Audio DIP and ELD Control State Transcoder A */
4401 #define   HSW_AUD_DIP_ELD_CTRL_ST_B	0x651b4 /* Audio DIP and ELD Control State Transcoder B */
4402 #define   HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \
4403 					HSW_AUD_DIP_ELD_CTRL_ST_A, \
4404 					HSW_AUD_DIP_ELD_CTRL_ST_B)
4405 
4406 /* Audio Digital Converter */
4407 #define   HSW_AUD_DIG_CNVT_1		0x65080 /* Audio Converter 1 */
4408 #define   HSW_AUD_DIG_CNVT_2		0x65180 /* Audio Converter 1 */
4409 #define   AUD_DIG_CNVT(pipe) _PIPE(pipe, \
4410 					HSW_AUD_DIG_CNVT_1, \
4411 					HSW_AUD_DIG_CNVT_2)
4412 #define   DIP_PORT_SEL_MASK		0x3
4413 
4414 #define   HSW_AUD_EDID_DATA_A		0x65050
4415 #define   HSW_AUD_EDID_DATA_B		0x65150
4416 #define   HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \
4417 					HSW_AUD_EDID_DATA_A, \
4418 					HSW_AUD_EDID_DATA_B)
4419 
4420 #define   HSW_AUD_PIPE_CONV_CFG		0x6507c /* Audio pipe and converter configs */
4421 #define   HSW_AUD_PIN_ELD_CP_VLD	0x650c0 /* Audio ELD and CP Ready Status */
4422 #define   AUDIO_INACTIVE_C		(1<<11)
4423 #define   AUDIO_INACTIVE_B		(1<<7)
4424 #define   AUDIO_INACTIVE_A		(1<<3)
4425 #define   AUDIO_OUTPUT_ENABLE_A		(1<<2)
4426 #define   AUDIO_OUTPUT_ENABLE_B		(1<<6)
4427 #define   AUDIO_OUTPUT_ENABLE_C		(1<<10)
4428 #define   AUDIO_ELD_VALID_A		(1<<0)
4429 #define   AUDIO_ELD_VALID_B		(1<<4)
4430 #define   AUDIO_ELD_VALID_C		(1<<8)
4431 #define   AUDIO_CP_READY_A		(1<<1)
4432 #define   AUDIO_CP_READY_B		(1<<5)
4433 #define   AUDIO_CP_READY_C		(1<<9)
4434 
4435 /* HSW Power Wells */
4436 #define HSW_PWR_WELL_CTL1			0x45400 /* BIOS */
4437 #define HSW_PWR_WELL_CTL2			0x45404 /* Driver */
4438 #define HSW_PWR_WELL_CTL3			0x45408 /* KVMR */
4439 #define HSW_PWR_WELL_CTL4			0x4540C /* Debug */
4440 #define   HSW_PWR_WELL_ENABLE			(1<<31)
4441 #define   HSW_PWR_WELL_STATE			(1<<30)
4442 #define HSW_PWR_WELL_CTL5			0x45410
4443 #define   HSW_PWR_WELL_ENABLE_SINGLE_STEP	(1<<31)
4444 #define   HSW_PWR_WELL_PWR_GATE_OVERRIDE	(1<<20)
4445 #define   HSW_PWR_WELL_FORCE_ON			(1<<19)
4446 #define HSW_PWR_WELL_CTL6			0x45414
4447 
4448 /* Per-pipe DDI Function Control */
4449 #define TRANS_DDI_FUNC_CTL_A		0x60400
4450 #define TRANS_DDI_FUNC_CTL_B		0x61400
4451 #define TRANS_DDI_FUNC_CTL_C		0x62400
4452 #define TRANS_DDI_FUNC_CTL_EDP		0x6F400
4453 #define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER(tran, TRANS_DDI_FUNC_CTL_A, \
4454 						   TRANS_DDI_FUNC_CTL_B)
4455 #define  TRANS_DDI_FUNC_ENABLE		(1<<31)
4456 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
4457 #define  TRANS_DDI_PORT_MASK		(7<<28)
4458 #define  TRANS_DDI_SELECT_PORT(x)	((x)<<28)
4459 #define  TRANS_DDI_PORT_NONE		(0<<28)
4460 #define  TRANS_DDI_MODE_SELECT_MASK	(7<<24)
4461 #define  TRANS_DDI_MODE_SELECT_HDMI	(0<<24)
4462 #define  TRANS_DDI_MODE_SELECT_DVI	(1<<24)
4463 #define  TRANS_DDI_MODE_SELECT_DP_SST	(2<<24)
4464 #define  TRANS_DDI_MODE_SELECT_DP_MST	(3<<24)
4465 #define  TRANS_DDI_MODE_SELECT_FDI	(4<<24)
4466 #define  TRANS_DDI_BPC_MASK		(7<<20)
4467 #define  TRANS_DDI_BPC_8		(0<<20)
4468 #define  TRANS_DDI_BPC_10		(1<<20)
4469 #define  TRANS_DDI_BPC_6		(2<<20)
4470 #define  TRANS_DDI_BPC_12		(3<<20)
4471 #define  TRANS_DDI_PVSYNC		(1<<17)
4472 #define  TRANS_DDI_PHSYNC		(1<<16)
4473 #define  TRANS_DDI_EDP_INPUT_MASK	(7<<12)
4474 #define  TRANS_DDI_EDP_INPUT_A_ON	(0<<12)
4475 #define  TRANS_DDI_EDP_INPUT_A_ONOFF	(4<<12)
4476 #define  TRANS_DDI_EDP_INPUT_B_ONOFF	(5<<12)
4477 #define  TRANS_DDI_EDP_INPUT_C_ONOFF	(6<<12)
4478 #define  TRANS_DDI_BFI_ENABLE		(1<<4)
4479 #define  TRANS_DDI_PORT_WIDTH_X1	(0<<1)
4480 #define  TRANS_DDI_PORT_WIDTH_X2	(1<<1)
4481 #define  TRANS_DDI_PORT_WIDTH_X4	(3<<1)
4482 
4483 /* DisplayPort Transport Control */
4484 #define DP_TP_CTL_A			0x64040
4485 #define DP_TP_CTL_B			0x64140
4486 #define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B)
4487 #define  DP_TP_CTL_ENABLE			(1<<31)
4488 #define  DP_TP_CTL_MODE_SST			(0<<27)
4489 #define  DP_TP_CTL_MODE_MST			(1<<27)
4490 #define  DP_TP_CTL_ENHANCED_FRAME_ENABLE	(1<<18)
4491 #define  DP_TP_CTL_FDI_AUTOTRAIN		(1<<15)
4492 #define  DP_TP_CTL_LINK_TRAIN_MASK		(7<<8)
4493 #define  DP_TP_CTL_LINK_TRAIN_PAT1		(0<<8)
4494 #define  DP_TP_CTL_LINK_TRAIN_PAT2		(1<<8)
4495 #define  DP_TP_CTL_LINK_TRAIN_PAT3		(4<<8)
4496 #define  DP_TP_CTL_LINK_TRAIN_IDLE		(2<<8)
4497 #define  DP_TP_CTL_LINK_TRAIN_NORMAL		(3<<8)
4498 #define  DP_TP_CTL_SCRAMBLE_DISABLE		(1<<7)
4499 
4500 /* DisplayPort Transport Status */
4501 #define DP_TP_STATUS_A			0x64044
4502 #define DP_TP_STATUS_B			0x64144
4503 #define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)
4504 #define  DP_TP_STATUS_IDLE_DONE		(1<<25)
4505 #define  DP_TP_STATUS_AUTOTRAIN_DONE	(1<<12)
4506 
4507 /* DDI Buffer Control */
4508 #define DDI_BUF_CTL_A				0x64000
4509 #define DDI_BUF_CTL_B				0x64100
4510 #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
4511 #define  DDI_BUF_CTL_ENABLE			(1<<31)
4512 #define  DDI_BUF_EMP_400MV_0DB_HSW		(0<<24)   /* Sel0 */
4513 #define  DDI_BUF_EMP_400MV_3_5DB_HSW		(1<<24)   /* Sel1 */
4514 #define  DDI_BUF_EMP_400MV_6DB_HSW		(2<<24)   /* Sel2 */
4515 #define  DDI_BUF_EMP_400MV_9_5DB_HSW		(3<<24)   /* Sel3 */
4516 #define  DDI_BUF_EMP_600MV_0DB_HSW		(4<<24)   /* Sel4 */
4517 #define  DDI_BUF_EMP_600MV_3_5DB_HSW		(5<<24)   /* Sel5 */
4518 #define  DDI_BUF_EMP_600MV_6DB_HSW		(6<<24)   /* Sel6 */
4519 #define  DDI_BUF_EMP_800MV_0DB_HSW		(7<<24)   /* Sel7 */
4520 #define  DDI_BUF_EMP_800MV_3_5DB_HSW		(8<<24)   /* Sel8 */
4521 #define  DDI_BUF_EMP_MASK			(0xf<<24)
4522 #define  DDI_BUF_IS_IDLE			(1<<7)
4523 #define  DDI_A_4_LANES				(1<<4)
4524 #define  DDI_PORT_WIDTH_X1			(0<<1)
4525 #define  DDI_PORT_WIDTH_X2			(1<<1)
4526 #define  DDI_PORT_WIDTH_X4			(3<<1)
4527 #define  DDI_INIT_DISPLAY_DETECTED		(1<<0)
4528 
4529 /* DDI Buffer Translations */
4530 #define DDI_BUF_TRANS_A				0x64E00
4531 #define DDI_BUF_TRANS_B				0x64E60
4532 #define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B)
4533 
4534 /* Sideband Interface (SBI) is programmed indirectly, via
4535  * SBI_ADDR, which contains the register offset; and SBI_DATA,
4536  * which contains the payload */
4537 #define SBI_ADDR			0xC6000
4538 #define SBI_DATA			0xC6004
4539 #define SBI_CTL_STAT			0xC6008
4540 #define  SBI_CTL_DEST_ICLK		(0x0<<16)
4541 #define  SBI_CTL_DEST_MPHY		(0x1<<16)
4542 #define  SBI_CTL_OP_IORD		(0x2<<8)
4543 #define  SBI_CTL_OP_IOWR		(0x3<<8)
4544 #define  SBI_CTL_OP_CRRD		(0x6<<8)
4545 #define  SBI_CTL_OP_CRWR		(0x7<<8)
4546 #define  SBI_RESPONSE_FAIL		(0x1<<1)
4547 #define  SBI_RESPONSE_SUCCESS		(0x0<<1)
4548 #define  SBI_BUSY			(0x1<<0)
4549 #define  SBI_READY			(0x0<<0)
4550 
4551 /* SBI offsets */
4552 #define  SBI_SSCDIVINTPHASE6			0x0600
4553 #define   SBI_SSCDIVINTPHASE_DIVSEL_MASK	((0x7f)<<1)
4554 #define   SBI_SSCDIVINTPHASE_DIVSEL(x)		((x)<<1)
4555 #define   SBI_SSCDIVINTPHASE_INCVAL_MASK	((0x7f)<<8)
4556 #define   SBI_SSCDIVINTPHASE_INCVAL(x)		((x)<<8)
4557 #define   SBI_SSCDIVINTPHASE_DIR(x)		((x)<<15)
4558 #define   SBI_SSCDIVINTPHASE_PROPAGATE		(1<<0)
4559 #define  SBI_SSCCTL				0x020c
4560 #define  SBI_SSCCTL6				0x060C
4561 #define   SBI_SSCCTL_PATHALT			(1<<3)
4562 #define   SBI_SSCCTL_DISABLE			(1<<0)
4563 #define  SBI_SSCAUXDIV6				0x0610
4564 #define   SBI_SSCAUXDIV_FINALDIV2SEL(x)		((x)<<4)
4565 #define  SBI_DBUFF0				0x2a00
4566 #define   SBI_DBUFF0_ENABLE			(1<<0)
4567 
4568 /* LPT PIXCLK_GATE */
4569 #define PIXCLK_GATE			0xC6020
4570 #define  PIXCLK_GATE_UNGATE		(1<<0)
4571 #define  PIXCLK_GATE_GATE		(0<<0)
4572 
4573 /* SPLL */
4574 #define SPLL_CTL			0x46020
4575 #define  SPLL_PLL_ENABLE		(1<<31)
4576 #define  SPLL_PLL_SSC			(1<<28)
4577 #define  SPLL_PLL_NON_SSC		(2<<28)
4578 #define  SPLL_PLL_FREQ_810MHz		(0<<26)
4579 #define  SPLL_PLL_FREQ_1350MHz		(1<<26)
4580 
4581 /* WRPLL */
4582 #define WRPLL_CTL1			0x46040
4583 #define WRPLL_CTL2			0x46060
4584 #define  WRPLL_PLL_ENABLE		(1<<31)
4585 #define  WRPLL_PLL_SELECT_SSC		(0x01<<28)
4586 #define  WRPLL_PLL_SELECT_NON_SSC	(0x02<<28)
4587 #define  WRPLL_PLL_SELECT_LCPLL_2700	(0x03<<28)
4588 /* WRPLL divider programming */
4589 #define  WRPLL_DIVIDER_REFERENCE(x)	((x)<<0)
4590 #define  WRPLL_DIVIDER_POST(x)		((x)<<8)
4591 #define  WRPLL_DIVIDER_FEEDBACK(x)	((x)<<16)
4592 
4593 /* Port clock selection */
4594 #define PORT_CLK_SEL_A			0x46100
4595 #define PORT_CLK_SEL_B			0x46104
4596 #define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B)
4597 #define  PORT_CLK_SEL_LCPLL_2700	(0<<29)
4598 #define  PORT_CLK_SEL_LCPLL_1350	(1<<29)
4599 #define  PORT_CLK_SEL_LCPLL_810		(2<<29)
4600 #define  PORT_CLK_SEL_SPLL		(3<<29)
4601 #define  PORT_CLK_SEL_WRPLL1		(4<<29)
4602 #define  PORT_CLK_SEL_WRPLL2		(5<<29)
4603 #define  PORT_CLK_SEL_NONE		(7<<29)
4604 
4605 /* Transcoder clock selection */
4606 #define TRANS_CLK_SEL_A			0x46140
4607 #define TRANS_CLK_SEL_B			0x46144
4608 #define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B)
4609 /* For each transcoder, we need to select the corresponding port clock */
4610 #define  TRANS_CLK_SEL_DISABLED		(0x0<<29)
4611 #define  TRANS_CLK_SEL_PORT(x)		((x+1)<<29)
4612 
4613 #define _TRANSA_MSA_MISC		0x60410
4614 #define _TRANSB_MSA_MISC		0x61410
4615 #define TRANS_MSA_MISC(tran) _TRANSCODER(tran, _TRANSA_MSA_MISC, \
4616 					       _TRANSB_MSA_MISC)
4617 #define  TRANS_MSA_SYNC_CLK		(1<<0)
4618 #define  TRANS_MSA_6_BPC		(0<<5)
4619 #define  TRANS_MSA_8_BPC		(1<<5)
4620 #define  TRANS_MSA_10_BPC		(2<<5)
4621 #define  TRANS_MSA_12_BPC		(3<<5)
4622 #define  TRANS_MSA_16_BPC		(4<<5)
4623 
4624 /* LCPLL Control */
4625 #define LCPLL_CTL			0x130040
4626 #define  LCPLL_PLL_DISABLE		(1<<31)
4627 #define  LCPLL_PLL_LOCK			(1<<30)
4628 #define  LCPLL_CLK_FREQ_MASK		(3<<26)
4629 #define  LCPLL_CLK_FREQ_450		(0<<26)
4630 #define  LCPLL_CD_CLOCK_DISABLE		(1<<25)
4631 #define  LCPLL_CD2X_CLOCK_DISABLE	(1<<23)
4632 #define  LCPLL_CD_SOURCE_FCLK		(1<<21)
4633 
4634 /* Pipe WM_LINETIME - watermark line time */
4635 #define PIPE_WM_LINETIME_A		0x45270
4636 #define PIPE_WM_LINETIME_B		0x45274
4637 #define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \
4638 					   PIPE_WM_LINETIME_B)
4639 #define   PIPE_WM_LINETIME_MASK			(0x1ff)
4640 #define   PIPE_WM_LINETIME_TIME(x)		((x))
4641 #define   PIPE_WM_LINETIME_IPS_LINETIME_MASK	(0x1ff<<16)
4642 #define   PIPE_WM_LINETIME_IPS_LINETIME(x)	((x)<<16)
4643 
4644 /* SFUSE_STRAP */
4645 #define SFUSE_STRAP			0xc2014
4646 #define  SFUSE_STRAP_DDIB_DETECTED	(1<<2)
4647 #define  SFUSE_STRAP_DDIC_DETECTED	(1<<1)
4648 #define  SFUSE_STRAP_DDID_DETECTED	(1<<0)
4649 
4650 #define WM_DBG				0x45280
4651 #define  WM_DBG_DISALLOW_MULTIPLE_LP	(1<<0)
4652 #define  WM_DBG_DISALLOW_MAXFIFO	(1<<1)
4653 #define  WM_DBG_DISALLOW_SPRITE		(1<<2)
4654 
4655 #endif /* _I915_REG_H_ */
4656