1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 2 * All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef _I915_REG_H_ 26 #define _I915_REG_H_ 27 28 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) 29 30 /* 31 * The Bridge device's PCI config space has information about the 32 * fb aperture size and the amount of pre-reserved memory. 33 * This is all handled in the intel-gtt.ko module. i915.ko only 34 * cares about the vga bit for the vga rbiter. 35 */ 36 #define INTEL_GMCH_CTRL 0x52 37 #define INTEL_GMCH_VGA_DISABLE (1 << 1) 38 39 /* PCI config space */ 40 41 #define HPLLCC 0xc0 /* 855 only */ 42 #define GC_CLOCK_CONTROL_MASK (0xf << 0) 43 #define GC_CLOCK_133_200 (0 << 0) 44 #define GC_CLOCK_100_200 (1 << 0) 45 #define GC_CLOCK_100_133 (2 << 0) 46 #define GC_CLOCK_166_250 (3 << 0) 47 #define GCFGC2 0xda 48 #define GCFGC 0xf0 /* 915+ only */ 49 #define GC_LOW_FREQUENCY_ENABLE (1 << 7) 50 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) 51 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) 52 #define GC_DISPLAY_CLOCK_MASK (7 << 4) 53 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) 54 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) 55 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) 56 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) 57 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) 58 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0) 59 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) 60 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) 61 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) 62 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) 63 #define I945_GC_RENDER_CLOCK_MASK (7 << 0) 64 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) 65 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) 66 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) 67 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) 68 #define I915_GC_RENDER_CLOCK_MASK (7 << 0) 69 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) 70 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) 71 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) 72 #define LBB 0xf4 73 74 /* Graphics reset regs */ 75 #define I965_GDRST 0xc0 /* PCI config register */ 76 #define ILK_GDSR 0x2ca4 /* MCHBAR offset */ 77 #define GRDOM_FULL (0<<2) 78 #define GRDOM_RENDER (1<<2) 79 #define GRDOM_MEDIA (3<<2) 80 81 #define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */ 82 #define GEN6_MBC_SNPCR_SHIFT 21 83 #define GEN6_MBC_SNPCR_MASK (3<<21) 84 #define GEN6_MBC_SNPCR_MAX (0<<21) 85 #define GEN6_MBC_SNPCR_MED (1<<21) 86 #define GEN6_MBC_SNPCR_LOW (2<<21) 87 #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */ 88 89 #define GEN6_GDRST 0x941c 90 #define GEN6_GRDOM_FULL (1 << 0) 91 #define GEN6_GRDOM_RENDER (1 << 1) 92 #define GEN6_GRDOM_MEDIA (1 << 2) 93 #define GEN6_GRDOM_BLT (1 << 3) 94 95 /* VGA stuff */ 96 97 #define VGA_ST01_MDA 0x3ba 98 #define VGA_ST01_CGA 0x3da 99 100 #define VGA_MSR_WRITE 0x3c2 101 #define VGA_MSR_READ 0x3cc 102 #define VGA_MSR_MEM_EN (1<<1) 103 #define VGA_MSR_CGA_MODE (1<<0) 104 105 #define VGA_SR_INDEX 0x3c4 106 #define VGA_SR_DATA 0x3c5 107 108 #define VGA_AR_INDEX 0x3c0 109 #define VGA_AR_VID_EN (1<<5) 110 #define VGA_AR_DATA_WRITE 0x3c0 111 #define VGA_AR_DATA_READ 0x3c1 112 113 #define VGA_GR_INDEX 0x3ce 114 #define VGA_GR_DATA 0x3cf 115 /* GR05 */ 116 #define VGA_GR_MEM_READ_MODE_SHIFT 3 117 #define VGA_GR_MEM_READ_MODE_PLANE 1 118 /* GR06 */ 119 #define VGA_GR_MEM_MODE_MASK 0xc 120 #define VGA_GR_MEM_MODE_SHIFT 2 121 #define VGA_GR_MEM_A0000_AFFFF 0 122 #define VGA_GR_MEM_A0000_BFFFF 1 123 #define VGA_GR_MEM_B0000_B7FFF 2 124 #define VGA_GR_MEM_B0000_BFFFF 3 125 126 #define VGA_DACMASK 0x3c6 127 #define VGA_DACRX 0x3c7 128 #define VGA_DACWX 0x3c8 129 #define VGA_DACDATA 0x3c9 130 131 #define VGA_CR_INDEX_MDA 0x3b4 132 #define VGA_CR_DATA_MDA 0x3b5 133 #define VGA_CR_INDEX_CGA 0x3d4 134 #define VGA_CR_DATA_CGA 0x3d5 135 136 /* 137 * Memory interface instructions used by the kernel 138 */ 139 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) 140 141 #define MI_NOOP MI_INSTR(0, 0) 142 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0) 143 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) 144 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) 145 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) 146 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) 147 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 148 #define MI_FLUSH MI_INSTR(0x04, 0) 149 #define MI_READ_FLUSH (1 << 0) 150 #define MI_EXE_FLUSH (1 << 1) 151 #define MI_NO_WRITE_FLUSH (1 << 2) 152 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ 153 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ 154 #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ 155 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) 156 #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) 157 #define MI_SUSPEND_FLUSH_EN (1<<0) 158 #define MI_REPORT_HEAD MI_INSTR(0x07, 0) 159 #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0) 160 #define MI_OVERLAY_CONTINUE (0x0<<21) 161 #define MI_OVERLAY_ON (0x1<<21) 162 #define MI_OVERLAY_OFF (0x2<<21) 163 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) 164 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) 165 #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) 166 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) 167 #define MI_SET_CONTEXT MI_INSTR(0x18, 0) 168 #define MI_MM_SPACE_GTT (1<<8) 169 #define MI_MM_SPACE_PHYSICAL (0<<8) 170 #define MI_SAVE_EXT_STATE_EN (1<<3) 171 #define MI_RESTORE_EXT_STATE_EN (1<<2) 172 #define MI_FORCE_RESTORE (1<<1) 173 #define MI_RESTORE_INHIBIT (1<<0) 174 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) 175 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ 176 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) 177 #define MI_STORE_DWORD_INDEX_SHIFT 2 178 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM: 179 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw 180 * simply ignores the register load under certain conditions. 181 * - One can actually load arbitrary many arbitrary registers: Simply issue x 182 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! 183 */ 184 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1) 185 #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ 186 #define MI_INVALIDATE_TLB (1<<18) 187 #define MI_INVALIDATE_BSD (1<<7) 188 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) 189 #define MI_BATCH_NON_SECURE (1) 190 #define MI_BATCH_NON_SECURE_I965 (1<<8) 191 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) 192 #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */ 193 #define MI_SEMAPHORE_GLOBAL_GTT (1<<22) 194 #define MI_SEMAPHORE_UPDATE (1<<21) 195 #define MI_SEMAPHORE_COMPARE (1<<20) 196 #define MI_SEMAPHORE_REGISTER (1<<18) 197 #define MI_SEMAPHORE_SYNC_RV (2<<16) 198 #define MI_SEMAPHORE_SYNC_RB (0<<16) 199 #define MI_SEMAPHORE_SYNC_VR (0<<16) 200 #define MI_SEMAPHORE_SYNC_VB (2<<16) 201 #define MI_SEMAPHORE_SYNC_BR (2<<16) 202 #define MI_SEMAPHORE_SYNC_BV (0<<16) 203 #define MI_SEMAPHORE_SYNC_INVALID (1<<0) 204 /* 205 * 3D instructions used by the kernel 206 */ 207 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) 208 209 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) 210 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 211 #define SC_UPDATE_SCISSOR (0x1<<1) 212 #define SC_ENABLE_MASK (0x1<<0) 213 #define SC_ENABLE (0x1<<0) 214 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) 215 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 216 #define SCI_YMIN_MASK (0xffff<<16) 217 #define SCI_XMIN_MASK (0xffff<<0) 218 #define SCI_YMAX_MASK (0xffff<<16) 219 #define SCI_XMAX_MASK (0xffff<<0) 220 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 221 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) 222 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) 223 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 224 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) 225 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) 226 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) 227 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) 228 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) 229 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) 230 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) 231 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) 232 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) 233 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) 234 #define BLT_DEPTH_8 (0<<24) 235 #define BLT_DEPTH_16_565 (1<<24) 236 #define BLT_DEPTH_16_1555 (2<<24) 237 #define BLT_DEPTH_32 (3<<24) 238 #define BLT_ROP_GXCOPY (0xcc<<16) 239 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ 240 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ 241 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) 242 #define ASYNC_FLIP (1<<22) 243 #define DISPLAY_PLANE_A (0<<20) 244 #define DISPLAY_PLANE_B (1<<20) 245 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2)) 246 #define PIPE_CONTROL_CS_STALL (1<<20) 247 #define PIPE_CONTROL_QW_WRITE (1<<14) 248 #define PIPE_CONTROL_DEPTH_STALL (1<<13) 249 #define PIPE_CONTROL_WRITE_FLUSH (1<<12) 250 #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ 251 #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */ 252 #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ 253 #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) 254 #define PIPE_CONTROL_NOTIFY (1<<8) 255 #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) 256 #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) 257 #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) 258 #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) 259 #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) 260 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ 261 262 263 /* 264 * Reset registers 265 */ 266 #define DEBUG_RESET_I830 0x6070 267 #define DEBUG_RESET_FULL (1<<7) 268 #define DEBUG_RESET_RENDER (1<<8) 269 #define DEBUG_RESET_DISPLAY (1<<9) 270 271 272 /* 273 * Fence registers 274 */ 275 #define FENCE_REG_830_0 0x2000 276 #define FENCE_REG_945_8 0x3000 277 #define I830_FENCE_START_MASK 0x07f80000 278 #define I830_FENCE_TILING_Y_SHIFT 12 279 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 280 #define I830_FENCE_PITCH_SHIFT 4 281 #define I830_FENCE_REG_VALID (1<<0) 282 #define I915_FENCE_MAX_PITCH_VAL 4 283 #define I830_FENCE_MAX_PITCH_VAL 6 284 #define I830_FENCE_MAX_SIZE_VAL (1<<8) 285 286 #define I915_FENCE_START_MASK 0x0ff00000 287 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) 288 289 #define FENCE_REG_965_0 0x03000 290 #define I965_FENCE_PITCH_SHIFT 2 291 #define I965_FENCE_TILING_Y_SHIFT 1 292 #define I965_FENCE_REG_VALID (1<<0) 293 #define I965_FENCE_MAX_PITCH_VAL 0x0400 294 295 #define FENCE_REG_SANDYBRIDGE_0 0x100000 296 #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 297 298 /* 299 * Instruction and interrupt control regs 300 */ 301 #define PGTBL_ER 0x02024 302 #define RENDER_RING_BASE 0x02000 303 #define BSD_RING_BASE 0x04000 304 #define GEN6_BSD_RING_BASE 0x12000 305 #define BLT_RING_BASE 0x22000 306 #define RING_TAIL(base) ((base)+0x30) 307 #define RING_HEAD(base) ((base)+0x34) 308 #define RING_START(base) ((base)+0x38) 309 #define RING_CTL(base) ((base)+0x3c) 310 #define RING_SYNC_0(base) ((base)+0x40) 311 #define RING_SYNC_1(base) ((base)+0x44) 312 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE)) 313 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE)) 314 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE)) 315 #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE)) 316 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE)) 317 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE)) 318 #define RING_MAX_IDLE(base) ((base)+0x54) 319 #define RING_HWS_PGA(base) ((base)+0x80) 320 #define RING_HWS_PGA_GEN6(base) ((base)+0x2080) 321 #define RENDER_HWS_PGA_GEN7 (0x04080) 322 #define BSD_HWS_PGA_GEN7 (0x04180) 323 #define BLT_HWS_PGA_GEN7 (0x04280) 324 #define RING_ACTHD(base) ((base)+0x74) 325 #define RING_NOPID(base) ((base)+0x94) 326 #define RING_IMR(base) ((base)+0xa8) 327 #define TAIL_ADDR 0x001FFFF8 328 #define HEAD_WRAP_COUNT 0xFFE00000 329 #define HEAD_WRAP_ONE 0x00200000 330 #define HEAD_ADDR 0x001FFFFC 331 #define RING_NR_PAGES 0x001FF000 332 #define RING_REPORT_MASK 0x00000006 333 #define RING_REPORT_64K 0x00000002 334 #define RING_REPORT_128K 0x00000004 335 #define RING_NO_REPORT 0x00000000 336 #define RING_VALID_MASK 0x00000001 337 #define RING_VALID 0x00000001 338 #define RING_INVALID 0x00000000 339 #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ 340 #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ 341 #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ 342 #if 0 343 #define PRB0_TAIL 0x02030 344 #define PRB0_HEAD 0x02034 345 #define PRB0_START 0x02038 346 #define PRB0_CTL 0x0203c 347 #define PRB1_TAIL 0x02040 /* 915+ only */ 348 #define PRB1_HEAD 0x02044 /* 915+ only */ 349 #define PRB1_START 0x02048 /* 915+ only */ 350 #define PRB1_CTL 0x0204c /* 915+ only */ 351 #endif 352 #define IPEIR_I965 0x02064 353 #define IPEHR_I965 0x02068 354 #define INSTDONE_I965 0x0206c 355 #define INSTPS 0x02070 /* 965+ only */ 356 #define INSTDONE1 0x0207c /* 965+ only */ 357 #define ACTHD_I965 0x02074 358 #define HWS_PGA 0x02080 359 #define HWS_ADDRESS_MASK 0xfffff000 360 #define HWS_START_ADDRESS_SHIFT 4 361 #define PWRCTXA 0x2088 /* 965GM+ only */ 362 #define PWRCTX_EN (1<<0) 363 #define IPEIR 0x02088 364 #define IPEHR 0x0208c 365 #define INSTDONE 0x02090 366 #define NOPID 0x02094 367 #define HWSTAM 0x02098 368 #define VCS_INSTDONE 0x1206C 369 #define VCS_IPEIR 0x12064 370 #define VCS_IPEHR 0x12068 371 #define VCS_ACTHD 0x12074 372 #define BCS_INSTDONE 0x2206C 373 #define BCS_IPEIR 0x22064 374 #define BCS_IPEHR 0x22068 375 #define BCS_ACTHD 0x22074 376 377 #define ERROR_GEN6 0x040a0 378 379 /* GM45+ chicken bits -- debug workaround bits that may be required 380 * for various sorts of correct behavior. The top 16 bits of each are 381 * the enables for writing to the corresponding low bit. 382 */ 383 #define _3D_CHICKEN 0x02084 384 #define _3D_CHICKEN2 0x0208c 385 /* Disables pipelining of read flushes past the SF-WIZ interface. 386 * Required on all Ironlake steppings according to the B-Spec, but the 387 * particular danger of not doing so is not specified. 388 */ 389 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) 390 #define _3D_CHICKEN3 0x02090 391 392 #define MI_MODE 0x0209c 393 # define VS_TIMER_DISPATCH (1 << 6) 394 # define MI_FLUSH_ENABLE (1 << 11) 395 396 #define GFX_MODE 0x02520 397 #define GFX_MODE_GEN7 0x0229c 398 #define GFX_RUN_LIST_ENABLE (1<<15) 399 #define GFX_TLB_INVALIDATE_ALWAYS (1<<13) 400 #define GFX_SURFACE_FAULT_ENABLE (1<<12) 401 #define GFX_REPLAY_MODE (1<<11) 402 #define GFX_PSMI_GRANULARITY (1<<10) 403 #define GFX_PPGTT_ENABLE (1<<9) 404 405 #define GFX_MODE_ENABLE(bit) (((bit) << 16) | (bit)) 406 #define GFX_MODE_DISABLE(bit) (((bit) << 16) | (0)) 407 408 #define SCPD0 0x0209c /* 915+ only */ 409 #define IER 0x020a0 410 #define IIR 0x020a4 411 #define IMR 0x020a8 412 #define ISR 0x020ac 413 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) 414 #define I915_DISPLAY_PORT_INTERRUPT (1<<17) 415 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) 416 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ 417 #define I915_HWB_OOM_INTERRUPT (1<<13) 418 #define I915_SYNC_STATUS_INTERRUPT (1<<12) 419 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) 420 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) 421 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) 422 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) 423 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) 424 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) 425 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) 426 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) 427 #define I915_DEBUG_INTERRUPT (1<<2) 428 #define I915_USER_INTERRUPT (1<<1) 429 #define I915_ASLE_INTERRUPT (1<<0) 430 #define I915_BSD_USER_INTERRUPT (1<<25) 431 #define EIR 0x020b0 432 #define EMR 0x020b4 433 #define ESR 0x020b8 434 #define GM45_ERROR_PAGE_TABLE (1<<5) 435 #define GM45_ERROR_MEM_PRIV (1<<4) 436 #define I915_ERROR_PAGE_TABLE (1<<4) 437 #define GM45_ERROR_CP_PRIV (1<<3) 438 #define I915_ERROR_MEMORY_REFRESH (1<<1) 439 #define I915_ERROR_INSTRUCTION (1<<0) 440 #define INSTPM 0x020c0 441 #define INSTPM_SELF_EN (1<<12) /* 915GM only */ 442 #define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts 443 will not assert AGPBUSY# and will only 444 be delivered when out of C3. */ 445 #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */ 446 #define ACTHD 0x020c8 447 #define FW_BLC 0x020d8 448 #define FW_BLC2 0x020dc 449 #define FW_BLC_SELF 0x020e0 /* 915+ only */ 450 #define FW_BLC_SELF_EN_MASK (1<<31) 451 #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ 452 #define FW_BLC_SELF_EN (1<<15) /* 945 only */ 453 #define MM_BURST_LENGTH 0x00700000 454 #define MM_FIFO_WATERMARK 0x0001F000 455 #define LM_BURST_LENGTH 0x00000700 456 #define LM_FIFO_WATERMARK 0x0000001F 457 #define MI_ARB_STATE 0x020e4 /* 915+ only */ 458 #define MI_ARB_MASK_SHIFT 16 /* shift for enable bits */ 459 460 /* Make render/texture TLB fetches lower priorty than associated data 461 * fetches. This is not turned on by default 462 */ 463 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) 464 465 /* Isoch request wait on GTT enable (Display A/B/C streams). 466 * Make isoch requests stall on the TLB update. May cause 467 * display underruns (test mode only) 468 */ 469 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) 470 471 /* Block grant count for isoch requests when block count is 472 * set to a finite value. 473 */ 474 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) 475 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ 476 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ 477 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ 478 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ 479 480 /* Enable render writes to complete in C2/C3/C4 power states. 481 * If this isn't enabled, render writes are prevented in low 482 * power states. That seems bad to me. 483 */ 484 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) 485 486 /* This acknowledges an async flip immediately instead 487 * of waiting for 2TLB fetches. 488 */ 489 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) 490 491 /* Enables non-sequential data reads through arbiter 492 */ 493 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) 494 495 /* Disable FSB snooping of cacheable write cycles from binner/render 496 * command stream 497 */ 498 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) 499 500 /* Arbiter time slice for non-isoch streams */ 501 #define MI_ARB_TIME_SLICE_MASK (7 << 5) 502 #define MI_ARB_TIME_SLICE_1 (0 << 5) 503 #define MI_ARB_TIME_SLICE_2 (1 << 5) 504 #define MI_ARB_TIME_SLICE_4 (2 << 5) 505 #define MI_ARB_TIME_SLICE_6 (3 << 5) 506 #define MI_ARB_TIME_SLICE_8 (4 << 5) 507 #define MI_ARB_TIME_SLICE_10 (5 << 5) 508 #define MI_ARB_TIME_SLICE_14 (6 << 5) 509 #define MI_ARB_TIME_SLICE_16 (7 << 5) 510 511 /* Low priority grace period page size */ 512 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ 513 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) 514 515 /* Disable display A/B trickle feed */ 516 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) 517 518 /* Set display plane priority */ 519 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ 520 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ 521 522 #define CACHE_MODE_0 0x02120 /* 915+ only */ 523 #define CM0_MASK_SHIFT 16 524 #define CM0_IZ_OPT_DISABLE (1<<6) 525 #define CM0_ZR_OPT_DISABLE (1<<5) 526 #define CM0_DEPTH_EVICT_DISABLE (1<<4) 527 #define CM0_COLOR_EVICT_DISABLE (1<<3) 528 #define CM0_DEPTH_WRITE_DISABLE (1<<1) 529 #define CM0_RC_OP_FLUSH_DISABLE (1<<0) 530 #define BB_ADDR 0x02140 /* 8 bytes */ 531 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ 532 #define ECOSKPD 0x021d0 533 #define ECO_GATING_CX_ONLY (1<<3) 534 #define ECO_FLIP_DONE (1<<0) 535 536 /* GEN6 interrupt control */ 537 #define GEN6_RENDER_HWSTAM 0x2098 538 #define GEN6_RENDER_IMR 0x20a8 539 #define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8) 540 #define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7) 541 #define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6) 542 #define GEN6_RENDER_L3_PARITY_ERROR (1 << 5) 543 #define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4) 544 #define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3) 545 #define GEN6_RENDER_SYNC_STATUS (1 << 2) 546 #define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1) 547 #define GEN6_RENDER_USER_INTERRUPT (1 << 0) 548 549 #define GEN6_BLITTER_HWSTAM 0x22098 550 #define GEN6_BLITTER_IMR 0x220a8 551 #define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26) 552 #define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25) 553 #define GEN6_BLITTER_SYNC_STATUS (1 << 24) 554 #define GEN6_BLITTER_USER_INTERRUPT (1 << 22) 555 556 #define GEN6_BLITTER_ECOSKPD 0x221d0 557 #define GEN6_BLITTER_LOCK_SHIFT 16 558 #define GEN6_BLITTER_FBC_NOTIFY (1<<3) 559 560 #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050 561 #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK (1 << 16) 562 #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE (1 << 0) 563 #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE 0 564 #define GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR (1 << 3) 565 566 #define GEN6_BSD_HWSTAM 0x12098 567 #define GEN6_BSD_IMR 0x120a8 568 #define GEN6_BSD_USER_INTERRUPT (1 << 12) 569 570 #define GEN6_BSD_RNCID 0x12198 571 572 /* 573 * Framebuffer compression (915+ only) 574 */ 575 576 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ 577 #define FBC_LL_BASE 0x03204 /* 4k page aligned */ 578 #define FBC_CONTROL 0x03208 579 #define FBC_CTL_EN (1<<31) 580 #define FBC_CTL_PERIODIC (1<<30) 581 #define FBC_CTL_INTERVAL_SHIFT (16) 582 #define FBC_CTL_UNCOMPRESSIBLE (1<<14) 583 #define FBC_CTL_C3_IDLE (1<<13) 584 #define FBC_CTL_STRIDE_SHIFT (5) 585 #define FBC_CTL_FENCENO (1<<0) 586 #define FBC_COMMAND 0x0320c 587 #define FBC_CMD_COMPRESS (1<<0) 588 #define FBC_STATUS 0x03210 589 #define FBC_STAT_COMPRESSING (1<<31) 590 #define FBC_STAT_COMPRESSED (1<<30) 591 #define FBC_STAT_MODIFIED (1<<29) 592 #define FBC_STAT_CURRENT_LINE (1<<0) 593 #define FBC_CONTROL2 0x03214 594 #define FBC_CTL_FENCE_DBL (0<<4) 595 #define FBC_CTL_IDLE_IMM (0<<2) 596 #define FBC_CTL_IDLE_FULL (1<<2) 597 #define FBC_CTL_IDLE_LINE (2<<2) 598 #define FBC_CTL_IDLE_DEBUG (3<<2) 599 #define FBC_CTL_CPU_FENCE (1<<1) 600 #define FBC_CTL_PLANEA (0<<0) 601 #define FBC_CTL_PLANEB (1<<0) 602 #define FBC_FENCE_OFF 0x0321b 603 #define FBC_TAG 0x03300 604 605 #define FBC_LL_SIZE (1536) 606 607 /* Framebuffer compression for GM45+ */ 608 #define DPFC_CB_BASE 0x3200 609 #define DPFC_CONTROL 0x3208 610 #define DPFC_CTL_EN (1<<31) 611 #define DPFC_CTL_PLANEA (0<<30) 612 #define DPFC_CTL_PLANEB (1<<30) 613 #define DPFC_CTL_FENCE_EN (1<<29) 614 #define DPFC_CTL_PERSISTENT_MODE (1<<25) 615 #define DPFC_SR_EN (1<<10) 616 #define DPFC_CTL_LIMIT_1X (0<<6) 617 #define DPFC_CTL_LIMIT_2X (1<<6) 618 #define DPFC_CTL_LIMIT_4X (2<<6) 619 #define DPFC_RECOMP_CTL 0x320c 620 #define DPFC_RECOMP_STALL_EN (1<<27) 621 #define DPFC_RECOMP_STALL_WM_SHIFT (16) 622 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) 623 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) 624 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) 625 #define DPFC_STATUS 0x3210 626 #define DPFC_INVAL_SEG_SHIFT (16) 627 #define DPFC_INVAL_SEG_MASK (0x07ff0000) 628 #define DPFC_COMP_SEG_SHIFT (0) 629 #define DPFC_COMP_SEG_MASK (0x000003ff) 630 #define DPFC_STATUS2 0x3214 631 #define DPFC_FENCE_YOFF 0x3218 632 #define DPFC_CHICKEN 0x3224 633 #define DPFC_HT_MODIFY (1<<31) 634 635 /* Framebuffer compression for Ironlake */ 636 #define ILK_DPFC_CB_BASE 0x43200 637 #define ILK_DPFC_CONTROL 0x43208 638 /* The bit 28-8 is reserved */ 639 #define DPFC_RESERVED (0x1FFFFF00) 640 #define ILK_DPFC_RECOMP_CTL 0x4320c 641 #define ILK_DPFC_STATUS 0x43210 642 #define ILK_DPFC_FENCE_YOFF 0x43218 643 #define ILK_DPFC_CHICKEN 0x43224 644 #define ILK_FBC_RT_BASE 0x2128 645 #define ILK_FBC_RT_VALID (1<<0) 646 647 #define ILK_DISPLAY_CHICKEN1 0x42000 648 #define ILK_FBCQ_DIS (1<<22) 649 #define ILK_PABSTRETCH_DIS (1<<21) 650 651 652 /* 653 * Framebuffer compression for Sandybridge 654 * 655 * The following two registers are of type GTTMMADR 656 */ 657 #define SNB_DPFC_CTL_SA 0x100100 658 #define SNB_CPU_FENCE_ENABLE (1<<29) 659 #define DPFC_CPU_FENCE_OFFSET 0x100104 660 661 662 /* 663 * GPIO regs 664 */ 665 #define GPIOA 0x5010 666 #define GPIOB 0x5014 667 #define GPIOC 0x5018 668 #define GPIOD 0x501c 669 #define GPIOE 0x5020 670 #define GPIOF 0x5024 671 #define GPIOG 0x5028 672 #define GPIOH 0x502c 673 # define GPIO_CLOCK_DIR_MASK (1 << 0) 674 # define GPIO_CLOCK_DIR_IN (0 << 1) 675 # define GPIO_CLOCK_DIR_OUT (1 << 1) 676 # define GPIO_CLOCK_VAL_MASK (1 << 2) 677 # define GPIO_CLOCK_VAL_OUT (1 << 3) 678 # define GPIO_CLOCK_VAL_IN (1 << 4) 679 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 680 # define GPIO_DATA_DIR_MASK (1 << 8) 681 # define GPIO_DATA_DIR_IN (0 << 9) 682 # define GPIO_DATA_DIR_OUT (1 << 9) 683 # define GPIO_DATA_VAL_MASK (1 << 10) 684 # define GPIO_DATA_VAL_OUT (1 << 11) 685 # define GPIO_DATA_VAL_IN (1 << 12) 686 # define GPIO_DATA_PULLUP_DISABLE (1 << 13) 687 688 #define GMBUS0 0x5100 /* clock/port select */ 689 #define GMBUS_RATE_100KHZ (0<<8) 690 #define GMBUS_RATE_50KHZ (1<<8) 691 #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ 692 #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ 693 #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ 694 #define GMBUS_PORT_DISABLED 0 695 #define GMBUS_PORT_SSC 1 696 #define GMBUS_PORT_VGADDC 2 697 #define GMBUS_PORT_PANEL 3 698 #define GMBUS_PORT_DPC 4 /* HDMIC */ 699 #define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ 700 /* 6 reserved */ 701 #define GMBUS_PORT_DPD 7 /* HDMID */ 702 #define GMBUS_NUM_PORTS 8 703 #define GMBUS1 0x5104 /* command/status */ 704 #define GMBUS_SW_CLR_INT (1<<31) 705 #define GMBUS_SW_RDY (1<<30) 706 #define GMBUS_ENT (1<<29) /* enable timeout */ 707 #define GMBUS_CYCLE_NONE (0<<25) 708 #define GMBUS_CYCLE_WAIT (1<<25) 709 #define GMBUS_CYCLE_INDEX (2<<25) 710 #define GMBUS_CYCLE_STOP (4<<25) 711 #define GMBUS_BYTE_COUNT_SHIFT 16 712 #define GMBUS_SLAVE_INDEX_SHIFT 8 713 #define GMBUS_SLAVE_ADDR_SHIFT 1 714 #define GMBUS_SLAVE_READ (1<<0) 715 #define GMBUS_SLAVE_WRITE (0<<0) 716 #define GMBUS2 0x5108 /* status */ 717 #define GMBUS_INUSE (1<<15) 718 #define GMBUS_HW_WAIT_PHASE (1<<14) 719 #define GMBUS_STALL_TIMEOUT (1<<13) 720 #define GMBUS_INT (1<<12) 721 #define GMBUS_HW_RDY (1<<11) 722 #define GMBUS_SATOER (1<<10) 723 #define GMBUS_ACTIVE (1<<9) 724 #define GMBUS3 0x510c /* data buffer bytes 3-0 */ 725 #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */ 726 #define GMBUS_SLAVE_TIMEOUT_EN (1<<4) 727 #define GMBUS_NAK_EN (1<<3) 728 #define GMBUS_IDLE_EN (1<<2) 729 #define GMBUS_HW_WAIT_EN (1<<1) 730 #define GMBUS_HW_RDY_EN (1<<0) 731 #define GMBUS5 0x5120 /* byte index */ 732 #define GMBUS_2BYTE_INDEX_EN (1<<31) 733 734 /* 735 * Clock control & power management 736 */ 737 738 #define VGA0 0x6000 739 #define VGA1 0x6004 740 #define VGA_PD 0x6010 741 #define VGA0_PD_P2_DIV_4 (1 << 7) 742 #define VGA0_PD_P1_DIV_2 (1 << 5) 743 #define VGA0_PD_P1_SHIFT 0 744 #define VGA0_PD_P1_MASK (0x1f << 0) 745 #define VGA1_PD_P2_DIV_4 (1 << 15) 746 #define VGA1_PD_P1_DIV_2 (1 << 13) 747 #define VGA1_PD_P1_SHIFT 8 748 #define VGA1_PD_P1_MASK (0x1f << 8) 749 #define _DPLL_A 0x06014 750 #define _DPLL_B 0x06018 751 #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B) 752 #define DPLL_VCO_ENABLE (1 << 31) 753 #define DPLL_DVO_HIGH_SPEED (1 << 30) 754 #define DPLL_SYNCLOCK_ENABLE (1 << 29) 755 #define DPLL_VGA_MODE_DIS (1 << 28) 756 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 757 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 758 #define DPLL_MODE_MASK (3 << 26) 759 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 760 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 761 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 762 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 763 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 764 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 765 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ 766 767 #define SRX_INDEX 0x3c4 768 #define SRX_DATA 0x3c5 769 #define SR01 1 770 #define SR01_SCREEN_OFF (1<<5) 771 772 #define PPCR 0x61204 773 #define PPCR_ON (1<<0) 774 775 #define DVOB 0x61140 776 #define DVOB_ON (1<<31) 777 #define DVOC 0x61160 778 #define DVOC_ON (1<<31) 779 #define LVDS 0x61180 780 #define LVDS_ON (1<<31) 781 782 /* Scratch pad debug 0 reg: 783 */ 784 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 785 /* 786 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 787 * this field (only one bit may be set). 788 */ 789 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 790 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 791 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 792 /* i830, required in DVO non-gang */ 793 #define PLL_P2_DIVIDE_BY_4 (1 << 23) 794 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 795 #define PLL_REF_INPUT_DREFCLK (0 << 13) 796 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 797 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 798 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 799 #define PLL_REF_INPUT_MASK (3 << 13) 800 #define PLL_LOAD_PULSE_PHASE_SHIFT 9 801 /* Ironlake */ 802 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 803 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) 804 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9) 805 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 806 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff 807 808 /* 809 * Parallel to Serial Load Pulse phase selection. 810 * Selects the phase for the 10X DPLL clock for the PCIe 811 * digital display port. The range is 4 to 13; 10 or more 812 * is just a flip delay. The default is 6 813 */ 814 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 815 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 816 /* 817 * SDVO multiplier for 945G/GM. Not used on 965. 818 */ 819 #define SDVO_MULTIPLIER_MASK 0x000000ff 820 #define SDVO_MULTIPLIER_SHIFT_HIRES 4 821 #define SDVO_MULTIPLIER_SHIFT_VGA 0 822 #define _DPLL_A_MD 0x0601c /* 965+ only */ 823 /* 824 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 825 * 826 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 827 */ 828 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 829 #define DPLL_MD_UDI_DIVIDER_SHIFT 24 830 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 831 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 832 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 833 /* 834 * SDVO/UDI pixel multiplier. 835 * 836 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 837 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 838 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 839 * dummy bytes in the datastream at an increased clock rate, with both sides of 840 * the link knowing how many bytes are fill. 841 * 842 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 843 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 844 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 845 * through an SDVO command. 846 * 847 * This register field has values of multiplication factor minus 1, with 848 * a maximum multiplier of 5 for SDVO. 849 */ 850 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 851 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 852 /* 853 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 854 * This best be set to the default value (3) or the CRT won't work. No, 855 * I don't entirely understand what this does... 856 */ 857 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 858 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 859 #define _DPLL_B_MD 0x06020 /* 965+ only */ 860 #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD) 861 #define _FPA0 0x06040 862 #define _FPA1 0x06044 863 #define _FPB0 0x06048 864 #define _FPB1 0x0604c 865 #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0) 866 #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1) 867 #define FP_N_DIV_MASK 0x003f0000 868 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 869 #define FP_N_DIV_SHIFT 16 870 #define FP_M1_DIV_MASK 0x00003f00 871 #define FP_M1_DIV_SHIFT 8 872 #define FP_M2_DIV_MASK 0x0000003f 873 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff 874 #define FP_M2_DIV_SHIFT 0 875 #define DPLL_TEST 0x606c 876 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 877 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 878 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 879 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 880 #define DPLLB_TEST_N_BYPASS (1 << 19) 881 #define DPLLB_TEST_M_BYPASS (1 << 18) 882 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 883 #define DPLLA_TEST_N_BYPASS (1 << 3) 884 #define DPLLA_TEST_M_BYPASS (1 << 2) 885 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 886 #define D_STATE 0x6104 887 #define DSTATE_GFX_RESET_I830 (1<<6) 888 #define DSTATE_PLL_D3_OFF (1<<3) 889 #define DSTATE_GFX_CLOCK_GATING (1<<1) 890 #define DSTATE_DOT_CLOCK_GATING (1<<0) 891 #define DSPCLK_GATE_D 0x6200 892 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 893 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 894 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 895 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ 896 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ 897 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ 898 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ 899 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ 900 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ 901 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ 902 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ 903 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ 904 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ 905 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ 906 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ 907 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ 908 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ 909 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ 910 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ 911 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 912 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) 913 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) 914 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) 915 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ 916 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ 917 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ 918 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) 919 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) 920 /** 921 * This bit must be set on the 830 to prevent hangs when turning off the 922 * overlay scaler. 923 */ 924 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 925 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) 926 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) 927 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ 928 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ 929 930 #define RENCLK_GATE_D1 0x6204 931 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ 932 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ 933 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) 934 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) 935 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) 936 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) 937 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) 938 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) 939 # define MAG_CLOCK_GATE_DISABLE (1 << 5) 940 /** This bit must be unset on 855,865 */ 941 # define MECI_CLOCK_GATE_DISABLE (1 << 4) 942 # define DCMP_CLOCK_GATE_DISABLE (1 << 3) 943 # define MEC_CLOCK_GATE_DISABLE (1 << 2) 944 # define MECO_CLOCK_GATE_DISABLE (1 << 1) 945 /** This bit must be set on 855,865. */ 946 # define SV_CLOCK_GATE_DISABLE (1 << 0) 947 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) 948 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) 949 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) 950 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) 951 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) 952 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) 953 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) 954 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) 955 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) 956 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) 957 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) 958 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) 959 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) 960 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) 961 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) 962 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) 963 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) 964 965 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) 966 /** This bit must always be set on 965G/965GM */ 967 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) 968 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) 969 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) 970 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) 971 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) 972 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) 973 /** This bit must always be set on 965G */ 974 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) 975 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) 976 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) 977 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) 978 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) 979 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) 980 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) 981 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) 982 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) 983 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) 984 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) 985 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) 986 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) 987 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) 988 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) 989 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) 990 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) 991 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) 992 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) 993 994 #define RENCLK_GATE_D2 0x6208 995 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) 996 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) 997 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) 998 #define RAMCLK_GATE_D 0x6210 /* CRL only */ 999 #define DEUC 0x6214 /* CRL only */ 1000 1001 /* 1002 * Palette regs 1003 */ 1004 1005 #define _PALETTE_A 0x0a000 1006 #define _PALETTE_B 0x0a800 1007 #define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B) 1008 1009 /* MCH MMIO space */ 1010 1011 /* 1012 * MCHBAR mirror. 1013 * 1014 * This mirrors the MCHBAR MMIO space whose location is determined by 1015 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in 1016 * every way. It is not accessible from the CP register read instructions. 1017 * 1018 */ 1019 #define MCHBAR_MIRROR_BASE 0x10000 1020 1021 #define MCHBAR_MIRROR_BASE_SNB 0x140000 1022 1023 /** 915-945 and GM965 MCH register controlling DRAM channel access */ 1024 #define DCC 0x10200 1025 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) 1026 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) 1027 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) 1028 #define DCC_ADDRESSING_MODE_MASK (3 << 0) 1029 #define DCC_CHANNEL_XOR_DISABLE (1 << 10) 1030 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9) 1031 1032 /** Pineview MCH register contains DDR3 setting */ 1033 #define CSHRDDR3CTL 0x101a8 1034 #define CSHRDDR3CTL_DDR3 (1 << 2) 1035 1036 /** 965 MCH register controlling DRAM channel configuration */ 1037 #define C0DRB3 0x10206 1038 #define C1DRB3 0x10606 1039 1040 /* Clocking configuration register */ 1041 #define CLKCFG 0x10c00 1042 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */ 1043 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */ 1044 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */ 1045 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */ 1046 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */ 1047 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */ 1048 /* Note, below two are guess */ 1049 #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */ 1050 #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */ 1051 #define CLKCFG_FSB_MASK (7 << 0) 1052 #define CLKCFG_MEM_533 (1 << 4) 1053 #define CLKCFG_MEM_667 (2 << 4) 1054 #define CLKCFG_MEM_800 (3 << 4) 1055 #define CLKCFG_MEM_MASK (7 << 4) 1056 1057 #define TSC1 0x11001 1058 #define TSE (1<<0) 1059 #define TR1 0x11006 1060 #define TSFS 0x11020 1061 #define TSFS_SLOPE_MASK 0x0000ff00 1062 #define TSFS_SLOPE_SHIFT 8 1063 #define TSFS_INTR_MASK 0x000000ff 1064 1065 #define CRSTANDVID 0x11100 1066 #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ 1067 #define PXVFREQ_PX_MASK 0x7f000000 1068 #define PXVFREQ_PX_SHIFT 24 1069 #define VIDFREQ_BASE 0x11110 1070 #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */ 1071 #define VIDFREQ2 0x11114 1072 #define VIDFREQ3 0x11118 1073 #define VIDFREQ4 0x1111c 1074 #define VIDFREQ_P0_MASK 0x1f000000 1075 #define VIDFREQ_P0_SHIFT 24 1076 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000 1077 #define VIDFREQ_P0_CSCLK_SHIFT 20 1078 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000 1079 #define VIDFREQ_P0_CRCLK_SHIFT 16 1080 #define VIDFREQ_P1_MASK 0x00001f00 1081 #define VIDFREQ_P1_SHIFT 8 1082 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0 1083 #define VIDFREQ_P1_CSCLK_SHIFT 4 1084 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f 1085 #define INTTOEXT_BASE_ILK 0x11300 1086 #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */ 1087 #define INTTOEXT_MAP3_SHIFT 24 1088 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) 1089 #define INTTOEXT_MAP2_SHIFT 16 1090 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) 1091 #define INTTOEXT_MAP1_SHIFT 8 1092 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) 1093 #define INTTOEXT_MAP0_SHIFT 0 1094 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) 1095 #define MEMSWCTL 0x11170 /* Ironlake only */ 1096 #define MEMCTL_CMD_MASK 0xe000 1097 #define MEMCTL_CMD_SHIFT 13 1098 #define MEMCTL_CMD_RCLK_OFF 0 1099 #define MEMCTL_CMD_RCLK_ON 1 1100 #define MEMCTL_CMD_CHFREQ 2 1101 #define MEMCTL_CMD_CHVID 3 1102 #define MEMCTL_CMD_VMMOFF 4 1103 #define MEMCTL_CMD_VMMON 5 1104 #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears 1105 when command complete */ 1106 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ 1107 #define MEMCTL_FREQ_SHIFT 8 1108 #define MEMCTL_SFCAVM (1<<7) 1109 #define MEMCTL_TGT_VID_MASK 0x007f 1110 #define MEMIHYST 0x1117c 1111 #define MEMINTREN 0x11180 /* 16 bits */ 1112 #define MEMINT_RSEXIT_EN (1<<8) 1113 #define MEMINT_CX_SUPR_EN (1<<7) 1114 #define MEMINT_CONT_BUSY_EN (1<<6) 1115 #define MEMINT_AVG_BUSY_EN (1<<5) 1116 #define MEMINT_EVAL_CHG_EN (1<<4) 1117 #define MEMINT_MON_IDLE_EN (1<<3) 1118 #define MEMINT_UP_EVAL_EN (1<<2) 1119 #define MEMINT_DOWN_EVAL_EN (1<<1) 1120 #define MEMINT_SW_CMD_EN (1<<0) 1121 #define MEMINTRSTR 0x11182 /* 16 bits */ 1122 #define MEM_RSEXIT_MASK 0xc000 1123 #define MEM_RSEXIT_SHIFT 14 1124 #define MEM_CONT_BUSY_MASK 0x3000 1125 #define MEM_CONT_BUSY_SHIFT 12 1126 #define MEM_AVG_BUSY_MASK 0x0c00 1127 #define MEM_AVG_BUSY_SHIFT 10 1128 #define MEM_EVAL_CHG_MASK 0x0300 1129 #define MEM_EVAL_BUSY_SHIFT 8 1130 #define MEM_MON_IDLE_MASK 0x00c0 1131 #define MEM_MON_IDLE_SHIFT 6 1132 #define MEM_UP_EVAL_MASK 0x0030 1133 #define MEM_UP_EVAL_SHIFT 4 1134 #define MEM_DOWN_EVAL_MASK 0x000c 1135 #define MEM_DOWN_EVAL_SHIFT 2 1136 #define MEM_SW_CMD_MASK 0x0003 1137 #define MEM_INT_STEER_GFX 0 1138 #define MEM_INT_STEER_CMR 1 1139 #define MEM_INT_STEER_SMI 2 1140 #define MEM_INT_STEER_SCI 3 1141 #define MEMINTRSTS 0x11184 1142 #define MEMINT_RSEXIT (1<<7) 1143 #define MEMINT_CONT_BUSY (1<<6) 1144 #define MEMINT_AVG_BUSY (1<<5) 1145 #define MEMINT_EVAL_CHG (1<<4) 1146 #define MEMINT_MON_IDLE (1<<3) 1147 #define MEMINT_UP_EVAL (1<<2) 1148 #define MEMINT_DOWN_EVAL (1<<1) 1149 #define MEMINT_SW_CMD (1<<0) 1150 #define MEMMODECTL 0x11190 1151 #define MEMMODE_BOOST_EN (1<<31) 1152 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ 1153 #define MEMMODE_BOOST_FREQ_SHIFT 24 1154 #define MEMMODE_IDLE_MODE_MASK 0x00030000 1155 #define MEMMODE_IDLE_MODE_SHIFT 16 1156 #define MEMMODE_IDLE_MODE_EVAL 0 1157 #define MEMMODE_IDLE_MODE_CONT 1 1158 #define MEMMODE_HWIDLE_EN (1<<15) 1159 #define MEMMODE_SWMODE_EN (1<<14) 1160 #define MEMMODE_RCLK_GATE (1<<13) 1161 #define MEMMODE_HW_UPDATE (1<<12) 1162 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ 1163 #define MEMMODE_FSTART_SHIFT 8 1164 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ 1165 #define MEMMODE_FMAX_SHIFT 4 1166 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ 1167 #define RCBMAXAVG 0x1119c 1168 #define MEMSWCTL2 0x1119e /* Cantiga only */ 1169 #define SWMEMCMD_RENDER_OFF (0 << 13) 1170 #define SWMEMCMD_RENDER_ON (1 << 13) 1171 #define SWMEMCMD_SWFREQ (2 << 13) 1172 #define SWMEMCMD_TARVID (3 << 13) 1173 #define SWMEMCMD_VRM_OFF (4 << 13) 1174 #define SWMEMCMD_VRM_ON (5 << 13) 1175 #define CMDSTS (1<<12) 1176 #define SFCAVM (1<<11) 1177 #define SWFREQ_MASK 0x0380 /* P0-7 */ 1178 #define SWFREQ_SHIFT 7 1179 #define TARVID_MASK 0x001f 1180 #define MEMSTAT_CTG 0x111a0 1181 #define RCBMINAVG 0x111a0 1182 #define RCUPEI 0x111b0 1183 #define RCDNEI 0x111b4 1184 #define RSTDBYCTL 0x111b8 1185 #define RS1EN (1<<31) 1186 #define RS2EN (1<<30) 1187 #define RS3EN (1<<29) 1188 #define D3RS3EN (1<<28) /* Display D3 imlies RS3 */ 1189 #define SWPROMORSX (1<<27) /* RSx promotion timers ignored */ 1190 #define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */ 1191 #define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */ 1192 #define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */ 1193 #define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */ 1194 #define RSX_STATUS_MASK (7<<20) 1195 #define RSX_STATUS_ON (0<<20) 1196 #define RSX_STATUS_RC1 (1<<20) 1197 #define RSX_STATUS_RC1E (2<<20) 1198 #define RSX_STATUS_RS1 (3<<20) 1199 #define RSX_STATUS_RS2 (4<<20) /* aka rc6 */ 1200 #define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */ 1201 #define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */ 1202 #define RSX_STATUS_RSVD2 (7<<20) 1203 #define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */ 1204 #define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */ 1205 #define JRSC (1<<17) /* rsx coupled to cpu c-state */ 1206 #define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */ 1207 #define RS1CONTSAV_MASK (3<<14) 1208 #define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */ 1209 #define RS1CONTSAV_RSVD (1<<14) 1210 #define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */ 1211 #define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */ 1212 #define NORMSLEXLAT_MASK (3<<12) 1213 #define SLOW_RS123 (0<<12) 1214 #define SLOW_RS23 (1<<12) 1215 #define SLOW_RS3 (2<<12) 1216 #define NORMAL_RS123 (3<<12) 1217 #define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */ 1218 #define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ 1219 #define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */ 1220 #define STATELOCK (1<<7) /* locked to rs_cstate if 0 */ 1221 #define RS_CSTATE_MASK (3<<4) 1222 #define RS_CSTATE_C367_RS1 (0<<4) 1223 #define RS_CSTATE_C36_RS1_C7_RS2 (1<<4) 1224 #define RS_CSTATE_RSVD (2<<4) 1225 #define RS_CSTATE_C367_RS2 (3<<4) 1226 #define REDSAVES (1<<3) /* no context save if was idle during rs0 */ 1227 #define REDRESTORES (1<<2) /* no restore if was idle during rs0 */ 1228 #define VIDCTL 0x111c0 1229 #define VIDSTS 0x111c8 1230 #define VIDSTART 0x111cc /* 8 bits */ 1231 #define MEMSTAT_ILK 0x111f8 1232 #define MEMSTAT_VID_MASK 0x7f00 1233 #define MEMSTAT_VID_SHIFT 8 1234 #define MEMSTAT_PSTATE_MASK 0x00f8 1235 #define MEMSTAT_PSTATE_SHIFT 3 1236 #define MEMSTAT_MON_ACTV (1<<2) 1237 #define MEMSTAT_SRC_CTL_MASK 0x0003 1238 #define MEMSTAT_SRC_CTL_CORE 0 1239 #define MEMSTAT_SRC_CTL_TRB 1 1240 #define MEMSTAT_SRC_CTL_THM 2 1241 #define MEMSTAT_SRC_CTL_STDBY 3 1242 #define RCPREVBSYTUPAVG 0x113b8 1243 #define RCPREVBSYTDNAVG 0x113bc 1244 #define PMMISC 0x11214 1245 #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */ 1246 #define SDEW 0x1124c 1247 #define CSIEW0 0x11250 1248 #define CSIEW1 0x11254 1249 #define CSIEW2 0x11258 1250 #define PEW 0x1125c 1251 #define DEW 0x11270 1252 #define MCHAFE 0x112c0 1253 #define CSIEC 0x112e0 1254 #define DMIEC 0x112e4 1255 #define DDREC 0x112e8 1256 #define PEG0EC 0x112ec 1257 #define PEG1EC 0x112f0 1258 #define GFXEC 0x112f4 1259 #define RPPREVBSYTUPAVG 0x113b8 1260 #define RPPREVBSYTDNAVG 0x113bc 1261 #define ECR 0x11600 1262 #define ECR_GPFE (1<<31) 1263 #define ECR_IMONE (1<<30) 1264 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ 1265 #define OGW0 0x11608 1266 #define OGW1 0x1160c 1267 #define EG0 0x11610 1268 #define EG1 0x11614 1269 #define EG2 0x11618 1270 #define EG3 0x1161c 1271 #define EG4 0x11620 1272 #define EG5 0x11624 1273 #define EG6 0x11628 1274 #define EG7 0x1162c 1275 #define PXW 0x11664 1276 #define PXWL 0x11680 1277 #define LCFUSE02 0x116c0 1278 #define LCFUSE_HIV_MASK 0x000000ff 1279 #define CSIPLL0 0x12c10 1280 #define DDRMPLL1 0X12c20 1281 #define PEG_BAND_GAP_DATA 0x14d68 1282 1283 #define GEN6_GT_PERF_STATUS 0x145948 1284 #define GEN6_RP_STATE_LIMITS 0x145994 1285 #define GEN6_RP_STATE_CAP 0x145998 1286 1287 /* 1288 * Logical Context regs 1289 */ 1290 #define CCID 0x2180 1291 #define CCID_EN (1<<0) 1292 /* 1293 * Overlay regs 1294 */ 1295 1296 #define OVADD 0x30000 1297 #define DOVSTA 0x30008 1298 #define OC_BUF (0x3<<20) 1299 #define OGAMC5 0x30010 1300 #define OGAMC4 0x30014 1301 #define OGAMC3 0x30018 1302 #define OGAMC2 0x3001c 1303 #define OGAMC1 0x30020 1304 #define OGAMC0 0x30024 1305 1306 /* 1307 * Display engine regs 1308 */ 1309 1310 /* Pipe A timing regs */ 1311 #define _HTOTAL_A 0x60000 1312 #define _HBLANK_A 0x60004 1313 #define _HSYNC_A 0x60008 1314 #define _VTOTAL_A 0x6000c 1315 #define _VBLANK_A 0x60010 1316 #define _VSYNC_A 0x60014 1317 #define _PIPEASRC 0x6001c 1318 #define _BCLRPAT_A 0x60020 1319 1320 /* Pipe B timing regs */ 1321 #define _HTOTAL_B 0x61000 1322 #define _HBLANK_B 0x61004 1323 #define _HSYNC_B 0x61008 1324 #define _VTOTAL_B 0x6100c 1325 #define _VBLANK_B 0x61010 1326 #define _VSYNC_B 0x61014 1327 #define _PIPEBSRC 0x6101c 1328 #define _BCLRPAT_B 0x61020 1329 1330 #define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B) 1331 #define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B) 1332 #define HSYNC(pipe) _PIPE(pipe, _HSYNC_A, _HSYNC_B) 1333 #define VTOTAL(pipe) _PIPE(pipe, _VTOTAL_A, _VTOTAL_B) 1334 #define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B) 1335 #define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B) 1336 #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B) 1337 1338 /* VGA port control */ 1339 #define ADPA 0x61100 1340 #define ADPA_DAC_ENABLE (1<<31) 1341 #define ADPA_DAC_DISABLE 0 1342 #define ADPA_PIPE_SELECT_MASK (1<<30) 1343 #define ADPA_PIPE_A_SELECT 0 1344 #define ADPA_PIPE_B_SELECT (1<<30) 1345 #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30) 1346 #define ADPA_USE_VGA_HVPOLARITY (1<<15) 1347 #define ADPA_SETS_HVPOLARITY 0 1348 #define ADPA_VSYNC_CNTL_DISABLE (1<<11) 1349 #define ADPA_VSYNC_CNTL_ENABLE 0 1350 #define ADPA_HSYNC_CNTL_DISABLE (1<<10) 1351 #define ADPA_HSYNC_CNTL_ENABLE 0 1352 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4) 1353 #define ADPA_VSYNC_ACTIVE_LOW 0 1354 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3) 1355 #define ADPA_HSYNC_ACTIVE_LOW 0 1356 #define ADPA_DPMS_MASK (~(3<<10)) 1357 #define ADPA_DPMS_ON (0<<10) 1358 #define ADPA_DPMS_SUSPEND (1<<10) 1359 #define ADPA_DPMS_STANDBY (2<<10) 1360 #define ADPA_DPMS_OFF (3<<10) 1361 1362 1363 /* Hotplug control (945+ only) */ 1364 #define PORT_HOTPLUG_EN 0x61110 1365 #define HDMIB_HOTPLUG_INT_EN (1 << 29) 1366 #define DPB_HOTPLUG_INT_EN (1 << 29) 1367 #define HDMIC_HOTPLUG_INT_EN (1 << 28) 1368 #define DPC_HOTPLUG_INT_EN (1 << 28) 1369 #define HDMID_HOTPLUG_INT_EN (1 << 27) 1370 #define DPD_HOTPLUG_INT_EN (1 << 27) 1371 #define SDVOB_HOTPLUG_INT_EN (1 << 26) 1372 #define SDVOC_HOTPLUG_INT_EN (1 << 25) 1373 #define TV_HOTPLUG_INT_EN (1 << 18) 1374 #define CRT_HOTPLUG_INT_EN (1 << 9) 1375 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 1376 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 1377 /* must use period 64 on GM45 according to docs */ 1378 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 1379 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 1380 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 1381 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 1382 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 1383 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 1384 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 1385 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 1386 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 1387 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 1388 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 1389 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 1390 1391 #define PORT_HOTPLUG_STAT 0x61114 1392 #define HDMIB_HOTPLUG_INT_STATUS (1 << 29) 1393 #define DPB_HOTPLUG_INT_STATUS (1 << 29) 1394 #define HDMIC_HOTPLUG_INT_STATUS (1 << 28) 1395 #define DPC_HOTPLUG_INT_STATUS (1 << 28) 1396 #define HDMID_HOTPLUG_INT_STATUS (1 << 27) 1397 #define DPD_HOTPLUG_INT_STATUS (1 << 27) 1398 #define CRT_HOTPLUG_INT_STATUS (1 << 11) 1399 #define TV_HOTPLUG_INT_STATUS (1 << 10) 1400 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 1401 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 1402 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 1403 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 1404 #define SDVOC_HOTPLUG_INT_STATUS (1 << 7) 1405 #define SDVOB_HOTPLUG_INT_STATUS (1 << 6) 1406 1407 /* SDVO port control */ 1408 #define SDVOB 0x61140 1409 #define SDVOC 0x61160 1410 #define SDVO_ENABLE (1 << 31) 1411 #define SDVO_PIPE_B_SELECT (1 << 30) 1412 #define SDVO_STALL_SELECT (1 << 29) 1413 #define SDVO_INTERRUPT_ENABLE (1 << 26) 1414 /** 1415 * 915G/GM SDVO pixel multiplier. 1416 * 1417 * Programmed value is multiplier - 1, up to 5x. 1418 * 1419 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 1420 */ 1421 #define SDVO_PORT_MULTIPLY_MASK (7 << 23) 1422 #define SDVO_PORT_MULTIPLY_SHIFT 23 1423 #define SDVO_PHASE_SELECT_MASK (15 << 19) 1424 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 1425 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 1426 #define SDVOC_GANG_MODE (1 << 16) 1427 #define SDVO_ENCODING_SDVO (0x0 << 10) 1428 #define SDVO_ENCODING_HDMI (0x2 << 10) 1429 /** Requird for HDMI operation */ 1430 #define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9) 1431 #define SDVO_COLOR_RANGE_16_235 (1 << 8) 1432 #define SDVO_BORDER_ENABLE (1 << 7) 1433 #define SDVO_AUDIO_ENABLE (1 << 6) 1434 /** New with 965, default is to be set */ 1435 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) 1436 /** New with 965, default is to be set */ 1437 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) 1438 #define SDVOB_PCIE_CONCURRENCY (1 << 3) 1439 #define SDVO_DETECTED (1 << 2) 1440 /* Bits to be preserved when writing */ 1441 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26)) 1442 #define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26)) 1443 1444 /* DVO port control */ 1445 #define DVOA 0x61120 1446 #define DVOB 0x61140 1447 #define DVOC 0x61160 1448 #define DVO_ENABLE (1 << 31) 1449 #define DVO_PIPE_B_SELECT (1 << 30) 1450 #define DVO_PIPE_STALL_UNUSED (0 << 28) 1451 #define DVO_PIPE_STALL (1 << 28) 1452 #define DVO_PIPE_STALL_TV (2 << 28) 1453 #define DVO_PIPE_STALL_MASK (3 << 28) 1454 #define DVO_USE_VGA_SYNC (1 << 15) 1455 #define DVO_DATA_ORDER_I740 (0 << 14) 1456 #define DVO_DATA_ORDER_FP (1 << 14) 1457 #define DVO_VSYNC_DISABLE (1 << 11) 1458 #define DVO_HSYNC_DISABLE (1 << 10) 1459 #define DVO_VSYNC_TRISTATE (1 << 9) 1460 #define DVO_HSYNC_TRISTATE (1 << 8) 1461 #define DVO_BORDER_ENABLE (1 << 7) 1462 #define DVO_DATA_ORDER_GBRG (1 << 6) 1463 #define DVO_DATA_ORDER_RGGB (0 << 6) 1464 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) 1465 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) 1466 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4) 1467 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3) 1468 #define DVO_BLANK_ACTIVE_HIGH (1 << 2) 1469 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ 1470 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ 1471 #define DVO_PRESERVE_MASK (0x7<<24) 1472 #define DVOA_SRCDIM 0x61124 1473 #define DVOB_SRCDIM 0x61144 1474 #define DVOC_SRCDIM 0x61164 1475 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12 1476 #define DVO_SRCDIM_VERTICAL_SHIFT 0 1477 1478 /* LVDS port control */ 1479 #define LVDS 0x61180 1480 /* 1481 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 1482 * the DPLL semantics change when the LVDS is assigned to that pipe. 1483 */ 1484 #define LVDS_PORT_EN (1 << 31) 1485 /* Selects pipe B for LVDS data. Must be set on pre-965. */ 1486 #define LVDS_PIPEB_SELECT (1 << 30) 1487 #define LVDS_PIPE_MASK (1 << 30) 1488 #define LVDS_PIPE(pipe) ((pipe) << 30) 1489 /* LVDS dithering flag on 965/g4x platform */ 1490 #define LVDS_ENABLE_DITHER (1 << 25) 1491 /* LVDS sync polarity flags. Set to invert (i.e. negative) */ 1492 #define LVDS_VSYNC_POLARITY (1 << 21) 1493 #define LVDS_HSYNC_POLARITY (1 << 20) 1494 1495 /* Enable border for unscaled (or aspect-scaled) display */ 1496 #define LVDS_BORDER_ENABLE (1 << 15) 1497 /* 1498 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 1499 * pixel. 1500 */ 1501 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 1502 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 1503 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 1504 /* 1505 * Controls the A3 data pair, which contains the additional LSBs for 24 bit 1506 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 1507 * on. 1508 */ 1509 #define LVDS_A3_POWER_MASK (3 << 6) 1510 #define LVDS_A3_POWER_DOWN (0 << 6) 1511 #define LVDS_A3_POWER_UP (3 << 6) 1512 /* 1513 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 1514 * is set. 1515 */ 1516 #define LVDS_CLKB_POWER_MASK (3 << 4) 1517 #define LVDS_CLKB_POWER_DOWN (0 << 4) 1518 #define LVDS_CLKB_POWER_UP (3 << 4) 1519 /* 1520 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 1521 * setting for whether we are in dual-channel mode. The B3 pair will 1522 * additionally only be powered up when LVDS_A3_POWER_UP is set. 1523 */ 1524 #define LVDS_B0B3_POWER_MASK (3 << 2) 1525 #define LVDS_B0B3_POWER_DOWN (0 << 2) 1526 #define LVDS_B0B3_POWER_UP (3 << 2) 1527 1528 /* Video Data Island Packet control */ 1529 #define VIDEO_DIP_DATA 0x61178 1530 #define VIDEO_DIP_CTL 0x61170 1531 #define VIDEO_DIP_ENABLE (1 << 31) 1532 #define VIDEO_DIP_PORT_B (1 << 29) 1533 #define VIDEO_DIP_PORT_C (2 << 29) 1534 #define VIDEO_DIP_ENABLE_AVI (1 << 21) 1535 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) 1536 #define VIDEO_DIP_ENABLE_SPD (8 << 21) 1537 #define VIDEO_DIP_SELECT_AVI (0 << 19) 1538 #define VIDEO_DIP_SELECT_VENDOR (1 << 19) 1539 #define VIDEO_DIP_SELECT_SPD (3 << 19) 1540 #define VIDEO_DIP_SELECT_MASK (3 << 19) 1541 #define VIDEO_DIP_FREQ_ONCE (0 << 16) 1542 #define VIDEO_DIP_FREQ_VSYNC (1 << 16) 1543 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) 1544 1545 /* Panel power sequencing */ 1546 #define PP_STATUS 0x61200 1547 #define PP_ON (1 << 31) 1548 /* 1549 * Indicates that all dependencies of the panel are on: 1550 * 1551 * - PLL enabled 1552 * - pipe enabled 1553 * - LVDS/DVOB/DVOC on 1554 */ 1555 #define PP_READY (1 << 30) 1556 #define PP_SEQUENCE_NONE (0 << 28) 1557 #define PP_SEQUENCE_POWER_UP (1 << 28) 1558 #define PP_SEQUENCE_POWER_DOWN (2 << 28) 1559 #define PP_SEQUENCE_MASK (3 << 28) 1560 #define PP_SEQUENCE_SHIFT 28 1561 #define PP_CYCLE_DELAY_ACTIVE (1 << 27) 1562 #define PP_SEQUENCE_STATE_MASK 0x0000000f 1563 #define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0) 1564 #define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0) 1565 #define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0) 1566 #define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0) 1567 #define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0) 1568 #define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0) 1569 #define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0) 1570 #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0) 1571 #define PP_SEQUENCE_STATE_RESET (0xf << 0) 1572 #define PP_CONTROL 0x61204 1573 #define POWER_TARGET_ON (1 << 0) 1574 #define PP_ON_DELAYS 0x61208 1575 #define PP_OFF_DELAYS 0x6120c 1576 #define PP_DIVISOR 0x61210 1577 1578 /* Panel fitting */ 1579 #define PFIT_CONTROL 0x61230 1580 #define PFIT_ENABLE (1 << 31) 1581 #define PFIT_PIPE_MASK (3 << 29) 1582 #define PFIT_PIPE_SHIFT 29 1583 #define VERT_INTERP_DISABLE (0 << 10) 1584 #define VERT_INTERP_BILINEAR (1 << 10) 1585 #define VERT_INTERP_MASK (3 << 10) 1586 #define VERT_AUTO_SCALE (1 << 9) 1587 #define HORIZ_INTERP_DISABLE (0 << 6) 1588 #define HORIZ_INTERP_BILINEAR (1 << 6) 1589 #define HORIZ_INTERP_MASK (3 << 6) 1590 #define HORIZ_AUTO_SCALE (1 << 5) 1591 #define PANEL_8TO6_DITHER_ENABLE (1 << 3) 1592 #define PFIT_FILTER_FUZZY (0 << 24) 1593 #define PFIT_SCALING_AUTO (0 << 26) 1594 #define PFIT_SCALING_PROGRAMMED (1 << 26) 1595 #define PFIT_SCALING_PILLAR (2 << 26) 1596 #define PFIT_SCALING_LETTER (3 << 26) 1597 #define PFIT_PGM_RATIOS 0x61234 1598 #define PFIT_VERT_SCALE_MASK 0xfff00000 1599 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 1600 /* Pre-965 */ 1601 #define PFIT_VERT_SCALE_SHIFT 20 1602 #define PFIT_VERT_SCALE_MASK 0xfff00000 1603 #define PFIT_HORIZ_SCALE_SHIFT 4 1604 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 1605 /* 965+ */ 1606 #define PFIT_VERT_SCALE_SHIFT_965 16 1607 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000 1608 #define PFIT_HORIZ_SCALE_SHIFT_965 0 1609 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff 1610 1611 #define PFIT_AUTO_RATIOS 0x61238 1612 1613 /* Backlight control */ 1614 #define BLC_PWM_CTL 0x61254 1615 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 1616 #define BLC_PWM_CTL2 0x61250 /* 965+ only */ 1617 #define BLM_COMBINATION_MODE (1 << 30) 1618 /* 1619 * This is the most significant 15 bits of the number of backlight cycles in a 1620 * complete cycle of the modulated backlight control. 1621 * 1622 * The actual value is this field multiplied by two. 1623 */ 1624 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) 1625 #define BLM_LEGACY_MODE (1 << 16) 1626 /* 1627 * This is the number of cycles out of the backlight modulation cycle for which 1628 * the backlight is on. 1629 * 1630 * This field must be no greater than the number of cycles in the complete 1631 * backlight modulation cycle. 1632 */ 1633 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) 1634 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) 1635 1636 #define BLC_HIST_CTL 0x61260 1637 1638 /* TV port control */ 1639 #define TV_CTL 0x68000 1640 /** Enables the TV encoder */ 1641 # define TV_ENC_ENABLE (1 << 31) 1642 /** Sources the TV encoder input from pipe B instead of A. */ 1643 # define TV_ENC_PIPEB_SELECT (1 << 30) 1644 /** Outputs composite video (DAC A only) */ 1645 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) 1646 /** Outputs SVideo video (DAC B/C) */ 1647 # define TV_ENC_OUTPUT_SVIDEO (1 << 28) 1648 /** Outputs Component video (DAC A/B/C) */ 1649 # define TV_ENC_OUTPUT_COMPONENT (2 << 28) 1650 /** Outputs Composite and SVideo (DAC A/B/C) */ 1651 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) 1652 # define TV_TRILEVEL_SYNC (1 << 21) 1653 /** Enables slow sync generation (945GM only) */ 1654 # define TV_SLOW_SYNC (1 << 20) 1655 /** Selects 4x oversampling for 480i and 576p */ 1656 # define TV_OVERSAMPLE_4X (0 << 18) 1657 /** Selects 2x oversampling for 720p and 1080i */ 1658 # define TV_OVERSAMPLE_2X (1 << 18) 1659 /** Selects no oversampling for 1080p */ 1660 # define TV_OVERSAMPLE_NONE (2 << 18) 1661 /** Selects 8x oversampling */ 1662 # define TV_OVERSAMPLE_8X (3 << 18) 1663 /** Selects progressive mode rather than interlaced */ 1664 # define TV_PROGRESSIVE (1 << 17) 1665 /** Sets the colorburst to PAL mode. Required for non-M PAL modes. */ 1666 # define TV_PAL_BURST (1 << 16) 1667 /** Field for setting delay of Y compared to C */ 1668 # define TV_YC_SKEW_MASK (7 << 12) 1669 /** Enables a fix for 480p/576p standard definition modes on the 915GM only */ 1670 # define TV_ENC_SDP_FIX (1 << 11) 1671 /** 1672 * Enables a fix for the 915GM only. 1673 * 1674 * Not sure what it does. 1675 */ 1676 # define TV_ENC_C0_FIX (1 << 10) 1677 /** Bits that must be preserved by software */ 1678 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) 1679 # define TV_FUSE_STATE_MASK (3 << 4) 1680 /** Read-only state that reports all features enabled */ 1681 # define TV_FUSE_STATE_ENABLED (0 << 4) 1682 /** Read-only state that reports that Macrovision is disabled in hardware*/ 1683 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) 1684 /** Read-only state that reports that TV-out is disabled in hardware. */ 1685 # define TV_FUSE_STATE_DISABLED (2 << 4) 1686 /** Normal operation */ 1687 # define TV_TEST_MODE_NORMAL (0 << 0) 1688 /** Encoder test pattern 1 - combo pattern */ 1689 # define TV_TEST_MODE_PATTERN_1 (1 << 0) 1690 /** Encoder test pattern 2 - full screen vertical 75% color bars */ 1691 # define TV_TEST_MODE_PATTERN_2 (2 << 0) 1692 /** Encoder test pattern 3 - full screen horizontal 75% color bars */ 1693 # define TV_TEST_MODE_PATTERN_3 (3 << 0) 1694 /** Encoder test pattern 4 - random noise */ 1695 # define TV_TEST_MODE_PATTERN_4 (4 << 0) 1696 /** Encoder test pattern 5 - linear color ramps */ 1697 # define TV_TEST_MODE_PATTERN_5 (5 << 0) 1698 /** 1699 * This test mode forces the DACs to 50% of full output. 1700 * 1701 * This is used for load detection in combination with TVDAC_SENSE_MASK 1702 */ 1703 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) 1704 # define TV_TEST_MODE_MASK (7 << 0) 1705 1706 #define TV_DAC 0x68004 1707 # define TV_DAC_SAVE 0x00ffff00 1708 /** 1709 * Reports that DAC state change logic has reported change (RO). 1710 * 1711 * This gets cleared when TV_DAC_STATE_EN is cleared 1712 */ 1713 # define TVDAC_STATE_CHG (1 << 31) 1714 # define TVDAC_SENSE_MASK (7 << 28) 1715 /** Reports that DAC A voltage is above the detect threshold */ 1716 # define TVDAC_A_SENSE (1 << 30) 1717 /** Reports that DAC B voltage is above the detect threshold */ 1718 # define TVDAC_B_SENSE (1 << 29) 1719 /** Reports that DAC C voltage is above the detect threshold */ 1720 # define TVDAC_C_SENSE (1 << 28) 1721 /** 1722 * Enables DAC state detection logic, for load-based TV detection. 1723 * 1724 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set 1725 * to off, for load detection to work. 1726 */ 1727 # define TVDAC_STATE_CHG_EN (1 << 27) 1728 /** Sets the DAC A sense value to high */ 1729 # define TVDAC_A_SENSE_CTL (1 << 26) 1730 /** Sets the DAC B sense value to high */ 1731 # define TVDAC_B_SENSE_CTL (1 << 25) 1732 /** Sets the DAC C sense value to high */ 1733 # define TVDAC_C_SENSE_CTL (1 << 24) 1734 /** Overrides the ENC_ENABLE and DAC voltage levels */ 1735 # define DAC_CTL_OVERRIDE (1 << 7) 1736 /** Sets the slew rate. Must be preserved in software */ 1737 # define ENC_TVDAC_SLEW_FAST (1 << 6) 1738 # define DAC_A_1_3_V (0 << 4) 1739 # define DAC_A_1_1_V (1 << 4) 1740 # define DAC_A_0_7_V (2 << 4) 1741 # define DAC_A_MASK (3 << 4) 1742 # define DAC_B_1_3_V (0 << 2) 1743 # define DAC_B_1_1_V (1 << 2) 1744 # define DAC_B_0_7_V (2 << 2) 1745 # define DAC_B_MASK (3 << 2) 1746 # define DAC_C_1_3_V (0 << 0) 1747 # define DAC_C_1_1_V (1 << 0) 1748 # define DAC_C_0_7_V (2 << 0) 1749 # define DAC_C_MASK (3 << 0) 1750 1751 /** 1752 * CSC coefficients are stored in a floating point format with 9 bits of 1753 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, 1754 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with 1755 * -1 (0x3) being the only legal negative value. 1756 */ 1757 #define TV_CSC_Y 0x68010 1758 # define TV_RY_MASK 0x07ff0000 1759 # define TV_RY_SHIFT 16 1760 # define TV_GY_MASK 0x00000fff 1761 # define TV_GY_SHIFT 0 1762 1763 #define TV_CSC_Y2 0x68014 1764 # define TV_BY_MASK 0x07ff0000 1765 # define TV_BY_SHIFT 16 1766 /** 1767 * Y attenuation for component video. 1768 * 1769 * Stored in 1.9 fixed point. 1770 */ 1771 # define TV_AY_MASK 0x000003ff 1772 # define TV_AY_SHIFT 0 1773 1774 #define TV_CSC_U 0x68018 1775 # define TV_RU_MASK 0x07ff0000 1776 # define TV_RU_SHIFT 16 1777 # define TV_GU_MASK 0x000007ff 1778 # define TV_GU_SHIFT 0 1779 1780 #define TV_CSC_U2 0x6801c 1781 # define TV_BU_MASK 0x07ff0000 1782 # define TV_BU_SHIFT 16 1783 /** 1784 * U attenuation for component video. 1785 * 1786 * Stored in 1.9 fixed point. 1787 */ 1788 # define TV_AU_MASK 0x000003ff 1789 # define TV_AU_SHIFT 0 1790 1791 #define TV_CSC_V 0x68020 1792 # define TV_RV_MASK 0x0fff0000 1793 # define TV_RV_SHIFT 16 1794 # define TV_GV_MASK 0x000007ff 1795 # define TV_GV_SHIFT 0 1796 1797 #define TV_CSC_V2 0x68024 1798 # define TV_BV_MASK 0x07ff0000 1799 # define TV_BV_SHIFT 16 1800 /** 1801 * V attenuation for component video. 1802 * 1803 * Stored in 1.9 fixed point. 1804 */ 1805 # define TV_AV_MASK 0x000007ff 1806 # define TV_AV_SHIFT 0 1807 1808 #define TV_CLR_KNOBS 0x68028 1809 /** 2s-complement brightness adjustment */ 1810 # define TV_BRIGHTNESS_MASK 0xff000000 1811 # define TV_BRIGHTNESS_SHIFT 24 1812 /** Contrast adjustment, as a 2.6 unsigned floating point number */ 1813 # define TV_CONTRAST_MASK 0x00ff0000 1814 # define TV_CONTRAST_SHIFT 16 1815 /** Saturation adjustment, as a 2.6 unsigned floating point number */ 1816 # define TV_SATURATION_MASK 0x0000ff00 1817 # define TV_SATURATION_SHIFT 8 1818 /** Hue adjustment, as an integer phase angle in degrees */ 1819 # define TV_HUE_MASK 0x000000ff 1820 # define TV_HUE_SHIFT 0 1821 1822 #define TV_CLR_LEVEL 0x6802c 1823 /** Controls the DAC level for black */ 1824 # define TV_BLACK_LEVEL_MASK 0x01ff0000 1825 # define TV_BLACK_LEVEL_SHIFT 16 1826 /** Controls the DAC level for blanking */ 1827 # define TV_BLANK_LEVEL_MASK 0x000001ff 1828 # define TV_BLANK_LEVEL_SHIFT 0 1829 1830 #define TV_H_CTL_1 0x68030 1831 /** Number of pixels in the hsync. */ 1832 # define TV_HSYNC_END_MASK 0x1fff0000 1833 # define TV_HSYNC_END_SHIFT 16 1834 /** Total number of pixels minus one in the line (display and blanking). */ 1835 # define TV_HTOTAL_MASK 0x00001fff 1836 # define TV_HTOTAL_SHIFT 0 1837 1838 #define TV_H_CTL_2 0x68034 1839 /** Enables the colorburst (needed for non-component color) */ 1840 # define TV_BURST_ENA (1 << 31) 1841 /** Offset of the colorburst from the start of hsync, in pixels minus one. */ 1842 # define TV_HBURST_START_SHIFT 16 1843 # define TV_HBURST_START_MASK 0x1fff0000 1844 /** Length of the colorburst */ 1845 # define TV_HBURST_LEN_SHIFT 0 1846 # define TV_HBURST_LEN_MASK 0x0001fff 1847 1848 #define TV_H_CTL_3 0x68038 1849 /** End of hblank, measured in pixels minus one from start of hsync */ 1850 # define TV_HBLANK_END_SHIFT 16 1851 # define TV_HBLANK_END_MASK 0x1fff0000 1852 /** Start of hblank, measured in pixels minus one from start of hsync */ 1853 # define TV_HBLANK_START_SHIFT 0 1854 # define TV_HBLANK_START_MASK 0x0001fff 1855 1856 #define TV_V_CTL_1 0x6803c 1857 /** XXX */ 1858 # define TV_NBR_END_SHIFT 16 1859 # define TV_NBR_END_MASK 0x07ff0000 1860 /** XXX */ 1861 # define TV_VI_END_F1_SHIFT 8 1862 # define TV_VI_END_F1_MASK 0x00003f00 1863 /** XXX */ 1864 # define TV_VI_END_F2_SHIFT 0 1865 # define TV_VI_END_F2_MASK 0x0000003f 1866 1867 #define TV_V_CTL_2 0x68040 1868 /** Length of vsync, in half lines */ 1869 # define TV_VSYNC_LEN_MASK 0x07ff0000 1870 # define TV_VSYNC_LEN_SHIFT 16 1871 /** Offset of the start of vsync in field 1, measured in one less than the 1872 * number of half lines. 1873 */ 1874 # define TV_VSYNC_START_F1_MASK 0x00007f00 1875 # define TV_VSYNC_START_F1_SHIFT 8 1876 /** 1877 * Offset of the start of vsync in field 2, measured in one less than the 1878 * number of half lines. 1879 */ 1880 # define TV_VSYNC_START_F2_MASK 0x0000007f 1881 # define TV_VSYNC_START_F2_SHIFT 0 1882 1883 #define TV_V_CTL_3 0x68044 1884 /** Enables generation of the equalization signal */ 1885 # define TV_EQUAL_ENA (1 << 31) 1886 /** Length of vsync, in half lines */ 1887 # define TV_VEQ_LEN_MASK 0x007f0000 1888 # define TV_VEQ_LEN_SHIFT 16 1889 /** Offset of the start of equalization in field 1, measured in one less than 1890 * the number of half lines. 1891 */ 1892 # define TV_VEQ_START_F1_MASK 0x0007f00 1893 # define TV_VEQ_START_F1_SHIFT 8 1894 /** 1895 * Offset of the start of equalization in field 2, measured in one less than 1896 * the number of half lines. 1897 */ 1898 # define TV_VEQ_START_F2_MASK 0x000007f 1899 # define TV_VEQ_START_F2_SHIFT 0 1900 1901 #define TV_V_CTL_4 0x68048 1902 /** 1903 * Offset to start of vertical colorburst, measured in one less than the 1904 * number of lines from vertical start. 1905 */ 1906 # define TV_VBURST_START_F1_MASK 0x003f0000 1907 # define TV_VBURST_START_F1_SHIFT 16 1908 /** 1909 * Offset to the end of vertical colorburst, measured in one less than the 1910 * number of lines from the start of NBR. 1911 */ 1912 # define TV_VBURST_END_F1_MASK 0x000000ff 1913 # define TV_VBURST_END_F1_SHIFT 0 1914 1915 #define TV_V_CTL_5 0x6804c 1916 /** 1917 * Offset to start of vertical colorburst, measured in one less than the 1918 * number of lines from vertical start. 1919 */ 1920 # define TV_VBURST_START_F2_MASK 0x003f0000 1921 # define TV_VBURST_START_F2_SHIFT 16 1922 /** 1923 * Offset to the end of vertical colorburst, measured in one less than the 1924 * number of lines from the start of NBR. 1925 */ 1926 # define TV_VBURST_END_F2_MASK 0x000000ff 1927 # define TV_VBURST_END_F2_SHIFT 0 1928 1929 #define TV_V_CTL_6 0x68050 1930 /** 1931 * Offset to start of vertical colorburst, measured in one less than the 1932 * number of lines from vertical start. 1933 */ 1934 # define TV_VBURST_START_F3_MASK 0x003f0000 1935 # define TV_VBURST_START_F3_SHIFT 16 1936 /** 1937 * Offset to the end of vertical colorburst, measured in one less than the 1938 * number of lines from the start of NBR. 1939 */ 1940 # define TV_VBURST_END_F3_MASK 0x000000ff 1941 # define TV_VBURST_END_F3_SHIFT 0 1942 1943 #define TV_V_CTL_7 0x68054 1944 /** 1945 * Offset to start of vertical colorburst, measured in one less than the 1946 * number of lines from vertical start. 1947 */ 1948 # define TV_VBURST_START_F4_MASK 0x003f0000 1949 # define TV_VBURST_START_F4_SHIFT 16 1950 /** 1951 * Offset to the end of vertical colorburst, measured in one less than the 1952 * number of lines from the start of NBR. 1953 */ 1954 # define TV_VBURST_END_F4_MASK 0x000000ff 1955 # define TV_VBURST_END_F4_SHIFT 0 1956 1957 #define TV_SC_CTL_1 0x68060 1958 /** Turns on the first subcarrier phase generation DDA */ 1959 # define TV_SC_DDA1_EN (1 << 31) 1960 /** Turns on the first subcarrier phase generation DDA */ 1961 # define TV_SC_DDA2_EN (1 << 30) 1962 /** Turns on the first subcarrier phase generation DDA */ 1963 # define TV_SC_DDA3_EN (1 << 29) 1964 /** Sets the subcarrier DDA to reset frequency every other field */ 1965 # define TV_SC_RESET_EVERY_2 (0 << 24) 1966 /** Sets the subcarrier DDA to reset frequency every fourth field */ 1967 # define TV_SC_RESET_EVERY_4 (1 << 24) 1968 /** Sets the subcarrier DDA to reset frequency every eighth field */ 1969 # define TV_SC_RESET_EVERY_8 (2 << 24) 1970 /** Sets the subcarrier DDA to never reset the frequency */ 1971 # define TV_SC_RESET_NEVER (3 << 24) 1972 /** Sets the peak amplitude of the colorburst.*/ 1973 # define TV_BURST_LEVEL_MASK 0x00ff0000 1974 # define TV_BURST_LEVEL_SHIFT 16 1975 /** Sets the increment of the first subcarrier phase generation DDA */ 1976 # define TV_SCDDA1_INC_MASK 0x00000fff 1977 # define TV_SCDDA1_INC_SHIFT 0 1978 1979 #define TV_SC_CTL_2 0x68064 1980 /** Sets the rollover for the second subcarrier phase generation DDA */ 1981 # define TV_SCDDA2_SIZE_MASK 0x7fff0000 1982 # define TV_SCDDA2_SIZE_SHIFT 16 1983 /** Sets the increent of the second subcarrier phase generation DDA */ 1984 # define TV_SCDDA2_INC_MASK 0x00007fff 1985 # define TV_SCDDA2_INC_SHIFT 0 1986 1987 #define TV_SC_CTL_3 0x68068 1988 /** Sets the rollover for the third subcarrier phase generation DDA */ 1989 # define TV_SCDDA3_SIZE_MASK 0x7fff0000 1990 # define TV_SCDDA3_SIZE_SHIFT 16 1991 /** Sets the increent of the third subcarrier phase generation DDA */ 1992 # define TV_SCDDA3_INC_MASK 0x00007fff 1993 # define TV_SCDDA3_INC_SHIFT 0 1994 1995 #define TV_WIN_POS 0x68070 1996 /** X coordinate of the display from the start of horizontal active */ 1997 # define TV_XPOS_MASK 0x1fff0000 1998 # define TV_XPOS_SHIFT 16 1999 /** Y coordinate of the display from the start of vertical active (NBR) */ 2000 # define TV_YPOS_MASK 0x00000fff 2001 # define TV_YPOS_SHIFT 0 2002 2003 #define TV_WIN_SIZE 0x68074 2004 /** Horizontal size of the display window, measured in pixels*/ 2005 # define TV_XSIZE_MASK 0x1fff0000 2006 # define TV_XSIZE_SHIFT 16 2007 /** 2008 * Vertical size of the display window, measured in pixels. 2009 * 2010 * Must be even for interlaced modes. 2011 */ 2012 # define TV_YSIZE_MASK 0x00000fff 2013 # define TV_YSIZE_SHIFT 0 2014 2015 #define TV_FILTER_CTL_1 0x68080 2016 /** 2017 * Enables automatic scaling calculation. 2018 * 2019 * If set, the rest of the registers are ignored, and the calculated values can 2020 * be read back from the register. 2021 */ 2022 # define TV_AUTO_SCALE (1 << 31) 2023 /** 2024 * Disables the vertical filter. 2025 * 2026 * This is required on modes more than 1024 pixels wide */ 2027 # define TV_V_FILTER_BYPASS (1 << 29) 2028 /** Enables adaptive vertical filtering */ 2029 # define TV_VADAPT (1 << 28) 2030 # define TV_VADAPT_MODE_MASK (3 << 26) 2031 /** Selects the least adaptive vertical filtering mode */ 2032 # define TV_VADAPT_MODE_LEAST (0 << 26) 2033 /** Selects the moderately adaptive vertical filtering mode */ 2034 # define TV_VADAPT_MODE_MODERATE (1 << 26) 2035 /** Selects the most adaptive vertical filtering mode */ 2036 # define TV_VADAPT_MODE_MOST (3 << 26) 2037 /** 2038 * Sets the horizontal scaling factor. 2039 * 2040 * This should be the fractional part of the horizontal scaling factor divided 2041 * by the oversampling rate. TV_HSCALE should be less than 1, and set to: 2042 * 2043 * (src width - 1) / ((oversample * dest width) - 1) 2044 */ 2045 # define TV_HSCALE_FRAC_MASK 0x00003fff 2046 # define TV_HSCALE_FRAC_SHIFT 0 2047 2048 #define TV_FILTER_CTL_2 0x68084 2049 /** 2050 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 2051 * 2052 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) 2053 */ 2054 # define TV_VSCALE_INT_MASK 0x00038000 2055 # define TV_VSCALE_INT_SHIFT 15 2056 /** 2057 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 2058 * 2059 * \sa TV_VSCALE_INT_MASK 2060 */ 2061 # define TV_VSCALE_FRAC_MASK 0x00007fff 2062 # define TV_VSCALE_FRAC_SHIFT 0 2063 2064 #define TV_FILTER_CTL_3 0x68088 2065 /** 2066 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 2067 * 2068 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) 2069 * 2070 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 2071 */ 2072 # define TV_VSCALE_IP_INT_MASK 0x00038000 2073 # define TV_VSCALE_IP_INT_SHIFT 15 2074 /** 2075 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 2076 * 2077 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 2078 * 2079 * \sa TV_VSCALE_IP_INT_MASK 2080 */ 2081 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff 2082 # define TV_VSCALE_IP_FRAC_SHIFT 0 2083 2084 #define TV_CC_CONTROL 0x68090 2085 # define TV_CC_ENABLE (1 << 31) 2086 /** 2087 * Specifies which field to send the CC data in. 2088 * 2089 * CC data is usually sent in field 0. 2090 */ 2091 # define TV_CC_FID_MASK (1 << 27) 2092 # define TV_CC_FID_SHIFT 27 2093 /** Sets the horizontal position of the CC data. Usually 135. */ 2094 # define TV_CC_HOFF_MASK 0x03ff0000 2095 # define TV_CC_HOFF_SHIFT 16 2096 /** Sets the vertical position of the CC data. Usually 21 */ 2097 # define TV_CC_LINE_MASK 0x0000003f 2098 # define TV_CC_LINE_SHIFT 0 2099 2100 #define TV_CC_DATA 0x68094 2101 # define TV_CC_RDY (1 << 31) 2102 /** Second word of CC data to be transmitted. */ 2103 # define TV_CC_DATA_2_MASK 0x007f0000 2104 # define TV_CC_DATA_2_SHIFT 16 2105 /** First word of CC data to be transmitted. */ 2106 # define TV_CC_DATA_1_MASK 0x0000007f 2107 # define TV_CC_DATA_1_SHIFT 0 2108 2109 #define TV_H_LUMA_0 0x68100 2110 #define TV_H_LUMA_59 0x681ec 2111 #define TV_H_CHROMA_0 0x68200 2112 #define TV_H_CHROMA_59 0x682ec 2113 #define TV_V_LUMA_0 0x68300 2114 #define TV_V_LUMA_42 0x683a8 2115 #define TV_V_CHROMA_0 0x68400 2116 #define TV_V_CHROMA_42 0x684a8 2117 2118 /* Display Port */ 2119 #define DP_A 0x64000 /* eDP */ 2120 #define DP_B 0x64100 2121 #define DP_C 0x64200 2122 #define DP_D 0x64300 2123 2124 #define DP_PORT_EN (1 << 31) 2125 #define DP_PIPEB_SELECT (1 << 30) 2126 #define DP_PIPE_MASK (1 << 30) 2127 2128 /* Link training mode - select a suitable mode for each stage */ 2129 #define DP_LINK_TRAIN_PAT_1 (0 << 28) 2130 #define DP_LINK_TRAIN_PAT_2 (1 << 28) 2131 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) 2132 #define DP_LINK_TRAIN_OFF (3 << 28) 2133 #define DP_LINK_TRAIN_MASK (3 << 28) 2134 #define DP_LINK_TRAIN_SHIFT 28 2135 2136 /* CPT Link training mode */ 2137 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) 2138 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) 2139 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) 2140 #define DP_LINK_TRAIN_OFF_CPT (3 << 8) 2141 #define DP_LINK_TRAIN_MASK_CPT (7 << 8) 2142 #define DP_LINK_TRAIN_SHIFT_CPT 8 2143 2144 /* Signal voltages. These are mostly controlled by the other end */ 2145 #define DP_VOLTAGE_0_4 (0 << 25) 2146 #define DP_VOLTAGE_0_6 (1 << 25) 2147 #define DP_VOLTAGE_0_8 (2 << 25) 2148 #define DP_VOLTAGE_1_2 (3 << 25) 2149 #define DP_VOLTAGE_MASK (7 << 25) 2150 #define DP_VOLTAGE_SHIFT 25 2151 2152 /* Signal pre-emphasis levels, like voltages, the other end tells us what 2153 * they want 2154 */ 2155 #define DP_PRE_EMPHASIS_0 (0 << 22) 2156 #define DP_PRE_EMPHASIS_3_5 (1 << 22) 2157 #define DP_PRE_EMPHASIS_6 (2 << 22) 2158 #define DP_PRE_EMPHASIS_9_5 (3 << 22) 2159 #define DP_PRE_EMPHASIS_MASK (7 << 22) 2160 #define DP_PRE_EMPHASIS_SHIFT 22 2161 2162 /* How many wires to use. I guess 3 was too hard */ 2163 #define DP_PORT_WIDTH_1 (0 << 19) 2164 #define DP_PORT_WIDTH_2 (1 << 19) 2165 #define DP_PORT_WIDTH_4 (3 << 19) 2166 #define DP_PORT_WIDTH_MASK (7 << 19) 2167 2168 /* Mystic DPCD version 1.1 special mode */ 2169 #define DP_ENHANCED_FRAMING (1 << 18) 2170 2171 /* eDP */ 2172 #define DP_PLL_FREQ_270MHZ (0 << 16) 2173 #define DP_PLL_FREQ_160MHZ (1 << 16) 2174 #define DP_PLL_FREQ_MASK (3 << 16) 2175 2176 /** locked once port is enabled */ 2177 #define DP_PORT_REVERSAL (1 << 15) 2178 2179 /* eDP */ 2180 #define DP_PLL_ENABLE (1 << 14) 2181 2182 /** sends the clock on lane 15 of the PEG for debug */ 2183 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 2184 2185 #define DP_SCRAMBLING_DISABLE (1 << 12) 2186 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) 2187 2188 /** limit RGB values to avoid confusing TVs */ 2189 #define DP_COLOR_RANGE_16_235 (1 << 8) 2190 2191 /** Turn on the audio link */ 2192 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) 2193 2194 /** vs and hs sync polarity */ 2195 #define DP_SYNC_VS_HIGH (1 << 4) 2196 #define DP_SYNC_HS_HIGH (1 << 3) 2197 2198 /** A fantasy */ 2199 #define DP_DETECTED (1 << 2) 2200 2201 /** The aux channel provides a way to talk to the 2202 * signal sink for DDC etc. Max packet size supported 2203 * is 20 bytes in each direction, hence the 5 fixed 2204 * data registers 2205 */ 2206 #define DPA_AUX_CH_CTL 0x64010 2207 #define DPA_AUX_CH_DATA1 0x64014 2208 #define DPA_AUX_CH_DATA2 0x64018 2209 #define DPA_AUX_CH_DATA3 0x6401c 2210 #define DPA_AUX_CH_DATA4 0x64020 2211 #define DPA_AUX_CH_DATA5 0x64024 2212 2213 #define DPB_AUX_CH_CTL 0x64110 2214 #define DPB_AUX_CH_DATA1 0x64114 2215 #define DPB_AUX_CH_DATA2 0x64118 2216 #define DPB_AUX_CH_DATA3 0x6411c 2217 #define DPB_AUX_CH_DATA4 0x64120 2218 #define DPB_AUX_CH_DATA5 0x64124 2219 2220 #define DPC_AUX_CH_CTL 0x64210 2221 #define DPC_AUX_CH_DATA1 0x64214 2222 #define DPC_AUX_CH_DATA2 0x64218 2223 #define DPC_AUX_CH_DATA3 0x6421c 2224 #define DPC_AUX_CH_DATA4 0x64220 2225 #define DPC_AUX_CH_DATA5 0x64224 2226 2227 #define DPD_AUX_CH_CTL 0x64310 2228 #define DPD_AUX_CH_DATA1 0x64314 2229 #define DPD_AUX_CH_DATA2 0x64318 2230 #define DPD_AUX_CH_DATA3 0x6431c 2231 #define DPD_AUX_CH_DATA4 0x64320 2232 #define DPD_AUX_CH_DATA5 0x64324 2233 2234 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) 2235 #define DP_AUX_CH_CTL_DONE (1 << 30) 2236 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) 2237 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) 2238 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) 2239 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) 2240 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) 2241 #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) 2242 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) 2243 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) 2244 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) 2245 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 2246 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) 2247 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 2248 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) 2249 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) 2250 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) 2251 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) 2252 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) 2253 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) 2254 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 2255 2256 /* 2257 * Computing GMCH M and N values for the Display Port link 2258 * 2259 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes 2260 * 2261 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) 2262 * 2263 * The GMCH value is used internally 2264 * 2265 * bytes_per_pixel is the number of bytes coming out of the plane, 2266 * which is after the LUTs, so we want the bytes for our color format. 2267 * For our current usage, this is always 3, one byte for R, G and B. 2268 */ 2269 #define _PIPEA_GMCH_DATA_M 0x70050 2270 #define _PIPEB_GMCH_DATA_M 0x71050 2271 2272 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 2273 #define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25) 2274 #define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25 2275 2276 #define PIPE_GMCH_DATA_M_MASK (0xffffff) 2277 2278 #define _PIPEA_GMCH_DATA_N 0x70054 2279 #define _PIPEB_GMCH_DATA_N 0x71054 2280 #define PIPE_GMCH_DATA_N_MASK (0xffffff) 2281 2282 /* 2283 * Computing Link M and N values for the Display Port link 2284 * 2285 * Link M / N = pixel_clock / ls_clk 2286 * 2287 * (the DP spec calls pixel_clock the 'strm_clk') 2288 * 2289 * The Link value is transmitted in the Main Stream 2290 * Attributes and VB-ID. 2291 */ 2292 2293 #define _PIPEA_DP_LINK_M 0x70060 2294 #define _PIPEB_DP_LINK_M 0x71060 2295 #define PIPEA_DP_LINK_M_MASK (0xffffff) 2296 2297 #define _PIPEA_DP_LINK_N 0x70064 2298 #define _PIPEB_DP_LINK_N 0x71064 2299 #define PIPEA_DP_LINK_N_MASK (0xffffff) 2300 2301 #define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M) 2302 #define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N) 2303 #define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M) 2304 #define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N) 2305 2306 /* Display & cursor control */ 2307 2308 /* Pipe A */ 2309 #define _PIPEADSL 0x70000 2310 #define DSL_LINEMASK 0x00000fff 2311 #define _PIPEACONF 0x70008 2312 #define PIPECONF_ENABLE (1<<31) 2313 #define PIPECONF_DISABLE 0 2314 #define PIPECONF_DOUBLE_WIDE (1<<30) 2315 #define I965_PIPECONF_ACTIVE (1<<30) 2316 #define PIPECONF_SINGLE_WIDE 0 2317 #define PIPECONF_PIPE_UNLOCKED 0 2318 #define PIPECONF_PIPE_LOCKED (1<<25) 2319 #define PIPECONF_PALETTE 0 2320 #define PIPECONF_GAMMA (1<<24) 2321 #define PIPECONF_FORCE_BORDER (1<<25) 2322 #define PIPECONF_PROGRESSIVE (0 << 21) 2323 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 2324 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) 2325 #define PIPECONF_INTERLACE_MASK (7 << 21) 2326 #define PIPECONF_CXSR_DOWNCLOCK (1<<16) 2327 #define PIPECONF_BPP_MASK (0x000000e0) 2328 #define PIPECONF_BPP_8 (0<<5) 2329 #define PIPECONF_BPP_10 (1<<5) 2330 #define PIPECONF_BPP_6 (2<<5) 2331 #define PIPECONF_BPP_12 (3<<5) 2332 #define PIPECONF_DITHER_EN (1<<4) 2333 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c) 2334 #define PIPECONF_DITHER_TYPE_SP (0<<2) 2335 #define PIPECONF_DITHER_TYPE_ST1 (1<<2) 2336 #define PIPECONF_DITHER_TYPE_ST2 (2<<2) 2337 #define PIPECONF_DITHER_TYPE_TEMP (3<<2) 2338 #define _PIPEASTAT 0x70024 2339 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) 2340 #define PIPE_CRC_ERROR_ENABLE (1UL<<29) 2341 #define PIPE_CRC_DONE_ENABLE (1UL<<28) 2342 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) 2343 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) 2344 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) 2345 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) 2346 #define PIPE_DPST_EVENT_ENABLE (1UL<<23) 2347 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) 2348 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) 2349 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) 2350 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ 2351 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ 2352 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) 2353 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) 2354 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) 2355 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) 2356 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) 2357 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) 2358 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) 2359 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) 2360 #define PIPE_DPST_EVENT_STATUS (1UL<<7) 2361 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) 2362 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) 2363 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) 2364 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ 2365 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ 2366 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) 2367 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) 2368 #define PIPE_BPC_MASK (7 << 5) /* Ironlake */ 2369 #define PIPE_8BPC (0 << 5) 2370 #define PIPE_10BPC (1 << 5) 2371 #define PIPE_6BPC (2 << 5) 2372 #define PIPE_12BPC (3 << 5) 2373 2374 #define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC) 2375 #define PIPECONF(pipe) _PIPE(pipe, _PIPEACONF, _PIPEBCONF) 2376 #define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL) 2377 #define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH) 2378 #define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL) 2379 #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT) 2380 2381 #define DSPARB 0x70030 2382 #define DSPARB_CSTART_MASK (0x7f << 7) 2383 #define DSPARB_CSTART_SHIFT 7 2384 #define DSPARB_BSTART_MASK (0x7f) 2385 #define DSPARB_BSTART_SHIFT 0 2386 #define DSPARB_BEND_SHIFT 9 /* on 855 */ 2387 #define DSPARB_AEND_SHIFT 0 2388 2389 #define DSPFW1 0x70034 2390 #define DSPFW_SR_SHIFT 23 2391 #define DSPFW_SR_MASK (0x1ff<<23) 2392 #define DSPFW_CURSORB_SHIFT 16 2393 #define DSPFW_CURSORB_MASK (0x3f<<16) 2394 #define DSPFW_PLANEB_SHIFT 8 2395 #define DSPFW_PLANEB_MASK (0x7f<<8) 2396 #define DSPFW_PLANEA_MASK (0x7f) 2397 #define DSPFW2 0x70038 2398 #define DSPFW_CURSORA_MASK 0x00003f00 2399 #define DSPFW_CURSORA_SHIFT 8 2400 #define DSPFW_PLANEC_MASK (0x7f) 2401 #define DSPFW3 0x7003c 2402 #define DSPFW_HPLL_SR_EN (1<<31) 2403 #define DSPFW_CURSOR_SR_SHIFT 24 2404 #define PINEVIEW_SELF_REFRESH_EN (1<<30) 2405 #define DSPFW_CURSOR_SR_MASK (0x3f<<24) 2406 #define DSPFW_HPLL_CURSOR_SHIFT 16 2407 #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) 2408 #define DSPFW_HPLL_SR_MASK (0x1ff) 2409 2410 /* FIFO watermark sizes etc */ 2411 #define G4X_FIFO_LINE_SIZE 64 2412 #define I915_FIFO_LINE_SIZE 64 2413 #define I830_FIFO_LINE_SIZE 32 2414 2415 #define G4X_FIFO_SIZE 127 2416 #define I965_FIFO_SIZE 512 2417 #define I945_FIFO_SIZE 127 2418 #define I915_FIFO_SIZE 95 2419 #define I855GM_FIFO_SIZE 127 /* In cachelines */ 2420 #define I830_FIFO_SIZE 95 2421 2422 #define G4X_MAX_WM 0x3f 2423 #define I915_MAX_WM 0x3f 2424 2425 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ 2426 #define PINEVIEW_FIFO_LINE_SIZE 64 2427 #define PINEVIEW_MAX_WM 0x1ff 2428 #define PINEVIEW_DFT_WM 0x3f 2429 #define PINEVIEW_DFT_HPLLOFF_WM 0 2430 #define PINEVIEW_GUARD_WM 10 2431 #define PINEVIEW_CURSOR_FIFO 64 2432 #define PINEVIEW_CURSOR_MAX_WM 0x3f 2433 #define PINEVIEW_CURSOR_DFT_WM 0 2434 #define PINEVIEW_CURSOR_GUARD_WM 5 2435 2436 #define I965_CURSOR_FIFO 64 2437 #define I965_CURSOR_MAX_WM 32 2438 #define I965_CURSOR_DFT_WM 8 2439 2440 /* define the Watermark register on Ironlake */ 2441 #define WM0_PIPEA_ILK 0x45100 2442 #define WM0_PIPE_PLANE_MASK (0x7f<<16) 2443 #define WM0_PIPE_PLANE_SHIFT 16 2444 #define WM0_PIPE_SPRITE_MASK (0x3f<<8) 2445 #define WM0_PIPE_SPRITE_SHIFT 8 2446 #define WM0_PIPE_CURSOR_MASK (0x1f) 2447 2448 #define WM0_PIPEB_ILK 0x45104 2449 #define WM0_PIPEC_IVB 0x45200 2450 #define WM1_LP_ILK 0x45108 2451 #define WM1_LP_SR_EN (1<<31) 2452 #define WM1_LP_LATENCY_SHIFT 24 2453 #define WM1_LP_LATENCY_MASK (0x7f<<24) 2454 #define WM1_LP_FBC_MASK (0xf<<20) 2455 #define WM1_LP_FBC_SHIFT 20 2456 #define WM1_LP_SR_MASK (0x1ff<<8) 2457 #define WM1_LP_SR_SHIFT 8 2458 #define WM1_LP_CURSOR_MASK (0x3f) 2459 #define WM2_LP_ILK 0x4510c 2460 #define WM2_LP_EN (1<<31) 2461 #define WM3_LP_ILK 0x45110 2462 #define WM3_LP_EN (1<<31) 2463 #define WM1S_LP_ILK 0x45120 2464 #define WM2S_LP_IVB 0x45124 2465 #define WM3S_LP_IVB 0x45128 2466 #define WM1S_LP_EN (1<<31) 2467 2468 /* Memory latency timer register */ 2469 #define MLTR_ILK 0x11222 2470 #define MLTR_WM1_SHIFT 0 2471 #define MLTR_WM2_SHIFT 8 2472 /* the unit of memory self-refresh latency time is 0.5us */ 2473 #define ILK_SRLT_MASK 0x3f 2474 #define ILK_LATENCY(shift) (I915_READ(MLTR_ILK) >> (shift) & ILK_SRLT_MASK) 2475 #define ILK_READ_WM1_LATENCY() ILK_LATENCY(MLTR_WM1_SHIFT) 2476 #define ILK_READ_WM2_LATENCY() ILK_LATENCY(MLTR_WM2_SHIFT) 2477 2478 /* define the fifo size on Ironlake */ 2479 #define ILK_DISPLAY_FIFO 128 2480 #define ILK_DISPLAY_MAXWM 64 2481 #define ILK_DISPLAY_DFTWM 8 2482 #define ILK_CURSOR_FIFO 32 2483 #define ILK_CURSOR_MAXWM 16 2484 #define ILK_CURSOR_DFTWM 8 2485 2486 #define ILK_DISPLAY_SR_FIFO 512 2487 #define ILK_DISPLAY_MAX_SRWM 0x1ff 2488 #define ILK_DISPLAY_DFT_SRWM 0x3f 2489 #define ILK_CURSOR_SR_FIFO 64 2490 #define ILK_CURSOR_MAX_SRWM 0x3f 2491 #define ILK_CURSOR_DFT_SRWM 8 2492 2493 #define ILK_FIFO_LINE_SIZE 64 2494 2495 /* define the WM info on Sandybridge */ 2496 #define SNB_DISPLAY_FIFO 128 2497 #define SNB_DISPLAY_MAXWM 0x7f /* bit 16:22 */ 2498 #define SNB_DISPLAY_DFTWM 8 2499 #define SNB_CURSOR_FIFO 32 2500 #define SNB_CURSOR_MAXWM 0x1f /* bit 4:0 */ 2501 #define SNB_CURSOR_DFTWM 8 2502 2503 #define SNB_DISPLAY_SR_FIFO 512 2504 #define SNB_DISPLAY_MAX_SRWM 0x1ff /* bit 16:8 */ 2505 #define SNB_DISPLAY_DFT_SRWM 0x3f 2506 #define SNB_CURSOR_SR_FIFO 64 2507 #define SNB_CURSOR_MAX_SRWM 0x3f /* bit 5:0 */ 2508 #define SNB_CURSOR_DFT_SRWM 8 2509 2510 #define SNB_FBC_MAX_SRWM 0xf /* bit 23:20 */ 2511 2512 #define SNB_FIFO_LINE_SIZE 64 2513 2514 2515 /* the address where we get all kinds of latency value */ 2516 #define SSKPD 0x5d10 2517 #define SSKPD_WM_MASK 0x3f 2518 #define SSKPD_WM0_SHIFT 0 2519 #define SSKPD_WM1_SHIFT 8 2520 #define SSKPD_WM2_SHIFT 16 2521 #define SSKPD_WM3_SHIFT 24 2522 2523 #define SNB_LATENCY(shift) (I915_READ(MCHBAR_MIRROR_BASE_SNB + SSKPD) >> (shift) & SSKPD_WM_MASK) 2524 #define SNB_READ_WM0_LATENCY() SNB_LATENCY(SSKPD_WM0_SHIFT) 2525 #define SNB_READ_WM1_LATENCY() SNB_LATENCY(SSKPD_WM1_SHIFT) 2526 #define SNB_READ_WM2_LATENCY() SNB_LATENCY(SSKPD_WM2_SHIFT) 2527 #define SNB_READ_WM3_LATENCY() SNB_LATENCY(SSKPD_WM3_SHIFT) 2528 2529 /* 2530 * The two pipe frame counter registers are not synchronized, so 2531 * reading a stable value is somewhat tricky. The following code 2532 * should work: 2533 * 2534 * do { 2535 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 2536 * PIPE_FRAME_HIGH_SHIFT; 2537 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 2538 * PIPE_FRAME_LOW_SHIFT); 2539 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 2540 * PIPE_FRAME_HIGH_SHIFT); 2541 * } while (high1 != high2); 2542 * frame = (high1 << 8) | low1; 2543 */ 2544 #define _PIPEAFRAMEHIGH 0x70040 2545 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 2546 #define PIPE_FRAME_HIGH_SHIFT 0 2547 #define _PIPEAFRAMEPIXEL 0x70044 2548 #define PIPE_FRAME_LOW_MASK 0xff000000 2549 #define PIPE_FRAME_LOW_SHIFT 24 2550 #define PIPE_PIXEL_MASK 0x00ffffff 2551 #define PIPE_PIXEL_SHIFT 0 2552 /* GM45+ just has to be different */ 2553 #define _PIPEA_FRMCOUNT_GM45 0x70040 2554 #define _PIPEA_FLIPCOUNT_GM45 0x70044 2555 #define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45) 2556 2557 /* Cursor A & B regs */ 2558 #define _CURACNTR 0x70080 2559 /* Old style CUR*CNTR flags (desktop 8xx) */ 2560 #define CURSOR_ENABLE 0x80000000 2561 #define CURSOR_GAMMA_ENABLE 0x40000000 2562 #define CURSOR_STRIDE_MASK 0x30000000 2563 #define CURSOR_FORMAT_SHIFT 24 2564 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) 2565 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) 2566 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) 2567 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) 2568 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) 2569 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) 2570 /* New style CUR*CNTR flags */ 2571 #define CURSOR_MODE 0x27 2572 #define CURSOR_MODE_DISABLE 0x00 2573 #define CURSOR_MODE_64_32B_AX 0x07 2574 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) 2575 #define MCURSOR_PIPE_SELECT (1 << 28) 2576 #define MCURSOR_PIPE_A 0x00 2577 #define MCURSOR_PIPE_B (1 << 28) 2578 #define MCURSOR_GAMMA_ENABLE (1 << 26) 2579 #define _CURABASE 0x70084 2580 #define _CURAPOS 0x70088 2581 #define CURSOR_POS_MASK 0x007FF 2582 #define CURSOR_POS_SIGN 0x8000 2583 #define CURSOR_X_SHIFT 0 2584 #define CURSOR_Y_SHIFT 16 2585 #define CURSIZE 0x700a0 2586 #define _CURBCNTR 0x700c0 2587 #define _CURBBASE 0x700c4 2588 #define _CURBPOS 0x700c8 2589 2590 #define _CURBCNTR_IVB 0x71080 2591 #define _CURBBASE_IVB 0x71084 2592 #define _CURBPOS_IVB 0x71088 2593 2594 #define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR) 2595 #define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE) 2596 #define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS) 2597 2598 #define CURCNTR_IVB(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR_IVB) 2599 #define CURBASE_IVB(pipe) _PIPE(pipe, _CURABASE, _CURBBASE_IVB) 2600 #define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB) 2601 2602 /* Display A control */ 2603 #define _DSPACNTR 0x70180 2604 #define DISPLAY_PLANE_ENABLE (1<<31) 2605 #define DISPLAY_PLANE_DISABLE 0 2606 #define DISPPLANE_GAMMA_ENABLE (1<<30) 2607 #define DISPPLANE_GAMMA_DISABLE 0 2608 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) 2609 #define DISPPLANE_8BPP (0x2<<26) 2610 #define DISPPLANE_15_16BPP (0x4<<26) 2611 #define DISPPLANE_16BPP (0x5<<26) 2612 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) 2613 #define DISPPLANE_32BPP (0x7<<26) 2614 #define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26) 2615 #define DISPPLANE_STEREO_ENABLE (1<<25) 2616 #define DISPPLANE_STEREO_DISABLE 0 2617 #define DISPPLANE_SEL_PIPE_SHIFT 24 2618 #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT) 2619 #define DISPPLANE_SEL_PIPE_A 0 2620 #define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT) 2621 #define DISPPLANE_SRC_KEY_ENABLE (1<<22) 2622 #define DISPPLANE_SRC_KEY_DISABLE 0 2623 #define DISPPLANE_LINE_DOUBLE (1<<20) 2624 #define DISPPLANE_NO_LINE_DOUBLE 0 2625 #define DISPPLANE_STEREO_POLARITY_FIRST 0 2626 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 2627 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ 2628 #define DISPPLANE_TILED (1<<10) 2629 #define _DSPAADDR 0x70184 2630 #define _DSPASTRIDE 0x70188 2631 #define _DSPAPOS 0x7018C /* reserved */ 2632 #define _DSPASIZE 0x70190 2633 #define _DSPASURF 0x7019C /* 965+ only */ 2634 #define _DSPATILEOFF 0x701A4 /* 965+ only */ 2635 2636 #define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR) 2637 #define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR) 2638 #define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE) 2639 #define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS) 2640 #define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE) 2641 #define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF) 2642 #define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF) 2643 2644 /* VBIOS flags */ 2645 #define SWF00 0x71410 2646 #define SWF01 0x71414 2647 #define SWF02 0x71418 2648 #define SWF03 0x7141c 2649 #define SWF04 0x71420 2650 #define SWF05 0x71424 2651 #define SWF06 0x71428 2652 #define SWF10 0x70410 2653 #define SWF11 0x70414 2654 #define SWF14 0x71420 2655 #define SWF30 0x72414 2656 #define SWF31 0x72418 2657 #define SWF32 0x7241c 2658 2659 /* Pipe B */ 2660 #define _PIPEBDSL 0x71000 2661 #define _PIPEBCONF 0x71008 2662 #define _PIPEBSTAT 0x71024 2663 #define _PIPEBFRAMEHIGH 0x71040 2664 #define _PIPEBFRAMEPIXEL 0x71044 2665 #define _PIPEB_FRMCOUNT_GM45 0x71040 2666 #define _PIPEB_FLIPCOUNT_GM45 0x71044 2667 2668 2669 /* Display B control */ 2670 #define _DSPBCNTR 0x71180 2671 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) 2672 #define DISPPLANE_ALPHA_TRANS_DISABLE 0 2673 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 2674 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 2675 #define _DSPBADDR 0x71184 2676 #define _DSPBSTRIDE 0x71188 2677 #define _DSPBPOS 0x7118C 2678 #define _DSPBSIZE 0x71190 2679 #define _DSPBSURF 0x7119C 2680 #define _DSPBTILEOFF 0x711A4 2681 2682 /* Sprite A control */ 2683 #define _DVSACNTR 0x72180 2684 #define DVS_ENABLE (1<<31) 2685 #define DVS_GAMMA_ENABLE (1<<30) 2686 #define DVS_PIXFORMAT_MASK (3<<25) 2687 #define DVS_FORMAT_YUV422 (0<<25) 2688 #define DVS_FORMAT_RGBX101010 (1<<25) 2689 #define DVS_FORMAT_RGBX888 (2<<25) 2690 #define DVS_FORMAT_RGBX161616 (3<<25) 2691 #define DVS_SOURCE_KEY (1<<22) 2692 #define DVS_RGB_ORDER_RGBX (1<<20) 2693 #define DVS_YUV_BYTE_ORDER_MASK (3<<16) 2694 #define DVS_YUV_ORDER_YUYV (0<<16) 2695 #define DVS_YUV_ORDER_UYVY (1<<16) 2696 #define DVS_YUV_ORDER_YVYU (2<<16) 2697 #define DVS_YUV_ORDER_VYUY (3<<16) 2698 #define DVS_DEST_KEY (1<<2) 2699 #define DVS_TRICKLE_FEED_DISABLE (1<<14) 2700 #define DVS_TILED (1<<10) 2701 #define _DVSALINOFF 0x72184 2702 #define _DVSASTRIDE 0x72188 2703 #define _DVSAPOS 0x7218c 2704 #define _DVSASIZE 0x72190 2705 #define _DVSAKEYVAL 0x72194 2706 #define _DVSAKEYMSK 0x72198 2707 #define _DVSASURF 0x7219c 2708 #define _DVSAKEYMAXVAL 0x721a0 2709 #define _DVSATILEOFF 0x721a4 2710 #define _DVSASURFLIVE 0x721ac 2711 #define _DVSASCALE 0x72204 2712 #define DVS_SCALE_ENABLE (1<<31) 2713 #define DVS_FILTER_MASK (3<<29) 2714 #define DVS_FILTER_MEDIUM (0<<29) 2715 #define DVS_FILTER_ENHANCING (1<<29) 2716 #define DVS_FILTER_SOFTENING (2<<29) 2717 #define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ 2718 #define DVS_VERTICAL_OFFSET_ENABLE (1<<27) 2719 #define _DVSAGAMC 0x72300 2720 2721 #define _DVSBCNTR 0x73180 2722 #define _DVSBLINOFF 0x73184 2723 #define _DVSBSTRIDE 0x73188 2724 #define _DVSBPOS 0x7318c 2725 #define _DVSBSIZE 0x73190 2726 #define _DVSBKEYVAL 0x73194 2727 #define _DVSBKEYMSK 0x73198 2728 #define _DVSBSURF 0x7319c 2729 #define _DVSBKEYMAXVAL 0x731a0 2730 #define _DVSBTILEOFF 0x731a4 2731 #define _DVSBSURFLIVE 0x731ac 2732 #define _DVSBSCALE 0x73204 2733 #define _DVSBGAMC 0x73300 2734 2735 #define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR) 2736 #define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) 2737 #define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) 2738 #define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS) 2739 #define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF) 2740 #define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) 2741 #define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE) 2742 #define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE) 2743 #define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) 2744 #define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) 2745 #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) 2746 2747 #define _SPRA_CTL 0x70280 2748 #define SPRITE_ENABLE (1<<31) 2749 #define SPRITE_GAMMA_ENABLE (1<<30) 2750 #define SPRITE_PIXFORMAT_MASK (7<<25) 2751 #define SPRITE_FORMAT_YUV422 (0<<25) 2752 #define SPRITE_FORMAT_RGBX101010 (1<<25) 2753 #define SPRITE_FORMAT_RGBX888 (2<<25) 2754 #define SPRITE_FORMAT_RGBX161616 (3<<25) 2755 #define SPRITE_FORMAT_YUV444 (4<<25) 2756 #define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */ 2757 #define SPRITE_CSC_ENABLE (1<<24) 2758 #define SPRITE_SOURCE_KEY (1<<22) 2759 #define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */ 2760 #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19) 2761 #define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */ 2762 #define SPRITE_YUV_BYTE_ORDER_MASK (3<<16) 2763 #define SPRITE_YUV_ORDER_YUYV (0<<16) 2764 #define SPRITE_YUV_ORDER_UYVY (1<<16) 2765 #define SPRITE_YUV_ORDER_YVYU (2<<16) 2766 #define SPRITE_YUV_ORDER_VYUY (3<<16) 2767 #define SPRITE_TRICKLE_FEED_DISABLE (1<<14) 2768 #define SPRITE_INT_GAMMA_ENABLE (1<<13) 2769 #define SPRITE_TILED (1<<10) 2770 #define SPRITE_DEST_KEY (1<<2) 2771 #define _SPRA_LINOFF 0x70284 2772 #define _SPRA_STRIDE 0x70288 2773 #define _SPRA_POS 0x7028c 2774 #define _SPRA_SIZE 0x70290 2775 #define _SPRA_KEYVAL 0x70294 2776 #define _SPRA_KEYMSK 0x70298 2777 #define _SPRA_SURF 0x7029c 2778 #define _SPRA_KEYMAX 0x702a0 2779 #define _SPRA_TILEOFF 0x702a4 2780 #define _SPRA_SCALE 0x70304 2781 #define SPRITE_SCALE_ENABLE (1<<31) 2782 #define SPRITE_FILTER_MASK (3<<29) 2783 #define SPRITE_FILTER_MEDIUM (0<<29) 2784 #define SPRITE_FILTER_ENHANCING (1<<29) 2785 #define SPRITE_FILTER_SOFTENING (2<<29) 2786 #define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ 2787 #define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27) 2788 #define _SPRA_GAMC 0x70400 2789 2790 #define _SPRB_CTL 0x71280 2791 #define _SPRB_LINOFF 0x71284 2792 #define _SPRB_STRIDE 0x71288 2793 #define _SPRB_POS 0x7128c 2794 #define _SPRB_SIZE 0x71290 2795 #define _SPRB_KEYVAL 0x71294 2796 #define _SPRB_KEYMSK 0x71298 2797 #define _SPRB_SURF 0x7129c 2798 #define _SPRB_KEYMAX 0x712a0 2799 #define _SPRB_TILEOFF 0x712a4 2800 #define _SPRB_SCALE 0x71304 2801 #define _SPRB_GAMC 0x71400 2802 2803 #define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL) 2804 #define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) 2805 #define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) 2806 #define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS) 2807 #define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) 2808 #define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) 2809 #define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) 2810 #define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF) 2811 #define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) 2812 #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) 2813 #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) 2814 #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) 2815 2816 /* VBIOS regs */ 2817 #define VGACNTRL 0x71400 2818 # define VGA_DISP_DISABLE (1 << 31) 2819 # define VGA_2X_MODE (1 << 30) 2820 # define VGA_PIPE_B_SELECT (1 << 29) 2821 2822 /* Ironlake */ 2823 2824 #define CPU_VGACNTRL 0x41000 2825 2826 #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 2827 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 2828 #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2) 2829 #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2) 2830 #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2) 2831 #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2) 2832 #define DIGITAL_PORTA_NO_DETECT (0 << 0) 2833 #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1) 2834 #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0) 2835 2836 /* refresh rate hardware control */ 2837 #define RR_HW_CTL 0x45300 2838 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff 2839 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 2840 2841 #define FDI_PLL_BIOS_0 0x46000 2842 #define FDI_PLL_FB_CLOCK_MASK 0xff 2843 #define FDI_PLL_BIOS_1 0x46004 2844 #define FDI_PLL_BIOS_2 0x46008 2845 #define DISPLAY_PORT_PLL_BIOS_0 0x4600c 2846 #define DISPLAY_PORT_PLL_BIOS_1 0x46010 2847 #define DISPLAY_PORT_PLL_BIOS_2 0x46014 2848 2849 #define PCH_DSPCLK_GATE_D 0x42020 2850 # define DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) 2851 # define DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) 2852 # define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7) 2853 # define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5) 2854 2855 #define PCH_3DCGDIS0 0x46020 2856 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) 2857 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) 2858 2859 #define PCH_3DCGDIS1 0x46024 2860 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) 2861 2862 #define FDI_PLL_FREQ_CTL 0x46030 2863 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) 2864 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 2865 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff 2866 2867 2868 #define _PIPEA_DATA_M1 0x60030 2869 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ 2870 #define TU_SIZE_MASK 0x7e000000 2871 #define PIPE_DATA_M1_OFFSET 0 2872 #define _PIPEA_DATA_N1 0x60034 2873 #define PIPE_DATA_N1_OFFSET 0 2874 2875 #define _PIPEA_DATA_M2 0x60038 2876 #define PIPE_DATA_M2_OFFSET 0 2877 #define _PIPEA_DATA_N2 0x6003c 2878 #define PIPE_DATA_N2_OFFSET 0 2879 2880 #define _PIPEA_LINK_M1 0x60040 2881 #define PIPE_LINK_M1_OFFSET 0 2882 #define _PIPEA_LINK_N1 0x60044 2883 #define PIPE_LINK_N1_OFFSET 0 2884 2885 #define _PIPEA_LINK_M2 0x60048 2886 #define PIPE_LINK_M2_OFFSET 0 2887 #define _PIPEA_LINK_N2 0x6004c 2888 #define PIPE_LINK_N2_OFFSET 0 2889 2890 /* PIPEB timing regs are same start from 0x61000 */ 2891 2892 #define _PIPEB_DATA_M1 0x61030 2893 #define _PIPEB_DATA_N1 0x61034 2894 2895 #define _PIPEB_DATA_M2 0x61038 2896 #define _PIPEB_DATA_N2 0x6103c 2897 2898 #define _PIPEB_LINK_M1 0x61040 2899 #define _PIPEB_LINK_N1 0x61044 2900 2901 #define _PIPEB_LINK_M2 0x61048 2902 #define _PIPEB_LINK_N2 0x6104c 2903 2904 #define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1) 2905 #define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1) 2906 #define PIPE_DATA_M2(pipe) _PIPE(pipe, _PIPEA_DATA_M2, _PIPEB_DATA_M2) 2907 #define PIPE_DATA_N2(pipe) _PIPE(pipe, _PIPEA_DATA_N2, _PIPEB_DATA_N2) 2908 #define PIPE_LINK_M1(pipe) _PIPE(pipe, _PIPEA_LINK_M1, _PIPEB_LINK_M1) 2909 #define PIPE_LINK_N1(pipe) _PIPE(pipe, _PIPEA_LINK_N1, _PIPEB_LINK_N1) 2910 #define PIPE_LINK_M2(pipe) _PIPE(pipe, _PIPEA_LINK_M2, _PIPEB_LINK_M2) 2911 #define PIPE_LINK_N2(pipe) _PIPE(pipe, _PIPEA_LINK_N2, _PIPEB_LINK_N2) 2912 2913 /* CPU panel fitter */ 2914 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ 2915 #define _PFA_CTL_1 0x68080 2916 #define _PFB_CTL_1 0x68880 2917 #define PF_ENABLE (1<<31) 2918 #define PF_FILTER_MASK (3<<23) 2919 #define PF_FILTER_PROGRAMMED (0<<23) 2920 #define PF_FILTER_MED_3x3 (1<<23) 2921 #define PF_FILTER_EDGE_ENHANCE (2<<23) 2922 #define PF_FILTER_EDGE_SOFTEN (3<<23) 2923 #define _PFA_WIN_SZ 0x68074 2924 #define _PFB_WIN_SZ 0x68874 2925 #define _PFA_WIN_POS 0x68070 2926 #define _PFB_WIN_POS 0x68870 2927 #define _PFA_VSCALE 0x68084 2928 #define _PFB_VSCALE 0x68884 2929 #define _PFA_HSCALE 0x68090 2930 #define _PFB_HSCALE 0x68890 2931 2932 #define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) 2933 #define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) 2934 #define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) 2935 #define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) 2936 #define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) 2937 2938 /* legacy palette */ 2939 #define _LGC_PALETTE_A 0x4a000 2940 #define _LGC_PALETTE_B 0x4a800 2941 #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) 2942 2943 /* interrupts */ 2944 #define DE_MASTER_IRQ_CONTROL (1 << 31) 2945 #define DE_SPRITEB_FLIP_DONE (1 << 29) 2946 #define DE_SPRITEA_FLIP_DONE (1 << 28) 2947 #define DE_PLANEB_FLIP_DONE (1 << 27) 2948 #define DE_PLANEA_FLIP_DONE (1 << 26) 2949 #define DE_PCU_EVENT (1 << 25) 2950 #define DE_GTT_FAULT (1 << 24) 2951 #define DE_POISON (1 << 23) 2952 #define DE_PERFORM_COUNTER (1 << 22) 2953 #define DE_PCH_EVENT (1 << 21) 2954 #define DE_AUX_CHANNEL_A (1 << 20) 2955 #define DE_DP_A_HOTPLUG (1 << 19) 2956 #define DE_GSE (1 << 18) 2957 #define DE_PIPEB_VBLANK (1 << 15) 2958 #define DE_PIPEB_EVEN_FIELD (1 << 14) 2959 #define DE_PIPEB_ODD_FIELD (1 << 13) 2960 #define DE_PIPEB_LINE_COMPARE (1 << 12) 2961 #define DE_PIPEB_VSYNC (1 << 11) 2962 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) 2963 #define DE_PIPEA_VBLANK (1 << 7) 2964 #define DE_PIPEA_EVEN_FIELD (1 << 6) 2965 #define DE_PIPEA_ODD_FIELD (1 << 5) 2966 #define DE_PIPEA_LINE_COMPARE (1 << 4) 2967 #define DE_PIPEA_VSYNC (1 << 3) 2968 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 2969 2970 /* More Ivybridge lolz */ 2971 #define DE_ERR_DEBUG_IVB (1<<30) 2972 #define DE_GSE_IVB (1<<29) 2973 #define DE_PCH_EVENT_IVB (1<<28) 2974 #define DE_DP_A_HOTPLUG_IVB (1<<27) 2975 #define DE_AUX_CHANNEL_A_IVB (1<<26) 2976 #define DE_SPRITEB_FLIP_DONE_IVB (1<<9) 2977 #define DE_SPRITEA_FLIP_DONE_IVB (1<<4) 2978 #define DE_PLANEB_FLIP_DONE_IVB (1<<8) 2979 #define DE_PLANEA_FLIP_DONE_IVB (1<<3) 2980 #define DE_PIPEB_VBLANK_IVB (1<<5) 2981 #define DE_PIPEA_VBLANK_IVB (1<<0) 2982 2983 #define DEISR 0x44000 2984 #define DEIMR 0x44004 2985 #define DEIIR 0x44008 2986 #define DEIER 0x4400c 2987 2988 /* GT interrupt */ 2989 #define GT_PIPE_NOTIFY (1 << 4) 2990 #define GT_SYNC_STATUS (1 << 2) 2991 #define GT_USER_INTERRUPT (1 << 0) 2992 #define GT_BSD_USER_INTERRUPT (1 << 5) 2993 #define GT_GEN6_BSD_USER_INTERRUPT (1 << 12) 2994 #define GT_BLT_USER_INTERRUPT (1 << 22) 2995 2996 #define GTISR 0x44010 2997 #define GTIMR 0x44014 2998 #define GTIIR 0x44018 2999 #define GTIER 0x4401c 3000 3001 #define ILK_DISPLAY_CHICKEN2 0x42004 3002 /* Required on all Ironlake and Sandybridge according to the B-Spec. */ 3003 #define ILK_ELPIN_409_SELECT (1 << 25) 3004 #define ILK_DPARB_GATE (1<<22) 3005 #define ILK_VSDPFD_FULL (1<<21) 3006 #define ILK_DISPLAY_CHICKEN_FUSES 0x42014 3007 #define ILK_INTERNAL_GRAPHICS_DISABLE (1<<31) 3008 #define ILK_INTERNAL_DISPLAY_DISABLE (1<<30) 3009 #define ILK_DISPLAY_DEBUG_DISABLE (1<<29) 3010 #define ILK_HDCP_DISABLE (1<<25) 3011 #define ILK_eDP_A_DISABLE (1<<24) 3012 #define ILK_DESKTOP (1<<23) 3013 #define ILK_DSPCLK_GATE 0x42020 3014 #define IVB_VRHUNIT_CLK_GATE (1<<28) 3015 #define ILK_DPARB_CLK_GATE (1<<5) 3016 #define ILK_DPFD_CLK_GATE (1<<7) 3017 3018 /* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */ 3019 #define ILK_CLK_FBC (1<<7) 3020 #define ILK_DPFC_DIS1 (1<<8) 3021 #define ILK_DPFC_DIS2 (1<<9) 3022 3023 #define IVB_CHICKEN3 0x4200c 3024 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) 3025 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) 3026 3027 #define DISP_ARB_CTL 0x45000 3028 #define DISP_TILE_SURFACE_SWIZZLING (1<<13) 3029 #define DISP_FBC_WM_DIS (1<<15) 3030 3031 /* PCH */ 3032 3033 /* south display engine interrupt */ 3034 #define SDE_AUDIO_POWER_D (1 << 27) 3035 #define SDE_AUDIO_POWER_C (1 << 26) 3036 #define SDE_AUDIO_POWER_B (1 << 25) 3037 #define SDE_AUDIO_POWER_SHIFT (25) 3038 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) 3039 #define SDE_GMBUS (1 << 24) 3040 #define SDE_AUDIO_HDCP_TRANSB (1 << 23) 3041 #define SDE_AUDIO_HDCP_TRANSA (1 << 22) 3042 #define SDE_AUDIO_HDCP_MASK (3 << 22) 3043 #define SDE_AUDIO_TRANSB (1 << 21) 3044 #define SDE_AUDIO_TRANSA (1 << 20) 3045 #define SDE_AUDIO_TRANS_MASK (3 << 20) 3046 #define SDE_POISON (1 << 19) 3047 /* 18 reserved */ 3048 #define SDE_FDI_RXB (1 << 17) 3049 #define SDE_FDI_RXA (1 << 16) 3050 #define SDE_FDI_MASK (3 << 16) 3051 #define SDE_AUXD (1 << 15) 3052 #define SDE_AUXC (1 << 14) 3053 #define SDE_AUXB (1 << 13) 3054 #define SDE_AUX_MASK (7 << 13) 3055 /* 12 reserved */ 3056 #define SDE_CRT_HOTPLUG (1 << 11) 3057 #define SDE_PORTD_HOTPLUG (1 << 10) 3058 #define SDE_PORTC_HOTPLUG (1 << 9) 3059 #define SDE_PORTB_HOTPLUG (1 << 8) 3060 #define SDE_SDVOB_HOTPLUG (1 << 6) 3061 #define SDE_HOTPLUG_MASK (0xf << 8) 3062 #define SDE_TRANSB_CRC_DONE (1 << 5) 3063 #define SDE_TRANSB_CRC_ERR (1 << 4) 3064 #define SDE_TRANSB_FIFO_UNDER (1 << 3) 3065 #define SDE_TRANSA_CRC_DONE (1 << 2) 3066 #define SDE_TRANSA_CRC_ERR (1 << 1) 3067 #define SDE_TRANSA_FIFO_UNDER (1 << 0) 3068 #define SDE_TRANS_MASK (0x3f) 3069 /* CPT */ 3070 #define SDE_CRT_HOTPLUG_CPT (1 << 19) 3071 #define SDE_PORTD_HOTPLUG_CPT (1 << 23) 3072 #define SDE_PORTC_HOTPLUG_CPT (1 << 22) 3073 #define SDE_PORTB_HOTPLUG_CPT (1 << 21) 3074 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ 3075 SDE_PORTD_HOTPLUG_CPT | \ 3076 SDE_PORTC_HOTPLUG_CPT | \ 3077 SDE_PORTB_HOTPLUG_CPT) 3078 3079 #define SDEISR 0xc4000 3080 #define SDEIMR 0xc4004 3081 #define SDEIIR 0xc4008 3082 #define SDEIER 0xc400c 3083 3084 /* digital port hotplug */ 3085 #define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */ 3086 #define PORTD_HOTPLUG_ENABLE (1 << 20) 3087 #define PORTD_PULSE_DURATION_2ms (0) 3088 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) 3089 #define PORTD_PULSE_DURATION_6ms (2 << 18) 3090 #define PORTD_PULSE_DURATION_100ms (3 << 18) 3091 #define PORTD_PULSE_DURATION_MASK (3 << 18) 3092 #define PORTD_HOTPLUG_NO_DETECT (0) 3093 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) 3094 #define PORTD_HOTPLUG_LONG_DETECT (1 << 17) 3095 #define PORTC_HOTPLUG_ENABLE (1 << 12) 3096 #define PORTC_PULSE_DURATION_2ms (0) 3097 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) 3098 #define PORTC_PULSE_DURATION_6ms (2 << 10) 3099 #define PORTC_PULSE_DURATION_100ms (3 << 10) 3100 #define PORTC_PULSE_DURATION_MASK (3 << 10) 3101 #define PORTC_HOTPLUG_NO_DETECT (0) 3102 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) 3103 #define PORTC_HOTPLUG_LONG_DETECT (1 << 9) 3104 #define PORTB_HOTPLUG_ENABLE (1 << 4) 3105 #define PORTB_PULSE_DURATION_2ms (0) 3106 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) 3107 #define PORTB_PULSE_DURATION_6ms (2 << 2) 3108 #define PORTB_PULSE_DURATION_100ms (3 << 2) 3109 #define PORTB_PULSE_DURATION_MASK (3 << 2) 3110 #define PORTB_HOTPLUG_NO_DETECT (0) 3111 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) 3112 #define PORTB_HOTPLUG_LONG_DETECT (1 << 1) 3113 3114 #define PCH_GPIOA 0xc5010 3115 #define PCH_GPIOB 0xc5014 3116 #define PCH_GPIOC 0xc5018 3117 #define PCH_GPIOD 0xc501c 3118 #define PCH_GPIOE 0xc5020 3119 #define PCH_GPIOF 0xc5024 3120 3121 #define PCH_GMBUS0 0xc5100 3122 #define PCH_GMBUS1 0xc5104 3123 #define PCH_GMBUS2 0xc5108 3124 #define PCH_GMBUS3 0xc510c 3125 #define PCH_GMBUS4 0xc5110 3126 #define PCH_GMBUS5 0xc5120 3127 3128 #define _PCH_DPLL_A 0xc6014 3129 #define _PCH_DPLL_B 0xc6018 3130 #define PCH_DPLL(pipe) (pipe == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) 3131 3132 #define _PCH_FPA0 0xc6040 3133 #define FP_CB_TUNE (0x3<<22) 3134 #define _PCH_FPA1 0xc6044 3135 #define _PCH_FPB0 0xc6048 3136 #define _PCH_FPB1 0xc604c 3137 #define PCH_FP0(pipe) (pipe == 0 ? _PCH_FPA0 : _PCH_FPB0) 3138 #define PCH_FP1(pipe) (pipe == 0 ? _PCH_FPA1 : _PCH_FPB1) 3139 3140 #define PCH_DPLL_TEST 0xc606c 3141 3142 #define PCH_DREF_CONTROL 0xC6200 3143 #define DREF_CONTROL_MASK 0x7fc3 3144 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) 3145 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) 3146 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) 3147 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13) 3148 #define DREF_SSC_SOURCE_DISABLE (0<<11) 3149 #define DREF_SSC_SOURCE_ENABLE (2<<11) 3150 #define DREF_SSC_SOURCE_MASK (3<<11) 3151 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) 3152 #define DREF_NONSPREAD_CK505_ENABLE (1<<9) 3153 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) 3154 #define DREF_NONSPREAD_SOURCE_MASK (3<<9) 3155 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) 3156 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) 3157 #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7) 3158 #define DREF_SSC4_DOWNSPREAD (0<<6) 3159 #define DREF_SSC4_CENTERSPREAD (1<<6) 3160 #define DREF_SSC1_DISABLE (0<<1) 3161 #define DREF_SSC1_ENABLE (1<<1) 3162 #define DREF_SSC4_DISABLE (0) 3163 #define DREF_SSC4_ENABLE (1) 3164 3165 #define PCH_RAWCLK_FREQ 0xc6204 3166 #define FDL_TP1_TIMER_SHIFT 12 3167 #define FDL_TP1_TIMER_MASK (3<<12) 3168 #define FDL_TP2_TIMER_SHIFT 10 3169 #define FDL_TP2_TIMER_MASK (3<<10) 3170 #define RAWCLK_FREQ_MASK 0x3ff 3171 3172 #define PCH_DPLL_TMR_CFG 0xc6208 3173 3174 #define PCH_SSC4_PARMS 0xc6210 3175 #define PCH_SSC4_AUX_PARMS 0xc6214 3176 3177 #define PCH_DPLL_SEL 0xc7000 3178 #define TRANSA_DPLL_ENABLE (1<<3) 3179 #define TRANSA_DPLLB_SEL (1<<0) 3180 #define TRANSA_DPLLA_SEL 0 3181 #define TRANSB_DPLL_ENABLE (1<<7) 3182 #define TRANSB_DPLLB_SEL (1<<4) 3183 #define TRANSB_DPLLA_SEL (0) 3184 #define TRANSC_DPLL_ENABLE (1<<11) 3185 #define TRANSC_DPLLB_SEL (1<<8) 3186 #define TRANSC_DPLLA_SEL (0) 3187 3188 /* transcoder */ 3189 3190 #define _TRANS_HTOTAL_A 0xe0000 3191 #define TRANS_HTOTAL_SHIFT 16 3192 #define TRANS_HACTIVE_SHIFT 0 3193 #define _TRANS_HBLANK_A 0xe0004 3194 #define TRANS_HBLANK_END_SHIFT 16 3195 #define TRANS_HBLANK_START_SHIFT 0 3196 #define _TRANS_HSYNC_A 0xe0008 3197 #define TRANS_HSYNC_END_SHIFT 16 3198 #define TRANS_HSYNC_START_SHIFT 0 3199 #define _TRANS_VTOTAL_A 0xe000c 3200 #define TRANS_VTOTAL_SHIFT 16 3201 #define TRANS_VACTIVE_SHIFT 0 3202 #define _TRANS_VBLANK_A 0xe0010 3203 #define TRANS_VBLANK_END_SHIFT 16 3204 #define TRANS_VBLANK_START_SHIFT 0 3205 #define _TRANS_VSYNC_A 0xe0014 3206 #define TRANS_VSYNC_END_SHIFT 16 3207 #define TRANS_VSYNC_START_SHIFT 0 3208 3209 #define _TRANSA_DATA_M1 0xe0030 3210 #define _TRANSA_DATA_N1 0xe0034 3211 #define _TRANSA_DATA_M2 0xe0038 3212 #define _TRANSA_DATA_N2 0xe003c 3213 #define _TRANSA_DP_LINK_M1 0xe0040 3214 #define _TRANSA_DP_LINK_N1 0xe0044 3215 #define _TRANSA_DP_LINK_M2 0xe0048 3216 #define _TRANSA_DP_LINK_N2 0xe004c 3217 3218 /* Per-transcoder DIP controls */ 3219 3220 #define _VIDEO_DIP_CTL_A 0xe0200 3221 #define _VIDEO_DIP_DATA_A 0xe0208 3222 #define _VIDEO_DIP_GCP_A 0xe0210 3223 3224 #define _VIDEO_DIP_CTL_B 0xe1200 3225 #define _VIDEO_DIP_DATA_B 0xe1208 3226 #define _VIDEO_DIP_GCP_B 0xe1210 3227 3228 #define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) 3229 #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) 3230 #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) 3231 3232 #define _TRANS_HTOTAL_B 0xe1000 3233 #define _TRANS_HBLANK_B 0xe1004 3234 #define _TRANS_HSYNC_B 0xe1008 3235 #define _TRANS_VTOTAL_B 0xe100c 3236 #define _TRANS_VBLANK_B 0xe1010 3237 #define _TRANS_VSYNC_B 0xe1014 3238 3239 #define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B) 3240 #define TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B) 3241 #define TRANS_HSYNC(pipe) _PIPE(pipe, _TRANS_HSYNC_A, _TRANS_HSYNC_B) 3242 #define TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B) 3243 #define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B) 3244 #define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B) 3245 3246 #define _TRANSB_DATA_M1 0xe1030 3247 #define _TRANSB_DATA_N1 0xe1034 3248 #define _TRANSB_DATA_M2 0xe1038 3249 #define _TRANSB_DATA_N2 0xe103c 3250 #define _TRANSB_DP_LINK_M1 0xe1040 3251 #define _TRANSB_DP_LINK_N1 0xe1044 3252 #define _TRANSB_DP_LINK_M2 0xe1048 3253 #define _TRANSB_DP_LINK_N2 0xe104c 3254 3255 #define TRANSDATA_M1(pipe) _PIPE(pipe, _TRANSA_DATA_M1, _TRANSB_DATA_M1) 3256 #define TRANSDATA_N1(pipe) _PIPE(pipe, _TRANSA_DATA_N1, _TRANSB_DATA_N1) 3257 #define TRANSDATA_M2(pipe) _PIPE(pipe, _TRANSA_DATA_M2, _TRANSB_DATA_M2) 3258 #define TRANSDATA_N2(pipe) _PIPE(pipe, _TRANSA_DATA_N2, _TRANSB_DATA_N2) 3259 #define TRANSDPLINK_M1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M1, _TRANSB_DP_LINK_M1) 3260 #define TRANSDPLINK_N1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N1, _TRANSB_DP_LINK_N1) 3261 #define TRANSDPLINK_M2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M2, _TRANSB_DP_LINK_M2) 3262 #define TRANSDPLINK_N2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N2, _TRANSB_DP_LINK_N2) 3263 3264 #define _TRANSACONF 0xf0008 3265 #define _TRANSBCONF 0xf1008 3266 #define TRANSCONF(plane) _PIPE(plane, _TRANSACONF, _TRANSBCONF) 3267 #define TRANS_DISABLE (0<<31) 3268 #define TRANS_ENABLE (1<<31) 3269 #define TRANS_STATE_MASK (1<<30) 3270 #define TRANS_STATE_DISABLE (0<<30) 3271 #define TRANS_STATE_ENABLE (1<<30) 3272 #define TRANS_FSYNC_DELAY_HB1 (0<<27) 3273 #define TRANS_FSYNC_DELAY_HB2 (1<<27) 3274 #define TRANS_FSYNC_DELAY_HB3 (2<<27) 3275 #define TRANS_FSYNC_DELAY_HB4 (3<<27) 3276 #define TRANS_DP_AUDIO_ONLY (1<<26) 3277 #define TRANS_DP_VIDEO_AUDIO (0<<26) 3278 #define TRANS_PROGRESSIVE (0<<21) 3279 #define TRANS_8BPC (0<<5) 3280 #define TRANS_10BPC (1<<5) 3281 #define TRANS_6BPC (2<<5) 3282 #define TRANS_12BPC (3<<5) 3283 3284 #define _TRANSA_CHICKEN2 0xf0064 3285 #define _TRANSB_CHICKEN2 0xf1064 3286 #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) 3287 #define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31) 3288 3289 #define SOUTH_CHICKEN1 0xc2000 3290 #define FDIA_PHASE_SYNC_SHIFT_OVR 19 3291 #define FDIA_PHASE_SYNC_SHIFT_EN 18 3292 #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) 3293 #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) 3294 #define SOUTH_CHICKEN2 0xc2004 3295 #define DPLS_EDP_PPS_FIX_DIS (1<<0) 3296 3297 #define _FDI_RXA_CHICKEN 0xc200c 3298 #define _FDI_RXB_CHICKEN 0xc2010 3299 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1) 3300 #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0) 3301 #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) 3302 3303 #define SOUTH_DSPCLK_GATE_D 0xc2020 3304 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) 3305 3306 /* CPU: FDI_TX */ 3307 #define _FDI_TXA_CTL 0x60100 3308 #define _FDI_TXB_CTL 0x61100 3309 #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) 3310 #define FDI_TX_DISABLE (0<<31) 3311 #define FDI_TX_ENABLE (1<<31) 3312 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28) 3313 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28) 3314 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) 3315 #define FDI_LINK_TRAIN_NONE (3<<28) 3316 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) 3317 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) 3318 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) 3319 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) 3320 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22) 3321 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22) 3322 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) 3323 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) 3324 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. 3325 SNB has different settings. */ 3326 /* SNB A-stepping */ 3327 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) 3328 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) 3329 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) 3330 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) 3331 /* SNB B-stepping */ 3332 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22) 3333 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22) 3334 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22) 3335 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) 3336 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22) 3337 #define FDI_DP_PORT_WIDTH_X1 (0<<19) 3338 #define FDI_DP_PORT_WIDTH_X2 (1<<19) 3339 #define FDI_DP_PORT_WIDTH_X3 (2<<19) 3340 #define FDI_DP_PORT_WIDTH_X4 (3<<19) 3341 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) 3342 /* Ironlake: hardwired to 1 */ 3343 #define FDI_TX_PLL_ENABLE (1<<14) 3344 3345 /* Ivybridge has different bits for lolz */ 3346 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8) 3347 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8) 3348 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8) 3349 #define FDI_LINK_TRAIN_NONE_IVB (3<<8) 3350 3351 /* both Tx and Rx */ 3352 #define FDI_COMPOSITE_SYNC (1<<11) 3353 #define FDI_LINK_TRAIN_AUTO (1<<10) 3354 #define FDI_SCRAMBLING_ENABLE (0<<7) 3355 #define FDI_SCRAMBLING_DISABLE (1<<7) 3356 3357 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */ 3358 #define _FDI_RXA_CTL 0xf000c 3359 #define _FDI_RXB_CTL 0xf100c 3360 #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) 3361 #define FDI_RX_ENABLE (1<<31) 3362 /* train, dp width same as FDI_TX */ 3363 #define FDI_FS_ERRC_ENABLE (1<<27) 3364 #define FDI_FE_ERRC_ENABLE (1<<26) 3365 #define FDI_DP_PORT_WIDTH_X8 (7<<19) 3366 #define FDI_8BPC (0<<16) 3367 #define FDI_10BPC (1<<16) 3368 #define FDI_6BPC (2<<16) 3369 #define FDI_12BPC (3<<16) 3370 #define FDI_LINK_REVERSE_OVERWRITE (1<<15) 3371 #define FDI_DMI_LINK_REVERSE_MASK (1<<14) 3372 #define FDI_RX_PLL_ENABLE (1<<13) 3373 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11) 3374 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10) 3375 #define FDI_FS_ERR_REPORT_ENABLE (1<<9) 3376 #define FDI_FE_ERR_REPORT_ENABLE (1<<8) 3377 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) 3378 #define FDI_PCDCLK (1<<4) 3379 /* CPT */ 3380 #define FDI_AUTO_TRAINING (1<<10) 3381 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8) 3382 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8) 3383 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8) 3384 #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) 3385 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) 3386 3387 #define _FDI_RXA_MISC 0xf0010 3388 #define _FDI_RXB_MISC 0xf1010 3389 #define _FDI_RXA_TUSIZE1 0xf0030 3390 #define _FDI_RXA_TUSIZE2 0xf0038 3391 #define _FDI_RXB_TUSIZE1 0xf1030 3392 #define _FDI_RXB_TUSIZE2 0xf1038 3393 #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) 3394 #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) 3395 #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) 3396 3397 /* FDI_RX interrupt register format */ 3398 #define FDI_RX_INTER_LANE_ALIGN (1<<10) 3399 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ 3400 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ 3401 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) 3402 #define FDI_RX_FS_CODE_ERR (1<<6) 3403 #define FDI_RX_FE_CODE_ERR (1<<5) 3404 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) 3405 #define FDI_RX_HDCP_LINK_FAIL (1<<3) 3406 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) 3407 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) 3408 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) 3409 3410 #define _FDI_RXA_IIR 0xf0014 3411 #define _FDI_RXA_IMR 0xf0018 3412 #define _FDI_RXB_IIR 0xf1014 3413 #define _FDI_RXB_IMR 0xf1018 3414 #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) 3415 #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) 3416 3417 #define FDI_PLL_CTL_1 0xfe000 3418 #define FDI_PLL_CTL_2 0xfe004 3419 3420 /* CRT */ 3421 #define PCH_ADPA 0xe1100 3422 #define ADPA_TRANS_SELECT_MASK (1<<30) 3423 #define ADPA_TRANS_A_SELECT 0 3424 #define ADPA_TRANS_B_SELECT (1<<30) 3425 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ 3426 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) 3427 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) 3428 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) 3429 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) 3430 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23) 3431 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) 3432 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) 3433 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) 3434 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) 3435 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) 3436 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) 3437 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) 3438 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) 3439 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) 3440 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) 3441 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) 3442 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) 3443 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) 3444 3445 /* or SDVOB */ 3446 #define HDMIB 0xe1140 3447 #define PORT_ENABLE (1 << 31) 3448 #define TRANSCODER(pipe) ((pipe) << 30) 3449 #define TRANSCODER_CPT(pipe) ((pipe) << 29) 3450 #define TRANSCODER_MASK (1 << 30) 3451 #define TRANSCODER_MASK_CPT (3 << 29) 3452 #define COLOR_FORMAT_8bpc (0) 3453 #define COLOR_FORMAT_12bpc (3 << 26) 3454 #define SDVOB_HOTPLUG_ENABLE (1 << 23) 3455 #define SDVO_ENCODING (0) 3456 #define TMDS_ENCODING (2 << 10) 3457 #define NULL_PACKET_VSYNC_ENABLE (1 << 9) 3458 /* CPT */ 3459 #define HDMI_MODE_SELECT (1 << 9) 3460 #define DVI_MODE_SELECT (0) 3461 #define SDVOB_BORDER_ENABLE (1 << 7) 3462 #define AUDIO_ENABLE (1 << 6) 3463 #define VSYNC_ACTIVE_HIGH (1 << 4) 3464 #define HSYNC_ACTIVE_HIGH (1 << 3) 3465 #define PORT_DETECTED (1 << 2) 3466 3467 /* PCH SDVOB multiplex with HDMIB */ 3468 #define PCH_SDVOB HDMIB 3469 3470 #define HDMIC 0xe1150 3471 #define HDMID 0xe1160 3472 3473 #define PCH_LVDS 0xe1180 3474 #define LVDS_DETECTED (1 << 1) 3475 3476 #define BLC_PWM_CPU_CTL2 0x48250 3477 #define PWM_ENABLE (1 << 31) 3478 #define PWM_PIPE_A (0 << 29) 3479 #define PWM_PIPE_B (1 << 29) 3480 #define BLC_PWM_CPU_CTL 0x48254 3481 3482 #define BLC_PWM_PCH_CTL1 0xc8250 3483 #define PWM_PCH_ENABLE (1 << 31) 3484 #define PWM_POLARITY_ACTIVE_LOW (1 << 29) 3485 #define PWM_POLARITY_ACTIVE_HIGH (0 << 29) 3486 #define PWM_POLARITY_ACTIVE_LOW2 (1 << 28) 3487 #define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28) 3488 3489 #define BLC_PWM_PCH_CTL2 0xc8254 3490 3491 #define PCH_PP_STATUS 0xc7200 3492 #define PCH_PP_CONTROL 0xc7204 3493 #define PANEL_UNLOCK_REGS (0xabcd << 16) 3494 #define PANEL_UNLOCK_MASK (0xffff << 16) 3495 #define EDP_FORCE_VDD (1 << 3) 3496 #define EDP_BLC_ENABLE (1 << 2) 3497 #define PANEL_POWER_RESET (1 << 1) 3498 #define PANEL_POWER_OFF (0 << 0) 3499 #define PANEL_POWER_ON (1 << 0) 3500 #define PCH_PP_ON_DELAYS 0xc7208 3501 #define PANEL_PORT_SELECT_MASK (3 << 30) 3502 #define PANEL_PORT_SELECT_LVDS (0 << 30) 3503 #define PANEL_PORT_SELECT_DPA (1 << 30) 3504 #define EDP_PANEL (1 << 30) 3505 #define PANEL_PORT_SELECT_DPC (2 << 30) 3506 #define PANEL_PORT_SELECT_DPD (3 << 30) 3507 #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000) 3508 #define PANEL_POWER_UP_DELAY_SHIFT 16 3509 #define PANEL_LIGHT_ON_DELAY_MASK (0x1fff) 3510 #define PANEL_LIGHT_ON_DELAY_SHIFT 0 3511 3512 #define PCH_PP_OFF_DELAYS 0xc720c 3513 #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000) 3514 #define PANEL_POWER_DOWN_DELAY_SHIFT 16 3515 #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff) 3516 #define PANEL_LIGHT_OFF_DELAY_SHIFT 0 3517 3518 #define PCH_PP_DIVISOR 0xc7210 3519 #define PP_REFERENCE_DIVIDER_MASK (0xffffff00) 3520 #define PP_REFERENCE_DIVIDER_SHIFT 8 3521 #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) 3522 #define PANEL_POWER_CYCLE_DELAY_SHIFT 0 3523 3524 #define PCH_DP_B 0xe4100 3525 #define PCH_DPB_AUX_CH_CTL 0xe4110 3526 #define PCH_DPB_AUX_CH_DATA1 0xe4114 3527 #define PCH_DPB_AUX_CH_DATA2 0xe4118 3528 #define PCH_DPB_AUX_CH_DATA3 0xe411c 3529 #define PCH_DPB_AUX_CH_DATA4 0xe4120 3530 #define PCH_DPB_AUX_CH_DATA5 0xe4124 3531 3532 #define PCH_DP_C 0xe4200 3533 #define PCH_DPC_AUX_CH_CTL 0xe4210 3534 #define PCH_DPC_AUX_CH_DATA1 0xe4214 3535 #define PCH_DPC_AUX_CH_DATA2 0xe4218 3536 #define PCH_DPC_AUX_CH_DATA3 0xe421c 3537 #define PCH_DPC_AUX_CH_DATA4 0xe4220 3538 #define PCH_DPC_AUX_CH_DATA5 0xe4224 3539 3540 #define PCH_DP_D 0xe4300 3541 #define PCH_DPD_AUX_CH_CTL 0xe4310 3542 #define PCH_DPD_AUX_CH_DATA1 0xe4314 3543 #define PCH_DPD_AUX_CH_DATA2 0xe4318 3544 #define PCH_DPD_AUX_CH_DATA3 0xe431c 3545 #define PCH_DPD_AUX_CH_DATA4 0xe4320 3546 #define PCH_DPD_AUX_CH_DATA5 0xe4324 3547 3548 /* CPT */ 3549 #define PORT_TRANS_A_SEL_CPT 0 3550 #define PORT_TRANS_B_SEL_CPT (1<<29) 3551 #define PORT_TRANS_C_SEL_CPT (2<<29) 3552 #define PORT_TRANS_SEL_MASK (3<<29) 3553 #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29) 3554 3555 #define TRANS_DP_CTL_A 0xe0300 3556 #define TRANS_DP_CTL_B 0xe1300 3557 #define TRANS_DP_CTL_C 0xe2300 3558 #define TRANS_DP_CTL(pipe) (TRANS_DP_CTL_A + (pipe) * 0x01000) 3559 #define TRANS_DP_OUTPUT_ENABLE (1<<31) 3560 #define TRANS_DP_PORT_SEL_B (0<<29) 3561 #define TRANS_DP_PORT_SEL_C (1<<29) 3562 #define TRANS_DP_PORT_SEL_D (2<<29) 3563 #define TRANS_DP_PORT_SEL_NONE (3<<29) 3564 #define TRANS_DP_PORT_SEL_MASK (3<<29) 3565 #define TRANS_DP_AUDIO_ONLY (1<<26) 3566 #define TRANS_DP_ENH_FRAMING (1<<18) 3567 #define TRANS_DP_8BPC (0<<9) 3568 #define TRANS_DP_10BPC (1<<9) 3569 #define TRANS_DP_6BPC (2<<9) 3570 #define TRANS_DP_12BPC (3<<9) 3571 #define TRANS_DP_BPC_MASK (3<<9) 3572 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4) 3573 #define TRANS_DP_VSYNC_ACTIVE_LOW 0 3574 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) 3575 #define TRANS_DP_HSYNC_ACTIVE_LOW 0 3576 #define TRANS_DP_SYNC_MASK (3<<3) 3577 3578 /* SNB eDP training params */ 3579 /* SNB A-stepping */ 3580 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) 3581 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) 3582 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) 3583 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) 3584 /* SNB B-stepping */ 3585 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22) 3586 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22) 3587 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22) 3588 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22) 3589 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22) 3590 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22) 3591 3592 /* IVB */ 3593 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22) 3594 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22) 3595 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22) 3596 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22) 3597 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22) 3598 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22) 3599 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x33 <<22) 3600 3601 /* legacy values */ 3602 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22) 3603 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22) 3604 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22) 3605 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22) 3606 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22) 3607 3608 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22) 3609 3610 #define FORCEWAKE 0xA18C 3611 #define FORCEWAKE_ACK 0x130090 3612 #define FORCEWAKE_MT 0xa188 /* multi-threaded */ 3613 #define FORCEWAKE_MT_ACK 0x130040 3614 #define ECOBUS 0xa180 3615 #define FORCEWAKE_MT_ENABLE (1<<5) 3616 3617 #define GT_FIFO_FREE_ENTRIES 0x120008 3618 #define GT_FIFO_NUM_RESERVED_ENTRIES 20 3619 3620 #define GEN6_UCGCTL2 0x9404 3621 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) 3622 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11) 3623 3624 #define GEN6_RPNSWREQ 0xA008 3625 #define GEN6_TURBO_DISABLE (1<<31) 3626 #define GEN6_FREQUENCY(x) ((x)<<25) 3627 #define GEN6_OFFSET(x) ((x)<<19) 3628 #define GEN6_AGGRESSIVE_TURBO (0<<15) 3629 #define GEN6_RC_VIDEO_FREQ 0xA00C 3630 #define GEN6_RC_CONTROL 0xA090 3631 #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16) 3632 #define GEN6_RC_CTL_RC6p_ENABLE (1<<17) 3633 #define GEN6_RC_CTL_RC6_ENABLE (1<<18) 3634 #define GEN6_RC_CTL_RC1e_ENABLE (1<<20) 3635 #define GEN6_RC_CTL_RC7_ENABLE (1<<22) 3636 #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27) 3637 #define GEN6_RC_CTL_HW_ENABLE (1<<31) 3638 #define GEN6_RP_DOWN_TIMEOUT 0xA010 3639 #define GEN6_RP_INTERRUPT_LIMITS 0xA014 3640 #define GEN6_RPSTAT1 0xA01C 3641 #define GEN6_CAGF_SHIFT 8 3642 #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) 3643 #define GEN6_RP_CONTROL 0xA024 3644 #define GEN6_RP_MEDIA_TURBO (1<<11) 3645 #define GEN6_RP_MEDIA_MODE_MASK (3<<9) 3646 #define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9) 3647 #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9) 3648 #define GEN6_RP_MEDIA_HW_MODE (1<<9) 3649 #define GEN6_RP_MEDIA_SW_MODE (0<<9) 3650 #define GEN6_RP_MEDIA_IS_GFX (1<<8) 3651 #define GEN6_RP_ENABLE (1<<7) 3652 #define GEN6_RP_UP_IDLE_MIN (0x1<<3) 3653 #define GEN6_RP_UP_BUSY_AVG (0x2<<3) 3654 #define GEN6_RP_UP_BUSY_CONT (0x4<<3) 3655 #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0) 3656 #define GEN6_RP_UP_THRESHOLD 0xA02C 3657 #define GEN6_RP_DOWN_THRESHOLD 0xA030 3658 #define GEN6_RP_CUR_UP_EI 0xA050 3659 #define GEN6_CURICONT_MASK 0xffffff 3660 #define GEN6_RP_CUR_UP 0xA054 3661 #define GEN6_CURBSYTAVG_MASK 0xffffff 3662 #define GEN6_RP_PREV_UP 0xA058 3663 #define GEN6_RP_CUR_DOWN_EI 0xA05C 3664 #define GEN6_CURIAVG_MASK 0xffffff 3665 #define GEN6_RP_CUR_DOWN 0xA060 3666 #define GEN6_RP_PREV_DOWN 0xA064 3667 #define GEN6_RP_UP_EI 0xA068 3668 #define GEN6_RP_DOWN_EI 0xA06C 3669 #define GEN6_RP_IDLE_HYSTERSIS 0xA070 3670 #define GEN6_RC_STATE 0xA094 3671 #define GEN6_RC1_WAKE_RATE_LIMIT 0xA098 3672 #define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C 3673 #define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0 3674 #define GEN6_RC_EVALUATION_INTERVAL 0xA0A8 3675 #define GEN6_RC_IDLE_HYSTERSIS 0xA0AC 3676 #define GEN6_RC_SLEEP 0xA0B0 3677 #define GEN6_RC1e_THRESHOLD 0xA0B4 3678 #define GEN6_RC6_THRESHOLD 0xA0B8 3679 #define GEN6_RC6p_THRESHOLD 0xA0BC 3680 #define GEN6_RC6pp_THRESHOLD 0xA0C0 3681 #define GEN6_PMINTRMSK 0xA168 3682 3683 #define GEN6_PMISR 0x44020 3684 #define GEN6_PMIMR 0x44024 /* rps_lock */ 3685 #define GEN6_PMIIR 0x44028 3686 #define GEN6_PMIER 0x4402C 3687 #define GEN6_PM_MBOX_EVENT (1<<25) 3688 #define GEN6_PM_THERMAL_EVENT (1<<24) 3689 #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6) 3690 #define GEN6_PM_RP_UP_THRESHOLD (1<<5) 3691 #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4) 3692 #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2) 3693 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1) 3694 #define GEN6_PM_DEFERRED_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \ 3695 GEN6_PM_RP_DOWN_THRESHOLD | \ 3696 GEN6_PM_RP_DOWN_TIMEOUT) 3697 3698 #define GEN6_PCODE_MAILBOX 0x138124 3699 #define GEN6_PCODE_READY (1<<31) 3700 #define GEN6_READ_OC_PARAMS 0xc 3701 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 3702 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 3703 #define GEN6_PCODE_DATA 0x138128 3704 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 3705 3706 #define GEN6_GT_CORE_STATUS 0x138060 3707 #define GEN6_CORE_CPD_STATE_MASK (7<<4) 3708 #define GEN6_RCn_MASK 7 3709 #define GEN6_RC0 0 3710 #define GEN6_RC3 2 3711 #define GEN6_RC6 3 3712 #define GEN6_RC7 4 3713 3714 #define G4X_AUD_VID_DID 0x62020 3715 #define INTEL_AUDIO_DEVCL 0x808629FB 3716 #define INTEL_AUDIO_DEVBLC 0x80862801 3717 #define INTEL_AUDIO_DEVCTG 0x80862802 3718 3719 #define G4X_AUD_CNTL_ST 0x620B4 3720 #define G4X_ELDV_DEVCL_DEVBLC (1 << 13) 3721 #define G4X_ELDV_DEVCTG (1 << 14) 3722 #define G4X_ELD_ADDR (0xf << 5) 3723 #define G4X_ELD_ACK (1 << 4) 3724 #define G4X_HDMIW_HDMIEDID 0x6210C 3725 3726 #define IBX_HDMIW_HDMIEDID_A 0xE2050 3727 #define IBX_AUD_CNTL_ST_A 0xE20B4 3728 #define IBX_ELD_BUFFER_SIZE (0x1f << 10) 3729 #define IBX_ELD_ADDRESS (0x1f << 5) 3730 #define IBX_ELD_ACK (1 << 4) 3731 #define IBX_AUD_CNTL_ST2 0xE20C0 3732 #define IBX_ELD_VALIDB (1 << 0) 3733 #define IBX_CP_READYB (1 << 1) 3734 3735 #define CPT_HDMIW_HDMIEDID_A 0xE5050 3736 #define CPT_AUD_CNTL_ST_A 0xE50B4 3737 #define CPT_AUD_CNTRL_ST2 0xE50C0 3738 3739 /* These are the 4 32-bit write offset registers for each stream 3740 * output buffer. It determines the offset from the 3741 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. 3742 */ 3743 #define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4) 3744 3745 #endif /* _I915_REG_H_ */ 3746