1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 2 * All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef _I915_REG_H_ 26 #define _I915_REG_H_ 27 28 #include <linux/bitfield.h> 29 #include <linux/bits.h> 30 31 /** 32 * DOC: The i915 register macro definition style guide 33 * 34 * Follow the style described here for new macros, and while changing existing 35 * macros. Do **not** mass change existing definitions just to update the style. 36 * 37 * Layout 38 * ~~~~~~ 39 * 40 * Keep helper macros near the top. For example, _PIPE() and friends. 41 * 42 * Prefix macros that generally should not be used outside of this file with 43 * underscore '_'. For example, _PIPE() and friends, single instances of 44 * registers that are defined solely for the use by function-like macros. 45 * 46 * Avoid using the underscore prefixed macros outside of this file. There are 47 * exceptions, but keep them to a minimum. 48 * 49 * There are two basic types of register definitions: Single registers and 50 * register groups. Register groups are registers which have two or more 51 * instances, for example one per pipe, port, transcoder, etc. Register groups 52 * should be defined using function-like macros. 53 * 54 * For single registers, define the register offset first, followed by register 55 * contents. 56 * 57 * For register groups, define the register instance offsets first, prefixed 58 * with underscore, followed by a function-like macro choosing the right 59 * instance based on the parameter, followed by register contents. 60 * 61 * Define the register contents (i.e. bit and bit field macros) from most 62 * significant to least significant bit. Indent the register content macros 63 * using two extra spaces between ``#define`` and the macro name. 64 * 65 * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents 66 * using ``REG_FIELD_PREP(mask, value)``. This will define the values already 67 * shifted in place, so they can be directly OR'd together. For convenience, 68 * function-like macros may be used to define bit fields, but do note that the 69 * macros may be needed to read as well as write the register contents. 70 * 71 * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name. 72 * 73 * Group the register and its contents together without blank lines, separate 74 * from other registers and their contents with one blank line. 75 * 76 * Indent macro values from macro names using TABs. Align values vertically. Use 77 * braces in macro values as needed to avoid unintended precedence after macro 78 * substitution. Use spaces in macro values according to kernel coding 79 * style. Use lower case in hexadecimal values. 80 * 81 * Naming 82 * ~~~~~~ 83 * 84 * Try to name registers according to the specs. If the register name changes in 85 * the specs from platform to another, stick to the original name. 86 * 87 * Try to re-use existing register macro definitions. Only add new macros for 88 * new register offsets, or when the register contents have changed enough to 89 * warrant a full redefinition. 90 * 91 * When a register macro changes for a new platform, prefix the new macro using 92 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The 93 * prefix signifies the start platform/generation using the register. 94 * 95 * When a bit (field) macro changes or gets added for a new platform, while 96 * retaining the existing register macro, add a platform acronym or generation 97 * suffix to the name. For example, ``_SKL`` or ``_GEN8``. 98 * 99 * Examples 100 * ~~~~~~~~ 101 * 102 * (Note that the values in the example are indented using spaces instead of 103 * TABs to avoid misalignment in generated documentation. Use TABs in the 104 * definitions.):: 105 * 106 * #define _FOO_A 0xf000 107 * #define _FOO_B 0xf001 108 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B) 109 * #define FOO_ENABLE REG_BIT(31) 110 * #define FOO_MODE_MASK REG_GENMASK(19, 16) 111 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0) 112 * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1) 113 * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2) 114 * 115 * #define BAR _MMIO(0xb000) 116 * #define GEN8_BAR _MMIO(0xb888) 117 */ 118 119 /** 120 * REG_BIT() - Prepare a u32 bit value 121 * @__n: 0-based bit number 122 * 123 * Local wrapper for BIT() to force u32, with compile time checks. 124 * 125 * @return: Value with bit @__n set. 126 */ 127 #define REG_BIT(__n) \ 128 ((u32)(BIT(__n) + \ 129 BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \ 130 ((__n) < 0 || (__n) > 31)))) 131 132 /** 133 * REG_GENMASK() - Prepare a continuous u32 bitmask 134 * @__high: 0-based high bit 135 * @__low: 0-based low bit 136 * 137 * Local wrapper for GENMASK() to force u32, with compile time checks. 138 * 139 * @return: Continuous bitmask from @__high to @__low, inclusive. 140 */ 141 #define REG_GENMASK(__high, __low) \ 142 ((u32)(GENMASK(__high, __low) + \ 143 BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \ 144 __is_constexpr(__low) && \ 145 ((__low) < 0 || (__high) > 31 || (__low) > (__high))))) 146 147 /* 148 * Local integer constant expression version of is_power_of_2(). 149 */ 150 #define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0)) 151 152 /** 153 * REG_FIELD_PREP() - Prepare a u32 bitfield value 154 * @__mask: shifted mask defining the field's length and position 155 * @__val: value to put in the field 156 * 157 * Local copy of FIELD_PREP() to generate an integer constant expression, force 158 * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK(). 159 * 160 * @return: @__val masked and shifted into the field defined by @__mask. 161 */ 162 #define REG_FIELD_PREP(__mask, __val) \ 163 ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \ 164 BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \ 165 BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \ 166 BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \ 167 BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0)))) 168 169 /** 170 * REG_FIELD_GET() - Extract a u32 bitfield value 171 * @__mask: shifted mask defining the field's length and position 172 * @__val: value to extract the bitfield value from 173 * 174 * Local wrapper for FIELD_GET() to force u32 and for consistency with 175 * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK(). 176 * 177 * @return: Masked and shifted value of the field defined by @__mask in @__val. 178 */ 179 #define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val)) 180 181 typedef struct { 182 u32 reg; 183 } i915_reg_t; 184 185 #define _MMIO(r) ((const i915_reg_t){ .reg = (r) }) 186 187 #define INVALID_MMIO_REG _MMIO(0) 188 189 static inline u32 i915_mmio_reg_offset(i915_reg_t reg) 190 { 191 return reg.reg; 192 } 193 194 static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b) 195 { 196 return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b); 197 } 198 199 static inline bool i915_mmio_reg_valid(i915_reg_t reg) 200 { 201 return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG); 202 } 203 204 #define VLV_DISPLAY_BASE 0x180000 205 #define VLV_MIPI_BASE VLV_DISPLAY_BASE 206 #define BXT_MIPI_BASE 0x60000 207 208 #define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display_mmio_offset) 209 210 /* 211 * Given the first two numbers __a and __b of arbitrarily many evenly spaced 212 * numbers, pick the 0-based __index'th value. 213 * 214 * Always prefer this over _PICK() if the numbers are evenly spaced. 215 */ 216 #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a))) 217 218 /* 219 * Given the arbitrary numbers in varargs, pick the 0-based __index'th number. 220 * 221 * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced. 222 */ 223 #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index]) 224 225 /* 226 * Named helper wrappers around _PICK_EVEN() and _PICK(). 227 */ 228 #define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b) 229 #define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b) 230 #define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b) 231 #define _PORT(port, a, b) _PICK_EVEN(port, a, b) 232 #define _PLL(pll, a, b) _PICK_EVEN(pll, a, b) 233 234 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) 235 #define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b)) 236 #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b)) 237 #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b)) 238 #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) 239 240 #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__) 241 242 #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) 243 #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) 244 #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) 245 246 /* 247 * Device info offset array based helpers for groups of registers with unevenly 248 * spaced base offsets. 249 */ 250 #define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \ 251 INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \ 252 DISPLAY_MMIO_BASE(dev_priv)) 253 #define _MMIO_TRANS2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->trans_offsets[(pipe)] - \ 254 INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \ 255 DISPLAY_MMIO_BASE(dev_priv)) 256 #define _CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \ 257 INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \ 258 DISPLAY_MMIO_BASE(dev_priv)) 259 260 #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value)) 261 #define _MASKED_FIELD(mask, value) ({ \ 262 if (__builtin_constant_p(mask)) \ 263 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \ 264 if (__builtin_constant_p(value)) \ 265 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \ 266 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \ 267 BUILD_BUG_ON_MSG((value) & ~(mask), \ 268 "Incorrect value for mask"); \ 269 __MASKED_FIELD(mask, value); }) 270 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) 271 #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0)) 272 273 /* Engine ID */ 274 275 #define RCS0_HW 0 276 #define VCS0_HW 1 277 #define BCS0_HW 2 278 #define VECS0_HW 3 279 #define VCS1_HW 4 280 #define VCS2_HW 6 281 #define VCS3_HW 7 282 #define VECS1_HW 12 283 284 /* Engine class */ 285 286 #define RENDER_CLASS 0 287 #define VIDEO_DECODE_CLASS 1 288 #define VIDEO_ENHANCEMENT_CLASS 2 289 #define COPY_ENGINE_CLASS 3 290 #define OTHER_CLASS 4 291 #define MAX_ENGINE_CLASS 4 292 293 #define OTHER_GUC_INSTANCE 0 294 #define OTHER_GTPM_INSTANCE 1 295 #define MAX_ENGINE_INSTANCE 3 296 297 /* PCI config space */ 298 299 #define MCHBAR_I915 0x44 300 #define MCHBAR_I965 0x48 301 #define MCHBAR_SIZE (4 * 4096) 302 303 #define DEVEN 0x54 304 #define DEVEN_MCHBAR_EN (1 << 28) 305 306 /* BSM in include/drm/i915_drm.h */ 307 308 #define HPLLCC 0xc0 /* 85x only */ 309 #define GC_CLOCK_CONTROL_MASK (0x7 << 0) 310 #define GC_CLOCK_133_200 (0 << 0) 311 #define GC_CLOCK_100_200 (1 << 0) 312 #define GC_CLOCK_100_133 (2 << 0) 313 #define GC_CLOCK_133_266 (3 << 0) 314 #define GC_CLOCK_133_200_2 (4 << 0) 315 #define GC_CLOCK_133_266_2 (5 << 0) 316 #define GC_CLOCK_166_266 (6 << 0) 317 #define GC_CLOCK_166_250 (7 << 0) 318 319 #define I915_GDRST 0xc0 /* PCI config register */ 320 #define GRDOM_FULL (0 << 2) 321 #define GRDOM_RENDER (1 << 2) 322 #define GRDOM_MEDIA (3 << 2) 323 #define GRDOM_MASK (3 << 2) 324 #define GRDOM_RESET_STATUS (1 << 1) 325 #define GRDOM_RESET_ENABLE (1 << 0) 326 327 /* BSpec only has register offset, PCI device and bit found empirically */ 328 #define I830_CLOCK_GATE 0xc8 /* device 0 */ 329 #define I830_L2_CACHE_CLOCK_GATE_DISABLE (1 << 2) 330 331 #define GCDGMBUS 0xcc 332 333 #define GCFGC2 0xda 334 #define GCFGC 0xf0 /* 915+ only */ 335 #define GC_LOW_FREQUENCY_ENABLE (1 << 7) 336 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) 337 #define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4) 338 #define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4) 339 #define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4) 340 #define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4) 341 #define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4) 342 #define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4) 343 #define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4) 344 #define GC_DISPLAY_CLOCK_MASK (7 << 4) 345 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) 346 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) 347 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) 348 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) 349 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) 350 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0) 351 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) 352 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) 353 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) 354 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) 355 #define I945_GC_RENDER_CLOCK_MASK (7 << 0) 356 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) 357 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) 358 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) 359 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) 360 #define I915_GC_RENDER_CLOCK_MASK (7 << 0) 361 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) 362 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) 363 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) 364 365 #define ASLE 0xe4 366 #define ASLS 0xfc 367 368 #define SWSCI 0xe8 369 #define SWSCI_SCISEL (1 << 15) 370 #define SWSCI_GSSCIE (1 << 0) 371 372 #define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */ 373 374 375 #define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4) 376 #define ILK_GRDOM_FULL (0 << 1) 377 #define ILK_GRDOM_RENDER (1 << 1) 378 #define ILK_GRDOM_MEDIA (3 << 1) 379 #define ILK_GRDOM_MASK (3 << 1) 380 #define ILK_GRDOM_RESET_ENABLE (1 << 0) 381 382 #define GEN6_MBCUNIT_SNPCR _MMIO(0x900c) /* for LLC config */ 383 #define GEN6_MBC_SNPCR_SHIFT 21 384 #define GEN6_MBC_SNPCR_MASK (3 << 21) 385 #define GEN6_MBC_SNPCR_MAX (0 << 21) 386 #define GEN6_MBC_SNPCR_MED (1 << 21) 387 #define GEN6_MBC_SNPCR_LOW (2 << 21) 388 #define GEN6_MBC_SNPCR_MIN (3 << 21) /* only 1/16th of the cache is shared */ 389 390 #define VLV_G3DCTL _MMIO(0x9024) 391 #define VLV_GSCKGCTL _MMIO(0x9028) 392 393 #define GEN6_MBCTL _MMIO(0x0907c) 394 #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) 395 #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) 396 #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) 397 #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) 398 #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0) 399 400 #define GEN6_GDRST _MMIO(0x941c) 401 #define GEN6_GRDOM_FULL (1 << 0) 402 #define GEN6_GRDOM_RENDER (1 << 1) 403 #define GEN6_GRDOM_MEDIA (1 << 2) 404 #define GEN6_GRDOM_BLT (1 << 3) 405 #define GEN6_GRDOM_VECS (1 << 4) 406 #define GEN9_GRDOM_GUC (1 << 5) 407 #define GEN8_GRDOM_MEDIA2 (1 << 7) 408 /* GEN11 changed all bit defs except for FULL & RENDER */ 409 #define GEN11_GRDOM_FULL GEN6_GRDOM_FULL 410 #define GEN11_GRDOM_RENDER GEN6_GRDOM_RENDER 411 #define GEN11_GRDOM_BLT (1 << 2) 412 #define GEN11_GRDOM_GUC (1 << 3) 413 #define GEN11_GRDOM_MEDIA (1 << 5) 414 #define GEN11_GRDOM_MEDIA2 (1 << 6) 415 #define GEN11_GRDOM_MEDIA3 (1 << 7) 416 #define GEN11_GRDOM_MEDIA4 (1 << 8) 417 #define GEN11_GRDOM_VECS (1 << 13) 418 #define GEN11_GRDOM_VECS2 (1 << 14) 419 #define GEN11_GRDOM_SFC0 (1 << 17) 420 #define GEN11_GRDOM_SFC1 (1 << 18) 421 422 #define GEN11_VCS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << ((instance) >> 1)) 423 #define GEN11_VECS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << (instance)) 424 425 #define GEN11_VCS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x88C) 426 #define GEN11_VCS_SFC_FORCED_LOCK_BIT (1 << 0) 427 #define GEN11_VCS_SFC_LOCK_STATUS(engine) _MMIO((engine)->mmio_base + 0x890) 428 #define GEN11_VCS_SFC_USAGE_BIT (1 << 0) 429 #define GEN11_VCS_SFC_LOCK_ACK_BIT (1 << 1) 430 431 #define GEN11_VECS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x201C) 432 #define GEN11_VECS_SFC_FORCED_LOCK_BIT (1 << 0) 433 #define GEN11_VECS_SFC_LOCK_ACK(engine) _MMIO((engine)->mmio_base + 0x2018) 434 #define GEN11_VECS_SFC_LOCK_ACK_BIT (1 << 0) 435 #define GEN11_VECS_SFC_USAGE(engine) _MMIO((engine)->mmio_base + 0x2014) 436 #define GEN11_VECS_SFC_USAGE_BIT (1 << 0) 437 438 #define RING_PP_DIR_BASE(base) _MMIO((base) + 0x228) 439 #define RING_PP_DIR_BASE_READ(base) _MMIO((base) + 0x518) 440 #define RING_PP_DIR_DCLV(base) _MMIO((base) + 0x220) 441 #define PP_DIR_DCLV_2G 0xffffffff 442 443 #define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8 + 4) 444 #define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8) 445 446 #define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8) 447 #define GEN8_RPCS_ENABLE (1 << 31) 448 #define GEN8_RPCS_S_CNT_ENABLE (1 << 18) 449 #define GEN8_RPCS_S_CNT_SHIFT 15 450 #define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT) 451 #define GEN11_RPCS_S_CNT_SHIFT 12 452 #define GEN11_RPCS_S_CNT_MASK (0x3f << GEN11_RPCS_S_CNT_SHIFT) 453 #define GEN8_RPCS_SS_CNT_ENABLE (1 << 11) 454 #define GEN8_RPCS_SS_CNT_SHIFT 8 455 #define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT) 456 #define GEN8_RPCS_EU_MAX_SHIFT 4 457 #define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT) 458 #define GEN8_RPCS_EU_MIN_SHIFT 0 459 #define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT) 460 461 #define WAIT_FOR_RC6_EXIT _MMIO(0x20CC) 462 /* HSW only */ 463 #define HSW_SELECTIVE_READ_ADDRESSING_SHIFT 2 464 #define HSW_SELECTIVE_READ_ADDRESSING_MASK (0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT) 465 #define HSW_SELECTIVE_WRITE_ADDRESS_SHIFT 4 466 #define HSW_SELECTIVE_WRITE_ADDRESS_MASK (0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT) 467 /* HSW+ */ 468 #define HSW_WAIT_FOR_RC6_EXIT_ENABLE (1 << 0) 469 #define HSW_RCS_CONTEXT_ENABLE (1 << 7) 470 #define HSW_RCS_INHIBIT (1 << 8) 471 /* Gen8 */ 472 #define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4 473 #define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT) 474 #define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4 475 #define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT) 476 #define GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE (1 << 6) 477 #define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT 9 478 #define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT) 479 #define GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT 11 480 #define GEN8_SELECTIVE_READ_SLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT) 481 #define GEN8_SELECTIVE_READ_ADDRESSING_ENABLE (1 << 13) 482 483 #define GAM_ECOCHK _MMIO(0x4090) 484 #define BDW_DISABLE_HDC_INVALIDATION (1 << 25) 485 #define ECOCHK_SNB_BIT (1 << 10) 486 #define ECOCHK_DIS_TLB (1 << 8) 487 #define HSW_ECOCHK_ARB_PRIO_SOL (1 << 6) 488 #define ECOCHK_PPGTT_CACHE64B (0x3 << 3) 489 #define ECOCHK_PPGTT_CACHE4B (0x0 << 3) 490 #define ECOCHK_PPGTT_GFDT_IVB (0x1 << 4) 491 #define ECOCHK_PPGTT_LLC_IVB (0x1 << 3) 492 #define ECOCHK_PPGTT_UC_HSW (0x1 << 3) 493 #define ECOCHK_PPGTT_WT_HSW (0x2 << 3) 494 #define ECOCHK_PPGTT_WB_HSW (0x3 << 3) 495 496 #define GAC_ECO_BITS _MMIO(0x14090) 497 #define ECOBITS_SNB_BIT (1 << 13) 498 #define ECOBITS_PPGTT_CACHE64B (3 << 8) 499 #define ECOBITS_PPGTT_CACHE4B (0 << 8) 500 501 #define GAB_CTL _MMIO(0x24000) 502 #define GAB_CTL_CONT_AFTER_PAGEFAULT (1 << 8) 503 504 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0) 505 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20) 506 #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18) 507 #define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4) 508 #define GEN6_STOLEN_RESERVED_1M (0 << 4) 509 #define GEN6_STOLEN_RESERVED_512K (1 << 4) 510 #define GEN6_STOLEN_RESERVED_256K (2 << 4) 511 #define GEN6_STOLEN_RESERVED_128K (3 << 4) 512 #define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5) 513 #define GEN7_STOLEN_RESERVED_1M (0 << 5) 514 #define GEN7_STOLEN_RESERVED_256K (1 << 5) 515 #define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7) 516 #define GEN8_STOLEN_RESERVED_1M (0 << 7) 517 #define GEN8_STOLEN_RESERVED_2M (1 << 7) 518 #define GEN8_STOLEN_RESERVED_4M (2 << 7) 519 #define GEN8_STOLEN_RESERVED_8M (3 << 7) 520 #define GEN6_STOLEN_RESERVED_ENABLE (1 << 0) 521 #define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20) 522 523 /* VGA stuff */ 524 525 #define VGA_ST01_MDA 0x3ba 526 #define VGA_ST01_CGA 0x3da 527 528 #define _VGA_MSR_WRITE _MMIO(0x3c2) 529 #define VGA_MSR_WRITE 0x3c2 530 #define VGA_MSR_READ 0x3cc 531 #define VGA_MSR_MEM_EN (1 << 1) 532 #define VGA_MSR_CGA_MODE (1 << 0) 533 534 #define VGA_SR_INDEX 0x3c4 535 #define SR01 1 536 #define VGA_SR_DATA 0x3c5 537 538 #define VGA_AR_INDEX 0x3c0 539 #define VGA_AR_VID_EN (1 << 5) 540 #define VGA_AR_DATA_WRITE 0x3c0 541 #define VGA_AR_DATA_READ 0x3c1 542 543 #define VGA_GR_INDEX 0x3ce 544 #define VGA_GR_DATA 0x3cf 545 /* GR05 */ 546 #define VGA_GR_MEM_READ_MODE_SHIFT 3 547 #define VGA_GR_MEM_READ_MODE_PLANE 1 548 /* GR06 */ 549 #define VGA_GR_MEM_MODE_MASK 0xc 550 #define VGA_GR_MEM_MODE_SHIFT 2 551 #define VGA_GR_MEM_A0000_AFFFF 0 552 #define VGA_GR_MEM_A0000_BFFFF 1 553 #define VGA_GR_MEM_B0000_B7FFF 2 554 #define VGA_GR_MEM_B0000_BFFFF 3 555 556 #define VGA_DACMASK 0x3c6 557 #define VGA_DACRX 0x3c7 558 #define VGA_DACWX 0x3c8 559 #define VGA_DACDATA 0x3c9 560 561 #define VGA_CR_INDEX_MDA 0x3b4 562 #define VGA_CR_DATA_MDA 0x3b5 563 #define VGA_CR_INDEX_CGA 0x3d4 564 #define VGA_CR_DATA_CGA 0x3d5 565 566 #define MI_PREDICATE_SRC0 _MMIO(0x2400) 567 #define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4) 568 #define MI_PREDICATE_SRC1 _MMIO(0x2408) 569 #define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4) 570 571 #define MI_PREDICATE_RESULT_2 _MMIO(0x2214) 572 #define LOWER_SLICE_ENABLED (1 << 0) 573 #define LOWER_SLICE_DISABLED (0 << 0) 574 575 /* 576 * Registers used only by the command parser 577 */ 578 #define BCS_SWCTRL _MMIO(0x22200) 579 580 #define GPGPU_THREADS_DISPATCHED _MMIO(0x2290) 581 #define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4) 582 #define HS_INVOCATION_COUNT _MMIO(0x2300) 583 #define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4) 584 #define DS_INVOCATION_COUNT _MMIO(0x2308) 585 #define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4) 586 #define IA_VERTICES_COUNT _MMIO(0x2310) 587 #define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4) 588 #define IA_PRIMITIVES_COUNT _MMIO(0x2318) 589 #define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4) 590 #define VS_INVOCATION_COUNT _MMIO(0x2320) 591 #define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4) 592 #define GS_INVOCATION_COUNT _MMIO(0x2328) 593 #define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4) 594 #define GS_PRIMITIVES_COUNT _MMIO(0x2330) 595 #define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4) 596 #define CL_INVOCATION_COUNT _MMIO(0x2338) 597 #define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4) 598 #define CL_PRIMITIVES_COUNT _MMIO(0x2340) 599 #define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4) 600 #define PS_INVOCATION_COUNT _MMIO(0x2348) 601 #define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4) 602 #define PS_DEPTH_COUNT _MMIO(0x2350) 603 #define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4) 604 605 /* There are the 4 64-bit counter registers, one for each stream output */ 606 #define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8) 607 #define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4) 608 609 #define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8) 610 #define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4) 611 612 #define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420) 613 #define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430) 614 #define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434) 615 #define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438) 616 #define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243C) 617 #define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440) 618 619 #define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500) 620 #define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504) 621 #define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508) 622 623 /* There are the 16 64-bit CS General Purpose Registers */ 624 #define HSW_CS_GPR(n) _MMIO(0x2600 + (n) * 8) 625 #define HSW_CS_GPR_UDW(n) _MMIO(0x2600 + (n) * 8 + 4) 626 627 #define GEN7_OACONTROL _MMIO(0x2360) 628 #define GEN7_OACONTROL_CTX_MASK 0xFFFFF000 629 #define GEN7_OACONTROL_TIMER_PERIOD_MASK 0x3F 630 #define GEN7_OACONTROL_TIMER_PERIOD_SHIFT 6 631 #define GEN7_OACONTROL_TIMER_ENABLE (1 << 5) 632 #define GEN7_OACONTROL_FORMAT_A13 (0 << 2) 633 #define GEN7_OACONTROL_FORMAT_A29 (1 << 2) 634 #define GEN7_OACONTROL_FORMAT_A13_B8_C8 (2 << 2) 635 #define GEN7_OACONTROL_FORMAT_A29_B8_C8 (3 << 2) 636 #define GEN7_OACONTROL_FORMAT_B4_C8 (4 << 2) 637 #define GEN7_OACONTROL_FORMAT_A45_B8_C8 (5 << 2) 638 #define GEN7_OACONTROL_FORMAT_B4_C8_A16 (6 << 2) 639 #define GEN7_OACONTROL_FORMAT_C4_B8 (7 << 2) 640 #define GEN7_OACONTROL_FORMAT_SHIFT 2 641 #define GEN7_OACONTROL_PER_CTX_ENABLE (1 << 1) 642 #define GEN7_OACONTROL_ENABLE (1 << 0) 643 644 #define GEN8_OACTXID _MMIO(0x2364) 645 646 #define GEN8_OA_DEBUG _MMIO(0x2B04) 647 #define GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1 << 5) 648 #define GEN9_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6) 649 #define GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2) 650 #define GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1) 651 652 #define GEN8_OACONTROL _MMIO(0x2B00) 653 #define GEN8_OA_REPORT_FORMAT_A12 (0 << 2) 654 #define GEN8_OA_REPORT_FORMAT_A12_B8_C8 (2 << 2) 655 #define GEN8_OA_REPORT_FORMAT_A36_B8_C8 (5 << 2) 656 #define GEN8_OA_REPORT_FORMAT_C4_B8 (7 << 2) 657 #define GEN8_OA_REPORT_FORMAT_SHIFT 2 658 #define GEN8_OA_SPECIFIC_CONTEXT_ENABLE (1 << 1) 659 #define GEN8_OA_COUNTER_ENABLE (1 << 0) 660 661 #define GEN8_OACTXCONTROL _MMIO(0x2360) 662 #define GEN8_OA_TIMER_PERIOD_MASK 0x3F 663 #define GEN8_OA_TIMER_PERIOD_SHIFT 2 664 #define GEN8_OA_TIMER_ENABLE (1 << 1) 665 #define GEN8_OA_COUNTER_RESUME (1 << 0) 666 667 #define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */ 668 #define GEN7_OABUFFER_OVERRUN_DISABLE (1 << 3) 669 #define GEN7_OABUFFER_EDGE_TRIGGER (1 << 2) 670 #define GEN7_OABUFFER_STOP_RESUME_ENABLE (1 << 1) 671 #define GEN7_OABUFFER_RESUME (1 << 0) 672 673 #define GEN8_OABUFFER_UDW _MMIO(0x23b4) 674 #define GEN8_OABUFFER _MMIO(0x2b14) 675 #define GEN8_OABUFFER_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */ 676 677 #define GEN7_OASTATUS1 _MMIO(0x2364) 678 #define GEN7_OASTATUS1_TAIL_MASK 0xffffffc0 679 #define GEN7_OASTATUS1_COUNTER_OVERFLOW (1 << 2) 680 #define GEN7_OASTATUS1_OABUFFER_OVERFLOW (1 << 1) 681 #define GEN7_OASTATUS1_REPORT_LOST (1 << 0) 682 683 #define GEN7_OASTATUS2 _MMIO(0x2368) 684 #define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0 685 #define GEN7_OASTATUS2_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */ 686 687 #define GEN8_OASTATUS _MMIO(0x2b08) 688 #define GEN8_OASTATUS_OVERRUN_STATUS (1 << 3) 689 #define GEN8_OASTATUS_COUNTER_OVERFLOW (1 << 2) 690 #define GEN8_OASTATUS_OABUFFER_OVERFLOW (1 << 1) 691 #define GEN8_OASTATUS_REPORT_LOST (1 << 0) 692 693 #define GEN8_OAHEADPTR _MMIO(0x2B0C) 694 #define GEN8_OAHEADPTR_MASK 0xffffffc0 695 #define GEN8_OATAILPTR _MMIO(0x2B10) 696 #define GEN8_OATAILPTR_MASK 0xffffffc0 697 698 #define OABUFFER_SIZE_128K (0 << 3) 699 #define OABUFFER_SIZE_256K (1 << 3) 700 #define OABUFFER_SIZE_512K (2 << 3) 701 #define OABUFFER_SIZE_1M (3 << 3) 702 #define OABUFFER_SIZE_2M (4 << 3) 703 #define OABUFFER_SIZE_4M (5 << 3) 704 #define OABUFFER_SIZE_8M (6 << 3) 705 #define OABUFFER_SIZE_16M (7 << 3) 706 707 /* 708 * Flexible, Aggregate EU Counter Registers. 709 * Note: these aren't contiguous 710 */ 711 #define EU_PERF_CNTL0 _MMIO(0xe458) 712 #define EU_PERF_CNTL1 _MMIO(0xe558) 713 #define EU_PERF_CNTL2 _MMIO(0xe658) 714 #define EU_PERF_CNTL3 _MMIO(0xe758) 715 #define EU_PERF_CNTL4 _MMIO(0xe45c) 716 #define EU_PERF_CNTL5 _MMIO(0xe55c) 717 #define EU_PERF_CNTL6 _MMIO(0xe65c) 718 719 /* 720 * OA Boolean state 721 */ 722 723 #define OASTARTTRIG1 _MMIO(0x2710) 724 #define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000 725 #define OASTARTTRIG1_THRESHOLD_MASK 0xffff 726 727 #define OASTARTTRIG2 _MMIO(0x2714) 728 #define OASTARTTRIG2_INVERT_A_0 (1 << 0) 729 #define OASTARTTRIG2_INVERT_A_1 (1 << 1) 730 #define OASTARTTRIG2_INVERT_A_2 (1 << 2) 731 #define OASTARTTRIG2_INVERT_A_3 (1 << 3) 732 #define OASTARTTRIG2_INVERT_A_4 (1 << 4) 733 #define OASTARTTRIG2_INVERT_A_5 (1 << 5) 734 #define OASTARTTRIG2_INVERT_A_6 (1 << 6) 735 #define OASTARTTRIG2_INVERT_A_7 (1 << 7) 736 #define OASTARTTRIG2_INVERT_A_8 (1 << 8) 737 #define OASTARTTRIG2_INVERT_A_9 (1 << 9) 738 #define OASTARTTRIG2_INVERT_A_10 (1 << 10) 739 #define OASTARTTRIG2_INVERT_A_11 (1 << 11) 740 #define OASTARTTRIG2_INVERT_A_12 (1 << 12) 741 #define OASTARTTRIG2_INVERT_A_13 (1 << 13) 742 #define OASTARTTRIG2_INVERT_A_14 (1 << 14) 743 #define OASTARTTRIG2_INVERT_A_15 (1 << 15) 744 #define OASTARTTRIG2_INVERT_B_0 (1 << 16) 745 #define OASTARTTRIG2_INVERT_B_1 (1 << 17) 746 #define OASTARTTRIG2_INVERT_B_2 (1 << 18) 747 #define OASTARTTRIG2_INVERT_B_3 (1 << 19) 748 #define OASTARTTRIG2_INVERT_C_0 (1 << 20) 749 #define OASTARTTRIG2_INVERT_C_1 (1 << 21) 750 #define OASTARTTRIG2_INVERT_D_0 (1 << 22) 751 #define OASTARTTRIG2_THRESHOLD_ENABLE (1 << 23) 752 #define OASTARTTRIG2_START_TRIG_FLAG_MBZ (1 << 24) 753 #define OASTARTTRIG2_EVENT_SELECT_0 (1 << 28) 754 #define OASTARTTRIG2_EVENT_SELECT_1 (1 << 29) 755 #define OASTARTTRIG2_EVENT_SELECT_2 (1 << 30) 756 #define OASTARTTRIG2_EVENT_SELECT_3 (1 << 31) 757 758 #define OASTARTTRIG3 _MMIO(0x2718) 759 #define OASTARTTRIG3_NOA_SELECT_MASK 0xf 760 #define OASTARTTRIG3_NOA_SELECT_8_SHIFT 0 761 #define OASTARTTRIG3_NOA_SELECT_9_SHIFT 4 762 #define OASTARTTRIG3_NOA_SELECT_10_SHIFT 8 763 #define OASTARTTRIG3_NOA_SELECT_11_SHIFT 12 764 #define OASTARTTRIG3_NOA_SELECT_12_SHIFT 16 765 #define OASTARTTRIG3_NOA_SELECT_13_SHIFT 20 766 #define OASTARTTRIG3_NOA_SELECT_14_SHIFT 24 767 #define OASTARTTRIG3_NOA_SELECT_15_SHIFT 28 768 769 #define OASTARTTRIG4 _MMIO(0x271c) 770 #define OASTARTTRIG4_NOA_SELECT_MASK 0xf 771 #define OASTARTTRIG4_NOA_SELECT_0_SHIFT 0 772 #define OASTARTTRIG4_NOA_SELECT_1_SHIFT 4 773 #define OASTARTTRIG4_NOA_SELECT_2_SHIFT 8 774 #define OASTARTTRIG4_NOA_SELECT_3_SHIFT 12 775 #define OASTARTTRIG4_NOA_SELECT_4_SHIFT 16 776 #define OASTARTTRIG4_NOA_SELECT_5_SHIFT 20 777 #define OASTARTTRIG4_NOA_SELECT_6_SHIFT 24 778 #define OASTARTTRIG4_NOA_SELECT_7_SHIFT 28 779 780 #define OASTARTTRIG5 _MMIO(0x2720) 781 #define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000 782 #define OASTARTTRIG5_THRESHOLD_MASK 0xffff 783 784 #define OASTARTTRIG6 _MMIO(0x2724) 785 #define OASTARTTRIG6_INVERT_A_0 (1 << 0) 786 #define OASTARTTRIG6_INVERT_A_1 (1 << 1) 787 #define OASTARTTRIG6_INVERT_A_2 (1 << 2) 788 #define OASTARTTRIG6_INVERT_A_3 (1 << 3) 789 #define OASTARTTRIG6_INVERT_A_4 (1 << 4) 790 #define OASTARTTRIG6_INVERT_A_5 (1 << 5) 791 #define OASTARTTRIG6_INVERT_A_6 (1 << 6) 792 #define OASTARTTRIG6_INVERT_A_7 (1 << 7) 793 #define OASTARTTRIG6_INVERT_A_8 (1 << 8) 794 #define OASTARTTRIG6_INVERT_A_9 (1 << 9) 795 #define OASTARTTRIG6_INVERT_A_10 (1 << 10) 796 #define OASTARTTRIG6_INVERT_A_11 (1 << 11) 797 #define OASTARTTRIG6_INVERT_A_12 (1 << 12) 798 #define OASTARTTRIG6_INVERT_A_13 (1 << 13) 799 #define OASTARTTRIG6_INVERT_A_14 (1 << 14) 800 #define OASTARTTRIG6_INVERT_A_15 (1 << 15) 801 #define OASTARTTRIG6_INVERT_B_0 (1 << 16) 802 #define OASTARTTRIG6_INVERT_B_1 (1 << 17) 803 #define OASTARTTRIG6_INVERT_B_2 (1 << 18) 804 #define OASTARTTRIG6_INVERT_B_3 (1 << 19) 805 #define OASTARTTRIG6_INVERT_C_0 (1 << 20) 806 #define OASTARTTRIG6_INVERT_C_1 (1 << 21) 807 #define OASTARTTRIG6_INVERT_D_0 (1 << 22) 808 #define OASTARTTRIG6_THRESHOLD_ENABLE (1 << 23) 809 #define OASTARTTRIG6_START_TRIG_FLAG_MBZ (1 << 24) 810 #define OASTARTTRIG6_EVENT_SELECT_4 (1 << 28) 811 #define OASTARTTRIG6_EVENT_SELECT_5 (1 << 29) 812 #define OASTARTTRIG6_EVENT_SELECT_6 (1 << 30) 813 #define OASTARTTRIG6_EVENT_SELECT_7 (1 << 31) 814 815 #define OASTARTTRIG7 _MMIO(0x2728) 816 #define OASTARTTRIG7_NOA_SELECT_MASK 0xf 817 #define OASTARTTRIG7_NOA_SELECT_8_SHIFT 0 818 #define OASTARTTRIG7_NOA_SELECT_9_SHIFT 4 819 #define OASTARTTRIG7_NOA_SELECT_10_SHIFT 8 820 #define OASTARTTRIG7_NOA_SELECT_11_SHIFT 12 821 #define OASTARTTRIG7_NOA_SELECT_12_SHIFT 16 822 #define OASTARTTRIG7_NOA_SELECT_13_SHIFT 20 823 #define OASTARTTRIG7_NOA_SELECT_14_SHIFT 24 824 #define OASTARTTRIG7_NOA_SELECT_15_SHIFT 28 825 826 #define OASTARTTRIG8 _MMIO(0x272c) 827 #define OASTARTTRIG8_NOA_SELECT_MASK 0xf 828 #define OASTARTTRIG8_NOA_SELECT_0_SHIFT 0 829 #define OASTARTTRIG8_NOA_SELECT_1_SHIFT 4 830 #define OASTARTTRIG8_NOA_SELECT_2_SHIFT 8 831 #define OASTARTTRIG8_NOA_SELECT_3_SHIFT 12 832 #define OASTARTTRIG8_NOA_SELECT_4_SHIFT 16 833 #define OASTARTTRIG8_NOA_SELECT_5_SHIFT 20 834 #define OASTARTTRIG8_NOA_SELECT_6_SHIFT 24 835 #define OASTARTTRIG8_NOA_SELECT_7_SHIFT 28 836 837 #define OAREPORTTRIG1 _MMIO(0x2740) 838 #define OAREPORTTRIG1_THRESHOLD_MASK 0xffff 839 #define OAREPORTTRIG1_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */ 840 841 #define OAREPORTTRIG2 _MMIO(0x2744) 842 #define OAREPORTTRIG2_INVERT_A_0 (1 << 0) 843 #define OAREPORTTRIG2_INVERT_A_1 (1 << 1) 844 #define OAREPORTTRIG2_INVERT_A_2 (1 << 2) 845 #define OAREPORTTRIG2_INVERT_A_3 (1 << 3) 846 #define OAREPORTTRIG2_INVERT_A_4 (1 << 4) 847 #define OAREPORTTRIG2_INVERT_A_5 (1 << 5) 848 #define OAREPORTTRIG2_INVERT_A_6 (1 << 6) 849 #define OAREPORTTRIG2_INVERT_A_7 (1 << 7) 850 #define OAREPORTTRIG2_INVERT_A_8 (1 << 8) 851 #define OAREPORTTRIG2_INVERT_A_9 (1 << 9) 852 #define OAREPORTTRIG2_INVERT_A_10 (1 << 10) 853 #define OAREPORTTRIG2_INVERT_A_11 (1 << 11) 854 #define OAREPORTTRIG2_INVERT_A_12 (1 << 12) 855 #define OAREPORTTRIG2_INVERT_A_13 (1 << 13) 856 #define OAREPORTTRIG2_INVERT_A_14 (1 << 14) 857 #define OAREPORTTRIG2_INVERT_A_15 (1 << 15) 858 #define OAREPORTTRIG2_INVERT_B_0 (1 << 16) 859 #define OAREPORTTRIG2_INVERT_B_1 (1 << 17) 860 #define OAREPORTTRIG2_INVERT_B_2 (1 << 18) 861 #define OAREPORTTRIG2_INVERT_B_3 (1 << 19) 862 #define OAREPORTTRIG2_INVERT_C_0 (1 << 20) 863 #define OAREPORTTRIG2_INVERT_C_1 (1 << 21) 864 #define OAREPORTTRIG2_INVERT_D_0 (1 << 22) 865 #define OAREPORTTRIG2_THRESHOLD_ENABLE (1 << 23) 866 #define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1 << 31) 867 868 #define OAREPORTTRIG3 _MMIO(0x2748) 869 #define OAREPORTTRIG3_NOA_SELECT_MASK 0xf 870 #define OAREPORTTRIG3_NOA_SELECT_8_SHIFT 0 871 #define OAREPORTTRIG3_NOA_SELECT_9_SHIFT 4 872 #define OAREPORTTRIG3_NOA_SELECT_10_SHIFT 8 873 #define OAREPORTTRIG3_NOA_SELECT_11_SHIFT 12 874 #define OAREPORTTRIG3_NOA_SELECT_12_SHIFT 16 875 #define OAREPORTTRIG3_NOA_SELECT_13_SHIFT 20 876 #define OAREPORTTRIG3_NOA_SELECT_14_SHIFT 24 877 #define OAREPORTTRIG3_NOA_SELECT_15_SHIFT 28 878 879 #define OAREPORTTRIG4 _MMIO(0x274c) 880 #define OAREPORTTRIG4_NOA_SELECT_MASK 0xf 881 #define OAREPORTTRIG4_NOA_SELECT_0_SHIFT 0 882 #define OAREPORTTRIG4_NOA_SELECT_1_SHIFT 4 883 #define OAREPORTTRIG4_NOA_SELECT_2_SHIFT 8 884 #define OAREPORTTRIG4_NOA_SELECT_3_SHIFT 12 885 #define OAREPORTTRIG4_NOA_SELECT_4_SHIFT 16 886 #define OAREPORTTRIG4_NOA_SELECT_5_SHIFT 20 887 #define OAREPORTTRIG4_NOA_SELECT_6_SHIFT 24 888 #define OAREPORTTRIG4_NOA_SELECT_7_SHIFT 28 889 890 #define OAREPORTTRIG5 _MMIO(0x2750) 891 #define OAREPORTTRIG5_THRESHOLD_MASK 0xffff 892 #define OAREPORTTRIG5_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */ 893 894 #define OAREPORTTRIG6 _MMIO(0x2754) 895 #define OAREPORTTRIG6_INVERT_A_0 (1 << 0) 896 #define OAREPORTTRIG6_INVERT_A_1 (1 << 1) 897 #define OAREPORTTRIG6_INVERT_A_2 (1 << 2) 898 #define OAREPORTTRIG6_INVERT_A_3 (1 << 3) 899 #define OAREPORTTRIG6_INVERT_A_4 (1 << 4) 900 #define OAREPORTTRIG6_INVERT_A_5 (1 << 5) 901 #define OAREPORTTRIG6_INVERT_A_6 (1 << 6) 902 #define OAREPORTTRIG6_INVERT_A_7 (1 << 7) 903 #define OAREPORTTRIG6_INVERT_A_8 (1 << 8) 904 #define OAREPORTTRIG6_INVERT_A_9 (1 << 9) 905 #define OAREPORTTRIG6_INVERT_A_10 (1 << 10) 906 #define OAREPORTTRIG6_INVERT_A_11 (1 << 11) 907 #define OAREPORTTRIG6_INVERT_A_12 (1 << 12) 908 #define OAREPORTTRIG6_INVERT_A_13 (1 << 13) 909 #define OAREPORTTRIG6_INVERT_A_14 (1 << 14) 910 #define OAREPORTTRIG6_INVERT_A_15 (1 << 15) 911 #define OAREPORTTRIG6_INVERT_B_0 (1 << 16) 912 #define OAREPORTTRIG6_INVERT_B_1 (1 << 17) 913 #define OAREPORTTRIG6_INVERT_B_2 (1 << 18) 914 #define OAREPORTTRIG6_INVERT_B_3 (1 << 19) 915 #define OAREPORTTRIG6_INVERT_C_0 (1 << 20) 916 #define OAREPORTTRIG6_INVERT_C_1 (1 << 21) 917 #define OAREPORTTRIG6_INVERT_D_0 (1 << 22) 918 #define OAREPORTTRIG6_THRESHOLD_ENABLE (1 << 23) 919 #define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1 << 31) 920 921 #define OAREPORTTRIG7 _MMIO(0x2758) 922 #define OAREPORTTRIG7_NOA_SELECT_MASK 0xf 923 #define OAREPORTTRIG7_NOA_SELECT_8_SHIFT 0 924 #define OAREPORTTRIG7_NOA_SELECT_9_SHIFT 4 925 #define OAREPORTTRIG7_NOA_SELECT_10_SHIFT 8 926 #define OAREPORTTRIG7_NOA_SELECT_11_SHIFT 12 927 #define OAREPORTTRIG7_NOA_SELECT_12_SHIFT 16 928 #define OAREPORTTRIG7_NOA_SELECT_13_SHIFT 20 929 #define OAREPORTTRIG7_NOA_SELECT_14_SHIFT 24 930 #define OAREPORTTRIG7_NOA_SELECT_15_SHIFT 28 931 932 #define OAREPORTTRIG8 _MMIO(0x275c) 933 #define OAREPORTTRIG8_NOA_SELECT_MASK 0xf 934 #define OAREPORTTRIG8_NOA_SELECT_0_SHIFT 0 935 #define OAREPORTTRIG8_NOA_SELECT_1_SHIFT 4 936 #define OAREPORTTRIG8_NOA_SELECT_2_SHIFT 8 937 #define OAREPORTTRIG8_NOA_SELECT_3_SHIFT 12 938 #define OAREPORTTRIG8_NOA_SELECT_4_SHIFT 16 939 #define OAREPORTTRIG8_NOA_SELECT_5_SHIFT 20 940 #define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24 941 #define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28 942 943 /* CECX_0 */ 944 #define OACEC_COMPARE_LESS_OR_EQUAL 6 945 #define OACEC_COMPARE_NOT_EQUAL 5 946 #define OACEC_COMPARE_LESS_THAN 4 947 #define OACEC_COMPARE_GREATER_OR_EQUAL 3 948 #define OACEC_COMPARE_EQUAL 2 949 #define OACEC_COMPARE_GREATER_THAN 1 950 #define OACEC_COMPARE_ANY_EQUAL 0 951 952 #define OACEC_COMPARE_VALUE_MASK 0xffff 953 #define OACEC_COMPARE_VALUE_SHIFT 3 954 955 #define OACEC_SELECT_NOA (0 << 19) 956 #define OACEC_SELECT_PREV (1 << 19) 957 #define OACEC_SELECT_BOOLEAN (2 << 19) 958 959 /* CECX_1 */ 960 #define OACEC_MASK_MASK 0xffff 961 #define OACEC_CONSIDERATIONS_MASK 0xffff 962 #define OACEC_CONSIDERATIONS_SHIFT 16 963 964 #define OACEC0_0 _MMIO(0x2770) 965 #define OACEC0_1 _MMIO(0x2774) 966 #define OACEC1_0 _MMIO(0x2778) 967 #define OACEC1_1 _MMIO(0x277c) 968 #define OACEC2_0 _MMIO(0x2780) 969 #define OACEC2_1 _MMIO(0x2784) 970 #define OACEC3_0 _MMIO(0x2788) 971 #define OACEC3_1 _MMIO(0x278c) 972 #define OACEC4_0 _MMIO(0x2790) 973 #define OACEC4_1 _MMIO(0x2794) 974 #define OACEC5_0 _MMIO(0x2798) 975 #define OACEC5_1 _MMIO(0x279c) 976 #define OACEC6_0 _MMIO(0x27a0) 977 #define OACEC6_1 _MMIO(0x27a4) 978 #define OACEC7_0 _MMIO(0x27a8) 979 #define OACEC7_1 _MMIO(0x27ac) 980 981 /* OA perf counters */ 982 #define OA_PERFCNT1_LO _MMIO(0x91B8) 983 #define OA_PERFCNT1_HI _MMIO(0x91BC) 984 #define OA_PERFCNT2_LO _MMIO(0x91C0) 985 #define OA_PERFCNT2_HI _MMIO(0x91C4) 986 #define OA_PERFCNT3_LO _MMIO(0x91C8) 987 #define OA_PERFCNT3_HI _MMIO(0x91CC) 988 #define OA_PERFCNT4_LO _MMIO(0x91D8) 989 #define OA_PERFCNT4_HI _MMIO(0x91DC) 990 991 #define OA_PERFMATRIX_LO _MMIO(0x91C8) 992 #define OA_PERFMATRIX_HI _MMIO(0x91CC) 993 994 /* RPM unit config (Gen8+) */ 995 #define RPM_CONFIG0 _MMIO(0x0D00) 996 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3 997 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT) 998 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 0 999 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 1 1000 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3 1001 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT) 1002 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0 1003 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1 1004 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2 1005 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3 1006 #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT 1 1007 #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT) 1008 1009 #define RPM_CONFIG1 _MMIO(0x0D04) 1010 #define GEN10_GT_NOA_ENABLE (1 << 9) 1011 1012 /* GPM unit config (Gen9+) */ 1013 #define CTC_MODE _MMIO(0xA26C) 1014 #define CTC_SOURCE_PARAMETER_MASK 1 1015 #define CTC_SOURCE_CRYSTAL_CLOCK 0 1016 #define CTC_SOURCE_DIVIDE_LOGIC 1 1017 #define CTC_SHIFT_PARAMETER_SHIFT 1 1018 #define CTC_SHIFT_PARAMETER_MASK (0x3 << CTC_SHIFT_PARAMETER_SHIFT) 1019 1020 /* RCP unit config (Gen8+) */ 1021 #define RCP_CONFIG _MMIO(0x0D08) 1022 1023 /* NOA (HSW) */ 1024 #define HSW_MBVID2_NOA0 _MMIO(0x9E80) 1025 #define HSW_MBVID2_NOA1 _MMIO(0x9E84) 1026 #define HSW_MBVID2_NOA2 _MMIO(0x9E88) 1027 #define HSW_MBVID2_NOA3 _MMIO(0x9E8C) 1028 #define HSW_MBVID2_NOA4 _MMIO(0x9E90) 1029 #define HSW_MBVID2_NOA5 _MMIO(0x9E94) 1030 #define HSW_MBVID2_NOA6 _MMIO(0x9E98) 1031 #define HSW_MBVID2_NOA7 _MMIO(0x9E9C) 1032 #define HSW_MBVID2_NOA8 _MMIO(0x9EA0) 1033 #define HSW_MBVID2_NOA9 _MMIO(0x9EA4) 1034 1035 #define HSW_MBVID2_MISR0 _MMIO(0x9EC0) 1036 1037 /* NOA (Gen8+) */ 1038 #define NOA_CONFIG(i) _MMIO(0x0D0C + (i) * 4) 1039 1040 #define MICRO_BP0_0 _MMIO(0x9800) 1041 #define MICRO_BP0_2 _MMIO(0x9804) 1042 #define MICRO_BP0_1 _MMIO(0x9808) 1043 1044 #define MICRO_BP1_0 _MMIO(0x980C) 1045 #define MICRO_BP1_2 _MMIO(0x9810) 1046 #define MICRO_BP1_1 _MMIO(0x9814) 1047 1048 #define MICRO_BP2_0 _MMIO(0x9818) 1049 #define MICRO_BP2_2 _MMIO(0x981C) 1050 #define MICRO_BP2_1 _MMIO(0x9820) 1051 1052 #define MICRO_BP3_0 _MMIO(0x9824) 1053 #define MICRO_BP3_2 _MMIO(0x9828) 1054 #define MICRO_BP3_1 _MMIO(0x982C) 1055 1056 #define MICRO_BP_TRIGGER _MMIO(0x9830) 1057 #define MICRO_BP3_COUNT_STATUS01 _MMIO(0x9834) 1058 #define MICRO_BP3_COUNT_STATUS23 _MMIO(0x9838) 1059 #define MICRO_BP_FIRED_ARMED _MMIO(0x983C) 1060 1061 #define GDT_CHICKEN_BITS _MMIO(0x9840) 1062 #define GT_NOA_ENABLE 0x00000080 1063 1064 #define NOA_DATA _MMIO(0x986C) 1065 #define NOA_WRITE _MMIO(0x9888) 1066 #define GEN10_NOA_WRITE_HIGH _MMIO(0x9884) 1067 1068 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 1069 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 1070 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL) 1071 1072 /* 1073 * Reset registers 1074 */ 1075 #define DEBUG_RESET_I830 _MMIO(0x6070) 1076 #define DEBUG_RESET_FULL (1 << 7) 1077 #define DEBUG_RESET_RENDER (1 << 8) 1078 #define DEBUG_RESET_DISPLAY (1 << 9) 1079 1080 /* 1081 * IOSF sideband 1082 */ 1083 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100) 1084 #define IOSF_DEVFN_SHIFT 24 1085 #define IOSF_OPCODE_SHIFT 16 1086 #define IOSF_PORT_SHIFT 8 1087 #define IOSF_BYTE_ENABLES_SHIFT 4 1088 #define IOSF_BAR_SHIFT 1 1089 #define IOSF_SB_BUSY (1 << 0) 1090 #define IOSF_PORT_BUNIT 0x03 1091 #define IOSF_PORT_PUNIT 0x04 1092 #define IOSF_PORT_NC 0x11 1093 #define IOSF_PORT_DPIO 0x12 1094 #define IOSF_PORT_GPIO_NC 0x13 1095 #define IOSF_PORT_CCK 0x14 1096 #define IOSF_PORT_DPIO_2 0x1a 1097 #define IOSF_PORT_FLISDSI 0x1b 1098 #define IOSF_PORT_GPIO_SC 0x48 1099 #define IOSF_PORT_GPIO_SUS 0xa8 1100 #define IOSF_PORT_CCU 0xa9 1101 #define CHV_IOSF_PORT_GPIO_N 0x13 1102 #define CHV_IOSF_PORT_GPIO_SE 0x48 1103 #define CHV_IOSF_PORT_GPIO_E 0xa8 1104 #define CHV_IOSF_PORT_GPIO_SW 0xb2 1105 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104) 1106 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108) 1107 1108 /* See configdb bunit SB addr map */ 1109 #define BUNIT_REG_BISOC 0x11 1110 1111 /* PUNIT_REG_*SSPM0 */ 1112 #define _SSPM0_SSC(val) ((val) << 0) 1113 #define SSPM0_SSC_MASK _SSPM0_SSC(0x3) 1114 #define SSPM0_SSC_PWR_ON _SSPM0_SSC(0x0) 1115 #define SSPM0_SSC_CLK_GATE _SSPM0_SSC(0x1) 1116 #define SSPM0_SSC_RESET _SSPM0_SSC(0x2) 1117 #define SSPM0_SSC_PWR_GATE _SSPM0_SSC(0x3) 1118 #define _SSPM0_SSS(val) ((val) << 24) 1119 #define SSPM0_SSS_MASK _SSPM0_SSS(0x3) 1120 #define SSPM0_SSS_PWR_ON _SSPM0_SSS(0x0) 1121 #define SSPM0_SSS_CLK_GATE _SSPM0_SSS(0x1) 1122 #define SSPM0_SSS_RESET _SSPM0_SSS(0x2) 1123 #define SSPM0_SSS_PWR_GATE _SSPM0_SSS(0x3) 1124 1125 /* PUNIT_REG_*SSPM1 */ 1126 #define SSPM1_FREQSTAT_SHIFT 24 1127 #define SSPM1_FREQSTAT_MASK (0x1f << SSPM1_FREQSTAT_SHIFT) 1128 #define SSPM1_FREQGUAR_SHIFT 8 1129 #define SSPM1_FREQGUAR_MASK (0x1f << SSPM1_FREQGUAR_SHIFT) 1130 #define SSPM1_FREQ_SHIFT 0 1131 #define SSPM1_FREQ_MASK (0x1f << SSPM1_FREQ_SHIFT) 1132 1133 #define PUNIT_REG_VEDSSPM0 0x32 1134 #define PUNIT_REG_VEDSSPM1 0x33 1135 1136 #define PUNIT_REG_DSPSSPM 0x36 1137 #define DSPFREQSTAT_SHIFT_CHV 24 1138 #define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV) 1139 #define DSPFREQGUAR_SHIFT_CHV 8 1140 #define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV) 1141 #define DSPFREQSTAT_SHIFT 30 1142 #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT) 1143 #define DSPFREQGUAR_SHIFT 14 1144 #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT) 1145 #define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */ 1146 #define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */ 1147 #define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */ 1148 #define _DP_SSC(val, pipe) ((val) << (2 * (pipe))) 1149 #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe)) 1150 #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe)) 1151 #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe)) 1152 #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe)) 1153 #define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe)) 1154 #define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16)) 1155 #define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe)) 1156 #define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe)) 1157 #define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe)) 1158 #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe)) 1159 #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe)) 1160 1161 #define PUNIT_REG_ISPSSPM0 0x39 1162 #define PUNIT_REG_ISPSSPM1 0x3a 1163 1164 /* 1165 * i915_power_well_id: 1166 * 1167 * IDs used to look up power wells. Power wells accessed directly bypassing 1168 * the power domains framework must be assigned a unique ID. The rest of power 1169 * wells must be assigned DISP_PW_ID_NONE. 1170 */ 1171 enum i915_power_well_id { 1172 DISP_PW_ID_NONE, 1173 1174 VLV_DISP_PW_DISP2D, 1175 BXT_DISP_PW_DPIO_CMN_A, 1176 VLV_DISP_PW_DPIO_CMN_BC, 1177 GLK_DISP_PW_DPIO_CMN_C, 1178 CHV_DISP_PW_DPIO_CMN_D, 1179 HSW_DISP_PW_GLOBAL, 1180 SKL_DISP_PW_MISC_IO, 1181 SKL_DISP_PW_1, 1182 SKL_DISP_PW_2, 1183 }; 1184 1185 #define PUNIT_REG_PWRGT_CTRL 0x60 1186 #define PUNIT_REG_PWRGT_STATUS 0x61 1187 #define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2)) 1188 #define PUNIT_PWRGT_PWR_ON(pw_idx) (0 << ((pw_idx) * 2)) 1189 #define PUNIT_PWRGT_CLK_GATE(pw_idx) (1 << ((pw_idx) * 2)) 1190 #define PUNIT_PWRGT_RESET(pw_idx) (2 << ((pw_idx) * 2)) 1191 #define PUNIT_PWRGT_PWR_GATE(pw_idx) (3 << ((pw_idx) * 2)) 1192 1193 #define PUNIT_PWGT_IDX_RENDER 0 1194 #define PUNIT_PWGT_IDX_MEDIA 1 1195 #define PUNIT_PWGT_IDX_DISP2D 3 1196 #define PUNIT_PWGT_IDX_DPIO_CMN_BC 5 1197 #define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01 6 1198 #define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23 7 1199 #define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01 8 1200 #define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23 9 1201 #define PUNIT_PWGT_IDX_DPIO_RX0 10 1202 #define PUNIT_PWGT_IDX_DPIO_RX1 11 1203 #define PUNIT_PWGT_IDX_DPIO_CMN_D 12 1204 1205 #define PUNIT_REG_GPU_LFM 0xd3 1206 #define PUNIT_REG_GPU_FREQ_REQ 0xd4 1207 #define PUNIT_REG_GPU_FREQ_STS 0xd8 1208 #define GPLLENABLE (1 << 4) 1209 #define GENFREQSTATUS (1 << 0) 1210 #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc 1211 #define PUNIT_REG_CZ_TIMESTAMP 0xce 1212 1213 #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */ 1214 #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */ 1215 1216 #define FB_GFX_FMAX_AT_VMAX_FUSE 0x136 1217 #define FB_GFX_FREQ_FUSE_MASK 0xff 1218 #define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24 1219 #define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16 1220 #define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8 1221 1222 #define FB_GFX_FMIN_AT_VMIN_FUSE 0x137 1223 #define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8 1224 1225 #define PUNIT_REG_DDR_SETUP2 0x139 1226 #define FORCE_DDR_FREQ_REQ_ACK (1 << 8) 1227 #define FORCE_DDR_LOW_FREQ (1 << 1) 1228 #define FORCE_DDR_HIGH_FREQ (1 << 0) 1229 1230 #define PUNIT_GPU_STATUS_REG 0xdb 1231 #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16 1232 #define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff 1233 #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8 1234 #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff 1235 1236 #define PUNIT_GPU_DUTYCYCLE_REG 0xdf 1237 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8 1238 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff 1239 1240 #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c 1241 #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3 1242 #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8 1243 #define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11 1244 #define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800 1245 #define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34 1246 #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007 1247 #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30 1248 #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27 1249 #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 1250 1251 #define VLV_TURBO_SOC_OVERRIDE 0x04 1252 #define VLV_OVERRIDE_EN 1 1253 #define VLV_SOC_TDP_EN (1 << 1) 1254 #define VLV_BIAS_CPU_125_SOC_875 (6 << 2) 1255 #define CHV_BIAS_CPU_50_SOC_50 (3 << 2) 1256 1257 /* vlv2 north clock has */ 1258 #define CCK_FUSE_REG 0x8 1259 #define CCK_FUSE_HPLL_FREQ_MASK 0x3 1260 #define CCK_REG_DSI_PLL_FUSE 0x44 1261 #define CCK_REG_DSI_PLL_CONTROL 0x48 1262 #define DSI_PLL_VCO_EN (1 << 31) 1263 #define DSI_PLL_LDO_GATE (1 << 30) 1264 #define DSI_PLL_P1_POST_DIV_SHIFT 17 1265 #define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17) 1266 #define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13) 1267 #define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12) 1268 #define DSI_PLL_MUX_MASK (3 << 9) 1269 #define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10) 1270 #define DSI_PLL_MUX_DSI0_CCK (1 << 10) 1271 #define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9) 1272 #define DSI_PLL_MUX_DSI1_CCK (1 << 9) 1273 #define DSI_PLL_CLK_GATE_MASK (0xf << 5) 1274 #define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8) 1275 #define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7) 1276 #define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6) 1277 #define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5) 1278 #define DSI_PLL_LOCK (1 << 0) 1279 #define CCK_REG_DSI_PLL_DIVIDER 0x4c 1280 #define DSI_PLL_LFSR (1 << 31) 1281 #define DSI_PLL_FRACTION_EN (1 << 30) 1282 #define DSI_PLL_FRAC_COUNTER_SHIFT 27 1283 #define DSI_PLL_FRAC_COUNTER_MASK (7 << 27) 1284 #define DSI_PLL_USYNC_CNT_SHIFT 18 1285 #define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18) 1286 #define DSI_PLL_N1_DIV_SHIFT 16 1287 #define DSI_PLL_N1_DIV_MASK (3 << 16) 1288 #define DSI_PLL_M1_DIV_SHIFT 0 1289 #define DSI_PLL_M1_DIV_MASK (0x1ff << 0) 1290 #define CCK_CZ_CLOCK_CONTROL 0x62 1291 #define CCK_GPLL_CLOCK_CONTROL 0x67 1292 #define CCK_DISPLAY_CLOCK_CONTROL 0x6b 1293 #define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c 1294 #define CCK_TRUNK_FORCE_ON (1 << 17) 1295 #define CCK_TRUNK_FORCE_OFF (1 << 16) 1296 #define CCK_FREQUENCY_STATUS (0x1f << 8) 1297 #define CCK_FREQUENCY_STATUS_SHIFT 8 1298 #define CCK_FREQUENCY_VALUES (0x1f << 0) 1299 1300 /* DPIO registers */ 1301 #define DPIO_DEVFN 0 1302 1303 #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110) 1304 #define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */ 1305 #define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */ 1306 #define DPIO_SFR_BYPASS (1 << 1) 1307 #define DPIO_CMNRST (1 << 0) 1308 1309 #define DPIO_PHY(pipe) ((pipe) >> 1) 1310 #define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy]) 1311 1312 /* 1313 * Per pipe/PLL DPIO regs 1314 */ 1315 #define _VLV_PLL_DW3_CH0 0x800c 1316 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ 1317 #define DPIO_POST_DIV_DAC 0 1318 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ 1319 #define DPIO_POST_DIV_LVDS1 2 1320 #define DPIO_POST_DIV_LVDS2 3 1321 #define DPIO_K_SHIFT (24) /* 4 bits */ 1322 #define DPIO_P1_SHIFT (21) /* 3 bits */ 1323 #define DPIO_P2_SHIFT (16) /* 5 bits */ 1324 #define DPIO_N_SHIFT (12) /* 4 bits */ 1325 #define DPIO_ENABLE_CALIBRATION (1 << 11) 1326 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ 1327 #define DPIO_M2DIV_MASK 0xff 1328 #define _VLV_PLL_DW3_CH1 0x802c 1329 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1) 1330 1331 #define _VLV_PLL_DW5_CH0 0x8014 1332 #define DPIO_REFSEL_OVERRIDE 27 1333 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ 1334 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ 1335 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ 1336 #define DPIO_PLL_REFCLK_SEL_MASK 3 1337 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ 1338 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ 1339 #define _VLV_PLL_DW5_CH1 0x8034 1340 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1) 1341 1342 #define _VLV_PLL_DW7_CH0 0x801c 1343 #define _VLV_PLL_DW7_CH1 0x803c 1344 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1) 1345 1346 #define _VLV_PLL_DW8_CH0 0x8040 1347 #define _VLV_PLL_DW8_CH1 0x8060 1348 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1) 1349 1350 #define VLV_PLL_DW9_BCAST 0xc044 1351 #define _VLV_PLL_DW9_CH0 0x8044 1352 #define _VLV_PLL_DW9_CH1 0x8064 1353 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1) 1354 1355 #define _VLV_PLL_DW10_CH0 0x8048 1356 #define _VLV_PLL_DW10_CH1 0x8068 1357 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1) 1358 1359 #define _VLV_PLL_DW11_CH0 0x804c 1360 #define _VLV_PLL_DW11_CH1 0x806c 1361 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1) 1362 1363 /* Spec for ref block start counts at DW10 */ 1364 #define VLV_REF_DW13 0x80ac 1365 1366 #define VLV_CMN_DW0 0x8100 1367 1368 /* 1369 * Per DDI channel DPIO regs 1370 */ 1371 1372 #define _VLV_PCS_DW0_CH0 0x8200 1373 #define _VLV_PCS_DW0_CH1 0x8400 1374 #define DPIO_PCS_TX_LANE2_RESET (1 << 16) 1375 #define DPIO_PCS_TX_LANE1_RESET (1 << 7) 1376 #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4) 1377 #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3) 1378 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1) 1379 1380 #define _VLV_PCS01_DW0_CH0 0x200 1381 #define _VLV_PCS23_DW0_CH0 0x400 1382 #define _VLV_PCS01_DW0_CH1 0x2600 1383 #define _VLV_PCS23_DW0_CH1 0x2800 1384 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1) 1385 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1) 1386 1387 #define _VLV_PCS_DW1_CH0 0x8204 1388 #define _VLV_PCS_DW1_CH1 0x8404 1389 #define CHV_PCS_REQ_SOFTRESET_EN (1 << 23) 1390 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22) 1391 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21) 1392 #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) 1393 #define DPIO_PCS_CLK_SOFT_RESET (1 << 5) 1394 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1) 1395 1396 #define _VLV_PCS01_DW1_CH0 0x204 1397 #define _VLV_PCS23_DW1_CH0 0x404 1398 #define _VLV_PCS01_DW1_CH1 0x2604 1399 #define _VLV_PCS23_DW1_CH1 0x2804 1400 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1) 1401 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1) 1402 1403 #define _VLV_PCS_DW8_CH0 0x8220 1404 #define _VLV_PCS_DW8_CH1 0x8420 1405 #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20) 1406 #define CHV_PCS_USEDCLKCHANNEL (1 << 21) 1407 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1) 1408 1409 #define _VLV_PCS01_DW8_CH0 0x0220 1410 #define _VLV_PCS23_DW8_CH0 0x0420 1411 #define _VLV_PCS01_DW8_CH1 0x2620 1412 #define _VLV_PCS23_DW8_CH1 0x2820 1413 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1) 1414 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1) 1415 1416 #define _VLV_PCS_DW9_CH0 0x8224 1417 #define _VLV_PCS_DW9_CH1 0x8424 1418 #define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13) 1419 #define DPIO_PCS_TX2MARGIN_000 (0 << 13) 1420 #define DPIO_PCS_TX2MARGIN_101 (1 << 13) 1421 #define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10) 1422 #define DPIO_PCS_TX1MARGIN_000 (0 << 10) 1423 #define DPIO_PCS_TX1MARGIN_101 (1 << 10) 1424 #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1) 1425 1426 #define _VLV_PCS01_DW9_CH0 0x224 1427 #define _VLV_PCS23_DW9_CH0 0x424 1428 #define _VLV_PCS01_DW9_CH1 0x2624 1429 #define _VLV_PCS23_DW9_CH1 0x2824 1430 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1) 1431 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1) 1432 1433 #define _CHV_PCS_DW10_CH0 0x8228 1434 #define _CHV_PCS_DW10_CH1 0x8428 1435 #define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30) 1436 #define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31) 1437 #define DPIO_PCS_TX2DEEMP_MASK (0xf << 24) 1438 #define DPIO_PCS_TX2DEEMP_9P5 (0 << 24) 1439 #define DPIO_PCS_TX2DEEMP_6P0 (2 << 24) 1440 #define DPIO_PCS_TX1DEEMP_MASK (0xf << 16) 1441 #define DPIO_PCS_TX1DEEMP_9P5 (0 << 16) 1442 #define DPIO_PCS_TX1DEEMP_6P0 (2 << 16) 1443 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1) 1444 1445 #define _VLV_PCS01_DW10_CH0 0x0228 1446 #define _VLV_PCS23_DW10_CH0 0x0428 1447 #define _VLV_PCS01_DW10_CH1 0x2628 1448 #define _VLV_PCS23_DW10_CH1 0x2828 1449 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1) 1450 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1) 1451 1452 #define _VLV_PCS_DW11_CH0 0x822c 1453 #define _VLV_PCS_DW11_CH1 0x842c 1454 #define DPIO_TX2_STAGGER_MASK(x) ((x) << 24) 1455 #define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3) 1456 #define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1) 1457 #define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0) 1458 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1) 1459 1460 #define _VLV_PCS01_DW11_CH0 0x022c 1461 #define _VLV_PCS23_DW11_CH0 0x042c 1462 #define _VLV_PCS01_DW11_CH1 0x262c 1463 #define _VLV_PCS23_DW11_CH1 0x282c 1464 #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1) 1465 #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1) 1466 1467 #define _VLV_PCS01_DW12_CH0 0x0230 1468 #define _VLV_PCS23_DW12_CH0 0x0430 1469 #define _VLV_PCS01_DW12_CH1 0x2630 1470 #define _VLV_PCS23_DW12_CH1 0x2830 1471 #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1) 1472 #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1) 1473 1474 #define _VLV_PCS_DW12_CH0 0x8230 1475 #define _VLV_PCS_DW12_CH1 0x8430 1476 #define DPIO_TX2_STAGGER_MULT(x) ((x) << 20) 1477 #define DPIO_TX1_STAGGER_MULT(x) ((x) << 16) 1478 #define DPIO_TX1_STAGGER_MASK(x) ((x) << 8) 1479 #define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6) 1480 #define DPIO_LANESTAGGER_STRAP(x) ((x) << 0) 1481 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1) 1482 1483 #define _VLV_PCS_DW14_CH0 0x8238 1484 #define _VLV_PCS_DW14_CH1 0x8438 1485 #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1) 1486 1487 #define _VLV_PCS_DW23_CH0 0x825c 1488 #define _VLV_PCS_DW23_CH1 0x845c 1489 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1) 1490 1491 #define _VLV_TX_DW2_CH0 0x8288 1492 #define _VLV_TX_DW2_CH1 0x8488 1493 #define DPIO_SWING_MARGIN000_SHIFT 16 1494 #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT) 1495 #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8 1496 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1) 1497 1498 #define _VLV_TX_DW3_CH0 0x828c 1499 #define _VLV_TX_DW3_CH1 0x848c 1500 /* The following bit for CHV phy */ 1501 #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27) 1502 #define DPIO_SWING_MARGIN101_SHIFT 16 1503 #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT) 1504 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1) 1505 1506 #define _VLV_TX_DW4_CH0 0x8290 1507 #define _VLV_TX_DW4_CH1 0x8490 1508 #define DPIO_SWING_DEEMPH9P5_SHIFT 24 1509 #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT) 1510 #define DPIO_SWING_DEEMPH6P0_SHIFT 16 1511 #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT) 1512 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1) 1513 1514 #define _VLV_TX3_DW4_CH0 0x690 1515 #define _VLV_TX3_DW4_CH1 0x2a90 1516 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1) 1517 1518 #define _VLV_TX_DW5_CH0 0x8294 1519 #define _VLV_TX_DW5_CH1 0x8494 1520 #define DPIO_TX_OCALINIT_EN (1 << 31) 1521 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1) 1522 1523 #define _VLV_TX_DW11_CH0 0x82ac 1524 #define _VLV_TX_DW11_CH1 0x84ac 1525 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1) 1526 1527 #define _VLV_TX_DW14_CH0 0x82b8 1528 #define _VLV_TX_DW14_CH1 0x84b8 1529 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1) 1530 1531 /* CHV dpPhy registers */ 1532 #define _CHV_PLL_DW0_CH0 0x8000 1533 #define _CHV_PLL_DW0_CH1 0x8180 1534 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1) 1535 1536 #define _CHV_PLL_DW1_CH0 0x8004 1537 #define _CHV_PLL_DW1_CH1 0x8184 1538 #define DPIO_CHV_N_DIV_SHIFT 8 1539 #define DPIO_CHV_M1_DIV_BY_2 (0 << 0) 1540 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1) 1541 1542 #define _CHV_PLL_DW2_CH0 0x8008 1543 #define _CHV_PLL_DW2_CH1 0x8188 1544 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1) 1545 1546 #define _CHV_PLL_DW3_CH0 0x800c 1547 #define _CHV_PLL_DW3_CH1 0x818c 1548 #define DPIO_CHV_FRAC_DIV_EN (1 << 16) 1549 #define DPIO_CHV_FIRST_MOD (0 << 8) 1550 #define DPIO_CHV_SECOND_MOD (1 << 8) 1551 #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0 1552 #define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0) 1553 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1) 1554 1555 #define _CHV_PLL_DW6_CH0 0x8018 1556 #define _CHV_PLL_DW6_CH1 0x8198 1557 #define DPIO_CHV_GAIN_CTRL_SHIFT 16 1558 #define DPIO_CHV_INT_COEFF_SHIFT 8 1559 #define DPIO_CHV_PROP_COEFF_SHIFT 0 1560 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1) 1561 1562 #define _CHV_PLL_DW8_CH0 0x8020 1563 #define _CHV_PLL_DW8_CH1 0x81A0 1564 #define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0 1565 #define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0) 1566 #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1) 1567 1568 #define _CHV_PLL_DW9_CH0 0x8024 1569 #define _CHV_PLL_DW9_CH1 0x81A4 1570 #define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */ 1571 #define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1) 1572 #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */ 1573 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1) 1574 1575 #define _CHV_CMN_DW0_CH0 0x8100 1576 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19 1577 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18 1578 #define DPIO_ALLDL_POWERDOWN (1 << 1) 1579 #define DPIO_ANYDL_POWERDOWN (1 << 0) 1580 1581 #define _CHV_CMN_DW5_CH0 0x8114 1582 #define CHV_BUFRIGHTENA1_DISABLE (0 << 20) 1583 #define CHV_BUFRIGHTENA1_NORMAL (1 << 20) 1584 #define CHV_BUFRIGHTENA1_FORCE (3 << 20) 1585 #define CHV_BUFRIGHTENA1_MASK (3 << 20) 1586 #define CHV_BUFLEFTENA1_DISABLE (0 << 22) 1587 #define CHV_BUFLEFTENA1_NORMAL (1 << 22) 1588 #define CHV_BUFLEFTENA1_FORCE (3 << 22) 1589 #define CHV_BUFLEFTENA1_MASK (3 << 22) 1590 1591 #define _CHV_CMN_DW13_CH0 0x8134 1592 #define _CHV_CMN_DW0_CH1 0x8080 1593 #define DPIO_CHV_S1_DIV_SHIFT 21 1594 #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */ 1595 #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */ 1596 #define DPIO_CHV_K_DIV_SHIFT 4 1597 #define DPIO_PLL_FREQLOCK (1 << 1) 1598 #define DPIO_PLL_LOCK (1 << 0) 1599 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1) 1600 1601 #define _CHV_CMN_DW14_CH0 0x8138 1602 #define _CHV_CMN_DW1_CH1 0x8084 1603 #define DPIO_AFC_RECAL (1 << 14) 1604 #define DPIO_DCLKP_EN (1 << 13) 1605 #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */ 1606 #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */ 1607 #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */ 1608 #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */ 1609 #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */ 1610 #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */ 1611 #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */ 1612 #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */ 1613 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1) 1614 1615 #define _CHV_CMN_DW19_CH0 0x814c 1616 #define _CHV_CMN_DW6_CH1 0x8098 1617 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */ 1618 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */ 1619 #define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */ 1620 #define CHV_CMN_USEDCLKCHANNEL (1 << 13) 1621 1622 #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1) 1623 1624 #define CHV_CMN_DW28 0x8170 1625 #define DPIO_CL1POWERDOWNEN (1 << 23) 1626 #define DPIO_DYNPWRDOWNEN_CH0 (1 << 22) 1627 #define DPIO_SUS_CLK_CONFIG_ON (0 << 0) 1628 #define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0) 1629 #define DPIO_SUS_CLK_CONFIG_GATE (2 << 0) 1630 #define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0) 1631 1632 #define CHV_CMN_DW30 0x8178 1633 #define DPIO_CL2_LDOFUSE_PWRENB (1 << 6) 1634 #define DPIO_LRC_BYPASS (1 << 3) 1635 1636 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \ 1637 (lane) * 0x200 + (offset)) 1638 1639 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80) 1640 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84) 1641 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88) 1642 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c) 1643 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90) 1644 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94) 1645 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98) 1646 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c) 1647 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0) 1648 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4) 1649 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8) 1650 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac) 1651 #define DPIO_FRC_LATENCY_SHFIT 8 1652 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8) 1653 #define DPIO_UPAR_SHIFT 30 1654 1655 /* BXT PHY registers */ 1656 #define _BXT_PHY0_BASE 0x6C000 1657 #define _BXT_PHY1_BASE 0x162000 1658 #define _BXT_PHY2_BASE 0x163000 1659 #define BXT_PHY_BASE(phy) _PHY3((phy), _BXT_PHY0_BASE, \ 1660 _BXT_PHY1_BASE, \ 1661 _BXT_PHY2_BASE) 1662 1663 #define _BXT_PHY(phy, reg) \ 1664 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg)) 1665 1666 #define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \ 1667 (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \ 1668 (reg_ch1) - _BXT_PHY0_BASE)) 1669 #define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \ 1670 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)) 1671 1672 #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090) 1673 #define MIPIO_RST_CTRL (1 << 2) 1674 1675 #define _BXT_PHY_CTL_DDI_A 0x64C00 1676 #define _BXT_PHY_CTL_DDI_B 0x64C10 1677 #define _BXT_PHY_CTL_DDI_C 0x64C20 1678 #define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10) 1679 #define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9) 1680 #define BXT_PHY_LANE_ENABLED (1 << 8) 1681 #define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \ 1682 _BXT_PHY_CTL_DDI_B) 1683 1684 #define _PHY_CTL_FAMILY_EDP 0x64C80 1685 #define _PHY_CTL_FAMILY_DDI 0x64C90 1686 #define _PHY_CTL_FAMILY_DDI_C 0x64CA0 1687 #define COMMON_RESET_DIS (1 << 31) 1688 #define BXT_PHY_CTL_FAMILY(phy) _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \ 1689 _PHY_CTL_FAMILY_EDP, \ 1690 _PHY_CTL_FAMILY_DDI_C) 1691 1692 /* BXT PHY PLL registers */ 1693 #define _PORT_PLL_A 0x46074 1694 #define _PORT_PLL_B 0x46078 1695 #define _PORT_PLL_C 0x4607c 1696 #define PORT_PLL_ENABLE (1 << 31) 1697 #define PORT_PLL_LOCK (1 << 30) 1698 #define PORT_PLL_REF_SEL (1 << 27) 1699 #define PORT_PLL_POWER_ENABLE (1 << 26) 1700 #define PORT_PLL_POWER_STATE (1 << 25) 1701 #define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B) 1702 1703 #define _PORT_PLL_EBB_0_A 0x162034 1704 #define _PORT_PLL_EBB_0_B 0x6C034 1705 #define _PORT_PLL_EBB_0_C 0x6C340 1706 #define PORT_PLL_P1_SHIFT 13 1707 #define PORT_PLL_P1_MASK (0x07 << PORT_PLL_P1_SHIFT) 1708 #define PORT_PLL_P1(x) ((x) << PORT_PLL_P1_SHIFT) 1709 #define PORT_PLL_P2_SHIFT 8 1710 #define PORT_PLL_P2_MASK (0x1f << PORT_PLL_P2_SHIFT) 1711 #define PORT_PLL_P2(x) ((x) << PORT_PLL_P2_SHIFT) 1712 #define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 1713 _PORT_PLL_EBB_0_B, \ 1714 _PORT_PLL_EBB_0_C) 1715 1716 #define _PORT_PLL_EBB_4_A 0x162038 1717 #define _PORT_PLL_EBB_4_B 0x6C038 1718 #define _PORT_PLL_EBB_4_C 0x6C344 1719 #define PORT_PLL_10BIT_CLK_ENABLE (1 << 13) 1720 #define PORT_PLL_RECALIBRATE (1 << 14) 1721 #define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 1722 _PORT_PLL_EBB_4_B, \ 1723 _PORT_PLL_EBB_4_C) 1724 1725 #define _PORT_PLL_0_A 0x162100 1726 #define _PORT_PLL_0_B 0x6C100 1727 #define _PORT_PLL_0_C 0x6C380 1728 /* PORT_PLL_0_A */ 1729 #define PORT_PLL_M2_MASK 0xFF 1730 /* PORT_PLL_1_A */ 1731 #define PORT_PLL_N_SHIFT 8 1732 #define PORT_PLL_N_MASK (0x0F << PORT_PLL_N_SHIFT) 1733 #define PORT_PLL_N(x) ((x) << PORT_PLL_N_SHIFT) 1734 /* PORT_PLL_2_A */ 1735 #define PORT_PLL_M2_FRAC_MASK 0x3FFFFF 1736 /* PORT_PLL_3_A */ 1737 #define PORT_PLL_M2_FRAC_ENABLE (1 << 16) 1738 /* PORT_PLL_6_A */ 1739 #define PORT_PLL_PROP_COEFF_MASK 0xF 1740 #define PORT_PLL_INT_COEFF_MASK (0x1F << 8) 1741 #define PORT_PLL_INT_COEFF(x) ((x) << 8) 1742 #define PORT_PLL_GAIN_CTL_MASK (0x07 << 16) 1743 #define PORT_PLL_GAIN_CTL(x) ((x) << 16) 1744 /* PORT_PLL_8_A */ 1745 #define PORT_PLL_TARGET_CNT_MASK 0x3FF 1746 /* PORT_PLL_9_A */ 1747 #define PORT_PLL_LOCK_THRESHOLD_SHIFT 1 1748 #define PORT_PLL_LOCK_THRESHOLD_MASK (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT) 1749 /* PORT_PLL_10_A */ 1750 #define PORT_PLL_DCO_AMP_OVR_EN_H (1 << 27) 1751 #define PORT_PLL_DCO_AMP_DEFAULT 15 1752 #define PORT_PLL_DCO_AMP_MASK 0x3c00 1753 #define PORT_PLL_DCO_AMP(x) ((x) << 10) 1754 #define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \ 1755 _PORT_PLL_0_B, \ 1756 _PORT_PLL_0_C) 1757 #define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \ 1758 (idx) * 4) 1759 1760 /* BXT PHY common lane registers */ 1761 #define _PORT_CL1CM_DW0_A 0x162000 1762 #define _PORT_CL1CM_DW0_BC 0x6C000 1763 #define PHY_POWER_GOOD (1 << 16) 1764 #define PHY_RESERVED (1 << 7) 1765 #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC) 1766 1767 #define _PORT_CL1CM_DW9_A 0x162024 1768 #define _PORT_CL1CM_DW9_BC 0x6C024 1769 #define IREF0RC_OFFSET_SHIFT 8 1770 #define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT) 1771 #define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC) 1772 1773 #define _PORT_CL1CM_DW10_A 0x162028 1774 #define _PORT_CL1CM_DW10_BC 0x6C028 1775 #define IREF1RC_OFFSET_SHIFT 8 1776 #define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT) 1777 #define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC) 1778 1779 #define _PORT_CL1CM_DW28_A 0x162070 1780 #define _PORT_CL1CM_DW28_BC 0x6C070 1781 #define OCL1_POWER_DOWN_EN (1 << 23) 1782 #define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22) 1783 #define SUS_CLK_CONFIG 0x3 1784 #define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC) 1785 1786 #define _PORT_CL1CM_DW30_A 0x162078 1787 #define _PORT_CL1CM_DW30_BC 0x6C078 1788 #define OCL2_LDOFUSE_PWR_DIS (1 << 6) 1789 #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC) 1790 1791 /* 1792 * CNL/ICL Port/COMBO-PHY Registers 1793 */ 1794 #define _ICL_COMBOPHY_A 0x162000 1795 #define _ICL_COMBOPHY_B 0x6C000 1796 #define _ICL_COMBOPHY(port) _PICK(port, _ICL_COMBOPHY_A, \ 1797 _ICL_COMBOPHY_B) 1798 1799 /* CNL/ICL Port CL_DW registers */ 1800 #define _ICL_PORT_CL_DW(dw, port) (_ICL_COMBOPHY(port) + \ 1801 4 * (dw)) 1802 1803 #define CNL_PORT_CL1CM_DW5 _MMIO(0x162014) 1804 #define ICL_PORT_CL_DW5(port) _MMIO(_ICL_PORT_CL_DW(5, port)) 1805 #define CL_POWER_DOWN_ENABLE (1 << 4) 1806 #define SUS_CLOCK_CONFIG (3 << 0) 1807 1808 #define ICL_PORT_CL_DW10(port) _MMIO(_ICL_PORT_CL_DW(10, port)) 1809 #define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25) 1810 #define PG_SEQ_DELAY_OVERRIDE_SHIFT 25 1811 #define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24) 1812 #define PWR_UP_ALL_LANES (0x0 << 4) 1813 #define PWR_DOWN_LN_3_2_1 (0xe << 4) 1814 #define PWR_DOWN_LN_3_2 (0xc << 4) 1815 #define PWR_DOWN_LN_3 (0x8 << 4) 1816 #define PWR_DOWN_LN_2_1_0 (0x7 << 4) 1817 #define PWR_DOWN_LN_1_0 (0x3 << 4) 1818 #define PWR_DOWN_LN_3_1 (0xa << 4) 1819 #define PWR_DOWN_LN_3_1_0 (0xb << 4) 1820 #define PWR_DOWN_LN_MASK (0xf << 4) 1821 #define PWR_DOWN_LN_SHIFT 4 1822 1823 #define ICL_PORT_CL_DW12(port) _MMIO(_ICL_PORT_CL_DW(12, port)) 1824 #define ICL_LANE_ENABLE_AUX (1 << 0) 1825 1826 /* CNL/ICL Port COMP_DW registers */ 1827 #define _ICL_PORT_COMP 0x100 1828 #define _ICL_PORT_COMP_DW(dw, port) (_ICL_COMBOPHY(port) + \ 1829 _ICL_PORT_COMP + 4 * (dw)) 1830 1831 #define CNL_PORT_COMP_DW0 _MMIO(0x162100) 1832 #define ICL_PORT_COMP_DW0(port) _MMIO(_ICL_PORT_COMP_DW(0, port)) 1833 #define COMP_INIT (1 << 31) 1834 1835 #define CNL_PORT_COMP_DW1 _MMIO(0x162104) 1836 #define ICL_PORT_COMP_DW1(port) _MMIO(_ICL_PORT_COMP_DW(1, port)) 1837 1838 #define CNL_PORT_COMP_DW3 _MMIO(0x16210c) 1839 #define ICL_PORT_COMP_DW3(port) _MMIO(_ICL_PORT_COMP_DW(3, port)) 1840 #define PROCESS_INFO_DOT_0 (0 << 26) 1841 #define PROCESS_INFO_DOT_1 (1 << 26) 1842 #define PROCESS_INFO_DOT_4 (2 << 26) 1843 #define PROCESS_INFO_MASK (7 << 26) 1844 #define PROCESS_INFO_SHIFT 26 1845 #define VOLTAGE_INFO_0_85V (0 << 24) 1846 #define VOLTAGE_INFO_0_95V (1 << 24) 1847 #define VOLTAGE_INFO_1_05V (2 << 24) 1848 #define VOLTAGE_INFO_MASK (3 << 24) 1849 #define VOLTAGE_INFO_SHIFT 24 1850 1851 #define ICL_PORT_COMP_DW8(port) _MMIO(_ICL_PORT_COMP_DW(8, port)) 1852 #define IREFGEN (1 << 24) 1853 1854 #define CNL_PORT_COMP_DW9 _MMIO(0x162124) 1855 #define ICL_PORT_COMP_DW9(port) _MMIO(_ICL_PORT_COMP_DW(9, port)) 1856 1857 #define CNL_PORT_COMP_DW10 _MMIO(0x162128) 1858 #define ICL_PORT_COMP_DW10(port) _MMIO(_ICL_PORT_COMP_DW(10, port)) 1859 1860 /* CNL/ICL Port PCS registers */ 1861 #define _CNL_PORT_PCS_DW1_GRP_AE 0x162304 1862 #define _CNL_PORT_PCS_DW1_GRP_B 0x162384 1863 #define _CNL_PORT_PCS_DW1_GRP_C 0x162B04 1864 #define _CNL_PORT_PCS_DW1_GRP_D 0x162B84 1865 #define _CNL_PORT_PCS_DW1_GRP_F 0x162A04 1866 #define _CNL_PORT_PCS_DW1_LN0_AE 0x162404 1867 #define _CNL_PORT_PCS_DW1_LN0_B 0x162604 1868 #define _CNL_PORT_PCS_DW1_LN0_C 0x162C04 1869 #define _CNL_PORT_PCS_DW1_LN0_D 0x162E04 1870 #define _CNL_PORT_PCS_DW1_LN0_F 0x162804 1871 #define CNL_PORT_PCS_DW1_GRP(port) _MMIO(_PICK(port, \ 1872 _CNL_PORT_PCS_DW1_GRP_AE, \ 1873 _CNL_PORT_PCS_DW1_GRP_B, \ 1874 _CNL_PORT_PCS_DW1_GRP_C, \ 1875 _CNL_PORT_PCS_DW1_GRP_D, \ 1876 _CNL_PORT_PCS_DW1_GRP_AE, \ 1877 _CNL_PORT_PCS_DW1_GRP_F)) 1878 #define CNL_PORT_PCS_DW1_LN0(port) _MMIO(_PICK(port, \ 1879 _CNL_PORT_PCS_DW1_LN0_AE, \ 1880 _CNL_PORT_PCS_DW1_LN0_B, \ 1881 _CNL_PORT_PCS_DW1_LN0_C, \ 1882 _CNL_PORT_PCS_DW1_LN0_D, \ 1883 _CNL_PORT_PCS_DW1_LN0_AE, \ 1884 _CNL_PORT_PCS_DW1_LN0_F)) 1885 1886 #define _ICL_PORT_PCS_AUX 0x300 1887 #define _ICL_PORT_PCS_GRP 0x600 1888 #define _ICL_PORT_PCS_LN(ln) (0x800 + (ln) * 0x100) 1889 #define _ICL_PORT_PCS_DW_AUX(dw, port) (_ICL_COMBOPHY(port) + \ 1890 _ICL_PORT_PCS_AUX + 4 * (dw)) 1891 #define _ICL_PORT_PCS_DW_GRP(dw, port) (_ICL_COMBOPHY(port) + \ 1892 _ICL_PORT_PCS_GRP + 4 * (dw)) 1893 #define _ICL_PORT_PCS_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \ 1894 _ICL_PORT_PCS_LN(ln) + 4 * (dw)) 1895 #define ICL_PORT_PCS_DW1_AUX(port) _MMIO(_ICL_PORT_PCS_DW_AUX(1, port)) 1896 #define ICL_PORT_PCS_DW1_GRP(port) _MMIO(_ICL_PORT_PCS_DW_GRP(1, port)) 1897 #define ICL_PORT_PCS_DW1_LN0(port) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, port)) 1898 #define COMMON_KEEPER_EN (1 << 26) 1899 1900 /* CNL/ICL Port TX registers */ 1901 #define _CNL_PORT_TX_AE_GRP_OFFSET 0x162340 1902 #define _CNL_PORT_TX_B_GRP_OFFSET 0x1623C0 1903 #define _CNL_PORT_TX_C_GRP_OFFSET 0x162B40 1904 #define _CNL_PORT_TX_D_GRP_OFFSET 0x162BC0 1905 #define _CNL_PORT_TX_F_GRP_OFFSET 0x162A40 1906 #define _CNL_PORT_TX_AE_LN0_OFFSET 0x162440 1907 #define _CNL_PORT_TX_B_LN0_OFFSET 0x162640 1908 #define _CNL_PORT_TX_C_LN0_OFFSET 0x162C40 1909 #define _CNL_PORT_TX_D_LN0_OFFSET 0x162E40 1910 #define _CNL_PORT_TX_F_LN0_OFFSET 0x162840 1911 #define _CNL_PORT_TX_DW_GRP(dw, port) (_PICK((port), \ 1912 _CNL_PORT_TX_AE_GRP_OFFSET, \ 1913 _CNL_PORT_TX_B_GRP_OFFSET, \ 1914 _CNL_PORT_TX_B_GRP_OFFSET, \ 1915 _CNL_PORT_TX_D_GRP_OFFSET, \ 1916 _CNL_PORT_TX_AE_GRP_OFFSET, \ 1917 _CNL_PORT_TX_F_GRP_OFFSET) + \ 1918 4 * (dw)) 1919 #define _CNL_PORT_TX_DW_LN0(dw, port) (_PICK((port), \ 1920 _CNL_PORT_TX_AE_LN0_OFFSET, \ 1921 _CNL_PORT_TX_B_LN0_OFFSET, \ 1922 _CNL_PORT_TX_B_LN0_OFFSET, \ 1923 _CNL_PORT_TX_D_LN0_OFFSET, \ 1924 _CNL_PORT_TX_AE_LN0_OFFSET, \ 1925 _CNL_PORT_TX_F_LN0_OFFSET) + \ 1926 4 * (dw)) 1927 1928 #define _ICL_PORT_TX_AUX 0x380 1929 #define _ICL_PORT_TX_GRP 0x680 1930 #define _ICL_PORT_TX_LN(ln) (0x880 + (ln) * 0x100) 1931 1932 #define _ICL_PORT_TX_DW_AUX(dw, port) (_ICL_COMBOPHY(port) + \ 1933 _ICL_PORT_TX_AUX + 4 * (dw)) 1934 #define _ICL_PORT_TX_DW_GRP(dw, port) (_ICL_COMBOPHY(port) + \ 1935 _ICL_PORT_TX_GRP + 4 * (dw)) 1936 #define _ICL_PORT_TX_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \ 1937 _ICL_PORT_TX_LN(ln) + 4 * (dw)) 1938 1939 #define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(2, port)) 1940 #define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(2, port)) 1941 #define ICL_PORT_TX_DW2_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(2, port)) 1942 #define ICL_PORT_TX_DW2_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(2, port)) 1943 #define ICL_PORT_TX_DW2_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(2, 0, port)) 1944 #define SWING_SEL_UPPER(x) (((x) >> 3) << 15) 1945 #define SWING_SEL_UPPER_MASK (1 << 15) 1946 #define SWING_SEL_LOWER(x) (((x) & 0x7) << 11) 1947 #define SWING_SEL_LOWER_MASK (0x7 << 11) 1948 #define FRC_LATENCY_OPTIM_MASK (0x7 << 8) 1949 #define FRC_LATENCY_OPTIM_VAL(x) ((x) << 8) 1950 #define RCOMP_SCALAR(x) ((x) << 0) 1951 #define RCOMP_SCALAR_MASK (0xFF << 0) 1952 1953 #define _CNL_PORT_TX_DW4_LN0_AE 0x162450 1954 #define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0 1955 #define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(4, (port))) 1956 #define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port))) 1957 #define CNL_PORT_TX_DW4_LN(ln, port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \ 1958 ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \ 1959 _CNL_PORT_TX_DW4_LN0_AE))) 1960 #define ICL_PORT_TX_DW4_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(4, port)) 1961 #define ICL_PORT_TX_DW4_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(4, port)) 1962 #define ICL_PORT_TX_DW4_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(4, 0, port)) 1963 #define ICL_PORT_TX_DW4_LN(ln, port) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, port)) 1964 #define LOADGEN_SELECT (1 << 31) 1965 #define POST_CURSOR_1(x) ((x) << 12) 1966 #define POST_CURSOR_1_MASK (0x3F << 12) 1967 #define POST_CURSOR_2(x) ((x) << 6) 1968 #define POST_CURSOR_2_MASK (0x3F << 6) 1969 #define CURSOR_COEFF(x) ((x) << 0) 1970 #define CURSOR_COEFF_MASK (0x3F << 0) 1971 1972 #define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(5, port)) 1973 #define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(5, port)) 1974 #define ICL_PORT_TX_DW5_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(5, port)) 1975 #define ICL_PORT_TX_DW5_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(5, port)) 1976 #define ICL_PORT_TX_DW5_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(5, 0, port)) 1977 #define TX_TRAINING_EN (1 << 31) 1978 #define TAP2_DISABLE (1 << 30) 1979 #define TAP3_DISABLE (1 << 29) 1980 #define SCALING_MODE_SEL(x) ((x) << 18) 1981 #define SCALING_MODE_SEL_MASK (0x7 << 18) 1982 #define RTERM_SELECT(x) ((x) << 3) 1983 #define RTERM_SELECT_MASK (0x7 << 3) 1984 1985 #define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(7, (port))) 1986 #define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(7, (port))) 1987 #define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port)) 1988 #define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port)) 1989 #define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port)) 1990 #define ICL_PORT_TX_DW7_LN(ln, port) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port)) 1991 #define N_SCALAR(x) ((x) << 24) 1992 #define N_SCALAR_MASK (0x7F << 24) 1993 1994 #define MG_PHY_PORT_LN(ln, port, ln0p1, ln0p2, ln1p1) \ 1995 _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1))) 1996 1997 #define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C 1998 #define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C 1999 #define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C 2000 #define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C 2001 #define MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C 2002 #define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C 2003 #define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C 2004 #define MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C 2005 #define MG_TX1_LINK_PARAMS(ln, port) \ 2006 MG_PHY_PORT_LN(ln, port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \ 2007 MG_TX_LINK_PARAMS_TX1LN0_PORT2, \ 2008 MG_TX_LINK_PARAMS_TX1LN1_PORT1) 2009 2010 #define MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC 2011 #define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC 2012 #define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC 2013 #define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC 2014 #define MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC 2015 #define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC 2016 #define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC 2017 #define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC 2018 #define MG_TX2_LINK_PARAMS(ln, port) \ 2019 MG_PHY_PORT_LN(ln, port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \ 2020 MG_TX_LINK_PARAMS_TX2LN0_PORT2, \ 2021 MG_TX_LINK_PARAMS_TX2LN1_PORT1) 2022 #define CRI_USE_FS32 (1 << 5) 2023 2024 #define MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C 2025 #define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C 2026 #define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C 2027 #define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C 2028 #define MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C 2029 #define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C 2030 #define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C 2031 #define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C 2032 #define MG_TX1_PISO_READLOAD(ln, port) \ 2033 MG_PHY_PORT_LN(ln, port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \ 2034 MG_TX_PISO_READLOAD_TX1LN0_PORT2, \ 2035 MG_TX_PISO_READLOAD_TX1LN1_PORT1) 2036 2037 #define MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC 2038 #define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC 2039 #define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC 2040 #define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC 2041 #define MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC 2042 #define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC 2043 #define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC 2044 #define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC 2045 #define MG_TX2_PISO_READLOAD(ln, port) \ 2046 MG_PHY_PORT_LN(ln, port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \ 2047 MG_TX_PISO_READLOAD_TX2LN0_PORT2, \ 2048 MG_TX_PISO_READLOAD_TX2LN1_PORT1) 2049 #define CRI_CALCINIT (1 << 1) 2050 2051 #define MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148 2052 #define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548 2053 #define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148 2054 #define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548 2055 #define MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148 2056 #define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548 2057 #define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148 2058 #define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548 2059 #define MG_TX1_SWINGCTRL(ln, port) \ 2060 MG_PHY_PORT_LN(ln, port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \ 2061 MG_TX_SWINGCTRL_TX1LN0_PORT2, \ 2062 MG_TX_SWINGCTRL_TX1LN1_PORT1) 2063 2064 #define MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8 2065 #define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8 2066 #define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8 2067 #define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8 2068 #define MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8 2069 #define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8 2070 #define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8 2071 #define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8 2072 #define MG_TX2_SWINGCTRL(ln, port) \ 2073 MG_PHY_PORT_LN(ln, port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \ 2074 MG_TX_SWINGCTRL_TX2LN0_PORT2, \ 2075 MG_TX_SWINGCTRL_TX2LN1_PORT1) 2076 #define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0) 2077 #define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0) 2078 2079 #define MG_TX_DRVCTRL_TX1LN0_TXPORT1 0x168144 2080 #define MG_TX_DRVCTRL_TX1LN1_TXPORT1 0x168544 2081 #define MG_TX_DRVCTRL_TX1LN0_TXPORT2 0x169144 2082 #define MG_TX_DRVCTRL_TX1LN1_TXPORT2 0x169544 2083 #define MG_TX_DRVCTRL_TX1LN0_TXPORT3 0x16A144 2084 #define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544 2085 #define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144 2086 #define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544 2087 #define MG_TX1_DRVCTRL(ln, port) \ 2088 MG_PHY_PORT_LN(ln, port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \ 2089 MG_TX_DRVCTRL_TX1LN0_TXPORT2, \ 2090 MG_TX_DRVCTRL_TX1LN1_TXPORT1) 2091 2092 #define MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4 2093 #define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4 2094 #define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4 2095 #define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4 2096 #define MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4 2097 #define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4 2098 #define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4 2099 #define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4 2100 #define MG_TX2_DRVCTRL(ln, port) \ 2101 MG_PHY_PORT_LN(ln, port, MG_TX_DRVCTRL_TX2LN0_PORT1, \ 2102 MG_TX_DRVCTRL_TX2LN0_PORT2, \ 2103 MG_TX_DRVCTRL_TX2LN1_PORT1) 2104 #define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24) 2105 #define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24) 2106 #define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22) 2107 #define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16) 2108 #define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16) 2109 #define CRI_LOADGEN_SEL(x) ((x) << 12) 2110 #define CRI_LOADGEN_SEL_MASK (0x3 << 12) 2111 2112 #define MG_CLKHUB_LN0_PORT1 0x16839C 2113 #define MG_CLKHUB_LN1_PORT1 0x16879C 2114 #define MG_CLKHUB_LN0_PORT2 0x16939C 2115 #define MG_CLKHUB_LN1_PORT2 0x16979C 2116 #define MG_CLKHUB_LN0_PORT3 0x16A39C 2117 #define MG_CLKHUB_LN1_PORT3 0x16A79C 2118 #define MG_CLKHUB_LN0_PORT4 0x16B39C 2119 #define MG_CLKHUB_LN1_PORT4 0x16B79C 2120 #define MG_CLKHUB(ln, port) \ 2121 MG_PHY_PORT_LN(ln, port, MG_CLKHUB_LN0_PORT1, \ 2122 MG_CLKHUB_LN0_PORT2, \ 2123 MG_CLKHUB_LN1_PORT1) 2124 #define CFG_LOW_RATE_LKREN_EN (1 << 11) 2125 2126 #define MG_TX_DCC_TX1LN0_PORT1 0x168110 2127 #define MG_TX_DCC_TX1LN1_PORT1 0x168510 2128 #define MG_TX_DCC_TX1LN0_PORT2 0x169110 2129 #define MG_TX_DCC_TX1LN1_PORT2 0x169510 2130 #define MG_TX_DCC_TX1LN0_PORT3 0x16A110 2131 #define MG_TX_DCC_TX1LN1_PORT3 0x16A510 2132 #define MG_TX_DCC_TX1LN0_PORT4 0x16B110 2133 #define MG_TX_DCC_TX1LN1_PORT4 0x16B510 2134 #define MG_TX1_DCC(ln, port) \ 2135 MG_PHY_PORT_LN(ln, port, MG_TX_DCC_TX1LN0_PORT1, \ 2136 MG_TX_DCC_TX1LN0_PORT2, \ 2137 MG_TX_DCC_TX1LN1_PORT1) 2138 #define MG_TX_DCC_TX2LN0_PORT1 0x168090 2139 #define MG_TX_DCC_TX2LN1_PORT1 0x168490 2140 #define MG_TX_DCC_TX2LN0_PORT2 0x169090 2141 #define MG_TX_DCC_TX2LN1_PORT2 0x169490 2142 #define MG_TX_DCC_TX2LN0_PORT3 0x16A090 2143 #define MG_TX_DCC_TX2LN1_PORT3 0x16A490 2144 #define MG_TX_DCC_TX2LN0_PORT4 0x16B090 2145 #define MG_TX_DCC_TX2LN1_PORT4 0x16B490 2146 #define MG_TX2_DCC(ln, port) \ 2147 MG_PHY_PORT_LN(ln, port, MG_TX_DCC_TX2LN0_PORT1, \ 2148 MG_TX_DCC_TX2LN0_PORT2, \ 2149 MG_TX_DCC_TX2LN1_PORT1) 2150 #define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25) 2151 #define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25) 2152 #define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24) 2153 2154 #define MG_DP_MODE_LN0_ACU_PORT1 0x1683A0 2155 #define MG_DP_MODE_LN1_ACU_PORT1 0x1687A0 2156 #define MG_DP_MODE_LN0_ACU_PORT2 0x1693A0 2157 #define MG_DP_MODE_LN1_ACU_PORT2 0x1697A0 2158 #define MG_DP_MODE_LN0_ACU_PORT3 0x16A3A0 2159 #define MG_DP_MODE_LN1_ACU_PORT3 0x16A7A0 2160 #define MG_DP_MODE_LN0_ACU_PORT4 0x16B3A0 2161 #define MG_DP_MODE_LN1_ACU_PORT4 0x16B7A0 2162 #define MG_DP_MODE(ln, port) \ 2163 MG_PHY_PORT_LN(ln, port, MG_DP_MODE_LN0_ACU_PORT1, \ 2164 MG_DP_MODE_LN0_ACU_PORT2, \ 2165 MG_DP_MODE_LN1_ACU_PORT1) 2166 #define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7) 2167 #define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6) 2168 #define MG_DP_MODE_CFG_TR2PWR_GATING (1 << 5) 2169 #define MG_DP_MODE_CFG_TRPWR_GATING (1 << 4) 2170 #define MG_DP_MODE_CFG_CLNPWR_GATING (1 << 3) 2171 #define MG_DP_MODE_CFG_DIGPWR_GATING (1 << 2) 2172 #define MG_DP_MODE_CFG_GAONPWR_GATING (1 << 1) 2173 2174 #define MG_MISC_SUS0_PORT1 0x168814 2175 #define MG_MISC_SUS0_PORT2 0x169814 2176 #define MG_MISC_SUS0_PORT3 0x16A814 2177 #define MG_MISC_SUS0_PORT4 0x16B814 2178 #define MG_MISC_SUS0(tc_port) \ 2179 _MMIO(_PORT(tc_port, MG_MISC_SUS0_PORT1, MG_MISC_SUS0_PORT2)) 2180 #define MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK (3 << 14) 2181 #define MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(x) ((x) << 14) 2182 #define MG_MISC_SUS0_CFG_TR2PWR_GATING (1 << 12) 2183 #define MG_MISC_SUS0_CFG_CL2PWR_GATING (1 << 11) 2184 #define MG_MISC_SUS0_CFG_GAONPWR_GATING (1 << 10) 2185 #define MG_MISC_SUS0_CFG_TRPWR_GATING (1 << 7) 2186 #define MG_MISC_SUS0_CFG_CL1PWR_GATING (1 << 6) 2187 #define MG_MISC_SUS0_CFG_DGPWR_GATING (1 << 5) 2188 2189 /* The spec defines this only for BXT PHY0, but lets assume that this 2190 * would exist for PHY1 too if it had a second channel. 2191 */ 2192 #define _PORT_CL2CM_DW6_A 0x162358 2193 #define _PORT_CL2CM_DW6_BC 0x6C358 2194 #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC) 2195 #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28) 2196 2197 #define FIA1_BASE 0x163000 2198 2199 /* ICL PHY DFLEX registers */ 2200 #define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE + 0x008C0) 2201 #define DFLEXDPMLE1_DPMLETC_MASK(tc_port) (0xf << (4 * (tc_port))) 2202 #define DFLEXDPMLE1_DPMLETC_ML0(tc_port) (1 << (4 * (tc_port))) 2203 #define DFLEXDPMLE1_DPMLETC_ML1_0(tc_port) (3 << (4 * (tc_port))) 2204 #define DFLEXDPMLE1_DPMLETC_ML3(tc_port) (8 << (4 * (tc_port))) 2205 #define DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) (12 << (4 * (tc_port))) 2206 #define DFLEXDPMLE1_DPMLETC_ML3_0(tc_port) (15 << (4 * (tc_port))) 2207 2208 /* BXT PHY Ref registers */ 2209 #define _PORT_REF_DW3_A 0x16218C 2210 #define _PORT_REF_DW3_BC 0x6C18C 2211 #define GRC_DONE (1 << 22) 2212 #define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC) 2213 2214 #define _PORT_REF_DW6_A 0x162198 2215 #define _PORT_REF_DW6_BC 0x6C198 2216 #define GRC_CODE_SHIFT 24 2217 #define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT) 2218 #define GRC_CODE_FAST_SHIFT 16 2219 #define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT) 2220 #define GRC_CODE_SLOW_SHIFT 8 2221 #define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT) 2222 #define GRC_CODE_NOM_MASK 0xFF 2223 #define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC) 2224 2225 #define _PORT_REF_DW8_A 0x1621A0 2226 #define _PORT_REF_DW8_BC 0x6C1A0 2227 #define GRC_DIS (1 << 15) 2228 #define GRC_RDY_OVRD (1 << 1) 2229 #define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC) 2230 2231 /* BXT PHY PCS registers */ 2232 #define _PORT_PCS_DW10_LN01_A 0x162428 2233 #define _PORT_PCS_DW10_LN01_B 0x6C428 2234 #define _PORT_PCS_DW10_LN01_C 0x6C828 2235 #define _PORT_PCS_DW10_GRP_A 0x162C28 2236 #define _PORT_PCS_DW10_GRP_B 0x6CC28 2237 #define _PORT_PCS_DW10_GRP_C 0x6CE28 2238 #define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2239 _PORT_PCS_DW10_LN01_B, \ 2240 _PORT_PCS_DW10_LN01_C) 2241 #define BXT_PORT_PCS_DW10_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2242 _PORT_PCS_DW10_GRP_B, \ 2243 _PORT_PCS_DW10_GRP_C) 2244 2245 #define TX2_SWING_CALC_INIT (1 << 31) 2246 #define TX1_SWING_CALC_INIT (1 << 30) 2247 2248 #define _PORT_PCS_DW12_LN01_A 0x162430 2249 #define _PORT_PCS_DW12_LN01_B 0x6C430 2250 #define _PORT_PCS_DW12_LN01_C 0x6C830 2251 #define _PORT_PCS_DW12_LN23_A 0x162630 2252 #define _PORT_PCS_DW12_LN23_B 0x6C630 2253 #define _PORT_PCS_DW12_LN23_C 0x6CA30 2254 #define _PORT_PCS_DW12_GRP_A 0x162c30 2255 #define _PORT_PCS_DW12_GRP_B 0x6CC30 2256 #define _PORT_PCS_DW12_GRP_C 0x6CE30 2257 #define LANESTAGGER_STRAP_OVRD (1 << 6) 2258 #define LANE_STAGGER_MASK 0x1F 2259 #define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2260 _PORT_PCS_DW12_LN01_B, \ 2261 _PORT_PCS_DW12_LN01_C) 2262 #define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2263 _PORT_PCS_DW12_LN23_B, \ 2264 _PORT_PCS_DW12_LN23_C) 2265 #define BXT_PORT_PCS_DW12_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2266 _PORT_PCS_DW12_GRP_B, \ 2267 _PORT_PCS_DW12_GRP_C) 2268 2269 /* BXT PHY TX registers */ 2270 #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \ 2271 ((lane) & 1) * 0x80) 2272 2273 #define _PORT_TX_DW2_LN0_A 0x162508 2274 #define _PORT_TX_DW2_LN0_B 0x6C508 2275 #define _PORT_TX_DW2_LN0_C 0x6C908 2276 #define _PORT_TX_DW2_GRP_A 0x162D08 2277 #define _PORT_TX_DW2_GRP_B 0x6CD08 2278 #define _PORT_TX_DW2_GRP_C 0x6CF08 2279 #define BXT_PORT_TX_DW2_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2280 _PORT_TX_DW2_LN0_B, \ 2281 _PORT_TX_DW2_LN0_C) 2282 #define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2283 _PORT_TX_DW2_GRP_B, \ 2284 _PORT_TX_DW2_GRP_C) 2285 #define MARGIN_000_SHIFT 16 2286 #define MARGIN_000 (0xFF << MARGIN_000_SHIFT) 2287 #define UNIQ_TRANS_SCALE_SHIFT 8 2288 #define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT) 2289 2290 #define _PORT_TX_DW3_LN0_A 0x16250C 2291 #define _PORT_TX_DW3_LN0_B 0x6C50C 2292 #define _PORT_TX_DW3_LN0_C 0x6C90C 2293 #define _PORT_TX_DW3_GRP_A 0x162D0C 2294 #define _PORT_TX_DW3_GRP_B 0x6CD0C 2295 #define _PORT_TX_DW3_GRP_C 0x6CF0C 2296 #define BXT_PORT_TX_DW3_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2297 _PORT_TX_DW3_LN0_B, \ 2298 _PORT_TX_DW3_LN0_C) 2299 #define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2300 _PORT_TX_DW3_GRP_B, \ 2301 _PORT_TX_DW3_GRP_C) 2302 #define SCALE_DCOMP_METHOD (1 << 26) 2303 #define UNIQUE_TRANGE_EN_METHOD (1 << 27) 2304 2305 #define _PORT_TX_DW4_LN0_A 0x162510 2306 #define _PORT_TX_DW4_LN0_B 0x6C510 2307 #define _PORT_TX_DW4_LN0_C 0x6C910 2308 #define _PORT_TX_DW4_GRP_A 0x162D10 2309 #define _PORT_TX_DW4_GRP_B 0x6CD10 2310 #define _PORT_TX_DW4_GRP_C 0x6CF10 2311 #define BXT_PORT_TX_DW4_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2312 _PORT_TX_DW4_LN0_B, \ 2313 _PORT_TX_DW4_LN0_C) 2314 #define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2315 _PORT_TX_DW4_GRP_B, \ 2316 _PORT_TX_DW4_GRP_C) 2317 #define DEEMPH_SHIFT 24 2318 #define DE_EMPHASIS (0xFF << DEEMPH_SHIFT) 2319 2320 #define _PORT_TX_DW5_LN0_A 0x162514 2321 #define _PORT_TX_DW5_LN0_B 0x6C514 2322 #define _PORT_TX_DW5_LN0_C 0x6C914 2323 #define _PORT_TX_DW5_GRP_A 0x162D14 2324 #define _PORT_TX_DW5_GRP_B 0x6CD14 2325 #define _PORT_TX_DW5_GRP_C 0x6CF14 2326 #define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2327 _PORT_TX_DW5_LN0_B, \ 2328 _PORT_TX_DW5_LN0_C) 2329 #define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2330 _PORT_TX_DW5_GRP_B, \ 2331 _PORT_TX_DW5_GRP_C) 2332 #define DCC_DELAY_RANGE_1 (1 << 9) 2333 #define DCC_DELAY_RANGE_2 (1 << 8) 2334 2335 #define _PORT_TX_DW14_LN0_A 0x162538 2336 #define _PORT_TX_DW14_LN0_B 0x6C538 2337 #define _PORT_TX_DW14_LN0_C 0x6C938 2338 #define LATENCY_OPTIM_SHIFT 30 2339 #define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT) 2340 #define BXT_PORT_TX_DW14_LN(phy, ch, lane) \ 2341 _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \ 2342 _PORT_TX_DW14_LN0_C) + \ 2343 _BXT_LANE_OFFSET(lane)) 2344 2345 /* UAIMI scratch pad register 1 */ 2346 #define UAIMI_SPR1 _MMIO(0x4F074) 2347 /* SKL VccIO mask */ 2348 #define SKL_VCCIO_MASK 0x1 2349 /* SKL balance leg register */ 2350 #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C) 2351 /* I_boost values */ 2352 #define BALANCE_LEG_SHIFT(port) (8 + 3 * (port)) 2353 #define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port))) 2354 /* Balance leg disable bits */ 2355 #define BALANCE_LEG_DISABLE_SHIFT 23 2356 #define BALANCE_LEG_DISABLE(port) (1 << (23 + (port))) 2357 2358 /* 2359 * Fence registers 2360 * [0-7] @ 0x2000 gen2,gen3 2361 * [8-15] @ 0x3000 945,g33,pnv 2362 * 2363 * [0-15] @ 0x3000 gen4,gen5 2364 * 2365 * [0-15] @ 0x100000 gen6,vlv,chv 2366 * [0-31] @ 0x100000 gen7+ 2367 */ 2368 #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4) 2369 #define I830_FENCE_START_MASK 0x07f80000 2370 #define I830_FENCE_TILING_Y_SHIFT 12 2371 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 2372 #define I830_FENCE_PITCH_SHIFT 4 2373 #define I830_FENCE_REG_VALID (1 << 0) 2374 #define I915_FENCE_MAX_PITCH_VAL 4 2375 #define I830_FENCE_MAX_PITCH_VAL 6 2376 #define I830_FENCE_MAX_SIZE_VAL (1 << 8) 2377 2378 #define I915_FENCE_START_MASK 0x0ff00000 2379 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) 2380 2381 #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8) 2382 #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4) 2383 #define I965_FENCE_PITCH_SHIFT 2 2384 #define I965_FENCE_TILING_Y_SHIFT 1 2385 #define I965_FENCE_REG_VALID (1 << 0) 2386 #define I965_FENCE_MAX_PITCH_VAL 0x0400 2387 2388 #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8) 2389 #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4) 2390 #define GEN6_FENCE_PITCH_SHIFT 32 2391 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 2392 2393 2394 /* control register for cpu gtt access */ 2395 #define TILECTL _MMIO(0x101000) 2396 #define TILECTL_SWZCTL (1 << 0) 2397 #define TILECTL_TLBPF (1 << 1) 2398 #define TILECTL_TLB_PREFETCH_DIS (1 << 2) 2399 #define TILECTL_BACKSNOOP_DIS (1 << 3) 2400 2401 /* 2402 * Instruction and interrupt control regs 2403 */ 2404 #define PGTBL_CTL _MMIO(0x02020) 2405 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ 2406 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ 2407 #define PGTBL_ER _MMIO(0x02024) 2408 #define PRB0_BASE (0x2030 - 0x30) 2409 #define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */ 2410 #define PRB2_BASE (0x2050 - 0x30) /* gen3 */ 2411 #define SRB0_BASE (0x2100 - 0x30) /* gen2 */ 2412 #define SRB1_BASE (0x2110 - 0x30) /* gen2 */ 2413 #define SRB2_BASE (0x2120 - 0x30) /* 830 */ 2414 #define SRB3_BASE (0x2130 - 0x30) /* 830 */ 2415 #define RENDER_RING_BASE 0x02000 2416 #define BSD_RING_BASE 0x04000 2417 #define GEN6_BSD_RING_BASE 0x12000 2418 #define GEN8_BSD2_RING_BASE 0x1c000 2419 #define GEN11_BSD_RING_BASE 0x1c0000 2420 #define GEN11_BSD2_RING_BASE 0x1c4000 2421 #define GEN11_BSD3_RING_BASE 0x1d0000 2422 #define GEN11_BSD4_RING_BASE 0x1d4000 2423 #define VEBOX_RING_BASE 0x1a000 2424 #define GEN11_VEBOX_RING_BASE 0x1c8000 2425 #define GEN11_VEBOX2_RING_BASE 0x1d8000 2426 #define BLT_RING_BASE 0x22000 2427 #define RING_TAIL(base) _MMIO((base) + 0x30) 2428 #define RING_HEAD(base) _MMIO((base) + 0x34) 2429 #define RING_START(base) _MMIO((base) + 0x38) 2430 #define RING_CTL(base) _MMIO((base) + 0x3c) 2431 #define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */ 2432 #define RING_SYNC_0(base) _MMIO((base) + 0x40) 2433 #define RING_SYNC_1(base) _MMIO((base) + 0x44) 2434 #define RING_SYNC_2(base) _MMIO((base) + 0x48) 2435 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE)) 2436 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE)) 2437 #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE)) 2438 #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE)) 2439 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE)) 2440 #define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE)) 2441 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE)) 2442 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE)) 2443 #define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE)) 2444 #define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE)) 2445 #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE)) 2446 #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE)) 2447 #define GEN6_NOSYNC INVALID_MMIO_REG 2448 #define RING_PSMI_CTL(base) _MMIO((base) + 0x50) 2449 #define RING_MAX_IDLE(base) _MMIO((base) + 0x54) 2450 #define RING_HWS_PGA(base) _MMIO((base) + 0x80) 2451 #define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080) 2452 #define RING_RESET_CTL(base) _MMIO((base) + 0xd0) 2453 #define RESET_CTL_CAT_ERROR REG_BIT(2) 2454 #define RESET_CTL_READY_TO_RESET REG_BIT(1) 2455 #define RESET_CTL_REQUEST_RESET REG_BIT(0) 2456 2457 #define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c) 2458 2459 #define HSW_GTT_CACHE_EN _MMIO(0x4024) 2460 #define GTT_CACHE_EN_ALL 0xF0007FFF 2461 #define GEN7_WR_WATERMARK _MMIO(0x4028) 2462 #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C) 2463 #define ARB_MODE _MMIO(0x4030) 2464 #define ARB_MODE_SWIZZLE_SNB (1 << 4) 2465 #define ARB_MODE_SWIZZLE_IVB (1 << 5) 2466 #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034) 2467 #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038) 2468 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ 2469 #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4) 2470 #define GEN7_LRA_LIMITS_REG_NUM 13 2471 #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070) 2472 #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074) 2473 2474 #define GAMTARBMODE _MMIO(0x04a08) 2475 #define ARB_MODE_BWGTLB_DISABLE (1 << 9) 2476 #define ARB_MODE_SWIZZLE_BDW (1 << 1) 2477 #define RENDER_HWS_PGA_GEN7 _MMIO(0x04080) 2478 #define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100 * (engine)->hw_id) 2479 #define GEN8_RING_FAULT_REG _MMIO(0x4094) 2480 #define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7) 2481 #define RING_FAULT_GTTSEL_MASK (1 << 11) 2482 #define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff) 2483 #define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3) 2484 #define RING_FAULT_VALID (1 << 0) 2485 #define DONE_REG _MMIO(0x40b0) 2486 #define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0) 2487 #define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4) 2488 #define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + (index) * 4) 2489 #define BSD_HWS_PGA_GEN7 _MMIO(0x04180) 2490 #define BLT_HWS_PGA_GEN7 _MMIO(0x04280) 2491 #define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380) 2492 #define RING_ACTHD(base) _MMIO((base) + 0x74) 2493 #define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c) 2494 #define RING_NOPID(base) _MMIO((base) + 0x94) 2495 #define RING_IMR(base) _MMIO((base) + 0xa8) 2496 #define RING_HWSTAM(base) _MMIO((base) + 0x98) 2497 #define RING_TIMESTAMP(base) _MMIO((base) + 0x358) 2498 #define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4) 2499 #define TAIL_ADDR 0x001FFFF8 2500 #define HEAD_WRAP_COUNT 0xFFE00000 2501 #define HEAD_WRAP_ONE 0x00200000 2502 #define HEAD_ADDR 0x001FFFFC 2503 #define RING_NR_PAGES 0x001FF000 2504 #define RING_REPORT_MASK 0x00000006 2505 #define RING_REPORT_64K 0x00000002 2506 #define RING_REPORT_128K 0x00000004 2507 #define RING_NO_REPORT 0x00000000 2508 #define RING_VALID_MASK 0x00000001 2509 #define RING_VALID 0x00000001 2510 #define RING_INVALID 0x00000000 2511 #define RING_WAIT_I8XX (1 << 0) /* gen2, PRBx_HEAD */ 2512 #define RING_WAIT (1 << 11) /* gen3+, PRBx_CTL */ 2513 #define RING_WAIT_SEMAPHORE (1 << 10) /* gen6+ */ 2514 2515 #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4) 2516 #define RING_FORCE_TO_NONPRIV_RW (0 << 28) /* CFL+ & Gen11+ */ 2517 #define RING_FORCE_TO_NONPRIV_RD (1 << 28) 2518 #define RING_FORCE_TO_NONPRIV_WR (2 << 28) 2519 #define RING_FORCE_TO_NONPRIV_RANGE_1 (0 << 0) /* CFL+ & Gen11+ */ 2520 #define RING_FORCE_TO_NONPRIV_RANGE_4 (1 << 0) 2521 #define RING_FORCE_TO_NONPRIV_RANGE_16 (2 << 0) 2522 #define RING_FORCE_TO_NONPRIV_RANGE_64 (3 << 0) 2523 #define RING_MAX_NONPRIV_SLOTS 12 2524 2525 #define GEN7_TLB_RD_ADDR _MMIO(0x4700) 2526 2527 #define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0) 2528 #define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1 << 18) 2529 2530 #define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080) 2531 #define GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF 2532 #define GAMW_ECO_DEV_CTX_RELOAD_DISABLE (1 << 7) 2533 2534 #define GAMT_CHKN_BIT_REG _MMIO(0x4ab8) 2535 #define GAMT_CHKN_DISABLE_L3_COH_PIPE (1 << 31) 2536 #define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1 << 28) 2537 #define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1 << 24) 2538 2539 #if 0 2540 #define PRB0_TAIL _MMIO(0x2030) 2541 #define PRB0_HEAD _MMIO(0x2034) 2542 #define PRB0_START _MMIO(0x2038) 2543 #define PRB0_CTL _MMIO(0x203c) 2544 #define PRB1_TAIL _MMIO(0x2040) /* 915+ only */ 2545 #define PRB1_HEAD _MMIO(0x2044) /* 915+ only */ 2546 #define PRB1_START _MMIO(0x2048) /* 915+ only */ 2547 #define PRB1_CTL _MMIO(0x204c) /* 915+ only */ 2548 #endif 2549 #define IPEIR_I965 _MMIO(0x2064) 2550 #define IPEHR_I965 _MMIO(0x2068) 2551 #define GEN7_SC_INSTDONE _MMIO(0x7100) 2552 #define GEN7_SAMPLER_INSTDONE _MMIO(0xe160) 2553 #define GEN7_ROW_INSTDONE _MMIO(0xe164) 2554 #define GEN8_MCR_SELECTOR _MMIO(0xfdc) 2555 #define GEN8_MCR_SLICE(slice) (((slice) & 3) << 26) 2556 #define GEN8_MCR_SLICE_MASK GEN8_MCR_SLICE(3) 2557 #define GEN8_MCR_SUBSLICE(subslice) (((subslice) & 3) << 24) 2558 #define GEN8_MCR_SUBSLICE_MASK GEN8_MCR_SUBSLICE(3) 2559 #define GEN11_MCR_SLICE(slice) (((slice) & 0xf) << 27) 2560 #define GEN11_MCR_SLICE_MASK GEN11_MCR_SLICE(0xf) 2561 #define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24) 2562 #define GEN11_MCR_SUBSLICE_MASK GEN11_MCR_SUBSLICE(0x7) 2563 #define RING_IPEIR(base) _MMIO((base) + 0x64) 2564 #define RING_IPEHR(base) _MMIO((base) + 0x68) 2565 /* 2566 * On GEN4, only the render ring INSTDONE exists and has a different 2567 * layout than the GEN7+ version. 2568 * The GEN2 counterpart of this register is GEN2_INSTDONE. 2569 */ 2570 #define RING_INSTDONE(base) _MMIO((base) + 0x6c) 2571 #define RING_INSTPS(base) _MMIO((base) + 0x70) 2572 #define RING_DMA_FADD(base) _MMIO((base) + 0x78) 2573 #define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60) /* gen8+ */ 2574 #define RING_INSTPM(base) _MMIO((base) + 0xc0) 2575 #define RING_MI_MODE(base) _MMIO((base) + 0x9c) 2576 #define INSTPS _MMIO(0x2070) /* 965+ only */ 2577 #define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */ 2578 #define ACTHD_I965 _MMIO(0x2074) 2579 #define HWS_PGA _MMIO(0x2080) 2580 #define HWS_ADDRESS_MASK 0xfffff000 2581 #define HWS_START_ADDRESS_SHIFT 4 2582 #define PWRCTXA _MMIO(0x2088) /* 965GM+ only */ 2583 #define PWRCTX_EN (1 << 0) 2584 #define IPEIR(base) _MMIO((base) + 0x88) 2585 #define IPEHR(base) _MMIO((base) + 0x8c) 2586 #define GEN2_INSTDONE _MMIO(0x2090) 2587 #define NOPID _MMIO(0x2094) 2588 #define HWSTAM _MMIO(0x2098) 2589 #define DMA_FADD_I8XX(base) _MMIO((base) + 0xd0) 2590 #define RING_BBSTATE(base) _MMIO((base) + 0x110) 2591 #define RING_BB_PPGTT (1 << 5) 2592 #define RING_SBBADDR(base) _MMIO((base) + 0x114) /* hsw+ */ 2593 #define RING_SBBSTATE(base) _MMIO((base) + 0x118) /* hsw+ */ 2594 #define RING_SBBADDR_UDW(base) _MMIO((base) + 0x11c) /* gen8+ */ 2595 #define RING_BBADDR(base) _MMIO((base) + 0x140) 2596 #define RING_BBADDR_UDW(base) _MMIO((base) + 0x168) /* gen8+ */ 2597 #define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+ */ 2598 #define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+ */ 2599 #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */ 2600 #define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */ 2601 2602 #define ERROR_GEN6 _MMIO(0x40a0) 2603 #define GEN7_ERR_INT _MMIO(0x44040) 2604 #define ERR_INT_POISON (1 << 31) 2605 #define ERR_INT_MMIO_UNCLAIMED (1 << 13) 2606 #define ERR_INT_PIPE_CRC_DONE_C (1 << 8) 2607 #define ERR_INT_FIFO_UNDERRUN_C (1 << 6) 2608 #define ERR_INT_PIPE_CRC_DONE_B (1 << 5) 2609 #define ERR_INT_FIFO_UNDERRUN_B (1 << 3) 2610 #define ERR_INT_PIPE_CRC_DONE_A (1 << 2) 2611 #define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3)) 2612 #define ERR_INT_FIFO_UNDERRUN_A (1 << 0) 2613 #define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) 2614 2615 #define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10) 2616 #define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14) 2617 #define FAULT_VA_HIGH_BITS (0xf << 0) 2618 #define FAULT_GTT_SEL (1 << 4) 2619 2620 #define FPGA_DBG _MMIO(0x42300) 2621 #define FPGA_DBG_RM_NOCLAIM (1 << 31) 2622 2623 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028) 2624 #define CLAIM_ER_CLR (1 << 31) 2625 #define CLAIM_ER_OVERFLOW (1 << 16) 2626 #define CLAIM_ER_CTR_MASK 0xffff 2627 2628 #define DERRMR _MMIO(0x44050) 2629 /* Note that HBLANK events are reserved on bdw+ */ 2630 #define DERRMR_PIPEA_SCANLINE (1 << 0) 2631 #define DERRMR_PIPEA_PRI_FLIP_DONE (1 << 1) 2632 #define DERRMR_PIPEA_SPR_FLIP_DONE (1 << 2) 2633 #define DERRMR_PIPEA_VBLANK (1 << 3) 2634 #define DERRMR_PIPEA_HBLANK (1 << 5) 2635 #define DERRMR_PIPEB_SCANLINE (1 << 8) 2636 #define DERRMR_PIPEB_PRI_FLIP_DONE (1 << 9) 2637 #define DERRMR_PIPEB_SPR_FLIP_DONE (1 << 10) 2638 #define DERRMR_PIPEB_VBLANK (1 << 11) 2639 #define DERRMR_PIPEB_HBLANK (1 << 13) 2640 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */ 2641 #define DERRMR_PIPEC_SCANLINE (1 << 14) 2642 #define DERRMR_PIPEC_PRI_FLIP_DONE (1 << 15) 2643 #define DERRMR_PIPEC_SPR_FLIP_DONE (1 << 20) 2644 #define DERRMR_PIPEC_VBLANK (1 << 21) 2645 #define DERRMR_PIPEC_HBLANK (1 << 22) 2646 2647 2648 /* GM45+ chicken bits -- debug workaround bits that may be required 2649 * for various sorts of correct behavior. The top 16 bits of each are 2650 * the enables for writing to the corresponding low bit. 2651 */ 2652 #define _3D_CHICKEN _MMIO(0x2084) 2653 #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10) 2654 #define _3D_CHICKEN2 _MMIO(0x208c) 2655 2656 #define FF_SLICE_CHICKEN _MMIO(0x2088) 2657 #define FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX (1 << 1) 2658 2659 /* Disables pipelining of read flushes past the SF-WIZ interface. 2660 * Required on all Ironlake steppings according to the B-Spec, but the 2661 * particular danger of not doing so is not specified. 2662 */ 2663 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) 2664 #define _3D_CHICKEN3 _MMIO(0x2090) 2665 #define _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX (1 << 12) 2666 #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) 2667 #define _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE (1 << 5) 2668 #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) 2669 #define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x) << 1) /* gen8+ */ 2670 #define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */ 2671 2672 #define MI_MODE _MMIO(0x209c) 2673 # define VS_TIMER_DISPATCH (1 << 6) 2674 # define MI_FLUSH_ENABLE (1 << 12) 2675 # define ASYNC_FLIP_PERF_DISABLE (1 << 14) 2676 # define MODE_IDLE (1 << 9) 2677 # define STOP_RING (1 << 8) 2678 2679 #define GEN6_GT_MODE _MMIO(0x20d0) 2680 #define GEN7_GT_MODE _MMIO(0x7008) 2681 #define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7)) 2682 #define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0) 2683 #define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1) 2684 #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0) 2685 #define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1) 2686 #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5) 2687 #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2)) 2688 #define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2)) 2689 2690 /* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */ 2691 #define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4) 2692 #define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2) 2693 #define GEN11_ENABLE_32_PLANE_MODE (1 << 7) 2694 2695 /* WaClearTdlStateAckDirtyBits */ 2696 #define GEN8_STATE_ACK _MMIO(0x20F0) 2697 #define GEN9_STATE_ACK_SLICE1 _MMIO(0x20F8) 2698 #define GEN9_STATE_ACK_SLICE2 _MMIO(0x2100) 2699 #define GEN9_STATE_ACK_TDL0 (1 << 12) 2700 #define GEN9_STATE_ACK_TDL1 (1 << 13) 2701 #define GEN9_STATE_ACK_TDL2 (1 << 14) 2702 #define GEN9_STATE_ACK_TDL3 (1 << 15) 2703 #define GEN9_SUBSLICE_TDL_ACK_BITS \ 2704 (GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \ 2705 GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0) 2706 2707 #define GFX_MODE _MMIO(0x2520) 2708 #define GFX_MODE_GEN7 _MMIO(0x229c) 2709 #define RING_MODE_GEN7(base) _MMIO((base) + 0x29c) 2710 #define GFX_RUN_LIST_ENABLE (1 << 15) 2711 #define GFX_INTERRUPT_STEERING (1 << 14) 2712 #define GFX_TLB_INVALIDATE_EXPLICIT (1 << 13) 2713 #define GFX_SURFACE_FAULT_ENABLE (1 << 12) 2714 #define GFX_REPLAY_MODE (1 << 11) 2715 #define GFX_PSMI_GRANULARITY (1 << 10) 2716 #define GFX_PPGTT_ENABLE (1 << 9) 2717 #define GEN8_GFX_PPGTT_48B (1 << 7) 2718 2719 #define GFX_FORWARD_VBLANK_MASK (3 << 5) 2720 #define GFX_FORWARD_VBLANK_NEVER (0 << 5) 2721 #define GFX_FORWARD_VBLANK_ALWAYS (1 << 5) 2722 #define GFX_FORWARD_VBLANK_COND (2 << 5) 2723 2724 #define GEN11_GFX_DISABLE_LEGACY_MODE (1 << 3) 2725 2726 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030) 2727 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034) 2728 #define SCPD0 _MMIO(0x209c) /* 915+ only */ 2729 #define GEN2_IER _MMIO(0x20a0) 2730 #define GEN2_IIR _MMIO(0x20a4) 2731 #define GEN2_IMR _MMIO(0x20a8) 2732 #define GEN2_ISR _MMIO(0x20ac) 2733 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060) 2734 #define GINT_DIS (1 << 22) 2735 #define GCFG_DIS (1 << 8) 2736 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064) 2737 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084) 2738 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0) 2739 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4) 2740 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8) 2741 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac) 2742 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120) 2743 #define VLV_PCBR_ADDR_SHIFT 12 2744 2745 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */ 2746 #define EIR _MMIO(0x20b0) 2747 #define EMR _MMIO(0x20b4) 2748 #define ESR _MMIO(0x20b8) 2749 #define GM45_ERROR_PAGE_TABLE (1 << 5) 2750 #define GM45_ERROR_MEM_PRIV (1 << 4) 2751 #define I915_ERROR_PAGE_TABLE (1 << 4) 2752 #define GM45_ERROR_CP_PRIV (1 << 3) 2753 #define I915_ERROR_MEMORY_REFRESH (1 << 1) 2754 #define I915_ERROR_INSTRUCTION (1 << 0) 2755 #define INSTPM _MMIO(0x20c0) 2756 #define INSTPM_SELF_EN (1 << 12) /* 915GM only */ 2757 #define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts 2758 will not assert AGPBUSY# and will only 2759 be delivered when out of C3. */ 2760 #define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */ 2761 #define INSTPM_TLB_INVALIDATE (1 << 9) 2762 #define INSTPM_SYNC_FLUSH (1 << 5) 2763 #define ACTHD(base) _MMIO((base) + 0xc8) 2764 #define MEM_MODE _MMIO(0x20cc) 2765 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */ 2766 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */ 2767 #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */ 2768 #define FW_BLC _MMIO(0x20d8) 2769 #define FW_BLC2 _MMIO(0x20dc) 2770 #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */ 2771 #define FW_BLC_SELF_EN_MASK (1 << 31) 2772 #define FW_BLC_SELF_FIFO_MASK (1 << 16) /* 945 only */ 2773 #define FW_BLC_SELF_EN (1 << 15) /* 945 only */ 2774 #define MM_BURST_LENGTH 0x00700000 2775 #define MM_FIFO_WATERMARK 0x0001F000 2776 #define LM_BURST_LENGTH 0x00000700 2777 #define LM_FIFO_WATERMARK 0x0000001F 2778 #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */ 2779 2780 #define MBUS_ABOX_CTL _MMIO(0x45038) 2781 #define MBUS_ABOX_BW_CREDIT_MASK (3 << 20) 2782 #define MBUS_ABOX_BW_CREDIT(x) ((x) << 20) 2783 #define MBUS_ABOX_B_CREDIT_MASK (0xF << 16) 2784 #define MBUS_ABOX_B_CREDIT(x) ((x) << 16) 2785 #define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8) 2786 #define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8) 2787 #define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0) 2788 #define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0) 2789 2790 #define _PIPEA_MBUS_DBOX_CTL 0x7003C 2791 #define _PIPEB_MBUS_DBOX_CTL 0x7103C 2792 #define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \ 2793 _PIPEB_MBUS_DBOX_CTL) 2794 #define MBUS_DBOX_BW_CREDIT_MASK (3 << 14) 2795 #define MBUS_DBOX_BW_CREDIT(x) ((x) << 14) 2796 #define MBUS_DBOX_B_CREDIT_MASK (0x1F << 8) 2797 #define MBUS_DBOX_B_CREDIT(x) ((x) << 8) 2798 #define MBUS_DBOX_A_CREDIT_MASK (0xF << 0) 2799 #define MBUS_DBOX_A_CREDIT(x) ((x) << 0) 2800 2801 #define MBUS_UBOX_CTL _MMIO(0x4503C) 2802 #define MBUS_BBOX_CTL_S1 _MMIO(0x45040) 2803 #define MBUS_BBOX_CTL_S2 _MMIO(0x45044) 2804 2805 /* Make render/texture TLB fetches lower priorty than associated data 2806 * fetches. This is not turned on by default 2807 */ 2808 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) 2809 2810 /* Isoch request wait on GTT enable (Display A/B/C streams). 2811 * Make isoch requests stall on the TLB update. May cause 2812 * display underruns (test mode only) 2813 */ 2814 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) 2815 2816 /* Block grant count for isoch requests when block count is 2817 * set to a finite value. 2818 */ 2819 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) 2820 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ 2821 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ 2822 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ 2823 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ 2824 2825 /* Enable render writes to complete in C2/C3/C4 power states. 2826 * If this isn't enabled, render writes are prevented in low 2827 * power states. That seems bad to me. 2828 */ 2829 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) 2830 2831 /* This acknowledges an async flip immediately instead 2832 * of waiting for 2TLB fetches. 2833 */ 2834 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) 2835 2836 /* Enables non-sequential data reads through arbiter 2837 */ 2838 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) 2839 2840 /* Disable FSB snooping of cacheable write cycles from binner/render 2841 * command stream 2842 */ 2843 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) 2844 2845 /* Arbiter time slice for non-isoch streams */ 2846 #define MI_ARB_TIME_SLICE_MASK (7 << 5) 2847 #define MI_ARB_TIME_SLICE_1 (0 << 5) 2848 #define MI_ARB_TIME_SLICE_2 (1 << 5) 2849 #define MI_ARB_TIME_SLICE_4 (2 << 5) 2850 #define MI_ARB_TIME_SLICE_6 (3 << 5) 2851 #define MI_ARB_TIME_SLICE_8 (4 << 5) 2852 #define MI_ARB_TIME_SLICE_10 (5 << 5) 2853 #define MI_ARB_TIME_SLICE_14 (6 << 5) 2854 #define MI_ARB_TIME_SLICE_16 (7 << 5) 2855 2856 /* Low priority grace period page size */ 2857 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ 2858 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) 2859 2860 /* Disable display A/B trickle feed */ 2861 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) 2862 2863 /* Set display plane priority */ 2864 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ 2865 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ 2866 2867 #define MI_STATE _MMIO(0x20e4) /* gen2 only */ 2868 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */ 2869 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */ 2870 2871 #define CACHE_MODE_0 _MMIO(0x2120) /* 915+ only */ 2872 #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1 << 8) 2873 #define CM0_IZ_OPT_DISABLE (1 << 6) 2874 #define CM0_ZR_OPT_DISABLE (1 << 5) 2875 #define CM0_STC_EVICT_DISABLE_LRA_SNB (1 << 5) 2876 #define CM0_DEPTH_EVICT_DISABLE (1 << 4) 2877 #define CM0_COLOR_EVICT_DISABLE (1 << 3) 2878 #define CM0_DEPTH_WRITE_DISABLE (1 << 1) 2879 #define CM0_RC_OP_FLUSH_DISABLE (1 << 0) 2880 #define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */ 2881 #define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008) 2882 #define GFX_FLSH_CNTL_EN (1 << 0) 2883 #define ECOSKPD _MMIO(0x21d0) 2884 #define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4) 2885 #define ECO_GATING_CX_ONLY (1 << 3) 2886 #define ECO_FLIP_DONE (1 << 0) 2887 2888 #define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */ 2889 #define RC_OP_FLUSH_ENABLE (1 << 0) 2890 #define HIZ_RAW_STALL_OPT_DISABLE (1 << 2) 2891 #define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */ 2892 #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1 << 6) 2893 #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1 << 6) 2894 #define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1 << 1) 2895 2896 #define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0) 2897 #define GEN6_BLITTER_LOCK_SHIFT 16 2898 #define GEN6_BLITTER_FBC_NOTIFY (1 << 3) 2899 2900 #define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050) 2901 #define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0) 2902 #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12) 2903 #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1 << 10) 2904 2905 #define GEN6_RCS_PWR_FSM _MMIO(0x22ac) 2906 #define GEN9_RCS_FE_FSM2 _MMIO(0x22a4) 2907 2908 #define GEN10_CACHE_MODE_SS _MMIO(0xe420) 2909 #define FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4) 2910 2911 /* Fuse readout registers for GT */ 2912 #define HSW_PAVP_FUSE1 _MMIO(0x911C) 2913 #define HSW_F1_EU_DIS_SHIFT 16 2914 #define HSW_F1_EU_DIS_MASK (0x3 << HSW_F1_EU_DIS_SHIFT) 2915 #define HSW_F1_EU_DIS_10EUS 0 2916 #define HSW_F1_EU_DIS_8EUS 1 2917 #define HSW_F1_EU_DIS_6EUS 2 2918 2919 #define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168) 2920 #define CHV_FGT_DISABLE_SS0 (1 << 10) 2921 #define CHV_FGT_DISABLE_SS1 (1 << 11) 2922 #define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16 2923 #define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT) 2924 #define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20 2925 #define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT) 2926 #define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24 2927 #define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT) 2928 #define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28 2929 #define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT) 2930 2931 #define GEN8_FUSE2 _MMIO(0x9120) 2932 #define GEN8_F2_SS_DIS_SHIFT 21 2933 #define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT) 2934 #define GEN8_F2_S_ENA_SHIFT 25 2935 #define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT) 2936 2937 #define GEN9_F2_SS_DIS_SHIFT 20 2938 #define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT) 2939 2940 #define GEN10_F2_S_ENA_SHIFT 22 2941 #define GEN10_F2_S_ENA_MASK (0x3f << GEN10_F2_S_ENA_SHIFT) 2942 #define GEN10_F2_SS_DIS_SHIFT 18 2943 #define GEN10_F2_SS_DIS_MASK (0xf << GEN10_F2_SS_DIS_SHIFT) 2944 2945 #define GEN10_MIRROR_FUSE3 _MMIO(0x9118) 2946 #define GEN10_L3BANK_PAIR_COUNT 4 2947 #define GEN10_L3BANK_MASK 0x0F 2948 2949 #define GEN8_EU_DISABLE0 _MMIO(0x9134) 2950 #define GEN8_EU_DIS0_S0_MASK 0xffffff 2951 #define GEN8_EU_DIS0_S1_SHIFT 24 2952 #define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT) 2953 2954 #define GEN8_EU_DISABLE1 _MMIO(0x9138) 2955 #define GEN8_EU_DIS1_S1_MASK 0xffff 2956 #define GEN8_EU_DIS1_S2_SHIFT 16 2957 #define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT) 2958 2959 #define GEN8_EU_DISABLE2 _MMIO(0x913c) 2960 #define GEN8_EU_DIS2_S2_MASK 0xff 2961 2962 #define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice) * 0x4) 2963 2964 #define GEN10_EU_DISABLE3 _MMIO(0x9140) 2965 #define GEN10_EU_DIS_SS_MASK 0xff 2966 2967 #define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140) 2968 #define GEN11_GT_VDBOX_DISABLE_MASK 0xff 2969 #define GEN11_GT_VEBOX_DISABLE_SHIFT 16 2970 #define GEN11_GT_VEBOX_DISABLE_MASK (0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT) 2971 2972 #define GEN11_EU_DISABLE _MMIO(0x9134) 2973 #define GEN11_EU_DIS_MASK 0xFF 2974 2975 #define GEN11_GT_SLICE_ENABLE _MMIO(0x9138) 2976 #define GEN11_GT_S_ENA_MASK 0xFF 2977 2978 #define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C) 2979 2980 #define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050) 2981 #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0) 2982 #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2) 2983 #define GEN6_BSD_SLEEP_INDICATOR (1 << 3) 2984 #define GEN6_BSD_GO_INDICATOR (1 << 4) 2985 2986 /* On modern GEN architectures interrupt control consists of two sets 2987 * of registers. The first set pertains to the ring generating the 2988 * interrupt. The second control is for the functional block generating the 2989 * interrupt. These are PM, GT, DE, etc. 2990 * 2991 * Luckily *knocks on wood* all the ring interrupt bits match up with the 2992 * GT interrupt bits, so we don't need to duplicate the defines. 2993 * 2994 * These defines should cover us well from SNB->HSW with minor exceptions 2995 * it can also work on ILK. 2996 */ 2997 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) 2998 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25) 2999 #define GT_BLT_USER_INTERRUPT (1 << 22) 3000 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15) 3001 #define GT_BSD_USER_INTERRUPT (1 << 12) 3002 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */ 3003 #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8) 3004 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */ 3005 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) 3006 #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3) 3007 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2) 3008 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1) 3009 #define GT_RENDER_USER_INTERRUPT (1 << 0) 3010 3011 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */ 3012 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */ 3013 3014 #define GT_PARITY_ERROR(dev_priv) \ 3015 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \ 3016 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0)) 3017 3018 /* These are all the "old" interrupts */ 3019 #define ILK_BSD_USER_INTERRUPT (1 << 5) 3020 3021 #define I915_PM_INTERRUPT (1 << 31) 3022 #define I915_ISP_INTERRUPT (1 << 22) 3023 #define I915_LPE_PIPE_B_INTERRUPT (1 << 21) 3024 #define I915_LPE_PIPE_A_INTERRUPT (1 << 20) 3025 #define I915_MIPIC_INTERRUPT (1 << 19) 3026 #define I915_MIPIA_INTERRUPT (1 << 18) 3027 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18) 3028 #define I915_DISPLAY_PORT_INTERRUPT (1 << 17) 3029 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16) 3030 #define I915_MASTER_ERROR_INTERRUPT (1 << 15) 3031 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14) 3032 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */ 3033 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13) 3034 #define I915_HWB_OOM_INTERRUPT (1 << 13) 3035 #define I915_LPE_PIPE_C_INTERRUPT (1 << 12) 3036 #define I915_SYNC_STATUS_INTERRUPT (1 << 12) 3037 #define I915_MISC_INTERRUPT (1 << 11) 3038 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11) 3039 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10) 3040 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10) 3041 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9) 3042 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9) 3043 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8) 3044 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8) 3045 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7) 3046 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6) 3047 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5) 3048 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4) 3049 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3) 3050 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2) 3051 #define I915_DEBUG_INTERRUPT (1 << 2) 3052 #define I915_WINVALID_INTERRUPT (1 << 1) 3053 #define I915_USER_INTERRUPT (1 << 1) 3054 #define I915_ASLE_INTERRUPT (1 << 0) 3055 #define I915_BSD_USER_INTERRUPT (1 << 25) 3056 3057 #define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000) 3058 #define I915_HDMI_LPE_AUDIO_SIZE 0x1000 3059 3060 /* DisplayPort Audio w/ LPE */ 3061 #define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38) 3062 #define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0) 3063 3064 #define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20) 3065 #define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30) 3066 #define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34) 3067 #define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \ 3068 _VLV_AUD_PORT_EN_B_DBG, \ 3069 _VLV_AUD_PORT_EN_C_DBG, \ 3070 _VLV_AUD_PORT_EN_D_DBG) 3071 #define VLV_AMP_MUTE (1 << 1) 3072 3073 #define GEN6_BSD_RNCID _MMIO(0x12198) 3074 3075 #define GEN7_FF_THREAD_MODE _MMIO(0x20a0) 3076 #define GEN7_FF_SCHED_MASK 0x0077070 3077 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19) 3078 #define GEN7_FF_TS_SCHED_HS1 (0x5 << 16) 3079 #define GEN7_FF_TS_SCHED_HS0 (0x3 << 16) 3080 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16) 3081 #define GEN7_FF_TS_SCHED_HW (0x0 << 16) /* Default */ 3082 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15) 3083 #define GEN7_FF_VS_SCHED_HS1 (0x5 << 12) 3084 #define GEN7_FF_VS_SCHED_HS0 (0x3 << 12) 3085 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */ 3086 #define GEN7_FF_VS_SCHED_HW (0x0 << 12) 3087 #define GEN7_FF_DS_SCHED_HS1 (0x5 << 4) 3088 #define GEN7_FF_DS_SCHED_HS0 (0x3 << 4) 3089 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */ 3090 #define GEN7_FF_DS_SCHED_HW (0x0 << 4) 3091 3092 /* 3093 * Framebuffer compression (915+ only) 3094 */ 3095 3096 #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */ 3097 #define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */ 3098 #define FBC_CONTROL _MMIO(0x3208) 3099 #define FBC_CTL_EN (1 << 31) 3100 #define FBC_CTL_PERIODIC (1 << 30) 3101 #define FBC_CTL_INTERVAL_SHIFT (16) 3102 #define FBC_CTL_UNCOMPRESSIBLE (1 << 14) 3103 #define FBC_CTL_C3_IDLE (1 << 13) 3104 #define FBC_CTL_STRIDE_SHIFT (5) 3105 #define FBC_CTL_FENCENO_SHIFT (0) 3106 #define FBC_COMMAND _MMIO(0x320c) 3107 #define FBC_CMD_COMPRESS (1 << 0) 3108 #define FBC_STATUS _MMIO(0x3210) 3109 #define FBC_STAT_COMPRESSING (1 << 31) 3110 #define FBC_STAT_COMPRESSED (1 << 30) 3111 #define FBC_STAT_MODIFIED (1 << 29) 3112 #define FBC_STAT_CURRENT_LINE_SHIFT (0) 3113 #define FBC_CONTROL2 _MMIO(0x3214) 3114 #define FBC_CTL_FENCE_DBL (0 << 4) 3115 #define FBC_CTL_IDLE_IMM (0 << 2) 3116 #define FBC_CTL_IDLE_FULL (1 << 2) 3117 #define FBC_CTL_IDLE_LINE (2 << 2) 3118 #define FBC_CTL_IDLE_DEBUG (3 << 2) 3119 #define FBC_CTL_CPU_FENCE (1 << 1) 3120 #define FBC_CTL_PLANE(plane) ((plane) << 0) 3121 #define FBC_FENCE_OFF _MMIO(0x3218) /* BSpec typo has 321Bh */ 3122 #define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) 3123 3124 #define FBC_LL_SIZE (1536) 3125 3126 #define FBC_LLC_READ_CTRL _MMIO(0x9044) 3127 #define FBC_LLC_FULLY_OPEN (1 << 30) 3128 3129 /* Framebuffer compression for GM45+ */ 3130 #define DPFC_CB_BASE _MMIO(0x3200) 3131 #define DPFC_CONTROL _MMIO(0x3208) 3132 #define DPFC_CTL_EN (1 << 31) 3133 #define DPFC_CTL_PLANE(plane) ((plane) << 30) 3134 #define IVB_DPFC_CTL_PLANE(plane) ((plane) << 29) 3135 #define DPFC_CTL_FENCE_EN (1 << 29) 3136 #define IVB_DPFC_CTL_FENCE_EN (1 << 28) 3137 #define DPFC_CTL_PERSISTENT_MODE (1 << 25) 3138 #define DPFC_SR_EN (1 << 10) 3139 #define DPFC_CTL_LIMIT_1X (0 << 6) 3140 #define DPFC_CTL_LIMIT_2X (1 << 6) 3141 #define DPFC_CTL_LIMIT_4X (2 << 6) 3142 #define DPFC_RECOMP_CTL _MMIO(0x320c) 3143 #define DPFC_RECOMP_STALL_EN (1 << 27) 3144 #define DPFC_RECOMP_STALL_WM_SHIFT (16) 3145 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) 3146 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) 3147 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) 3148 #define DPFC_STATUS _MMIO(0x3210) 3149 #define DPFC_INVAL_SEG_SHIFT (16) 3150 #define DPFC_INVAL_SEG_MASK (0x07ff0000) 3151 #define DPFC_COMP_SEG_SHIFT (0) 3152 #define DPFC_COMP_SEG_MASK (0x000007ff) 3153 #define DPFC_STATUS2 _MMIO(0x3214) 3154 #define DPFC_FENCE_YOFF _MMIO(0x3218) 3155 #define DPFC_CHICKEN _MMIO(0x3224) 3156 #define DPFC_HT_MODIFY (1 << 31) 3157 3158 /* Framebuffer compression for Ironlake */ 3159 #define ILK_DPFC_CB_BASE _MMIO(0x43200) 3160 #define ILK_DPFC_CONTROL _MMIO(0x43208) 3161 #define FBC_CTL_FALSE_COLOR (1 << 10) 3162 /* The bit 28-8 is reserved */ 3163 #define DPFC_RESERVED (0x1FFFFF00) 3164 #define ILK_DPFC_RECOMP_CTL _MMIO(0x4320c) 3165 #define ILK_DPFC_STATUS _MMIO(0x43210) 3166 #define ILK_DPFC_COMP_SEG_MASK 0x7ff 3167 #define IVB_FBC_STATUS2 _MMIO(0x43214) 3168 #define IVB_FBC_COMP_SEG_MASK 0x7ff 3169 #define BDW_FBC_COMP_SEG_MASK 0xfff 3170 #define ILK_DPFC_FENCE_YOFF _MMIO(0x43218) 3171 #define ILK_DPFC_CHICKEN _MMIO(0x43224) 3172 #define ILK_DPFC_DISABLE_DUMMY0 (1 << 8) 3173 #define ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL (1 << 14) 3174 #define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1 << 23) 3175 #define ILK_FBC_RT_BASE _MMIO(0x2128) 3176 #define ILK_FBC_RT_VALID (1 << 0) 3177 #define SNB_FBC_FRONT_BUFFER (1 << 1) 3178 3179 #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000) 3180 #define ILK_FBCQ_DIS (1 << 22) 3181 #define ILK_PABSTRETCH_DIS (1 << 21) 3182 3183 3184 /* 3185 * Framebuffer compression for Sandybridge 3186 * 3187 * The following two registers are of type GTTMMADR 3188 */ 3189 #define SNB_DPFC_CTL_SA _MMIO(0x100100) 3190 #define SNB_CPU_FENCE_ENABLE (1 << 29) 3191 #define DPFC_CPU_FENCE_OFFSET _MMIO(0x100104) 3192 3193 /* Framebuffer compression for Ivybridge */ 3194 #define IVB_FBC_RT_BASE _MMIO(0x7020) 3195 3196 #define IPS_CTL _MMIO(0x43408) 3197 #define IPS_ENABLE (1 << 31) 3198 3199 #define MSG_FBC_REND_STATE _MMIO(0x50380) 3200 #define FBC_REND_NUKE (1 << 2) 3201 #define FBC_REND_CACHE_CLEAN (1 << 1) 3202 3203 /* 3204 * GPIO regs 3205 */ 3206 #define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \ 3207 4 * (gpio)) 3208 3209 # define GPIO_CLOCK_DIR_MASK (1 << 0) 3210 # define GPIO_CLOCK_DIR_IN (0 << 1) 3211 # define GPIO_CLOCK_DIR_OUT (1 << 1) 3212 # define GPIO_CLOCK_VAL_MASK (1 << 2) 3213 # define GPIO_CLOCK_VAL_OUT (1 << 3) 3214 # define GPIO_CLOCK_VAL_IN (1 << 4) 3215 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 3216 # define GPIO_DATA_DIR_MASK (1 << 8) 3217 # define GPIO_DATA_DIR_IN (0 << 9) 3218 # define GPIO_DATA_DIR_OUT (1 << 9) 3219 # define GPIO_DATA_VAL_MASK (1 << 10) 3220 # define GPIO_DATA_VAL_OUT (1 << 11) 3221 # define GPIO_DATA_VAL_IN (1 << 12) 3222 # define GPIO_DATA_PULLUP_DISABLE (1 << 13) 3223 3224 #define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */ 3225 #define GMBUS_AKSV_SELECT (1 << 11) 3226 #define GMBUS_RATE_100KHZ (0 << 8) 3227 #define GMBUS_RATE_50KHZ (1 << 8) 3228 #define GMBUS_RATE_400KHZ (2 << 8) /* reserved on Pineview */ 3229 #define GMBUS_RATE_1MHZ (3 << 8) /* reserved on Pineview */ 3230 #define GMBUS_HOLD_EXT (1 << 7) /* 300ns hold time, rsvd on Pineview */ 3231 #define GMBUS_BYTE_CNT_OVERRIDE (1 << 6) 3232 #define GMBUS_PIN_DISABLED 0 3233 #define GMBUS_PIN_SSC 1 3234 #define GMBUS_PIN_VGADDC 2 3235 #define GMBUS_PIN_PANEL 3 3236 #define GMBUS_PIN_DPD_CHV 3 /* HDMID_CHV */ 3237 #define GMBUS_PIN_DPC 4 /* HDMIC */ 3238 #define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */ 3239 #define GMBUS_PIN_DPD 6 /* HDMID */ 3240 #define GMBUS_PIN_RESERVED 7 /* 7 reserved */ 3241 #define GMBUS_PIN_1_BXT 1 /* BXT+ (atom) and CNP+ (big core) */ 3242 #define GMBUS_PIN_2_BXT 2 3243 #define GMBUS_PIN_3_BXT 3 3244 #define GMBUS_PIN_4_CNP 4 3245 #define GMBUS_PIN_9_TC1_ICP 9 3246 #define GMBUS_PIN_10_TC2_ICP 10 3247 #define GMBUS_PIN_11_TC3_ICP 11 3248 #define GMBUS_PIN_12_TC4_ICP 12 3249 3250 #define GMBUS_NUM_PINS 13 /* including 0 */ 3251 #define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */ 3252 #define GMBUS_SW_CLR_INT (1 << 31) 3253 #define GMBUS_SW_RDY (1 << 30) 3254 #define GMBUS_ENT (1 << 29) /* enable timeout */ 3255 #define GMBUS_CYCLE_NONE (0 << 25) 3256 #define GMBUS_CYCLE_WAIT (1 << 25) 3257 #define GMBUS_CYCLE_INDEX (2 << 25) 3258 #define GMBUS_CYCLE_STOP (4 << 25) 3259 #define GMBUS_BYTE_COUNT_SHIFT 16 3260 #define GMBUS_BYTE_COUNT_MAX 256U 3261 #define GEN9_GMBUS_BYTE_COUNT_MAX 511U 3262 #define GMBUS_SLAVE_INDEX_SHIFT 8 3263 #define GMBUS_SLAVE_ADDR_SHIFT 1 3264 #define GMBUS_SLAVE_READ (1 << 0) 3265 #define GMBUS_SLAVE_WRITE (0 << 0) 3266 #define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */ 3267 #define GMBUS_INUSE (1 << 15) 3268 #define GMBUS_HW_WAIT_PHASE (1 << 14) 3269 #define GMBUS_STALL_TIMEOUT (1 << 13) 3270 #define GMBUS_INT (1 << 12) 3271 #define GMBUS_HW_RDY (1 << 11) 3272 #define GMBUS_SATOER (1 << 10) 3273 #define GMBUS_ACTIVE (1 << 9) 3274 #define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */ 3275 #define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */ 3276 #define GMBUS_SLAVE_TIMEOUT_EN (1 << 4) 3277 #define GMBUS_NAK_EN (1 << 3) 3278 #define GMBUS_IDLE_EN (1 << 2) 3279 #define GMBUS_HW_WAIT_EN (1 << 1) 3280 #define GMBUS_HW_RDY_EN (1 << 0) 3281 #define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */ 3282 #define GMBUS_2BYTE_INDEX_EN (1 << 31) 3283 3284 /* 3285 * Clock control & power management 3286 */ 3287 #define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014) 3288 #define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018) 3289 #define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030) 3290 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) 3291 3292 #define VGA0 _MMIO(0x6000) 3293 #define VGA1 _MMIO(0x6004) 3294 #define VGA_PD _MMIO(0x6010) 3295 #define VGA0_PD_P2_DIV_4 (1 << 7) 3296 #define VGA0_PD_P1_DIV_2 (1 << 5) 3297 #define VGA0_PD_P1_SHIFT 0 3298 #define VGA0_PD_P1_MASK (0x1f << 0) 3299 #define VGA1_PD_P2_DIV_4 (1 << 15) 3300 #define VGA1_PD_P1_DIV_2 (1 << 13) 3301 #define VGA1_PD_P1_SHIFT 8 3302 #define VGA1_PD_P1_MASK (0x1f << 8) 3303 #define DPLL_VCO_ENABLE (1 << 31) 3304 #define DPLL_SDVO_HIGH_SPEED (1 << 30) 3305 #define DPLL_DVO_2X_MODE (1 << 30) 3306 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) 3307 #define DPLL_SYNCLOCK_ENABLE (1 << 29) 3308 #define DPLL_REF_CLK_ENABLE_VLV (1 << 29) 3309 #define DPLL_VGA_MODE_DIS (1 << 28) 3310 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 3311 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 3312 #define DPLL_MODE_MASK (3 << 26) 3313 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 3314 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 3315 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 3316 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 3317 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 3318 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 3319 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ 3320 #define DPLL_LOCK_VLV (1 << 15) 3321 #define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14) 3322 #define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13) 3323 #define DPLL_SSC_REF_CLK_CHV (1 << 13) 3324 #define DPLL_PORTC_READY_MASK (0xf << 4) 3325 #define DPLL_PORTB_READY_MASK (0xf) 3326 3327 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 3328 3329 /* Additional CHV pll/phy registers */ 3330 #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240) 3331 #define DPLL_PORTD_READY_MASK (0xf) 3332 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100) 3333 #define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27)) 3334 #define PHY_LDO_DELAY_0NS 0x0 3335 #define PHY_LDO_DELAY_200NS 0x1 3336 #define PHY_LDO_DELAY_600NS 0x2 3337 #define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23)) 3338 #define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11)) 3339 #define PHY_CH_SU_PSR 0x1 3340 #define PHY_CH_DEEP_PSR 0x7 3341 #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2)) 3342 #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy)) 3343 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104) 3344 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30)) 3345 #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch)))) 3346 #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline)))) 3347 3348 /* 3349 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 3350 * this field (only one bit may be set). 3351 */ 3352 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 3353 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 3354 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 3355 /* i830, required in DVO non-gang */ 3356 #define PLL_P2_DIVIDE_BY_4 (1 << 23) 3357 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 3358 #define PLL_REF_INPUT_DREFCLK (0 << 13) 3359 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 3360 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 3361 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 3362 #define PLL_REF_INPUT_MASK (3 << 13) 3363 #define PLL_LOAD_PULSE_PHASE_SHIFT 9 3364 /* Ironlake */ 3365 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 3366 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) 3367 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9) 3368 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 3369 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff 3370 3371 /* 3372 * Parallel to Serial Load Pulse phase selection. 3373 * Selects the phase for the 10X DPLL clock for the PCIe 3374 * digital display port. The range is 4 to 13; 10 or more 3375 * is just a flip delay. The default is 6 3376 */ 3377 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 3378 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 3379 /* 3380 * SDVO multiplier for 945G/GM. Not used on 965. 3381 */ 3382 #define SDVO_MULTIPLIER_MASK 0x000000ff 3383 #define SDVO_MULTIPLIER_SHIFT_HIRES 4 3384 #define SDVO_MULTIPLIER_SHIFT_VGA 0 3385 3386 #define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c) 3387 #define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020) 3388 #define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c) 3389 #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) 3390 3391 /* 3392 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 3393 * 3394 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 3395 */ 3396 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 3397 #define DPLL_MD_UDI_DIVIDER_SHIFT 24 3398 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 3399 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 3400 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 3401 /* 3402 * SDVO/UDI pixel multiplier. 3403 * 3404 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 3405 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 3406 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 3407 * dummy bytes in the datastream at an increased clock rate, with both sides of 3408 * the link knowing how many bytes are fill. 3409 * 3410 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 3411 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 3412 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 3413 * through an SDVO command. 3414 * 3415 * This register field has values of multiplication factor minus 1, with 3416 * a maximum multiplier of 5 for SDVO. 3417 */ 3418 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 3419 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 3420 /* 3421 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 3422 * This best be set to the default value (3) or the CRT won't work. No, 3423 * I don't entirely understand what this does... 3424 */ 3425 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 3426 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 3427 3428 #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024) 3429 3430 #define _FPA0 0x6040 3431 #define _FPA1 0x6044 3432 #define _FPB0 0x6048 3433 #define _FPB1 0x604c 3434 #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0) 3435 #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1) 3436 #define FP_N_DIV_MASK 0x003f0000 3437 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 3438 #define FP_N_DIV_SHIFT 16 3439 #define FP_M1_DIV_MASK 0x00003f00 3440 #define FP_M1_DIV_SHIFT 8 3441 #define FP_M2_DIV_MASK 0x0000003f 3442 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff 3443 #define FP_M2_DIV_SHIFT 0 3444 #define DPLL_TEST _MMIO(0x606c) 3445 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 3446 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 3447 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 3448 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 3449 #define DPLLB_TEST_N_BYPASS (1 << 19) 3450 #define DPLLB_TEST_M_BYPASS (1 << 18) 3451 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 3452 #define DPLLA_TEST_N_BYPASS (1 << 3) 3453 #define DPLLA_TEST_M_BYPASS (1 << 2) 3454 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 3455 #define D_STATE _MMIO(0x6104) 3456 #define DSTATE_GFX_RESET_I830 (1 << 6) 3457 #define DSTATE_PLL_D3_OFF (1 << 3) 3458 #define DSTATE_GFX_CLOCK_GATING (1 << 1) 3459 #define DSTATE_DOT_CLOCK_GATING (1 << 0) 3460 #define DSPCLK_GATE_D _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x6200) 3461 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 3462 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 3463 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 3464 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ 3465 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ 3466 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ 3467 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ 3468 # define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */ 3469 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ 3470 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ 3471 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ 3472 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ 3473 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ 3474 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ 3475 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ 3476 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ 3477 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ 3478 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ 3479 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ 3480 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ 3481 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 3482 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) 3483 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) 3484 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) 3485 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ 3486 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ 3487 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ 3488 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) 3489 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) 3490 /* 3491 * This bit must be set on the 830 to prevent hangs when turning off the 3492 * overlay scaler. 3493 */ 3494 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 3495 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) 3496 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) 3497 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ 3498 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ 3499 3500 #define RENCLK_GATE_D1 _MMIO(0x6204) 3501 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ 3502 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ 3503 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) 3504 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) 3505 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) 3506 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) 3507 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) 3508 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) 3509 # define MAG_CLOCK_GATE_DISABLE (1 << 5) 3510 /* This bit must be unset on 855,865 */ 3511 # define MECI_CLOCK_GATE_DISABLE (1 << 4) 3512 # define DCMP_CLOCK_GATE_DISABLE (1 << 3) 3513 # define MEC_CLOCK_GATE_DISABLE (1 << 2) 3514 # define MECO_CLOCK_GATE_DISABLE (1 << 1) 3515 /* This bit must be set on 855,865. */ 3516 # define SV_CLOCK_GATE_DISABLE (1 << 0) 3517 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) 3518 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) 3519 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) 3520 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) 3521 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) 3522 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) 3523 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) 3524 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) 3525 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) 3526 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) 3527 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) 3528 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) 3529 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) 3530 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) 3531 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) 3532 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) 3533 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) 3534 3535 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) 3536 /* This bit must always be set on 965G/965GM */ 3537 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) 3538 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) 3539 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) 3540 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) 3541 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) 3542 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) 3543 /* This bit must always be set on 965G */ 3544 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) 3545 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) 3546 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) 3547 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) 3548 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) 3549 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) 3550 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) 3551 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) 3552 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) 3553 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) 3554 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) 3555 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) 3556 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) 3557 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) 3558 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) 3559 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) 3560 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) 3561 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) 3562 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) 3563 3564 #define RENCLK_GATE_D2 _MMIO(0x6208) 3565 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) 3566 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) 3567 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) 3568 3569 #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */ 3570 #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4) 3571 3572 #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */ 3573 #define DEUC _MMIO(0x6214) /* CRL only */ 3574 3575 #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500) 3576 #define FW_CSPWRDWNEN (1 << 15) 3577 3578 #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504) 3579 3580 #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508) 3581 #define CDCLK_FREQ_SHIFT 4 3582 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT) 3583 #define CZCLK_FREQ_MASK 0xf 3584 3585 #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C) 3586 #define PFI_CREDIT_63 (9 << 28) /* chv only */ 3587 #define PFI_CREDIT_31 (8 << 28) /* chv only */ 3588 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */ 3589 #define PFI_CREDIT_RESEND (1 << 27) 3590 #define VGA_FAST_MODE_DISABLE (1 << 14) 3591 3592 #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510) 3593 3594 /* 3595 * Palette regs 3596 */ 3597 #define _PALETTE_A 0xa000 3598 #define _PALETTE_B 0xa800 3599 #define _CHV_PALETTE_C 0xc000 3600 #define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \ 3601 _PICK((pipe), _PALETTE_A, \ 3602 _PALETTE_B, _CHV_PALETTE_C) + \ 3603 (i) * 4) 3604 3605 /* MCH MMIO space */ 3606 3607 /* 3608 * MCHBAR mirror. 3609 * 3610 * This mirrors the MCHBAR MMIO space whose location is determined by 3611 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in 3612 * every way. It is not accessible from the CP register read instructions. 3613 * 3614 * Starting from Haswell, you can't write registers using the MCHBAR mirror, 3615 * just read. 3616 */ 3617 #define MCHBAR_MIRROR_BASE 0x10000 3618 3619 #define MCHBAR_MIRROR_BASE_SNB 0x140000 3620 3621 #define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34) 3622 #define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48) 3623 #define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16) 3624 #define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4) 3625 #define G4X_STOLEN_RESERVED_ENABLE (1 << 0) 3626 3627 /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */ 3628 #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04) 3629 3630 /* 915-945 and GM965 MCH register controlling DRAM channel access */ 3631 #define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200) 3632 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) 3633 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) 3634 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) 3635 #define DCC_ADDRESSING_MODE_MASK (3 << 0) 3636 #define DCC_CHANNEL_XOR_DISABLE (1 << 10) 3637 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9) 3638 #define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204) 3639 #define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20) 3640 3641 /* Pineview MCH register contains DDR3 setting */ 3642 #define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8) 3643 #define CSHRDDR3CTL_DDR3 (1 << 2) 3644 3645 /* 965 MCH register controlling DRAM channel configuration */ 3646 #define C0DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x206) 3647 #define C1DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x606) 3648 3649 /* snb MCH registers for reading the DRAM channel configuration */ 3650 #define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004) 3651 #define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008) 3652 #define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C) 3653 #define MAD_DIMM_ECC_MASK (0x3 << 24) 3654 #define MAD_DIMM_ECC_OFF (0x0 << 24) 3655 #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24) 3656 #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24) 3657 #define MAD_DIMM_ECC_ON (0x3 << 24) 3658 #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22) 3659 #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21) 3660 #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */ 3661 #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */ 3662 #define MAD_DIMM_B_DUAL_RANK (0x1 << 18) 3663 #define MAD_DIMM_A_DUAL_RANK (0x1 << 17) 3664 #define MAD_DIMM_A_SELECT (0x1 << 16) 3665 /* DIMM sizes are in multiples of 256mb. */ 3666 #define MAD_DIMM_B_SIZE_SHIFT 8 3667 #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT) 3668 #define MAD_DIMM_A_SIZE_SHIFT 0 3669 #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) 3670 3671 /* snb MCH registers for priority tuning */ 3672 #define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10) 3673 #define MCH_SSKPD_WM0_MASK 0x3f 3674 #define MCH_SSKPD_WM0_VAL 0xc 3675 3676 #define MCH_SECP_NRG_STTS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x592c) 3677 3678 /* Clocking configuration register */ 3679 #define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00) 3680 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */ 3681 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */ 3682 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */ 3683 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */ 3684 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */ 3685 #define CLKCFG_FSB_1067_ALT (0 << 0) /* hrawclk 266 */ 3686 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */ 3687 /* 3688 * Note that on at least on ELK the below value is reported for both 3689 * 333 and 400 MHz BIOS FSB setting, but given that the gmch datasheet 3690 * lists only 200/266/333 MHz FSB as supported let's decode it as 333 MHz. 3691 */ 3692 #define CLKCFG_FSB_1333_ALT (4 << 0) /* hrawclk 333 */ 3693 #define CLKCFG_FSB_MASK (7 << 0) 3694 #define CLKCFG_MEM_533 (1 << 4) 3695 #define CLKCFG_MEM_667 (2 << 4) 3696 #define CLKCFG_MEM_800 (3 << 4) 3697 #define CLKCFG_MEM_MASK (7 << 4) 3698 3699 #define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38) 3700 #define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f) 3701 3702 #define TSC1 _MMIO(0x11001) 3703 #define TSE (1 << 0) 3704 #define TR1 _MMIO(0x11006) 3705 #define TSFS _MMIO(0x11020) 3706 #define TSFS_SLOPE_MASK 0x0000ff00 3707 #define TSFS_SLOPE_SHIFT 8 3708 #define TSFS_INTR_MASK 0x000000ff 3709 3710 #define CRSTANDVID _MMIO(0x11100) 3711 #define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ 3712 #define PXVFREQ_PX_MASK 0x7f000000 3713 #define PXVFREQ_PX_SHIFT 24 3714 #define VIDFREQ_BASE _MMIO(0x11110) 3715 #define VIDFREQ1 _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */ 3716 #define VIDFREQ2 _MMIO(0x11114) 3717 #define VIDFREQ3 _MMIO(0x11118) 3718 #define VIDFREQ4 _MMIO(0x1111c) 3719 #define VIDFREQ_P0_MASK 0x1f000000 3720 #define VIDFREQ_P0_SHIFT 24 3721 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000 3722 #define VIDFREQ_P0_CSCLK_SHIFT 20 3723 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000 3724 #define VIDFREQ_P0_CRCLK_SHIFT 16 3725 #define VIDFREQ_P1_MASK 0x00001f00 3726 #define VIDFREQ_P1_SHIFT 8 3727 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0 3728 #define VIDFREQ_P1_CSCLK_SHIFT 4 3729 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f 3730 #define INTTOEXT_BASE_ILK _MMIO(0x11300) 3731 #define INTTOEXT_BASE _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */ 3732 #define INTTOEXT_MAP3_SHIFT 24 3733 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) 3734 #define INTTOEXT_MAP2_SHIFT 16 3735 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) 3736 #define INTTOEXT_MAP1_SHIFT 8 3737 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) 3738 #define INTTOEXT_MAP0_SHIFT 0 3739 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) 3740 #define MEMSWCTL _MMIO(0x11170) /* Ironlake only */ 3741 #define MEMCTL_CMD_MASK 0xe000 3742 #define MEMCTL_CMD_SHIFT 13 3743 #define MEMCTL_CMD_RCLK_OFF 0 3744 #define MEMCTL_CMD_RCLK_ON 1 3745 #define MEMCTL_CMD_CHFREQ 2 3746 #define MEMCTL_CMD_CHVID 3 3747 #define MEMCTL_CMD_VMMOFF 4 3748 #define MEMCTL_CMD_VMMON 5 3749 #define MEMCTL_CMD_STS (1 << 12) /* write 1 triggers command, clears 3750 when command complete */ 3751 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ 3752 #define MEMCTL_FREQ_SHIFT 8 3753 #define MEMCTL_SFCAVM (1 << 7) 3754 #define MEMCTL_TGT_VID_MASK 0x007f 3755 #define MEMIHYST _MMIO(0x1117c) 3756 #define MEMINTREN _MMIO(0x11180) /* 16 bits */ 3757 #define MEMINT_RSEXIT_EN (1 << 8) 3758 #define MEMINT_CX_SUPR_EN (1 << 7) 3759 #define MEMINT_CONT_BUSY_EN (1 << 6) 3760 #define MEMINT_AVG_BUSY_EN (1 << 5) 3761 #define MEMINT_EVAL_CHG_EN (1 << 4) 3762 #define MEMINT_MON_IDLE_EN (1 << 3) 3763 #define MEMINT_UP_EVAL_EN (1 << 2) 3764 #define MEMINT_DOWN_EVAL_EN (1 << 1) 3765 #define MEMINT_SW_CMD_EN (1 << 0) 3766 #define MEMINTRSTR _MMIO(0x11182) /* 16 bits */ 3767 #define MEM_RSEXIT_MASK 0xc000 3768 #define MEM_RSEXIT_SHIFT 14 3769 #define MEM_CONT_BUSY_MASK 0x3000 3770 #define MEM_CONT_BUSY_SHIFT 12 3771 #define MEM_AVG_BUSY_MASK 0x0c00 3772 #define MEM_AVG_BUSY_SHIFT 10 3773 #define MEM_EVAL_CHG_MASK 0x0300 3774 #define MEM_EVAL_BUSY_SHIFT 8 3775 #define MEM_MON_IDLE_MASK 0x00c0 3776 #define MEM_MON_IDLE_SHIFT 6 3777 #define MEM_UP_EVAL_MASK 0x0030 3778 #define MEM_UP_EVAL_SHIFT 4 3779 #define MEM_DOWN_EVAL_MASK 0x000c 3780 #define MEM_DOWN_EVAL_SHIFT 2 3781 #define MEM_SW_CMD_MASK 0x0003 3782 #define MEM_INT_STEER_GFX 0 3783 #define MEM_INT_STEER_CMR 1 3784 #define MEM_INT_STEER_SMI 2 3785 #define MEM_INT_STEER_SCI 3 3786 #define MEMINTRSTS _MMIO(0x11184) 3787 #define MEMINT_RSEXIT (1 << 7) 3788 #define MEMINT_CONT_BUSY (1 << 6) 3789 #define MEMINT_AVG_BUSY (1 << 5) 3790 #define MEMINT_EVAL_CHG (1 << 4) 3791 #define MEMINT_MON_IDLE (1 << 3) 3792 #define MEMINT_UP_EVAL (1 << 2) 3793 #define MEMINT_DOWN_EVAL (1 << 1) 3794 #define MEMINT_SW_CMD (1 << 0) 3795 #define MEMMODECTL _MMIO(0x11190) 3796 #define MEMMODE_BOOST_EN (1 << 31) 3797 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ 3798 #define MEMMODE_BOOST_FREQ_SHIFT 24 3799 #define MEMMODE_IDLE_MODE_MASK 0x00030000 3800 #define MEMMODE_IDLE_MODE_SHIFT 16 3801 #define MEMMODE_IDLE_MODE_EVAL 0 3802 #define MEMMODE_IDLE_MODE_CONT 1 3803 #define MEMMODE_HWIDLE_EN (1 << 15) 3804 #define MEMMODE_SWMODE_EN (1 << 14) 3805 #define MEMMODE_RCLK_GATE (1 << 13) 3806 #define MEMMODE_HW_UPDATE (1 << 12) 3807 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ 3808 #define MEMMODE_FSTART_SHIFT 8 3809 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ 3810 #define MEMMODE_FMAX_SHIFT 4 3811 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ 3812 #define RCBMAXAVG _MMIO(0x1119c) 3813 #define MEMSWCTL2 _MMIO(0x1119e) /* Cantiga only */ 3814 #define SWMEMCMD_RENDER_OFF (0 << 13) 3815 #define SWMEMCMD_RENDER_ON (1 << 13) 3816 #define SWMEMCMD_SWFREQ (2 << 13) 3817 #define SWMEMCMD_TARVID (3 << 13) 3818 #define SWMEMCMD_VRM_OFF (4 << 13) 3819 #define SWMEMCMD_VRM_ON (5 << 13) 3820 #define CMDSTS (1 << 12) 3821 #define SFCAVM (1 << 11) 3822 #define SWFREQ_MASK 0x0380 /* P0-7 */ 3823 #define SWFREQ_SHIFT 7 3824 #define TARVID_MASK 0x001f 3825 #define MEMSTAT_CTG _MMIO(0x111a0) 3826 #define RCBMINAVG _MMIO(0x111a0) 3827 #define RCUPEI _MMIO(0x111b0) 3828 #define RCDNEI _MMIO(0x111b4) 3829 #define RSTDBYCTL _MMIO(0x111b8) 3830 #define RS1EN (1 << 31) 3831 #define RS2EN (1 << 30) 3832 #define RS3EN (1 << 29) 3833 #define D3RS3EN (1 << 28) /* Display D3 imlies RS3 */ 3834 #define SWPROMORSX (1 << 27) /* RSx promotion timers ignored */ 3835 #define RCWAKERW (1 << 26) /* Resetwarn from PCH causes wakeup */ 3836 #define DPRSLPVREN (1 << 25) /* Fast voltage ramp enable */ 3837 #define GFXTGHYST (1 << 24) /* Hysteresis to allow trunk gating */ 3838 #define RCX_SW_EXIT (1 << 23) /* Leave RSx and prevent re-entry */ 3839 #define RSX_STATUS_MASK (7 << 20) 3840 #define RSX_STATUS_ON (0 << 20) 3841 #define RSX_STATUS_RC1 (1 << 20) 3842 #define RSX_STATUS_RC1E (2 << 20) 3843 #define RSX_STATUS_RS1 (3 << 20) 3844 #define RSX_STATUS_RS2 (4 << 20) /* aka rc6 */ 3845 #define RSX_STATUS_RSVD (5 << 20) /* deep rc6 unsupported on ilk */ 3846 #define RSX_STATUS_RS3 (6 << 20) /* rs3 unsupported on ilk */ 3847 #define RSX_STATUS_RSVD2 (7 << 20) 3848 #define UWRCRSXE (1 << 19) /* wake counter limit prevents rsx */ 3849 #define RSCRP (1 << 18) /* rs requests control on rs1/2 reqs */ 3850 #define JRSC (1 << 17) /* rsx coupled to cpu c-state */ 3851 #define RS2INC0 (1 << 16) /* allow rs2 in cpu c0 */ 3852 #define RS1CONTSAV_MASK (3 << 14) 3853 #define RS1CONTSAV_NO_RS1 (0 << 14) /* rs1 doesn't save/restore context */ 3854 #define RS1CONTSAV_RSVD (1 << 14) 3855 #define RS1CONTSAV_SAVE_RS1 (2 << 14) /* rs1 saves context */ 3856 #define RS1CONTSAV_FULL_RS1 (3 << 14) /* rs1 saves and restores context */ 3857 #define NORMSLEXLAT_MASK (3 << 12) 3858 #define SLOW_RS123 (0 << 12) 3859 #define SLOW_RS23 (1 << 12) 3860 #define SLOW_RS3 (2 << 12) 3861 #define NORMAL_RS123 (3 << 12) 3862 #define RCMODE_TIMEOUT (1 << 11) /* 0 is eval interval method */ 3863 #define IMPROMOEN (1 << 10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ 3864 #define RCENTSYNC (1 << 9) /* rs coupled to cpu c-state (3/6/7) */ 3865 #define STATELOCK (1 << 7) /* locked to rs_cstate if 0 */ 3866 #define RS_CSTATE_MASK (3 << 4) 3867 #define RS_CSTATE_C367_RS1 (0 << 4) 3868 #define RS_CSTATE_C36_RS1_C7_RS2 (1 << 4) 3869 #define RS_CSTATE_RSVD (2 << 4) 3870 #define RS_CSTATE_C367_RS2 (3 << 4) 3871 #define REDSAVES (1 << 3) /* no context save if was idle during rs0 */ 3872 #define REDRESTORES (1 << 2) /* no restore if was idle during rs0 */ 3873 #define VIDCTL _MMIO(0x111c0) 3874 #define VIDSTS _MMIO(0x111c8) 3875 #define VIDSTART _MMIO(0x111cc) /* 8 bits */ 3876 #define MEMSTAT_ILK _MMIO(0x111f8) 3877 #define MEMSTAT_VID_MASK 0x7f00 3878 #define MEMSTAT_VID_SHIFT 8 3879 #define MEMSTAT_PSTATE_MASK 0x00f8 3880 #define MEMSTAT_PSTATE_SHIFT 3 3881 #define MEMSTAT_MON_ACTV (1 << 2) 3882 #define MEMSTAT_SRC_CTL_MASK 0x0003 3883 #define MEMSTAT_SRC_CTL_CORE 0 3884 #define MEMSTAT_SRC_CTL_TRB 1 3885 #define MEMSTAT_SRC_CTL_THM 2 3886 #define MEMSTAT_SRC_CTL_STDBY 3 3887 #define RCPREVBSYTUPAVG _MMIO(0x113b8) 3888 #define RCPREVBSYTDNAVG _MMIO(0x113bc) 3889 #define PMMISC _MMIO(0x11214) 3890 #define MCPPCE_EN (1 << 0) /* enable PM_MSG from PCH->MPC */ 3891 #define SDEW _MMIO(0x1124c) 3892 #define CSIEW0 _MMIO(0x11250) 3893 #define CSIEW1 _MMIO(0x11254) 3894 #define CSIEW2 _MMIO(0x11258) 3895 #define PEW(i) _MMIO(0x1125c + (i) * 4) /* 5 registers */ 3896 #define DEW(i) _MMIO(0x11270 + (i) * 4) /* 3 registers */ 3897 #define MCHAFE _MMIO(0x112c0) 3898 #define CSIEC _MMIO(0x112e0) 3899 #define DMIEC _MMIO(0x112e4) 3900 #define DDREC _MMIO(0x112e8) 3901 #define PEG0EC _MMIO(0x112ec) 3902 #define PEG1EC _MMIO(0x112f0) 3903 #define GFXEC _MMIO(0x112f4) 3904 #define RPPREVBSYTUPAVG _MMIO(0x113b8) 3905 #define RPPREVBSYTDNAVG _MMIO(0x113bc) 3906 #define ECR _MMIO(0x11600) 3907 #define ECR_GPFE (1 << 31) 3908 #define ECR_IMONE (1 << 30) 3909 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ 3910 #define OGW0 _MMIO(0x11608) 3911 #define OGW1 _MMIO(0x1160c) 3912 #define EG0 _MMIO(0x11610) 3913 #define EG1 _MMIO(0x11614) 3914 #define EG2 _MMIO(0x11618) 3915 #define EG3 _MMIO(0x1161c) 3916 #define EG4 _MMIO(0x11620) 3917 #define EG5 _MMIO(0x11624) 3918 #define EG6 _MMIO(0x11628) 3919 #define EG7 _MMIO(0x1162c) 3920 #define PXW(i) _MMIO(0x11664 + (i) * 4) /* 4 registers */ 3921 #define PXWL(i) _MMIO(0x11680 + (i) * 8) /* 8 registers */ 3922 #define LCFUSE02 _MMIO(0x116c0) 3923 #define LCFUSE_HIV_MASK 0x000000ff 3924 #define CSIPLL0 _MMIO(0x12c10) 3925 #define DDRMPLL1 _MMIO(0X12c20) 3926 #define PEG_BAND_GAP_DATA _MMIO(0x14d68) 3927 3928 #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c) 3929 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7 3930 3931 #define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948) 3932 #define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070) 3933 #define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994) 3934 #define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998) 3935 #define BXT_RP_STATE_CAP _MMIO(0x138170) 3936 3937 /* 3938 * Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS 3939 * 8300) freezing up around GPU hangs. Looks as if even 3940 * scheduling/timer interrupts start misbehaving if the RPS 3941 * EI/thresholds are "bad", leading to a very sluggish or even 3942 * frozen machine. 3943 */ 3944 #define INTERVAL_1_28_US(us) roundup(((us) * 100) >> 7, 25) 3945 #define INTERVAL_1_33_US(us) (((us) * 3) >> 2) 3946 #define INTERVAL_0_833_US(us) (((us) * 6) / 5) 3947 #define GT_INTERVAL_FROM_US(dev_priv, us) (INTEL_GEN(dev_priv) >= 9 ? \ 3948 (IS_GEN9_LP(dev_priv) ? \ 3949 INTERVAL_0_833_US(us) : \ 3950 INTERVAL_1_33_US(us)) : \ 3951 INTERVAL_1_28_US(us)) 3952 3953 #define INTERVAL_1_28_TO_US(interval) (((interval) << 7) / 100) 3954 #define INTERVAL_1_33_TO_US(interval) (((interval) << 2) / 3) 3955 #define INTERVAL_0_833_TO_US(interval) (((interval) * 5) / 6) 3956 #define GT_PM_INTERVAL_TO_US(dev_priv, interval) (INTEL_GEN(dev_priv) >= 9 ? \ 3957 (IS_GEN9_LP(dev_priv) ? \ 3958 INTERVAL_0_833_TO_US(interval) : \ 3959 INTERVAL_1_33_TO_US(interval)) : \ 3960 INTERVAL_1_28_TO_US(interval)) 3961 3962 /* 3963 * Logical Context regs 3964 */ 3965 #define CCID(base) _MMIO((base) + 0x180) 3966 #define CCID_EN BIT(0) 3967 #define CCID_EXTENDED_STATE_RESTORE BIT(2) 3968 #define CCID_EXTENDED_STATE_SAVE BIT(3) 3969 /* 3970 * Notes on SNB/IVB/VLV context size: 3971 * - Power context is saved elsewhere (LLC or stolen) 3972 * - Ring/execlist context is saved on SNB, not on IVB 3973 * - Extended context size already includes render context size 3974 * - We always need to follow the extended context size. 3975 * SNB BSpec has comments indicating that we should use the 3976 * render context size instead if execlists are disabled, but 3977 * based on empirical testing that's just nonsense. 3978 * - Pipelined/VF state is saved on SNB/IVB respectively 3979 * - GT1 size just indicates how much of render context 3980 * doesn't need saving on GT1 3981 */ 3982 #define CXT_SIZE _MMIO(0x21a0) 3983 #define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f) 3984 #define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f) 3985 #define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f) 3986 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f) 3987 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f) 3988 #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \ 3989 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \ 3990 GEN6_CXT_PIPELINE_SIZE(cxt_reg)) 3991 #define GEN7_CXT_SIZE _MMIO(0x21a8) 3992 #define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f) 3993 #define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7) 3994 #define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f) 3995 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f) 3996 #define GEN7_CXT_GT1_SIZE(ctx_reg) (((ctx_reg) >> 6) & 0x7) 3997 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) (((ctx_reg) >> 0) & 0x3f) 3998 #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \ 3999 GEN7_CXT_VFSTATE_SIZE(ctx_reg)) 4000 4001 enum { 4002 INTEL_ADVANCED_CONTEXT = 0, 4003 INTEL_LEGACY_32B_CONTEXT, 4004 INTEL_ADVANCED_AD_CONTEXT, 4005 INTEL_LEGACY_64B_CONTEXT 4006 }; 4007 4008 enum { 4009 FAULT_AND_HANG = 0, 4010 FAULT_AND_HALT, /* Debug only */ 4011 FAULT_AND_STREAM, 4012 FAULT_AND_CONTINUE /* Unsupported */ 4013 }; 4014 4015 #define GEN8_CTX_VALID (1 << 0) 4016 #define GEN8_CTX_FORCE_PD_RESTORE (1 << 1) 4017 #define GEN8_CTX_FORCE_RESTORE (1 << 2) 4018 #define GEN8_CTX_L3LLC_COHERENT (1 << 5) 4019 #define GEN8_CTX_PRIVILEGE (1 << 8) 4020 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3 4021 4022 #define GEN8_CTX_ID_SHIFT 32 4023 #define GEN8_CTX_ID_WIDTH 21 4024 #define GEN11_SW_CTX_ID_SHIFT 37 4025 #define GEN11_SW_CTX_ID_WIDTH 11 4026 #define GEN11_ENGINE_CLASS_SHIFT 61 4027 #define GEN11_ENGINE_CLASS_WIDTH 3 4028 #define GEN11_ENGINE_INSTANCE_SHIFT 48 4029 #define GEN11_ENGINE_INSTANCE_WIDTH 6 4030 4031 #define CHV_CLK_CTL1 _MMIO(0x101100) 4032 #define VLV_CLK_CTL2 _MMIO(0x101104) 4033 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28 4034 4035 /* 4036 * Overlay regs 4037 */ 4038 4039 #define OVADD _MMIO(0x30000) 4040 #define DOVSTA _MMIO(0x30008) 4041 #define OC_BUF (0x3 << 20) 4042 #define OGAMC5 _MMIO(0x30010) 4043 #define OGAMC4 _MMIO(0x30014) 4044 #define OGAMC3 _MMIO(0x30018) 4045 #define OGAMC2 _MMIO(0x3001c) 4046 #define OGAMC1 _MMIO(0x30020) 4047 #define OGAMC0 _MMIO(0x30024) 4048 4049 /* 4050 * GEN9 clock gating regs 4051 */ 4052 #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530) 4053 #define DARBF_GATING_DIS (1 << 27) 4054 #define PWM2_GATING_DIS (1 << 14) 4055 #define PWM1_GATING_DIS (1 << 13) 4056 4057 #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C) 4058 #define BXT_GMBUS_GATING_DIS (1 << 14) 4059 4060 #define _CLKGATE_DIS_PSL_A 0x46520 4061 #define _CLKGATE_DIS_PSL_B 0x46524 4062 #define _CLKGATE_DIS_PSL_C 0x46528 4063 #define DUPS1_GATING_DIS (1 << 15) 4064 #define DUPS2_GATING_DIS (1 << 19) 4065 #define DUPS3_GATING_DIS (1 << 23) 4066 #define DPF_GATING_DIS (1 << 10) 4067 #define DPF_RAM_GATING_DIS (1 << 9) 4068 #define DPFR_GATING_DIS (1 << 8) 4069 4070 #define CLKGATE_DIS_PSL(pipe) \ 4071 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B) 4072 4073 /* 4074 * GEN10 clock gating regs 4075 */ 4076 #define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4) 4077 #define SARBUNIT_CLKGATE_DIS (1 << 5) 4078 #define RCCUNIT_CLKGATE_DIS (1 << 7) 4079 #define MSCUNIT_CLKGATE_DIS (1 << 10) 4080 4081 #define SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524) 4082 #define GWUNIT_CLKGATE_DIS (1 << 16) 4083 4084 #define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434) 4085 #define VFUNIT_CLKGATE_DIS (1 << 20) 4086 4087 #define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560) 4088 #define CGPSF_CLKGATE_DIS (1 << 3) 4089 4090 /* 4091 * Display engine regs 4092 */ 4093 4094 /* Pipe A CRC regs */ 4095 #define _PIPE_CRC_CTL_A 0x60050 4096 #define PIPE_CRC_ENABLE (1 << 31) 4097 /* skl+ source selection */ 4098 #define PIPE_CRC_SOURCE_PLANE_1_SKL (0 << 28) 4099 #define PIPE_CRC_SOURCE_PLANE_2_SKL (2 << 28) 4100 #define PIPE_CRC_SOURCE_DMUX_SKL (4 << 28) 4101 #define PIPE_CRC_SOURCE_PLANE_3_SKL (6 << 28) 4102 #define PIPE_CRC_SOURCE_PLANE_4_SKL (7 << 28) 4103 #define PIPE_CRC_SOURCE_PLANE_5_SKL (5 << 28) 4104 #define PIPE_CRC_SOURCE_PLANE_6_SKL (3 << 28) 4105 #define PIPE_CRC_SOURCE_PLANE_7_SKL (1 << 28) 4106 /* ivb+ source selection */ 4107 #define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29) 4108 #define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29) 4109 #define PIPE_CRC_SOURCE_PF_IVB (2 << 29) 4110 /* ilk+ source selection */ 4111 #define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28) 4112 #define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28) 4113 #define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28) 4114 /* embedded DP port on the north display block, reserved on ivb */ 4115 #define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28) 4116 #define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */ 4117 /* vlv source selection */ 4118 #define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27) 4119 #define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27) 4120 #define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27) 4121 /* with DP port the pipe source is invalid */ 4122 #define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27) 4123 #define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27) 4124 #define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27) 4125 /* gen3+ source selection */ 4126 #define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28) 4127 #define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28) 4128 #define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28) 4129 /* with DP/TV port the pipe source is invalid */ 4130 #define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28) 4131 #define PIPE_CRC_SOURCE_TV_PRE (4 << 28) 4132 #define PIPE_CRC_SOURCE_TV_POST (5 << 28) 4133 #define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28) 4134 #define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28) 4135 /* gen2 doesn't have source selection bits */ 4136 #define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30) 4137 4138 #define _PIPE_CRC_RES_1_A_IVB 0x60064 4139 #define _PIPE_CRC_RES_2_A_IVB 0x60068 4140 #define _PIPE_CRC_RES_3_A_IVB 0x6006c 4141 #define _PIPE_CRC_RES_4_A_IVB 0x60070 4142 #define _PIPE_CRC_RES_5_A_IVB 0x60074 4143 4144 #define _PIPE_CRC_RES_RED_A 0x60060 4145 #define _PIPE_CRC_RES_GREEN_A 0x60064 4146 #define _PIPE_CRC_RES_BLUE_A 0x60068 4147 #define _PIPE_CRC_RES_RES1_A_I915 0x6006c 4148 #define _PIPE_CRC_RES_RES2_A_G4X 0x60080 4149 4150 /* Pipe B CRC regs */ 4151 #define _PIPE_CRC_RES_1_B_IVB 0x61064 4152 #define _PIPE_CRC_RES_2_B_IVB 0x61068 4153 #define _PIPE_CRC_RES_3_B_IVB 0x6106c 4154 #define _PIPE_CRC_RES_4_B_IVB 0x61070 4155 #define _PIPE_CRC_RES_5_B_IVB 0x61074 4156 4157 #define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A) 4158 #define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB) 4159 #define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB) 4160 #define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB) 4161 #define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB) 4162 #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB) 4163 4164 #define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A) 4165 #define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A) 4166 #define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A) 4167 #define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915) 4168 #define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X) 4169 4170 /* Pipe A timing regs */ 4171 #define _HTOTAL_A 0x60000 4172 #define _HBLANK_A 0x60004 4173 #define _HSYNC_A 0x60008 4174 #define _VTOTAL_A 0x6000c 4175 #define _VBLANK_A 0x60010 4176 #define _VSYNC_A 0x60014 4177 #define _PIPEASRC 0x6001c 4178 #define _BCLRPAT_A 0x60020 4179 #define _VSYNCSHIFT_A 0x60028 4180 #define _PIPE_MULT_A 0x6002c 4181 4182 /* Pipe B timing regs */ 4183 #define _HTOTAL_B 0x61000 4184 #define _HBLANK_B 0x61004 4185 #define _HSYNC_B 0x61008 4186 #define _VTOTAL_B 0x6100c 4187 #define _VBLANK_B 0x61010 4188 #define _VSYNC_B 0x61014 4189 #define _PIPEBSRC 0x6101c 4190 #define _BCLRPAT_B 0x61020 4191 #define _VSYNCSHIFT_B 0x61028 4192 #define _PIPE_MULT_B 0x6102c 4193 4194 /* DSI 0 timing regs */ 4195 #define _HTOTAL_DSI0 0x6b000 4196 #define _HSYNC_DSI0 0x6b008 4197 #define _VTOTAL_DSI0 0x6b00c 4198 #define _VSYNC_DSI0 0x6b014 4199 #define _VSYNCSHIFT_DSI0 0x6b028 4200 4201 /* DSI 1 timing regs */ 4202 #define _HTOTAL_DSI1 0x6b800 4203 #define _HSYNC_DSI1 0x6b808 4204 #define _VTOTAL_DSI1 0x6b80c 4205 #define _VSYNC_DSI1 0x6b814 4206 #define _VSYNCSHIFT_DSI1 0x6b828 4207 4208 #define TRANSCODER_A_OFFSET 0x60000 4209 #define TRANSCODER_B_OFFSET 0x61000 4210 #define TRANSCODER_C_OFFSET 0x62000 4211 #define CHV_TRANSCODER_C_OFFSET 0x63000 4212 #define TRANSCODER_EDP_OFFSET 0x6f000 4213 #define TRANSCODER_DSI0_OFFSET 0x6b000 4214 #define TRANSCODER_DSI1_OFFSET 0x6b800 4215 4216 #define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A) 4217 #define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A) 4218 #define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A) 4219 #define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A) 4220 #define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A) 4221 #define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A) 4222 #define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A) 4223 #define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A) 4224 #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC) 4225 #define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A) 4226 4227 /* HSW+ eDP PSR registers */ 4228 #define HSW_EDP_PSR_BASE 0x64800 4229 #define BDW_EDP_PSR_BASE 0x6f800 4230 #define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0) 4231 #define EDP_PSR_ENABLE (1 << 31) 4232 #define BDW_PSR_SINGLE_FRAME (1 << 30) 4233 #define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1 << 29) /* SW can't modify */ 4234 #define EDP_PSR_LINK_STANDBY (1 << 27) 4235 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3 << 25) 4236 #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0 << 25) 4237 #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1 << 25) 4238 #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2 << 25) 4239 #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3 << 25) 4240 #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20 4241 #define EDP_PSR_SKIP_AUX_EXIT (1 << 12) 4242 #define EDP_PSR_TP1_TP2_SEL (0 << 11) 4243 #define EDP_PSR_TP1_TP3_SEL (1 << 11) 4244 #define EDP_PSR_CRC_ENABLE (1 << 10) /* BDW+ */ 4245 #define EDP_PSR_TP2_TP3_TIME_500us (0 << 8) 4246 #define EDP_PSR_TP2_TP3_TIME_100us (1 << 8) 4247 #define EDP_PSR_TP2_TP3_TIME_2500us (2 << 8) 4248 #define EDP_PSR_TP2_TP3_TIME_0us (3 << 8) 4249 #define EDP_PSR_TP4_TIME_0US (3 << 6) /* ICL+ */ 4250 #define EDP_PSR_TP1_TIME_500us (0 << 4) 4251 #define EDP_PSR_TP1_TIME_100us (1 << 4) 4252 #define EDP_PSR_TP1_TIME_2500us (2 << 4) 4253 #define EDP_PSR_TP1_TIME_0us (3 << 4) 4254 #define EDP_PSR_IDLE_FRAME_SHIFT 0 4255 4256 /* Bspec claims those aren't shifted but stay at 0x64800 */ 4257 #define EDP_PSR_IMR _MMIO(0x64834) 4258 #define EDP_PSR_IIR _MMIO(0x64838) 4259 #define EDP_PSR_ERROR(shift) (1 << ((shift) + 2)) 4260 #define EDP_PSR_POST_EXIT(shift) (1 << ((shift) + 1)) 4261 #define EDP_PSR_PRE_ENTRY(shift) (1 << (shift)) 4262 #define EDP_PSR_TRANSCODER_C_SHIFT 24 4263 #define EDP_PSR_TRANSCODER_B_SHIFT 16 4264 #define EDP_PSR_TRANSCODER_A_SHIFT 8 4265 #define EDP_PSR_TRANSCODER_EDP_SHIFT 0 4266 4267 #define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10) 4268 #define EDP_PSR_AUX_CTL_TIME_OUT_MASK (3 << 26) 4269 #define EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK (0x1f << 20) 4270 #define EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK (0xf << 16) 4271 #define EDP_PSR_AUX_CTL_ERROR_INTERRUPT (1 << 11) 4272 #define EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK (0x7ff) 4273 4274 #define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */ 4275 4276 #define EDP_PSR_STATUS _MMIO(dev_priv->psr_mmio_base + 0x40) 4277 #define EDP_PSR_STATUS_STATE_MASK (7 << 29) 4278 #define EDP_PSR_STATUS_STATE_SHIFT 29 4279 #define EDP_PSR_STATUS_STATE_IDLE (0 << 29) 4280 #define EDP_PSR_STATUS_STATE_SRDONACK (1 << 29) 4281 #define EDP_PSR_STATUS_STATE_SRDENT (2 << 29) 4282 #define EDP_PSR_STATUS_STATE_BUFOFF (3 << 29) 4283 #define EDP_PSR_STATUS_STATE_BUFON (4 << 29) 4284 #define EDP_PSR_STATUS_STATE_AUXACK (5 << 29) 4285 #define EDP_PSR_STATUS_STATE_SRDOFFACK (6 << 29) 4286 #define EDP_PSR_STATUS_LINK_MASK (3 << 26) 4287 #define EDP_PSR_STATUS_LINK_FULL_OFF (0 << 26) 4288 #define EDP_PSR_STATUS_LINK_FULL_ON (1 << 26) 4289 #define EDP_PSR_STATUS_LINK_STANDBY (2 << 26) 4290 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20 4291 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f 4292 #define EDP_PSR_STATUS_COUNT_SHIFT 16 4293 #define EDP_PSR_STATUS_COUNT_MASK 0xf 4294 #define EDP_PSR_STATUS_AUX_ERROR (1 << 15) 4295 #define EDP_PSR_STATUS_AUX_SENDING (1 << 12) 4296 #define EDP_PSR_STATUS_SENDING_IDLE (1 << 9) 4297 #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1 << 8) 4298 #define EDP_PSR_STATUS_SENDING_TP1 (1 << 4) 4299 #define EDP_PSR_STATUS_IDLE_MASK 0xf 4300 4301 #define EDP_PSR_PERF_CNT _MMIO(dev_priv->psr_mmio_base + 0x44) 4302 #define EDP_PSR_PERF_CNT_MASK 0xffffff 4303 4304 #define EDP_PSR_DEBUG _MMIO(dev_priv->psr_mmio_base + 0x60) /* PSR_MASK on SKL+ */ 4305 #define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1 << 28) 4306 #define EDP_PSR_DEBUG_MASK_LPSP (1 << 27) 4307 #define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26) 4308 #define EDP_PSR_DEBUG_MASK_HPD (1 << 25) 4309 #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ */ 4310 #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */ 4311 4312 #define EDP_PSR2_CTL _MMIO(0x6f900) 4313 #define EDP_PSR2_ENABLE (1 << 31) 4314 #define EDP_SU_TRACK_ENABLE (1 << 30) 4315 #define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */ 4316 #define EDP_Y_COORDINATE_ENABLE (1 << 25) /* GLK and CNL+ */ 4317 #define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20) 4318 #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20) 4319 #define EDP_PSR2_TP2_TIME_500us (0 << 8) 4320 #define EDP_PSR2_TP2_TIME_100us (1 << 8) 4321 #define EDP_PSR2_TP2_TIME_2500us (2 << 8) 4322 #define EDP_PSR2_TP2_TIME_50us (3 << 8) 4323 #define EDP_PSR2_TP2_TIME_MASK (3 << 8) 4324 #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 4325 #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4) 4326 #define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4) 4327 #define EDP_PSR2_IDLE_FRAME_MASK 0xf 4328 #define EDP_PSR2_IDLE_FRAME_SHIFT 0 4329 4330 #define _PSR_EVENT_TRANS_A 0x60848 4331 #define _PSR_EVENT_TRANS_B 0x61848 4332 #define _PSR_EVENT_TRANS_C 0x62848 4333 #define _PSR_EVENT_TRANS_D 0x63848 4334 #define _PSR_EVENT_TRANS_EDP 0x6F848 4335 #define PSR_EVENT(trans) _MMIO_TRANS2(trans, _PSR_EVENT_TRANS_A) 4336 #define PSR_EVENT_PSR2_WD_TIMER_EXPIRE (1 << 17) 4337 #define PSR_EVENT_PSR2_DISABLED (1 << 16) 4338 #define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN (1 << 15) 4339 #define PSR_EVENT_SU_CRC_FIFO_UNDERRUN (1 << 14) 4340 #define PSR_EVENT_GRAPHICS_RESET (1 << 12) 4341 #define PSR_EVENT_PCH_INTERRUPT (1 << 11) 4342 #define PSR_EVENT_MEMORY_UP (1 << 10) 4343 #define PSR_EVENT_FRONT_BUFFER_MODIFY (1 << 9) 4344 #define PSR_EVENT_WD_TIMER_EXPIRE (1 << 8) 4345 #define PSR_EVENT_PIPE_REGISTERS_UPDATE (1 << 6) 4346 #define PSR_EVENT_REGISTER_UPDATE (1 << 5) /* Reserved in ICL+ */ 4347 #define PSR_EVENT_HDCP_ENABLE (1 << 4) 4348 #define PSR_EVENT_KVMR_SESSION_ENABLE (1 << 3) 4349 #define PSR_EVENT_VBI_ENABLE (1 << 2) 4350 #define PSR_EVENT_LPSP_MODE_EXIT (1 << 1) 4351 #define PSR_EVENT_PSR_DISABLE (1 << 0) 4352 4353 #define EDP_PSR2_STATUS _MMIO(0x6f940) 4354 #define EDP_PSR2_STATUS_STATE_MASK (0xf << 28) 4355 #define EDP_PSR2_STATUS_STATE_SHIFT 28 4356 4357 #define _PSR2_SU_STATUS_0 0x6F914 4358 #define _PSR2_SU_STATUS_1 0x6F918 4359 #define _PSR2_SU_STATUS_2 0x6F91C 4360 #define _PSR2_SU_STATUS(index) _MMIO(_PICK_EVEN((index), _PSR2_SU_STATUS_0, _PSR2_SU_STATUS_1)) 4361 #define PSR2_SU_STATUS(frame) (_PSR2_SU_STATUS((frame) / 3)) 4362 #define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10) 4363 #define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame)) 4364 #define PSR2_SU_STATUS_FRAMES 8 4365 4366 /* VGA port control */ 4367 #define ADPA _MMIO(0x61100) 4368 #define PCH_ADPA _MMIO(0xe1100) 4369 #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100) 4370 4371 #define ADPA_DAC_ENABLE (1 << 31) 4372 #define ADPA_DAC_DISABLE 0 4373 #define ADPA_PIPE_SEL_SHIFT 30 4374 #define ADPA_PIPE_SEL_MASK (1 << 30) 4375 #define ADPA_PIPE_SEL(pipe) ((pipe) << 30) 4376 #define ADPA_PIPE_SEL_SHIFT_CPT 29 4377 #define ADPA_PIPE_SEL_MASK_CPT (3 << 29) 4378 #define ADPA_PIPE_SEL_CPT(pipe) ((pipe) << 29) 4379 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ 4380 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0 << 24) 4381 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3 << 24) 4382 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24) 4383 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2 << 24) 4384 #define ADPA_CRT_HOTPLUG_ENABLE (1 << 23) 4385 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0 << 22) 4386 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1 << 22) 4387 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0 << 21) 4388 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1 << 21) 4389 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0 << 20) 4390 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1 << 20) 4391 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0 << 18) 4392 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1 << 18) 4393 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2 << 18) 4394 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3 << 18) 4395 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0 << 17) 4396 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1 << 17) 4397 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16) 4398 #define ADPA_USE_VGA_HVPOLARITY (1 << 15) 4399 #define ADPA_SETS_HVPOLARITY 0 4400 #define ADPA_VSYNC_CNTL_DISABLE (1 << 10) 4401 #define ADPA_VSYNC_CNTL_ENABLE 0 4402 #define ADPA_HSYNC_CNTL_DISABLE (1 << 11) 4403 #define ADPA_HSYNC_CNTL_ENABLE 0 4404 #define ADPA_VSYNC_ACTIVE_HIGH (1 << 4) 4405 #define ADPA_VSYNC_ACTIVE_LOW 0 4406 #define ADPA_HSYNC_ACTIVE_HIGH (1 << 3) 4407 #define ADPA_HSYNC_ACTIVE_LOW 0 4408 #define ADPA_DPMS_MASK (~(3 << 10)) 4409 #define ADPA_DPMS_ON (0 << 10) 4410 #define ADPA_DPMS_SUSPEND (1 << 10) 4411 #define ADPA_DPMS_STANDBY (2 << 10) 4412 #define ADPA_DPMS_OFF (3 << 10) 4413 4414 4415 /* Hotplug control (945+ only) */ 4416 #define PORT_HOTPLUG_EN _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110) 4417 #define PORTB_HOTPLUG_INT_EN (1 << 29) 4418 #define PORTC_HOTPLUG_INT_EN (1 << 28) 4419 #define PORTD_HOTPLUG_INT_EN (1 << 27) 4420 #define SDVOB_HOTPLUG_INT_EN (1 << 26) 4421 #define SDVOC_HOTPLUG_INT_EN (1 << 25) 4422 #define TV_HOTPLUG_INT_EN (1 << 18) 4423 #define CRT_HOTPLUG_INT_EN (1 << 9) 4424 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \ 4425 PORTC_HOTPLUG_INT_EN | \ 4426 PORTD_HOTPLUG_INT_EN | \ 4427 SDVOC_HOTPLUG_INT_EN | \ 4428 SDVOB_HOTPLUG_INT_EN | \ 4429 CRT_HOTPLUG_INT_EN) 4430 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 4431 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 4432 /* must use period 64 on GM45 according to docs */ 4433 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 4434 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 4435 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 4436 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 4437 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 4438 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 4439 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 4440 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 4441 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 4442 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 4443 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 4444 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 4445 4446 #define PORT_HOTPLUG_STAT _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114) 4447 /* 4448 * HDMI/DP bits are g4x+ 4449 * 4450 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused. 4451 * Please check the detailed lore in the commit message for for experimental 4452 * evidence. 4453 */ 4454 /* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */ 4455 #define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29) 4456 #define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28) 4457 #define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27) 4458 /* G4X/VLV/CHV DP/HDMI bits again match Bspec */ 4459 #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27) 4460 #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) 4461 #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29) 4462 #define PORTD_HOTPLUG_INT_STATUS (3 << 21) 4463 #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21) 4464 #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21) 4465 #define PORTC_HOTPLUG_INT_STATUS (3 << 19) 4466 #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19) 4467 #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19) 4468 #define PORTB_HOTPLUG_INT_STATUS (3 << 17) 4469 #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17) 4470 #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17) 4471 /* CRT/TV common between gen3+ */ 4472 #define CRT_HOTPLUG_INT_STATUS (1 << 11) 4473 #define TV_HOTPLUG_INT_STATUS (1 << 10) 4474 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 4475 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 4476 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 4477 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 4478 #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6) 4479 #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5) 4480 #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4) 4481 #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4) 4482 4483 /* SDVO is different across gen3/4 */ 4484 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) 4485 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) 4486 /* 4487 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, 4488 * since reality corrobates that they're the same as on gen3. But keep these 4489 * bits here (and the comment!) to help any other lost wanderers back onto the 4490 * right tracks. 4491 */ 4492 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) 4493 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) 4494 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) 4495 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) 4496 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \ 4497 SDVOB_HOTPLUG_INT_STATUS_G4X | \ 4498 SDVOC_HOTPLUG_INT_STATUS_G4X | \ 4499 PORTB_HOTPLUG_INT_STATUS | \ 4500 PORTC_HOTPLUG_INT_STATUS | \ 4501 PORTD_HOTPLUG_INT_STATUS) 4502 4503 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \ 4504 SDVOB_HOTPLUG_INT_STATUS_I915 | \ 4505 SDVOC_HOTPLUG_INT_STATUS_I915 | \ 4506 PORTB_HOTPLUG_INT_STATUS | \ 4507 PORTC_HOTPLUG_INT_STATUS | \ 4508 PORTD_HOTPLUG_INT_STATUS) 4509 4510 /* SDVO and HDMI port control. 4511 * The same register may be used for SDVO or HDMI */ 4512 #define _GEN3_SDVOB 0x61140 4513 #define _GEN3_SDVOC 0x61160 4514 #define GEN3_SDVOB _MMIO(_GEN3_SDVOB) 4515 #define GEN3_SDVOC _MMIO(_GEN3_SDVOC) 4516 #define GEN4_HDMIB GEN3_SDVOB 4517 #define GEN4_HDMIC GEN3_SDVOC 4518 #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140) 4519 #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160) 4520 #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C) 4521 #define PCH_SDVOB _MMIO(0xe1140) 4522 #define PCH_HDMIB PCH_SDVOB 4523 #define PCH_HDMIC _MMIO(0xe1150) 4524 #define PCH_HDMID _MMIO(0xe1160) 4525 4526 #define PORT_DFT_I9XX _MMIO(0x61150) 4527 #define DC_BALANCE_RESET (1 << 25) 4528 #define PORT_DFT2_G4X _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154) 4529 #define DC_BALANCE_RESET_VLV (1 << 31) 4530 #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0)) 4531 #define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */ 4532 #define PIPE_B_SCRAMBLE_RESET (1 << 1) 4533 #define PIPE_A_SCRAMBLE_RESET (1 << 0) 4534 4535 /* Gen 3 SDVO bits: */ 4536 #define SDVO_ENABLE (1 << 31) 4537 #define SDVO_PIPE_SEL_SHIFT 30 4538 #define SDVO_PIPE_SEL_MASK (1 << 30) 4539 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30) 4540 #define SDVO_STALL_SELECT (1 << 29) 4541 #define SDVO_INTERRUPT_ENABLE (1 << 26) 4542 /* 4543 * 915G/GM SDVO pixel multiplier. 4544 * Programmed value is multiplier - 1, up to 5x. 4545 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 4546 */ 4547 #define SDVO_PORT_MULTIPLY_MASK (7 << 23) 4548 #define SDVO_PORT_MULTIPLY_SHIFT 23 4549 #define SDVO_PHASE_SELECT_MASK (15 << 19) 4550 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 4551 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 4552 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */ 4553 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */ 4554 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */ 4555 #define SDVO_DETECTED (1 << 2) 4556 /* Bits to be preserved when writing */ 4557 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \ 4558 SDVO_INTERRUPT_ENABLE) 4559 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE) 4560 4561 /* Gen 4 SDVO/HDMI bits: */ 4562 #define SDVO_COLOR_FORMAT_8bpc (0 << 26) 4563 #define SDVO_COLOR_FORMAT_MASK (7 << 26) 4564 #define SDVO_ENCODING_SDVO (0 << 10) 4565 #define SDVO_ENCODING_HDMI (2 << 10) 4566 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */ 4567 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */ 4568 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */ 4569 #define HDMI_AUDIO_ENABLE (1 << 6) /* HDMI only */ 4570 /* VSYNC/HSYNC bits new with 965, default is to be set */ 4571 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) 4572 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) 4573 4574 /* Gen 5 (IBX) SDVO/HDMI bits: */ 4575 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */ 4576 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */ 4577 4578 /* Gen 6 (CPT) SDVO/HDMI bits: */ 4579 #define SDVO_PIPE_SEL_SHIFT_CPT 29 4580 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29) 4581 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29) 4582 4583 /* CHV SDVO/HDMI bits: */ 4584 #define SDVO_PIPE_SEL_SHIFT_CHV 24 4585 #define SDVO_PIPE_SEL_MASK_CHV (3 << 24) 4586 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24) 4587 4588 4589 /* DVO port control */ 4590 #define _DVOA 0x61120 4591 #define DVOA _MMIO(_DVOA) 4592 #define _DVOB 0x61140 4593 #define DVOB _MMIO(_DVOB) 4594 #define _DVOC 0x61160 4595 #define DVOC _MMIO(_DVOC) 4596 #define DVO_ENABLE (1 << 31) 4597 #define DVO_PIPE_SEL_SHIFT 30 4598 #define DVO_PIPE_SEL_MASK (1 << 30) 4599 #define DVO_PIPE_SEL(pipe) ((pipe) << 30) 4600 #define DVO_PIPE_STALL_UNUSED (0 << 28) 4601 #define DVO_PIPE_STALL (1 << 28) 4602 #define DVO_PIPE_STALL_TV (2 << 28) 4603 #define DVO_PIPE_STALL_MASK (3 << 28) 4604 #define DVO_USE_VGA_SYNC (1 << 15) 4605 #define DVO_DATA_ORDER_I740 (0 << 14) 4606 #define DVO_DATA_ORDER_FP (1 << 14) 4607 #define DVO_VSYNC_DISABLE (1 << 11) 4608 #define DVO_HSYNC_DISABLE (1 << 10) 4609 #define DVO_VSYNC_TRISTATE (1 << 9) 4610 #define DVO_HSYNC_TRISTATE (1 << 8) 4611 #define DVO_BORDER_ENABLE (1 << 7) 4612 #define DVO_DATA_ORDER_GBRG (1 << 6) 4613 #define DVO_DATA_ORDER_RGGB (0 << 6) 4614 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) 4615 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) 4616 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4) 4617 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3) 4618 #define DVO_BLANK_ACTIVE_HIGH (1 << 2) 4619 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ 4620 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ 4621 #define DVO_PRESERVE_MASK (0x7 << 24) 4622 #define DVOA_SRCDIM _MMIO(0x61124) 4623 #define DVOB_SRCDIM _MMIO(0x61144) 4624 #define DVOC_SRCDIM _MMIO(0x61164) 4625 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12 4626 #define DVO_SRCDIM_VERTICAL_SHIFT 0 4627 4628 /* LVDS port control */ 4629 #define LVDS _MMIO(0x61180) 4630 /* 4631 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 4632 * the DPLL semantics change when the LVDS is assigned to that pipe. 4633 */ 4634 #define LVDS_PORT_EN (1 << 31) 4635 /* Selects pipe B for LVDS data. Must be set on pre-965. */ 4636 #define LVDS_PIPE_SEL_SHIFT 30 4637 #define LVDS_PIPE_SEL_MASK (1 << 30) 4638 #define LVDS_PIPE_SEL(pipe) ((pipe) << 30) 4639 #define LVDS_PIPE_SEL_SHIFT_CPT 29 4640 #define LVDS_PIPE_SEL_MASK_CPT (3 << 29) 4641 #define LVDS_PIPE_SEL_CPT(pipe) ((pipe) << 29) 4642 /* LVDS dithering flag on 965/g4x platform */ 4643 #define LVDS_ENABLE_DITHER (1 << 25) 4644 /* LVDS sync polarity flags. Set to invert (i.e. negative) */ 4645 #define LVDS_VSYNC_POLARITY (1 << 21) 4646 #define LVDS_HSYNC_POLARITY (1 << 20) 4647 4648 /* Enable border for unscaled (or aspect-scaled) display */ 4649 #define LVDS_BORDER_ENABLE (1 << 15) 4650 /* 4651 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 4652 * pixel. 4653 */ 4654 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 4655 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 4656 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 4657 /* 4658 * Controls the A3 data pair, which contains the additional LSBs for 24 bit 4659 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 4660 * on. 4661 */ 4662 #define LVDS_A3_POWER_MASK (3 << 6) 4663 #define LVDS_A3_POWER_DOWN (0 << 6) 4664 #define LVDS_A3_POWER_UP (3 << 6) 4665 /* 4666 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 4667 * is set. 4668 */ 4669 #define LVDS_CLKB_POWER_MASK (3 << 4) 4670 #define LVDS_CLKB_POWER_DOWN (0 << 4) 4671 #define LVDS_CLKB_POWER_UP (3 << 4) 4672 /* 4673 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 4674 * setting for whether we are in dual-channel mode. The B3 pair will 4675 * additionally only be powered up when LVDS_A3_POWER_UP is set. 4676 */ 4677 #define LVDS_B0B3_POWER_MASK (3 << 2) 4678 #define LVDS_B0B3_POWER_DOWN (0 << 2) 4679 #define LVDS_B0B3_POWER_UP (3 << 2) 4680 4681 /* Video Data Island Packet control */ 4682 #define VIDEO_DIP_DATA _MMIO(0x61178) 4683 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC 4684 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte 4685 * of the infoframe structure specified by CEA-861. */ 4686 #define VIDEO_DIP_DATA_SIZE 32 4687 #define VIDEO_DIP_VSC_DATA_SIZE 36 4688 #define VIDEO_DIP_PPS_DATA_SIZE 132 4689 #define VIDEO_DIP_CTL _MMIO(0x61170) 4690 /* Pre HSW: */ 4691 #define VIDEO_DIP_ENABLE (1 << 31) 4692 #define VIDEO_DIP_PORT(port) ((port) << 29) 4693 #define VIDEO_DIP_PORT_MASK (3 << 29) 4694 #define VIDEO_DIP_ENABLE_GCP (1 << 25) /* ilk+ */ 4695 #define VIDEO_DIP_ENABLE_AVI (1 << 21) 4696 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) 4697 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) /* ilk+ */ 4698 #define VIDEO_DIP_ENABLE_SPD (8 << 21) 4699 #define VIDEO_DIP_SELECT_AVI (0 << 19) 4700 #define VIDEO_DIP_SELECT_VENDOR (1 << 19) 4701 #define VIDEO_DIP_SELECT_GAMUT (2 << 19) 4702 #define VIDEO_DIP_SELECT_SPD (3 << 19) 4703 #define VIDEO_DIP_SELECT_MASK (3 << 19) 4704 #define VIDEO_DIP_FREQ_ONCE (0 << 16) 4705 #define VIDEO_DIP_FREQ_VSYNC (1 << 16) 4706 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) 4707 #define VIDEO_DIP_FREQ_MASK (3 << 16) 4708 /* HSW and later: */ 4709 #define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28) 4710 #define PSR_VSC_BIT_7_SET (1 << 27) 4711 #define VSC_SELECT_MASK (0x3 << 25) 4712 #define VSC_SELECT_SHIFT 25 4713 #define VSC_DIP_HW_HEA_DATA (0 << 25) 4714 #define VSC_DIP_HW_HEA_SW_DATA (1 << 25) 4715 #define VSC_DIP_HW_DATA_SW_HEA (2 << 25) 4716 #define VSC_DIP_SW_HEA_DATA (3 << 25) 4717 #define VDIP_ENABLE_PPS (1 << 24) 4718 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) 4719 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) 4720 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) 4721 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) 4722 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) 4723 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) 4724 4725 /* Panel power sequencing */ 4726 #define PPS_BASE 0x61200 4727 #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE) 4728 #define PCH_PPS_BASE 0xC7200 4729 4730 #define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \ 4731 PPS_BASE + (reg) + \ 4732 (pps_idx) * 0x100) 4733 4734 #define _PP_STATUS 0x61200 4735 #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS) 4736 #define PP_ON REG_BIT(31) 4737 4738 #define _PP_CONTROL_1 0xc7204 4739 #define _PP_CONTROL_2 0xc7304 4740 #define ICP_PP_CONTROL(x) _MMIO(((x) == 1) ? _PP_CONTROL_1 : \ 4741 _PP_CONTROL_2) 4742 #define POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4) 4743 #define VDD_OVERRIDE_FORCE REG_BIT(3) 4744 #define BACKLIGHT_ENABLE REG_BIT(2) 4745 #define PWR_DOWN_ON_RESET REG_BIT(1) 4746 #define PWR_STATE_TARGET REG_BIT(0) 4747 /* 4748 * Indicates that all dependencies of the panel are on: 4749 * 4750 * - PLL enabled 4751 * - pipe enabled 4752 * - LVDS/DVOB/DVOC on 4753 */ 4754 #define PP_READY REG_BIT(30) 4755 #define PP_SEQUENCE_MASK REG_GENMASK(29, 28) 4756 #define PP_SEQUENCE_NONE REG_FIELD_PREP(PP_SEQUENCE_MASK, 0) 4757 #define PP_SEQUENCE_POWER_UP REG_FIELD_PREP(PP_SEQUENCE_MASK, 1) 4758 #define PP_SEQUENCE_POWER_DOWN REG_FIELD_PREP(PP_SEQUENCE_MASK, 2) 4759 #define PP_CYCLE_DELAY_ACTIVE REG_BIT(27) 4760 #define PP_SEQUENCE_STATE_MASK REG_GENMASK(3, 0) 4761 #define PP_SEQUENCE_STATE_OFF_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0) 4762 #define PP_SEQUENCE_STATE_OFF_S0_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1) 4763 #define PP_SEQUENCE_STATE_OFF_S0_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2) 4764 #define PP_SEQUENCE_STATE_OFF_S0_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3) 4765 #define PP_SEQUENCE_STATE_ON_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8) 4766 #define PP_SEQUENCE_STATE_ON_S1_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9) 4767 #define PP_SEQUENCE_STATE_ON_S1_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa) 4768 #define PP_SEQUENCE_STATE_ON_S1_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb) 4769 #define PP_SEQUENCE_STATE_RESET REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf) 4770 4771 #define _PP_CONTROL 0x61204 4772 #define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL) 4773 #define PANEL_UNLOCK_MASK REG_GENMASK(31, 16) 4774 #define PANEL_UNLOCK_REGS REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd) 4775 #define BXT_POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4) 4776 #define EDP_FORCE_VDD REG_BIT(3) 4777 #define EDP_BLC_ENABLE REG_BIT(2) 4778 #define PANEL_POWER_RESET REG_BIT(1) 4779 #define PANEL_POWER_ON REG_BIT(0) 4780 4781 #define _PP_ON_DELAYS 0x61208 4782 #define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS) 4783 #define PANEL_PORT_SELECT_MASK REG_GENMASK(31, 30) 4784 #define PANEL_PORT_SELECT_LVDS REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0) 4785 #define PANEL_PORT_SELECT_DPA REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1) 4786 #define PANEL_PORT_SELECT_DPC REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 2) 4787 #define PANEL_PORT_SELECT_DPD REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 3) 4788 #define PANEL_PORT_SELECT_VLV(port) REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, port) 4789 #define PANEL_POWER_UP_DELAY_MASK REG_GENMASK(28, 16) 4790 #define PANEL_LIGHT_ON_DELAY_MASK REG_GENMASK(12, 0) 4791 4792 #define _PP_OFF_DELAYS 0x6120C 4793 #define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS) 4794 #define PANEL_POWER_DOWN_DELAY_MASK REG_GENMASK(28, 16) 4795 #define PANEL_LIGHT_OFF_DELAY_MASK REG_GENMASK(12, 0) 4796 4797 #define _PP_DIVISOR 0x61210 4798 #define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR) 4799 #define PP_REFERENCE_DIVIDER_MASK REG_GENMASK(31, 8) 4800 #define PANEL_POWER_CYCLE_DELAY_MASK REG_GENMASK(4, 0) 4801 4802 /* Panel fitting */ 4803 #define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230) 4804 #define PFIT_ENABLE (1 << 31) 4805 #define PFIT_PIPE_MASK (3 << 29) 4806 #define PFIT_PIPE_SHIFT 29 4807 #define VERT_INTERP_DISABLE (0 << 10) 4808 #define VERT_INTERP_BILINEAR (1 << 10) 4809 #define VERT_INTERP_MASK (3 << 10) 4810 #define VERT_AUTO_SCALE (1 << 9) 4811 #define HORIZ_INTERP_DISABLE (0 << 6) 4812 #define HORIZ_INTERP_BILINEAR (1 << 6) 4813 #define HORIZ_INTERP_MASK (3 << 6) 4814 #define HORIZ_AUTO_SCALE (1 << 5) 4815 #define PANEL_8TO6_DITHER_ENABLE (1 << 3) 4816 #define PFIT_FILTER_FUZZY (0 << 24) 4817 #define PFIT_SCALING_AUTO (0 << 26) 4818 #define PFIT_SCALING_PROGRAMMED (1 << 26) 4819 #define PFIT_SCALING_PILLAR (2 << 26) 4820 #define PFIT_SCALING_LETTER (3 << 26) 4821 #define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234) 4822 /* Pre-965 */ 4823 #define PFIT_VERT_SCALE_SHIFT 20 4824 #define PFIT_VERT_SCALE_MASK 0xfff00000 4825 #define PFIT_HORIZ_SCALE_SHIFT 4 4826 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 4827 /* 965+ */ 4828 #define PFIT_VERT_SCALE_SHIFT_965 16 4829 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000 4830 #define PFIT_HORIZ_SCALE_SHIFT_965 0 4831 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff 4832 4833 #define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238) 4834 4835 #define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250) 4836 #define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350) 4837 #define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \ 4838 _VLV_BLC_PWM_CTL2_B) 4839 4840 #define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61254) 4841 #define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61354) 4842 #define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \ 4843 _VLV_BLC_PWM_CTL_B) 4844 4845 #define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260) 4846 #define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360) 4847 #define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \ 4848 _VLV_BLC_HIST_CTL_B) 4849 4850 /* Backlight control */ 4851 #define BLC_PWM_CTL2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+ only */ 4852 #define BLM_PWM_ENABLE (1 << 31) 4853 #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ 4854 #define BLM_PIPE_SELECT (1 << 29) 4855 #define BLM_PIPE_SELECT_IVB (3 << 29) 4856 #define BLM_PIPE_A (0 << 29) 4857 #define BLM_PIPE_B (1 << 29) 4858 #define BLM_PIPE_C (2 << 29) /* ivb + */ 4859 #define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */ 4860 #define BLM_TRANSCODER_B BLM_PIPE_B 4861 #define BLM_TRANSCODER_C BLM_PIPE_C 4862 #define BLM_TRANSCODER_EDP (3 << 29) 4863 #define BLM_PIPE(pipe) ((pipe) << 29) 4864 #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */ 4865 #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26) 4866 #define BLM_PHASE_IN_ENABLE (1 << 25) 4867 #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24) 4868 #define BLM_PHASE_IN_TIME_BASE_SHIFT (16) 4869 #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16) 4870 #define BLM_PHASE_IN_COUNT_SHIFT (8) 4871 #define BLM_PHASE_IN_COUNT_MASK (0xff << 8) 4872 #define BLM_PHASE_IN_INCR_SHIFT (0) 4873 #define BLM_PHASE_IN_INCR_MASK (0xff << 0) 4874 #define BLC_PWM_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254) 4875 /* 4876 * This is the most significant 15 bits of the number of backlight cycles in a 4877 * complete cycle of the modulated backlight control. 4878 * 4879 * The actual value is this field multiplied by two. 4880 */ 4881 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 4882 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) 4883 #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */ 4884 /* 4885 * This is the number of cycles out of the backlight modulation cycle for which 4886 * the backlight is on. 4887 * 4888 * This field must be no greater than the number of cycles in the complete 4889 * backlight modulation cycle. 4890 */ 4891 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) 4892 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) 4893 #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) 4894 #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ 4895 4896 #define BLC_HIST_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260) 4897 #define BLM_HISTOGRAM_ENABLE (1 << 31) 4898 4899 /* New registers for PCH-split platforms. Safe where new bits show up, the 4900 * register layout machtes with gen4 BLC_PWM_CTL[12]. */ 4901 #define BLC_PWM_CPU_CTL2 _MMIO(0x48250) 4902 #define BLC_PWM_CPU_CTL _MMIO(0x48254) 4903 4904 #define HSW_BLC_PWM2_CTL _MMIO(0x48350) 4905 4906 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is 4907 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */ 4908 #define BLC_PWM_PCH_CTL1 _MMIO(0xc8250) 4909 #define BLM_PCH_PWM_ENABLE (1 << 31) 4910 #define BLM_PCH_OVERRIDE_ENABLE (1 << 30) 4911 #define BLM_PCH_POLARITY (1 << 29) 4912 #define BLC_PWM_PCH_CTL2 _MMIO(0xc8254) 4913 4914 #define UTIL_PIN_CTL _MMIO(0x48400) 4915 #define UTIL_PIN_ENABLE (1 << 31) 4916 4917 #define UTIL_PIN_PIPE(x) ((x) << 29) 4918 #define UTIL_PIN_PIPE_MASK (3 << 29) 4919 #define UTIL_PIN_MODE_PWM (1 << 24) 4920 #define UTIL_PIN_MODE_MASK (0xf << 24) 4921 #define UTIL_PIN_POLARITY (1 << 22) 4922 4923 /* BXT backlight register definition. */ 4924 #define _BXT_BLC_PWM_CTL1 0xC8250 4925 #define BXT_BLC_PWM_ENABLE (1 << 31) 4926 #define BXT_BLC_PWM_POLARITY (1 << 29) 4927 #define _BXT_BLC_PWM_FREQ1 0xC8254 4928 #define _BXT_BLC_PWM_DUTY1 0xC8258 4929 4930 #define _BXT_BLC_PWM_CTL2 0xC8350 4931 #define _BXT_BLC_PWM_FREQ2 0xC8354 4932 #define _BXT_BLC_PWM_DUTY2 0xC8358 4933 4934 #define BXT_BLC_PWM_CTL(controller) _MMIO_PIPE(controller, \ 4935 _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2) 4936 #define BXT_BLC_PWM_FREQ(controller) _MMIO_PIPE(controller, \ 4937 _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2) 4938 #define BXT_BLC_PWM_DUTY(controller) _MMIO_PIPE(controller, \ 4939 _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2) 4940 4941 #define PCH_GTC_CTL _MMIO(0xe7000) 4942 #define PCH_GTC_ENABLE (1 << 31) 4943 4944 /* TV port control */ 4945 #define TV_CTL _MMIO(0x68000) 4946 /* Enables the TV encoder */ 4947 # define TV_ENC_ENABLE (1 << 31) 4948 /* Sources the TV encoder input from pipe B instead of A. */ 4949 # define TV_ENC_PIPE_SEL_SHIFT 30 4950 # define TV_ENC_PIPE_SEL_MASK (1 << 30) 4951 # define TV_ENC_PIPE_SEL(pipe) ((pipe) << 30) 4952 /* Outputs composite video (DAC A only) */ 4953 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) 4954 /* Outputs SVideo video (DAC B/C) */ 4955 # define TV_ENC_OUTPUT_SVIDEO (1 << 28) 4956 /* Outputs Component video (DAC A/B/C) */ 4957 # define TV_ENC_OUTPUT_COMPONENT (2 << 28) 4958 /* Outputs Composite and SVideo (DAC A/B/C) */ 4959 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) 4960 # define TV_TRILEVEL_SYNC (1 << 21) 4961 /* Enables slow sync generation (945GM only) */ 4962 # define TV_SLOW_SYNC (1 << 20) 4963 /* Selects 4x oversampling for 480i and 576p */ 4964 # define TV_OVERSAMPLE_4X (0 << 18) 4965 /* Selects 2x oversampling for 720p and 1080i */ 4966 # define TV_OVERSAMPLE_2X (1 << 18) 4967 /* Selects no oversampling for 1080p */ 4968 # define TV_OVERSAMPLE_NONE (2 << 18) 4969 /* Selects 8x oversampling */ 4970 # define TV_OVERSAMPLE_8X (3 << 18) 4971 # define TV_OVERSAMPLE_MASK (3 << 18) 4972 /* Selects progressive mode rather than interlaced */ 4973 # define TV_PROGRESSIVE (1 << 17) 4974 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */ 4975 # define TV_PAL_BURST (1 << 16) 4976 /* Field for setting delay of Y compared to C */ 4977 # define TV_YC_SKEW_MASK (7 << 12) 4978 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */ 4979 # define TV_ENC_SDP_FIX (1 << 11) 4980 /* 4981 * Enables a fix for the 915GM only. 4982 * 4983 * Not sure what it does. 4984 */ 4985 # define TV_ENC_C0_FIX (1 << 10) 4986 /* Bits that must be preserved by software */ 4987 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) 4988 # define TV_FUSE_STATE_MASK (3 << 4) 4989 /* Read-only state that reports all features enabled */ 4990 # define TV_FUSE_STATE_ENABLED (0 << 4) 4991 /* Read-only state that reports that Macrovision is disabled in hardware*/ 4992 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) 4993 /* Read-only state that reports that TV-out is disabled in hardware. */ 4994 # define TV_FUSE_STATE_DISABLED (2 << 4) 4995 /* Normal operation */ 4996 # define TV_TEST_MODE_NORMAL (0 << 0) 4997 /* Encoder test pattern 1 - combo pattern */ 4998 # define TV_TEST_MODE_PATTERN_1 (1 << 0) 4999 /* Encoder test pattern 2 - full screen vertical 75% color bars */ 5000 # define TV_TEST_MODE_PATTERN_2 (2 << 0) 5001 /* Encoder test pattern 3 - full screen horizontal 75% color bars */ 5002 # define TV_TEST_MODE_PATTERN_3 (3 << 0) 5003 /* Encoder test pattern 4 - random noise */ 5004 # define TV_TEST_MODE_PATTERN_4 (4 << 0) 5005 /* Encoder test pattern 5 - linear color ramps */ 5006 # define TV_TEST_MODE_PATTERN_5 (5 << 0) 5007 /* 5008 * This test mode forces the DACs to 50% of full output. 5009 * 5010 * This is used for load detection in combination with TVDAC_SENSE_MASK 5011 */ 5012 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) 5013 # define TV_TEST_MODE_MASK (7 << 0) 5014 5015 #define TV_DAC _MMIO(0x68004) 5016 # define TV_DAC_SAVE 0x00ffff00 5017 /* 5018 * Reports that DAC state change logic has reported change (RO). 5019 * 5020 * This gets cleared when TV_DAC_STATE_EN is cleared 5021 */ 5022 # define TVDAC_STATE_CHG (1 << 31) 5023 # define TVDAC_SENSE_MASK (7 << 28) 5024 /* Reports that DAC A voltage is above the detect threshold */ 5025 # define TVDAC_A_SENSE (1 << 30) 5026 /* Reports that DAC B voltage is above the detect threshold */ 5027 # define TVDAC_B_SENSE (1 << 29) 5028 /* Reports that DAC C voltage is above the detect threshold */ 5029 # define TVDAC_C_SENSE (1 << 28) 5030 /* 5031 * Enables DAC state detection logic, for load-based TV detection. 5032 * 5033 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set 5034 * to off, for load detection to work. 5035 */ 5036 # define TVDAC_STATE_CHG_EN (1 << 27) 5037 /* Sets the DAC A sense value to high */ 5038 # define TVDAC_A_SENSE_CTL (1 << 26) 5039 /* Sets the DAC B sense value to high */ 5040 # define TVDAC_B_SENSE_CTL (1 << 25) 5041 /* Sets the DAC C sense value to high */ 5042 # define TVDAC_C_SENSE_CTL (1 << 24) 5043 /* Overrides the ENC_ENABLE and DAC voltage levels */ 5044 # define DAC_CTL_OVERRIDE (1 << 7) 5045 /* Sets the slew rate. Must be preserved in software */ 5046 # define ENC_TVDAC_SLEW_FAST (1 << 6) 5047 # define DAC_A_1_3_V (0 << 4) 5048 # define DAC_A_1_1_V (1 << 4) 5049 # define DAC_A_0_7_V (2 << 4) 5050 # define DAC_A_MASK (3 << 4) 5051 # define DAC_B_1_3_V (0 << 2) 5052 # define DAC_B_1_1_V (1 << 2) 5053 # define DAC_B_0_7_V (2 << 2) 5054 # define DAC_B_MASK (3 << 2) 5055 # define DAC_C_1_3_V (0 << 0) 5056 # define DAC_C_1_1_V (1 << 0) 5057 # define DAC_C_0_7_V (2 << 0) 5058 # define DAC_C_MASK (3 << 0) 5059 5060 /* 5061 * CSC coefficients are stored in a floating point format with 9 bits of 5062 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, 5063 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with 5064 * -1 (0x3) being the only legal negative value. 5065 */ 5066 #define TV_CSC_Y _MMIO(0x68010) 5067 # define TV_RY_MASK 0x07ff0000 5068 # define TV_RY_SHIFT 16 5069 # define TV_GY_MASK 0x00000fff 5070 # define TV_GY_SHIFT 0 5071 5072 #define TV_CSC_Y2 _MMIO(0x68014) 5073 # define TV_BY_MASK 0x07ff0000 5074 # define TV_BY_SHIFT 16 5075 /* 5076 * Y attenuation for component video. 5077 * 5078 * Stored in 1.9 fixed point. 5079 */ 5080 # define TV_AY_MASK 0x000003ff 5081 # define TV_AY_SHIFT 0 5082 5083 #define TV_CSC_U _MMIO(0x68018) 5084 # define TV_RU_MASK 0x07ff0000 5085 # define TV_RU_SHIFT 16 5086 # define TV_GU_MASK 0x000007ff 5087 # define TV_GU_SHIFT 0 5088 5089 #define TV_CSC_U2 _MMIO(0x6801c) 5090 # define TV_BU_MASK 0x07ff0000 5091 # define TV_BU_SHIFT 16 5092 /* 5093 * U attenuation for component video. 5094 * 5095 * Stored in 1.9 fixed point. 5096 */ 5097 # define TV_AU_MASK 0x000003ff 5098 # define TV_AU_SHIFT 0 5099 5100 #define TV_CSC_V _MMIO(0x68020) 5101 # define TV_RV_MASK 0x0fff0000 5102 # define TV_RV_SHIFT 16 5103 # define TV_GV_MASK 0x000007ff 5104 # define TV_GV_SHIFT 0 5105 5106 #define TV_CSC_V2 _MMIO(0x68024) 5107 # define TV_BV_MASK 0x07ff0000 5108 # define TV_BV_SHIFT 16 5109 /* 5110 * V attenuation for component video. 5111 * 5112 * Stored in 1.9 fixed point. 5113 */ 5114 # define TV_AV_MASK 0x000007ff 5115 # define TV_AV_SHIFT 0 5116 5117 #define TV_CLR_KNOBS _MMIO(0x68028) 5118 /* 2s-complement brightness adjustment */ 5119 # define TV_BRIGHTNESS_MASK 0xff000000 5120 # define TV_BRIGHTNESS_SHIFT 24 5121 /* Contrast adjustment, as a 2.6 unsigned floating point number */ 5122 # define TV_CONTRAST_MASK 0x00ff0000 5123 # define TV_CONTRAST_SHIFT 16 5124 /* Saturation adjustment, as a 2.6 unsigned floating point number */ 5125 # define TV_SATURATION_MASK 0x0000ff00 5126 # define TV_SATURATION_SHIFT 8 5127 /* Hue adjustment, as an integer phase angle in degrees */ 5128 # define TV_HUE_MASK 0x000000ff 5129 # define TV_HUE_SHIFT 0 5130 5131 #define TV_CLR_LEVEL _MMIO(0x6802c) 5132 /* Controls the DAC level for black */ 5133 # define TV_BLACK_LEVEL_MASK 0x01ff0000 5134 # define TV_BLACK_LEVEL_SHIFT 16 5135 /* Controls the DAC level for blanking */ 5136 # define TV_BLANK_LEVEL_MASK 0x000001ff 5137 # define TV_BLANK_LEVEL_SHIFT 0 5138 5139 #define TV_H_CTL_1 _MMIO(0x68030) 5140 /* Number of pixels in the hsync. */ 5141 # define TV_HSYNC_END_MASK 0x1fff0000 5142 # define TV_HSYNC_END_SHIFT 16 5143 /* Total number of pixels minus one in the line (display and blanking). */ 5144 # define TV_HTOTAL_MASK 0x00001fff 5145 # define TV_HTOTAL_SHIFT 0 5146 5147 #define TV_H_CTL_2 _MMIO(0x68034) 5148 /* Enables the colorburst (needed for non-component color) */ 5149 # define TV_BURST_ENA (1 << 31) 5150 /* Offset of the colorburst from the start of hsync, in pixels minus one. */ 5151 # define TV_HBURST_START_SHIFT 16 5152 # define TV_HBURST_START_MASK 0x1fff0000 5153 /* Length of the colorburst */ 5154 # define TV_HBURST_LEN_SHIFT 0 5155 # define TV_HBURST_LEN_MASK 0x0001fff 5156 5157 #define TV_H_CTL_3 _MMIO(0x68038) 5158 /* End of hblank, measured in pixels minus one from start of hsync */ 5159 # define TV_HBLANK_END_SHIFT 16 5160 # define TV_HBLANK_END_MASK 0x1fff0000 5161 /* Start of hblank, measured in pixels minus one from start of hsync */ 5162 # define TV_HBLANK_START_SHIFT 0 5163 # define TV_HBLANK_START_MASK 0x0001fff 5164 5165 #define TV_V_CTL_1 _MMIO(0x6803c) 5166 /* XXX */ 5167 # define TV_NBR_END_SHIFT 16 5168 # define TV_NBR_END_MASK 0x07ff0000 5169 /* XXX */ 5170 # define TV_VI_END_F1_SHIFT 8 5171 # define TV_VI_END_F1_MASK 0x00003f00 5172 /* XXX */ 5173 # define TV_VI_END_F2_SHIFT 0 5174 # define TV_VI_END_F2_MASK 0x0000003f 5175 5176 #define TV_V_CTL_2 _MMIO(0x68040) 5177 /* Length of vsync, in half lines */ 5178 # define TV_VSYNC_LEN_MASK 0x07ff0000 5179 # define TV_VSYNC_LEN_SHIFT 16 5180 /* Offset of the start of vsync in field 1, measured in one less than the 5181 * number of half lines. 5182 */ 5183 # define TV_VSYNC_START_F1_MASK 0x00007f00 5184 # define TV_VSYNC_START_F1_SHIFT 8 5185 /* 5186 * Offset of the start of vsync in field 2, measured in one less than the 5187 * number of half lines. 5188 */ 5189 # define TV_VSYNC_START_F2_MASK 0x0000007f 5190 # define TV_VSYNC_START_F2_SHIFT 0 5191 5192 #define TV_V_CTL_3 _MMIO(0x68044) 5193 /* Enables generation of the equalization signal */ 5194 # define TV_EQUAL_ENA (1 << 31) 5195 /* Length of vsync, in half lines */ 5196 # define TV_VEQ_LEN_MASK 0x007f0000 5197 # define TV_VEQ_LEN_SHIFT 16 5198 /* Offset of the start of equalization in field 1, measured in one less than 5199 * the number of half lines. 5200 */ 5201 # define TV_VEQ_START_F1_MASK 0x0007f00 5202 # define TV_VEQ_START_F1_SHIFT 8 5203 /* 5204 * Offset of the start of equalization in field 2, measured in one less than 5205 * the number of half lines. 5206 */ 5207 # define TV_VEQ_START_F2_MASK 0x000007f 5208 # define TV_VEQ_START_F2_SHIFT 0 5209 5210 #define TV_V_CTL_4 _MMIO(0x68048) 5211 /* 5212 * Offset to start of vertical colorburst, measured in one less than the 5213 * number of lines from vertical start. 5214 */ 5215 # define TV_VBURST_START_F1_MASK 0x003f0000 5216 # define TV_VBURST_START_F1_SHIFT 16 5217 /* 5218 * Offset to the end of vertical colorburst, measured in one less than the 5219 * number of lines from the start of NBR. 5220 */ 5221 # define TV_VBURST_END_F1_MASK 0x000000ff 5222 # define TV_VBURST_END_F1_SHIFT 0 5223 5224 #define TV_V_CTL_5 _MMIO(0x6804c) 5225 /* 5226 * Offset to start of vertical colorburst, measured in one less than the 5227 * number of lines from vertical start. 5228 */ 5229 # define TV_VBURST_START_F2_MASK 0x003f0000 5230 # define TV_VBURST_START_F2_SHIFT 16 5231 /* 5232 * Offset to the end of vertical colorburst, measured in one less than the 5233 * number of lines from the start of NBR. 5234 */ 5235 # define TV_VBURST_END_F2_MASK 0x000000ff 5236 # define TV_VBURST_END_F2_SHIFT 0 5237 5238 #define TV_V_CTL_6 _MMIO(0x68050) 5239 /* 5240 * Offset to start of vertical colorburst, measured in one less than the 5241 * number of lines from vertical start. 5242 */ 5243 # define TV_VBURST_START_F3_MASK 0x003f0000 5244 # define TV_VBURST_START_F3_SHIFT 16 5245 /* 5246 * Offset to the end of vertical colorburst, measured in one less than the 5247 * number of lines from the start of NBR. 5248 */ 5249 # define TV_VBURST_END_F3_MASK 0x000000ff 5250 # define TV_VBURST_END_F3_SHIFT 0 5251 5252 #define TV_V_CTL_7 _MMIO(0x68054) 5253 /* 5254 * Offset to start of vertical colorburst, measured in one less than the 5255 * number of lines from vertical start. 5256 */ 5257 # define TV_VBURST_START_F4_MASK 0x003f0000 5258 # define TV_VBURST_START_F4_SHIFT 16 5259 /* 5260 * Offset to the end of vertical colorburst, measured in one less than the 5261 * number of lines from the start of NBR. 5262 */ 5263 # define TV_VBURST_END_F4_MASK 0x000000ff 5264 # define TV_VBURST_END_F4_SHIFT 0 5265 5266 #define TV_SC_CTL_1 _MMIO(0x68060) 5267 /* Turns on the first subcarrier phase generation DDA */ 5268 # define TV_SC_DDA1_EN (1 << 31) 5269 /* Turns on the first subcarrier phase generation DDA */ 5270 # define TV_SC_DDA2_EN (1 << 30) 5271 /* Turns on the first subcarrier phase generation DDA */ 5272 # define TV_SC_DDA3_EN (1 << 29) 5273 /* Sets the subcarrier DDA to reset frequency every other field */ 5274 # define TV_SC_RESET_EVERY_2 (0 << 24) 5275 /* Sets the subcarrier DDA to reset frequency every fourth field */ 5276 # define TV_SC_RESET_EVERY_4 (1 << 24) 5277 /* Sets the subcarrier DDA to reset frequency every eighth field */ 5278 # define TV_SC_RESET_EVERY_8 (2 << 24) 5279 /* Sets the subcarrier DDA to never reset the frequency */ 5280 # define TV_SC_RESET_NEVER (3 << 24) 5281 /* Sets the peak amplitude of the colorburst.*/ 5282 # define TV_BURST_LEVEL_MASK 0x00ff0000 5283 # define TV_BURST_LEVEL_SHIFT 16 5284 /* Sets the increment of the first subcarrier phase generation DDA */ 5285 # define TV_SCDDA1_INC_MASK 0x00000fff 5286 # define TV_SCDDA1_INC_SHIFT 0 5287 5288 #define TV_SC_CTL_2 _MMIO(0x68064) 5289 /* Sets the rollover for the second subcarrier phase generation DDA */ 5290 # define TV_SCDDA2_SIZE_MASK 0x7fff0000 5291 # define TV_SCDDA2_SIZE_SHIFT 16 5292 /* Sets the increent of the second subcarrier phase generation DDA */ 5293 # define TV_SCDDA2_INC_MASK 0x00007fff 5294 # define TV_SCDDA2_INC_SHIFT 0 5295 5296 #define TV_SC_CTL_3 _MMIO(0x68068) 5297 /* Sets the rollover for the third subcarrier phase generation DDA */ 5298 # define TV_SCDDA3_SIZE_MASK 0x7fff0000 5299 # define TV_SCDDA3_SIZE_SHIFT 16 5300 /* Sets the increent of the third subcarrier phase generation DDA */ 5301 # define TV_SCDDA3_INC_MASK 0x00007fff 5302 # define TV_SCDDA3_INC_SHIFT 0 5303 5304 #define TV_WIN_POS _MMIO(0x68070) 5305 /* X coordinate of the display from the start of horizontal active */ 5306 # define TV_XPOS_MASK 0x1fff0000 5307 # define TV_XPOS_SHIFT 16 5308 /* Y coordinate of the display from the start of vertical active (NBR) */ 5309 # define TV_YPOS_MASK 0x00000fff 5310 # define TV_YPOS_SHIFT 0 5311 5312 #define TV_WIN_SIZE _MMIO(0x68074) 5313 /* Horizontal size of the display window, measured in pixels*/ 5314 # define TV_XSIZE_MASK 0x1fff0000 5315 # define TV_XSIZE_SHIFT 16 5316 /* 5317 * Vertical size of the display window, measured in pixels. 5318 * 5319 * Must be even for interlaced modes. 5320 */ 5321 # define TV_YSIZE_MASK 0x00000fff 5322 # define TV_YSIZE_SHIFT 0 5323 5324 #define TV_FILTER_CTL_1 _MMIO(0x68080) 5325 /* 5326 * Enables automatic scaling calculation. 5327 * 5328 * If set, the rest of the registers are ignored, and the calculated values can 5329 * be read back from the register. 5330 */ 5331 # define TV_AUTO_SCALE (1 << 31) 5332 /* 5333 * Disables the vertical filter. 5334 * 5335 * This is required on modes more than 1024 pixels wide */ 5336 # define TV_V_FILTER_BYPASS (1 << 29) 5337 /* Enables adaptive vertical filtering */ 5338 # define TV_VADAPT (1 << 28) 5339 # define TV_VADAPT_MODE_MASK (3 << 26) 5340 /* Selects the least adaptive vertical filtering mode */ 5341 # define TV_VADAPT_MODE_LEAST (0 << 26) 5342 /* Selects the moderately adaptive vertical filtering mode */ 5343 # define TV_VADAPT_MODE_MODERATE (1 << 26) 5344 /* Selects the most adaptive vertical filtering mode */ 5345 # define TV_VADAPT_MODE_MOST (3 << 26) 5346 /* 5347 * Sets the horizontal scaling factor. 5348 * 5349 * This should be the fractional part of the horizontal scaling factor divided 5350 * by the oversampling rate. TV_HSCALE should be less than 1, and set to: 5351 * 5352 * (src width - 1) / ((oversample * dest width) - 1) 5353 */ 5354 # define TV_HSCALE_FRAC_MASK 0x00003fff 5355 # define TV_HSCALE_FRAC_SHIFT 0 5356 5357 #define TV_FILTER_CTL_2 _MMIO(0x68084) 5358 /* 5359 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 5360 * 5361 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) 5362 */ 5363 # define TV_VSCALE_INT_MASK 0x00038000 5364 # define TV_VSCALE_INT_SHIFT 15 5365 /* 5366 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 5367 * 5368 * \sa TV_VSCALE_INT_MASK 5369 */ 5370 # define TV_VSCALE_FRAC_MASK 0x00007fff 5371 # define TV_VSCALE_FRAC_SHIFT 0 5372 5373 #define TV_FILTER_CTL_3 _MMIO(0x68088) 5374 /* 5375 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 5376 * 5377 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) 5378 * 5379 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 5380 */ 5381 # define TV_VSCALE_IP_INT_MASK 0x00038000 5382 # define TV_VSCALE_IP_INT_SHIFT 15 5383 /* 5384 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 5385 * 5386 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 5387 * 5388 * \sa TV_VSCALE_IP_INT_MASK 5389 */ 5390 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff 5391 # define TV_VSCALE_IP_FRAC_SHIFT 0 5392 5393 #define TV_CC_CONTROL _MMIO(0x68090) 5394 # define TV_CC_ENABLE (1 << 31) 5395 /* 5396 * Specifies which field to send the CC data in. 5397 * 5398 * CC data is usually sent in field 0. 5399 */ 5400 # define TV_CC_FID_MASK (1 << 27) 5401 # define TV_CC_FID_SHIFT 27 5402 /* Sets the horizontal position of the CC data. Usually 135. */ 5403 # define TV_CC_HOFF_MASK 0x03ff0000 5404 # define TV_CC_HOFF_SHIFT 16 5405 /* Sets the vertical position of the CC data. Usually 21 */ 5406 # define TV_CC_LINE_MASK 0x0000003f 5407 # define TV_CC_LINE_SHIFT 0 5408 5409 #define TV_CC_DATA _MMIO(0x68094) 5410 # define TV_CC_RDY (1 << 31) 5411 /* Second word of CC data to be transmitted. */ 5412 # define TV_CC_DATA_2_MASK 0x007f0000 5413 # define TV_CC_DATA_2_SHIFT 16 5414 /* First word of CC data to be transmitted. */ 5415 # define TV_CC_DATA_1_MASK 0x0000007f 5416 # define TV_CC_DATA_1_SHIFT 0 5417 5418 #define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */ 5419 #define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */ 5420 #define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */ 5421 #define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */ 5422 5423 /* Display Port */ 5424 #define DP_A _MMIO(0x64000) /* eDP */ 5425 #define DP_B _MMIO(0x64100) 5426 #define DP_C _MMIO(0x64200) 5427 #define DP_D _MMIO(0x64300) 5428 5429 #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100) 5430 #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200) 5431 #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300) 5432 5433 #define DP_PORT_EN (1 << 31) 5434 #define DP_PIPE_SEL_SHIFT 30 5435 #define DP_PIPE_SEL_MASK (1 << 30) 5436 #define DP_PIPE_SEL(pipe) ((pipe) << 30) 5437 #define DP_PIPE_SEL_SHIFT_IVB 29 5438 #define DP_PIPE_SEL_MASK_IVB (3 << 29) 5439 #define DP_PIPE_SEL_IVB(pipe) ((pipe) << 29) 5440 #define DP_PIPE_SEL_SHIFT_CHV 16 5441 #define DP_PIPE_SEL_MASK_CHV (3 << 16) 5442 #define DP_PIPE_SEL_CHV(pipe) ((pipe) << 16) 5443 5444 /* Link training mode - select a suitable mode for each stage */ 5445 #define DP_LINK_TRAIN_PAT_1 (0 << 28) 5446 #define DP_LINK_TRAIN_PAT_2 (1 << 28) 5447 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) 5448 #define DP_LINK_TRAIN_OFF (3 << 28) 5449 #define DP_LINK_TRAIN_MASK (3 << 28) 5450 #define DP_LINK_TRAIN_SHIFT 28 5451 5452 /* CPT Link training mode */ 5453 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) 5454 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) 5455 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) 5456 #define DP_LINK_TRAIN_OFF_CPT (3 << 8) 5457 #define DP_LINK_TRAIN_MASK_CPT (7 << 8) 5458 #define DP_LINK_TRAIN_SHIFT_CPT 8 5459 5460 /* Signal voltages. These are mostly controlled by the other end */ 5461 #define DP_VOLTAGE_0_4 (0 << 25) 5462 #define DP_VOLTAGE_0_6 (1 << 25) 5463 #define DP_VOLTAGE_0_8 (2 << 25) 5464 #define DP_VOLTAGE_1_2 (3 << 25) 5465 #define DP_VOLTAGE_MASK (7 << 25) 5466 #define DP_VOLTAGE_SHIFT 25 5467 5468 /* Signal pre-emphasis levels, like voltages, the other end tells us what 5469 * they want 5470 */ 5471 #define DP_PRE_EMPHASIS_0 (0 << 22) 5472 #define DP_PRE_EMPHASIS_3_5 (1 << 22) 5473 #define DP_PRE_EMPHASIS_6 (2 << 22) 5474 #define DP_PRE_EMPHASIS_9_5 (3 << 22) 5475 #define DP_PRE_EMPHASIS_MASK (7 << 22) 5476 #define DP_PRE_EMPHASIS_SHIFT 22 5477 5478 /* How many wires to use. I guess 3 was too hard */ 5479 #define DP_PORT_WIDTH(width) (((width) - 1) << 19) 5480 #define DP_PORT_WIDTH_MASK (7 << 19) 5481 #define DP_PORT_WIDTH_SHIFT 19 5482 5483 /* Mystic DPCD version 1.1 special mode */ 5484 #define DP_ENHANCED_FRAMING (1 << 18) 5485 5486 /* eDP */ 5487 #define DP_PLL_FREQ_270MHZ (0 << 16) 5488 #define DP_PLL_FREQ_162MHZ (1 << 16) 5489 #define DP_PLL_FREQ_MASK (3 << 16) 5490 5491 /* locked once port is enabled */ 5492 #define DP_PORT_REVERSAL (1 << 15) 5493 5494 /* eDP */ 5495 #define DP_PLL_ENABLE (1 << 14) 5496 5497 /* sends the clock on lane 15 of the PEG for debug */ 5498 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 5499 5500 #define DP_SCRAMBLING_DISABLE (1 << 12) 5501 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) 5502 5503 /* limit RGB values to avoid confusing TVs */ 5504 #define DP_COLOR_RANGE_16_235 (1 << 8) 5505 5506 /* Turn on the audio link */ 5507 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) 5508 5509 /* vs and hs sync polarity */ 5510 #define DP_SYNC_VS_HIGH (1 << 4) 5511 #define DP_SYNC_HS_HIGH (1 << 3) 5512 5513 /* A fantasy */ 5514 #define DP_DETECTED (1 << 2) 5515 5516 /* The aux channel provides a way to talk to the 5517 * signal sink for DDC etc. Max packet size supported 5518 * is 20 bytes in each direction, hence the 5 fixed 5519 * data registers 5520 */ 5521 #define _DPA_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64010) 5522 #define _DPA_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64014) 5523 #define _DPA_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64018) 5524 #define _DPA_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6401c) 5525 #define _DPA_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64020) 5526 #define _DPA_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64024) 5527 5528 #define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110) 5529 #define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114) 5530 #define _DPB_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64118) 5531 #define _DPB_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6411c) 5532 #define _DPB_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64120) 5533 #define _DPB_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64124) 5534 5535 #define _DPC_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64210) 5536 #define _DPC_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64214) 5537 #define _DPC_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64218) 5538 #define _DPC_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6421c) 5539 #define _DPC_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64220) 5540 #define _DPC_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64224) 5541 5542 #define _DPD_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64310) 5543 #define _DPD_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64314) 5544 #define _DPD_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64318) 5545 #define _DPD_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6431c) 5546 #define _DPD_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64320) 5547 #define _DPD_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64324) 5548 5549 #define _DPE_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64410) 5550 #define _DPE_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64414) 5551 #define _DPE_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64418) 5552 #define _DPE_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6441c) 5553 #define _DPE_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64420) 5554 #define _DPE_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64424) 5555 5556 #define _DPF_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64510) 5557 #define _DPF_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64514) 5558 #define _DPF_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64518) 5559 #define _DPF_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6451c) 5560 #define _DPF_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64520) 5561 #define _DPF_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64524) 5562 5563 #define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL) 5564 #define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ 5565 5566 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) 5567 #define DP_AUX_CH_CTL_DONE (1 << 30) 5568 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) 5569 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) 5570 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) 5571 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) 5572 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) 5573 #define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */ 5574 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) 5575 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) 5576 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) 5577 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 5578 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) 5579 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 5580 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) 5581 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) 5582 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) 5583 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) 5584 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) 5585 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) 5586 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 5587 #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14) 5588 #define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13) 5589 #define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12) 5590 #define DP_AUX_CH_CTL_TBT_IO (1 << 11) 5591 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5) 5592 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5) 5593 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1) 5594 5595 /* 5596 * Computing GMCH M and N values for the Display Port link 5597 * 5598 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes 5599 * 5600 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) 5601 * 5602 * The GMCH value is used internally 5603 * 5604 * bytes_per_pixel is the number of bytes coming out of the plane, 5605 * which is after the LUTs, so we want the bytes for our color format. 5606 * For our current usage, this is always 3, one byte for R, G and B. 5607 */ 5608 #define _PIPEA_DATA_M_G4X 0x70050 5609 #define _PIPEB_DATA_M_G4X 0x71050 5610 5611 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 5612 #define TU_SIZE(x) (((x) - 1) << 25) /* default size 64 */ 5613 #define TU_SIZE_SHIFT 25 5614 #define TU_SIZE_MASK (0x3f << 25) 5615 5616 #define DATA_LINK_M_N_MASK (0xffffff) 5617 #define DATA_LINK_N_MAX (0x800000) 5618 5619 #define _PIPEA_DATA_N_G4X 0x70054 5620 #define _PIPEB_DATA_N_G4X 0x71054 5621 #define PIPE_GMCH_DATA_N_MASK (0xffffff) 5622 5623 /* 5624 * Computing Link M and N values for the Display Port link 5625 * 5626 * Link M / N = pixel_clock / ls_clk 5627 * 5628 * (the DP spec calls pixel_clock the 'strm_clk') 5629 * 5630 * The Link value is transmitted in the Main Stream 5631 * Attributes and VB-ID. 5632 */ 5633 5634 #define _PIPEA_LINK_M_G4X 0x70060 5635 #define _PIPEB_LINK_M_G4X 0x71060 5636 #define PIPEA_DP_LINK_M_MASK (0xffffff) 5637 5638 #define _PIPEA_LINK_N_G4X 0x70064 5639 #define _PIPEB_LINK_N_G4X 0x71064 5640 #define PIPEA_DP_LINK_N_MASK (0xffffff) 5641 5642 #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X) 5643 #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X) 5644 #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X) 5645 #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X) 5646 5647 /* Display & cursor control */ 5648 5649 /* Pipe A */ 5650 #define _PIPEADSL 0x70000 5651 #define DSL_LINEMASK_GEN2 0x00000fff 5652 #define DSL_LINEMASK_GEN3 0x00001fff 5653 #define _PIPEACONF 0x70008 5654 #define PIPECONF_ENABLE (1 << 31) 5655 #define PIPECONF_DISABLE 0 5656 #define PIPECONF_DOUBLE_WIDE (1 << 30) 5657 #define I965_PIPECONF_ACTIVE (1 << 30) 5658 #define PIPECONF_DSI_PLL_LOCKED (1 << 29) /* vlv & pipe A only */ 5659 #define PIPECONF_FRAME_START_DELAY_MASK (3 << 27) 5660 #define PIPECONF_SINGLE_WIDE 0 5661 #define PIPECONF_PIPE_UNLOCKED 0 5662 #define PIPECONF_PIPE_LOCKED (1 << 25) 5663 #define PIPECONF_FORCE_BORDER (1 << 25) 5664 #define PIPECONF_GAMMA_MODE_MASK_I9XX (1 << 24) /* gmch */ 5665 #define PIPECONF_GAMMA_MODE_MASK_ILK (3 << 24) /* ilk-ivb */ 5666 #define PIPECONF_GAMMA_MODE_8BIT (0 << 24) /* gmch,ilk-ivb */ 5667 #define PIPECONF_GAMMA_MODE_10BIT (1 << 24) /* gmch,ilk-ivb */ 5668 #define PIPECONF_GAMMA_MODE_12BIT (2 << 24) /* ilk-ivb */ 5669 #define PIPECONF_GAMMA_MODE_SPLIT (3 << 24) /* ivb */ 5670 #define PIPECONF_GAMMA_MODE(x) ((x) << 24) /* pass in GAMMA_MODE_MODE_* */ 5671 #define PIPECONF_GAMMA_MODE_SHIFT 24 5672 #define PIPECONF_INTERLACE_MASK (7 << 21) 5673 #define PIPECONF_INTERLACE_MASK_HSW (3 << 21) 5674 /* Note that pre-gen3 does not support interlaced display directly. Panel 5675 * fitting must be disabled on pre-ilk for interlaced. */ 5676 #define PIPECONF_PROGRESSIVE (0 << 21) 5677 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ 5678 #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ 5679 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 5680 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ 5681 /* Ironlake and later have a complete new set of values for interlaced. PFIT 5682 * means panel fitter required, PF means progressive fetch, DBL means power 5683 * saving pixel doubling. */ 5684 #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) 5685 #define PIPECONF_INTERLACED_ILK (3 << 21) 5686 #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ 5687 #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ 5688 #define PIPECONF_INTERLACE_MODE_MASK (7 << 21) 5689 #define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20) 5690 #define PIPECONF_CXSR_DOWNCLOCK (1 << 16) 5691 #define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14) 5692 #define PIPECONF_COLOR_RANGE_SELECT (1 << 13) 5693 #define PIPECONF_BPC_MASK (0x7 << 5) 5694 #define PIPECONF_8BPC (0 << 5) 5695 #define PIPECONF_10BPC (1 << 5) 5696 #define PIPECONF_6BPC (2 << 5) 5697 #define PIPECONF_12BPC (3 << 5) 5698 #define PIPECONF_DITHER_EN (1 << 4) 5699 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c) 5700 #define PIPECONF_DITHER_TYPE_SP (0 << 2) 5701 #define PIPECONF_DITHER_TYPE_ST1 (1 << 2) 5702 #define PIPECONF_DITHER_TYPE_ST2 (2 << 2) 5703 #define PIPECONF_DITHER_TYPE_TEMP (3 << 2) 5704 #define _PIPEASTAT 0x70024 5705 #define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31) 5706 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30) 5707 #define PIPE_CRC_ERROR_ENABLE (1UL << 29) 5708 #define PIPE_CRC_DONE_ENABLE (1UL << 28) 5709 #define PERF_COUNTER2_INTERRUPT_EN (1UL << 27) 5710 #define PIPE_GMBUS_EVENT_ENABLE (1UL << 27) 5711 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26) 5712 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26) 5713 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25) 5714 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24) 5715 #define PIPE_DPST_EVENT_ENABLE (1UL << 23) 5716 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22) 5717 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22) 5718 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21) 5719 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20) 5720 #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL << 19) 5721 #define PERF_COUNTER_INTERRUPT_EN (1UL << 19) 5722 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */ 5723 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) /* 965 or later */ 5724 #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL << 17) 5725 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17) 5726 #define PIPEA_HBLANK_INT_EN_VLV (1UL << 16) 5727 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16) 5728 #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL << 15) 5729 #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL << 14) 5730 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13) 5731 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12) 5732 #define PERF_COUNTER2_INTERRUPT_STATUS (1UL << 11) 5733 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11) 5734 #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL << 10) 5735 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10) 5736 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9) 5737 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8) 5738 #define PIPE_DPST_EVENT_STATUS (1UL << 7) 5739 #define PIPE_A_PSR_STATUS_VLV (1UL << 6) 5740 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6) 5741 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5) 5742 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4) 5743 #define PIPE_B_PSR_STATUS_VLV (1UL << 3) 5744 #define PERF_COUNTER_INTERRUPT_STATUS (1UL << 3) 5745 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */ 5746 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) /* 965 or later */ 5747 #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL << 1) 5748 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1) 5749 #define PIPE_HBLANK_INT_STATUS (1UL << 0) 5750 #define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0) 5751 5752 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 5753 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff 5754 5755 #define PIPE_A_OFFSET 0x70000 5756 #define PIPE_B_OFFSET 0x71000 5757 #define PIPE_C_OFFSET 0x72000 5758 #define CHV_PIPE_C_OFFSET 0x74000 5759 /* 5760 * There's actually no pipe EDP. Some pipe registers have 5761 * simply shifted from the pipe to the transcoder, while 5762 * keeping their original offset. Thus we need PIPE_EDP_OFFSET 5763 * to access such registers in transcoder EDP. 5764 */ 5765 #define PIPE_EDP_OFFSET 0x7f000 5766 5767 /* ICL DSI 0 and 1 */ 5768 #define PIPE_DSI0_OFFSET 0x7b000 5769 #define PIPE_DSI1_OFFSET 0x7b800 5770 5771 #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF) 5772 #define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL) 5773 #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH) 5774 #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL) 5775 #define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT) 5776 5777 #define _PIPEAGCMAX 0x70010 5778 #define _PIPEBGCMAX 0x71010 5779 #define PIPEGCMAX(pipe, i) _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4) 5780 5781 #define _PIPE_MISC_A 0x70030 5782 #define _PIPE_MISC_B 0x71030 5783 #define PIPEMISC_YUV420_ENABLE (1 << 27) 5784 #define PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26) 5785 #define PIPEMISC_HDR_MODE_PRECISION (1 << 23) /* icl+ */ 5786 #define PIPEMISC_OUTPUT_COLORSPACE_YUV (1 << 11) 5787 #define PIPEMISC_DITHER_BPC_MASK (7 << 5) 5788 #define PIPEMISC_DITHER_8_BPC (0 << 5) 5789 #define PIPEMISC_DITHER_10_BPC (1 << 5) 5790 #define PIPEMISC_DITHER_6_BPC (2 << 5) 5791 #define PIPEMISC_DITHER_12_BPC (3 << 5) 5792 #define PIPEMISC_DITHER_ENABLE (1 << 4) 5793 #define PIPEMISC_DITHER_TYPE_MASK (3 << 2) 5794 #define PIPEMISC_DITHER_TYPE_SP (0 << 2) 5795 #define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A) 5796 5797 /* Skylake+ pipe bottom (background) color */ 5798 #define _SKL_BOTTOM_COLOR_A 0x70034 5799 #define SKL_BOTTOM_COLOR_GAMMA_ENABLE (1 << 31) 5800 #define SKL_BOTTOM_COLOR_CSC_ENABLE (1 << 30) 5801 #define SKL_BOTTOM_COLOR(pipe) _MMIO_PIPE2(pipe, _SKL_BOTTOM_COLOR_A) 5802 5803 #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028) 5804 #define PIPEB_LINE_COMPARE_INT_EN (1 << 29) 5805 #define PIPEB_HLINE_INT_EN (1 << 28) 5806 #define PIPEB_VBLANK_INT_EN (1 << 27) 5807 #define SPRITED_FLIP_DONE_INT_EN (1 << 26) 5808 #define SPRITEC_FLIP_DONE_INT_EN (1 << 25) 5809 #define PLANEB_FLIP_DONE_INT_EN (1 << 24) 5810 #define PIPE_PSR_INT_EN (1 << 22) 5811 #define PIPEA_LINE_COMPARE_INT_EN (1 << 21) 5812 #define PIPEA_HLINE_INT_EN (1 << 20) 5813 #define PIPEA_VBLANK_INT_EN (1 << 19) 5814 #define SPRITEB_FLIP_DONE_INT_EN (1 << 18) 5815 #define SPRITEA_FLIP_DONE_INT_EN (1 << 17) 5816 #define PLANEA_FLIPDONE_INT_EN (1 << 16) 5817 #define PIPEC_LINE_COMPARE_INT_EN (1 << 13) 5818 #define PIPEC_HLINE_INT_EN (1 << 12) 5819 #define PIPEC_VBLANK_INT_EN (1 << 11) 5820 #define SPRITEF_FLIPDONE_INT_EN (1 << 10) 5821 #define SPRITEE_FLIPDONE_INT_EN (1 << 9) 5822 #define PLANEC_FLIPDONE_INT_EN (1 << 8) 5823 5824 #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ 5825 #define SPRITEF_INVALID_GTT_INT_EN (1 << 27) 5826 #define SPRITEE_INVALID_GTT_INT_EN (1 << 26) 5827 #define PLANEC_INVALID_GTT_INT_EN (1 << 25) 5828 #define CURSORC_INVALID_GTT_INT_EN (1 << 24) 5829 #define CURSORB_INVALID_GTT_INT_EN (1 << 23) 5830 #define CURSORA_INVALID_GTT_INT_EN (1 << 22) 5831 #define SPRITED_INVALID_GTT_INT_EN (1 << 21) 5832 #define SPRITEC_INVALID_GTT_INT_EN (1 << 20) 5833 #define PLANEB_INVALID_GTT_INT_EN (1 << 19) 5834 #define SPRITEB_INVALID_GTT_INT_EN (1 << 18) 5835 #define SPRITEA_INVALID_GTT_INT_EN (1 << 17) 5836 #define PLANEA_INVALID_GTT_INT_EN (1 << 16) 5837 #define DPINVGTT_EN_MASK 0xff0000 5838 #define DPINVGTT_EN_MASK_CHV 0xfff0000 5839 #define SPRITEF_INVALID_GTT_STATUS (1 << 11) 5840 #define SPRITEE_INVALID_GTT_STATUS (1 << 10) 5841 #define PLANEC_INVALID_GTT_STATUS (1 << 9) 5842 #define CURSORC_INVALID_GTT_STATUS (1 << 8) 5843 #define CURSORB_INVALID_GTT_STATUS (1 << 7) 5844 #define CURSORA_INVALID_GTT_STATUS (1 << 6) 5845 #define SPRITED_INVALID_GTT_STATUS (1 << 5) 5846 #define SPRITEC_INVALID_GTT_STATUS (1 << 4) 5847 #define PLANEB_INVALID_GTT_STATUS (1 << 3) 5848 #define SPRITEB_INVALID_GTT_STATUS (1 << 2) 5849 #define SPRITEA_INVALID_GTT_STATUS (1 << 1) 5850 #define PLANEA_INVALID_GTT_STATUS (1 << 0) 5851 #define DPINVGTT_STATUS_MASK 0xff 5852 #define DPINVGTT_STATUS_MASK_CHV 0xfff 5853 5854 #define DSPARB _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030) 5855 #define DSPARB_CSTART_MASK (0x7f << 7) 5856 #define DSPARB_CSTART_SHIFT 7 5857 #define DSPARB_BSTART_MASK (0x7f) 5858 #define DSPARB_BSTART_SHIFT 0 5859 #define DSPARB_BEND_SHIFT 9 /* on 855 */ 5860 #define DSPARB_AEND_SHIFT 0 5861 #define DSPARB_SPRITEA_SHIFT_VLV 0 5862 #define DSPARB_SPRITEA_MASK_VLV (0xff << 0) 5863 #define DSPARB_SPRITEB_SHIFT_VLV 8 5864 #define DSPARB_SPRITEB_MASK_VLV (0xff << 8) 5865 #define DSPARB_SPRITEC_SHIFT_VLV 16 5866 #define DSPARB_SPRITEC_MASK_VLV (0xff << 16) 5867 #define DSPARB_SPRITED_SHIFT_VLV 24 5868 #define DSPARB_SPRITED_MASK_VLV (0xff << 24) 5869 #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */ 5870 #define DSPARB_SPRITEA_HI_SHIFT_VLV 0 5871 #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0) 5872 #define DSPARB_SPRITEB_HI_SHIFT_VLV 4 5873 #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4) 5874 #define DSPARB_SPRITEC_HI_SHIFT_VLV 8 5875 #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8) 5876 #define DSPARB_SPRITED_HI_SHIFT_VLV 12 5877 #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12) 5878 #define DSPARB_SPRITEE_HI_SHIFT_VLV 16 5879 #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16) 5880 #define DSPARB_SPRITEF_HI_SHIFT_VLV 20 5881 #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20) 5882 #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */ 5883 #define DSPARB_SPRITEE_SHIFT_VLV 0 5884 #define DSPARB_SPRITEE_MASK_VLV (0xff << 0) 5885 #define DSPARB_SPRITEF_SHIFT_VLV 8 5886 #define DSPARB_SPRITEF_MASK_VLV (0xff << 8) 5887 5888 /* pnv/gen4/g4x/vlv/chv */ 5889 #define DSPFW1 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034) 5890 #define DSPFW_SR_SHIFT 23 5891 #define DSPFW_SR_MASK (0x1ff << 23) 5892 #define DSPFW_CURSORB_SHIFT 16 5893 #define DSPFW_CURSORB_MASK (0x3f << 16) 5894 #define DSPFW_PLANEB_SHIFT 8 5895 #define DSPFW_PLANEB_MASK (0x7f << 8) 5896 #define DSPFW_PLANEB_MASK_VLV (0xff << 8) /* vlv/chv */ 5897 #define DSPFW_PLANEA_SHIFT 0 5898 #define DSPFW_PLANEA_MASK (0x7f << 0) 5899 #define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */ 5900 #define DSPFW2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038) 5901 #define DSPFW_FBC_SR_EN (1 << 31) /* g4x */ 5902 #define DSPFW_FBC_SR_SHIFT 28 5903 #define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */ 5904 #define DSPFW_FBC_HPLL_SR_SHIFT 24 5905 #define DSPFW_FBC_HPLL_SR_MASK (0xf << 24) /* g4x */ 5906 #define DSPFW_SPRITEB_SHIFT (16) 5907 #define DSPFW_SPRITEB_MASK (0x7f << 16) /* g4x */ 5908 #define DSPFW_SPRITEB_MASK_VLV (0xff << 16) /* vlv/chv */ 5909 #define DSPFW_CURSORA_SHIFT 8 5910 #define DSPFW_CURSORA_MASK (0x3f << 8) 5911 #define DSPFW_PLANEC_OLD_SHIFT 0 5912 #define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */ 5913 #define DSPFW_SPRITEA_SHIFT 0 5914 #define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */ 5915 #define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */ 5916 #define DSPFW3 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c) 5917 #define DSPFW_HPLL_SR_EN (1 << 31) 5918 #define PINEVIEW_SELF_REFRESH_EN (1 << 30) 5919 #define DSPFW_CURSOR_SR_SHIFT 24 5920 #define DSPFW_CURSOR_SR_MASK (0x3f << 24) 5921 #define DSPFW_HPLL_CURSOR_SHIFT 16 5922 #define DSPFW_HPLL_CURSOR_MASK (0x3f << 16) 5923 #define DSPFW_HPLL_SR_SHIFT 0 5924 #define DSPFW_HPLL_SR_MASK (0x1ff << 0) 5925 5926 /* vlv/chv */ 5927 #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070) 5928 #define DSPFW_SPRITEB_WM1_SHIFT 16 5929 #define DSPFW_SPRITEB_WM1_MASK (0xff << 16) 5930 #define DSPFW_CURSORA_WM1_SHIFT 8 5931 #define DSPFW_CURSORA_WM1_MASK (0x3f << 8) 5932 #define DSPFW_SPRITEA_WM1_SHIFT 0 5933 #define DSPFW_SPRITEA_WM1_MASK (0xff << 0) 5934 #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074) 5935 #define DSPFW_PLANEB_WM1_SHIFT 24 5936 #define DSPFW_PLANEB_WM1_MASK (0xff << 24) 5937 #define DSPFW_PLANEA_WM1_SHIFT 16 5938 #define DSPFW_PLANEA_WM1_MASK (0xff << 16) 5939 #define DSPFW_CURSORB_WM1_SHIFT 8 5940 #define DSPFW_CURSORB_WM1_MASK (0x3f << 8) 5941 #define DSPFW_CURSOR_SR_WM1_SHIFT 0 5942 #define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0) 5943 #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078) 5944 #define DSPFW_SR_WM1_SHIFT 0 5945 #define DSPFW_SR_WM1_MASK (0x1ff << 0) 5946 #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c) 5947 #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */ 5948 #define DSPFW_SPRITED_WM1_SHIFT 24 5949 #define DSPFW_SPRITED_WM1_MASK (0xff << 24) 5950 #define DSPFW_SPRITED_SHIFT 16 5951 #define DSPFW_SPRITED_MASK_VLV (0xff << 16) 5952 #define DSPFW_SPRITEC_WM1_SHIFT 8 5953 #define DSPFW_SPRITEC_WM1_MASK (0xff << 8) 5954 #define DSPFW_SPRITEC_SHIFT 0 5955 #define DSPFW_SPRITEC_MASK_VLV (0xff << 0) 5956 #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8) 5957 #define DSPFW_SPRITEF_WM1_SHIFT 24 5958 #define DSPFW_SPRITEF_WM1_MASK (0xff << 24) 5959 #define DSPFW_SPRITEF_SHIFT 16 5960 #define DSPFW_SPRITEF_MASK_VLV (0xff << 16) 5961 #define DSPFW_SPRITEE_WM1_SHIFT 8 5962 #define DSPFW_SPRITEE_WM1_MASK (0xff << 8) 5963 #define DSPFW_SPRITEE_SHIFT 0 5964 #define DSPFW_SPRITEE_MASK_VLV (0xff << 0) 5965 #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */ 5966 #define DSPFW_PLANEC_WM1_SHIFT 24 5967 #define DSPFW_PLANEC_WM1_MASK (0xff << 24) 5968 #define DSPFW_PLANEC_SHIFT 16 5969 #define DSPFW_PLANEC_MASK_VLV (0xff << 16) 5970 #define DSPFW_CURSORC_WM1_SHIFT 8 5971 #define DSPFW_CURSORC_WM1_MASK (0x3f << 16) 5972 #define DSPFW_CURSORC_SHIFT 0 5973 #define DSPFW_CURSORC_MASK (0x3f << 0) 5974 5975 /* vlv/chv high order bits */ 5976 #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064) 5977 #define DSPFW_SR_HI_SHIFT 24 5978 #define DSPFW_SR_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */ 5979 #define DSPFW_SPRITEF_HI_SHIFT 23 5980 #define DSPFW_SPRITEF_HI_MASK (1 << 23) 5981 #define DSPFW_SPRITEE_HI_SHIFT 22 5982 #define DSPFW_SPRITEE_HI_MASK (1 << 22) 5983 #define DSPFW_PLANEC_HI_SHIFT 21 5984 #define DSPFW_PLANEC_HI_MASK (1 << 21) 5985 #define DSPFW_SPRITED_HI_SHIFT 20 5986 #define DSPFW_SPRITED_HI_MASK (1 << 20) 5987 #define DSPFW_SPRITEC_HI_SHIFT 16 5988 #define DSPFW_SPRITEC_HI_MASK (1 << 16) 5989 #define DSPFW_PLANEB_HI_SHIFT 12 5990 #define DSPFW_PLANEB_HI_MASK (1 << 12) 5991 #define DSPFW_SPRITEB_HI_SHIFT 8 5992 #define DSPFW_SPRITEB_HI_MASK (1 << 8) 5993 #define DSPFW_SPRITEA_HI_SHIFT 4 5994 #define DSPFW_SPRITEA_HI_MASK (1 << 4) 5995 #define DSPFW_PLANEA_HI_SHIFT 0 5996 #define DSPFW_PLANEA_HI_MASK (1 << 0) 5997 #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068) 5998 #define DSPFW_SR_WM1_HI_SHIFT 24 5999 #define DSPFW_SR_WM1_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */ 6000 #define DSPFW_SPRITEF_WM1_HI_SHIFT 23 6001 #define DSPFW_SPRITEF_WM1_HI_MASK (1 << 23) 6002 #define DSPFW_SPRITEE_WM1_HI_SHIFT 22 6003 #define DSPFW_SPRITEE_WM1_HI_MASK (1 << 22) 6004 #define DSPFW_PLANEC_WM1_HI_SHIFT 21 6005 #define DSPFW_PLANEC_WM1_HI_MASK (1 << 21) 6006 #define DSPFW_SPRITED_WM1_HI_SHIFT 20 6007 #define DSPFW_SPRITED_WM1_HI_MASK (1 << 20) 6008 #define DSPFW_SPRITEC_WM1_HI_SHIFT 16 6009 #define DSPFW_SPRITEC_WM1_HI_MASK (1 << 16) 6010 #define DSPFW_PLANEB_WM1_HI_SHIFT 12 6011 #define DSPFW_PLANEB_WM1_HI_MASK (1 << 12) 6012 #define DSPFW_SPRITEB_WM1_HI_SHIFT 8 6013 #define DSPFW_SPRITEB_WM1_HI_MASK (1 << 8) 6014 #define DSPFW_SPRITEA_WM1_HI_SHIFT 4 6015 #define DSPFW_SPRITEA_WM1_HI_MASK (1 << 4) 6016 #define DSPFW_PLANEA_WM1_HI_SHIFT 0 6017 #define DSPFW_PLANEA_WM1_HI_MASK (1 << 0) 6018 6019 /* drain latency register values*/ 6020 #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe)) 6021 #define DDL_CURSOR_SHIFT 24 6022 #define DDL_SPRITE_SHIFT(sprite) (8 + 8 * (sprite)) 6023 #define DDL_PLANE_SHIFT 0 6024 #define DDL_PRECISION_HIGH (1 << 7) 6025 #define DDL_PRECISION_LOW (0 << 7) 6026 #define DRAIN_LATENCY_MASK 0x7f 6027 6028 #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400) 6029 #define CBR_PND_DEADLINE_DISABLE (1 << 31) 6030 #define CBR_PWM_CLOCK_MUX_SELECT (1 << 30) 6031 6032 #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450) 6033 #define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */ 6034 6035 /* FIFO watermark sizes etc */ 6036 #define G4X_FIFO_LINE_SIZE 64 6037 #define I915_FIFO_LINE_SIZE 64 6038 #define I830_FIFO_LINE_SIZE 32 6039 6040 #define VALLEYVIEW_FIFO_SIZE 255 6041 #define G4X_FIFO_SIZE 127 6042 #define I965_FIFO_SIZE 512 6043 #define I945_FIFO_SIZE 127 6044 #define I915_FIFO_SIZE 95 6045 #define I855GM_FIFO_SIZE 127 /* In cachelines */ 6046 #define I830_FIFO_SIZE 95 6047 6048 #define VALLEYVIEW_MAX_WM 0xff 6049 #define G4X_MAX_WM 0x3f 6050 #define I915_MAX_WM 0x3f 6051 6052 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ 6053 #define PINEVIEW_FIFO_LINE_SIZE 64 6054 #define PINEVIEW_MAX_WM 0x1ff 6055 #define PINEVIEW_DFT_WM 0x3f 6056 #define PINEVIEW_DFT_HPLLOFF_WM 0 6057 #define PINEVIEW_GUARD_WM 10 6058 #define PINEVIEW_CURSOR_FIFO 64 6059 #define PINEVIEW_CURSOR_MAX_WM 0x3f 6060 #define PINEVIEW_CURSOR_DFT_WM 0 6061 #define PINEVIEW_CURSOR_GUARD_WM 5 6062 6063 #define VALLEYVIEW_CURSOR_MAX_WM 64 6064 #define I965_CURSOR_FIFO 64 6065 #define I965_CURSOR_MAX_WM 32 6066 #define I965_CURSOR_DFT_WM 8 6067 6068 /* Watermark register definitions for SKL */ 6069 #define _CUR_WM_A_0 0x70140 6070 #define _CUR_WM_B_0 0x71140 6071 #define _PLANE_WM_1_A_0 0x70240 6072 #define _PLANE_WM_1_B_0 0x71240 6073 #define _PLANE_WM_2_A_0 0x70340 6074 #define _PLANE_WM_2_B_0 0x71340 6075 #define _PLANE_WM_TRANS_1_A_0 0x70268 6076 #define _PLANE_WM_TRANS_1_B_0 0x71268 6077 #define _PLANE_WM_TRANS_2_A_0 0x70368 6078 #define _PLANE_WM_TRANS_2_B_0 0x71368 6079 #define _CUR_WM_TRANS_A_0 0x70168 6080 #define _CUR_WM_TRANS_B_0 0x71168 6081 #define PLANE_WM_EN (1 << 31) 6082 #define PLANE_WM_IGNORE_LINES (1 << 30) 6083 #define PLANE_WM_LINES_SHIFT 14 6084 #define PLANE_WM_LINES_MASK 0x1f 6085 #define PLANE_WM_BLOCKS_MASK 0x7ff /* skl+: 10 bits, icl+ 11 bits */ 6086 6087 #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0) 6088 #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level))) 6089 #define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0) 6090 6091 #define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0) 6092 #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0) 6093 #define _PLANE_WM_BASE(pipe, plane) \ 6094 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe)) 6095 #define PLANE_WM(pipe, plane, level) \ 6096 _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level))) 6097 #define _PLANE_WM_TRANS_1(pipe) \ 6098 _PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0) 6099 #define _PLANE_WM_TRANS_2(pipe) \ 6100 _PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0) 6101 #define PLANE_WM_TRANS(pipe, plane) \ 6102 _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))) 6103 6104 /* define the Watermark register on Ironlake */ 6105 #define WM0_PIPEA_ILK _MMIO(0x45100) 6106 #define WM0_PIPE_PLANE_MASK (0xffff << 16) 6107 #define WM0_PIPE_PLANE_SHIFT 16 6108 #define WM0_PIPE_SPRITE_MASK (0xff << 8) 6109 #define WM0_PIPE_SPRITE_SHIFT 8 6110 #define WM0_PIPE_CURSOR_MASK (0xff) 6111 6112 #define WM0_PIPEB_ILK _MMIO(0x45104) 6113 #define WM0_PIPEC_IVB _MMIO(0x45200) 6114 #define WM1_LP_ILK _MMIO(0x45108) 6115 #define WM1_LP_SR_EN (1 << 31) 6116 #define WM1_LP_LATENCY_SHIFT 24 6117 #define WM1_LP_LATENCY_MASK (0x7f << 24) 6118 #define WM1_LP_FBC_MASK (0xf << 20) 6119 #define WM1_LP_FBC_SHIFT 20 6120 #define WM1_LP_FBC_SHIFT_BDW 19 6121 #define WM1_LP_SR_MASK (0x7ff << 8) 6122 #define WM1_LP_SR_SHIFT 8 6123 #define WM1_LP_CURSOR_MASK (0xff) 6124 #define WM2_LP_ILK _MMIO(0x4510c) 6125 #define WM2_LP_EN (1 << 31) 6126 #define WM3_LP_ILK _MMIO(0x45110) 6127 #define WM3_LP_EN (1 << 31) 6128 #define WM1S_LP_ILK _MMIO(0x45120) 6129 #define WM2S_LP_IVB _MMIO(0x45124) 6130 #define WM3S_LP_IVB _MMIO(0x45128) 6131 #define WM1S_LP_EN (1 << 31) 6132 6133 #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \ 6134 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \ 6135 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur)) 6136 6137 /* Memory latency timer register */ 6138 #define MLTR_ILK _MMIO(0x11222) 6139 #define MLTR_WM1_SHIFT 0 6140 #define MLTR_WM2_SHIFT 8 6141 /* the unit of memory self-refresh latency time is 0.5us */ 6142 #define ILK_SRLT_MASK 0x3f 6143 6144 6145 /* the address where we get all kinds of latency value */ 6146 #define SSKPD _MMIO(0x5d10) 6147 #define SSKPD_WM_MASK 0x3f 6148 #define SSKPD_WM0_SHIFT 0 6149 #define SSKPD_WM1_SHIFT 8 6150 #define SSKPD_WM2_SHIFT 16 6151 #define SSKPD_WM3_SHIFT 24 6152 6153 /* 6154 * The two pipe frame counter registers are not synchronized, so 6155 * reading a stable value is somewhat tricky. The following code 6156 * should work: 6157 * 6158 * do { 6159 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 6160 * PIPE_FRAME_HIGH_SHIFT; 6161 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 6162 * PIPE_FRAME_LOW_SHIFT); 6163 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 6164 * PIPE_FRAME_HIGH_SHIFT); 6165 * } while (high1 != high2); 6166 * frame = (high1 << 8) | low1; 6167 */ 6168 #define _PIPEAFRAMEHIGH 0x70040 6169 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 6170 #define PIPE_FRAME_HIGH_SHIFT 0 6171 #define _PIPEAFRAMEPIXEL 0x70044 6172 #define PIPE_FRAME_LOW_MASK 0xff000000 6173 #define PIPE_FRAME_LOW_SHIFT 24 6174 #define PIPE_PIXEL_MASK 0x00ffffff 6175 #define PIPE_PIXEL_SHIFT 0 6176 /* GM45+ just has to be different */ 6177 #define _PIPEA_FRMCOUNT_G4X 0x70040 6178 #define _PIPEA_FLIPCOUNT_G4X 0x70044 6179 #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X) 6180 #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X) 6181 6182 /* Cursor A & B regs */ 6183 #define _CURACNTR 0x70080 6184 /* Old style CUR*CNTR flags (desktop 8xx) */ 6185 #define CURSOR_ENABLE 0x80000000 6186 #define CURSOR_GAMMA_ENABLE 0x40000000 6187 #define CURSOR_STRIDE_SHIFT 28 6188 #define CURSOR_STRIDE(x) ((ffs(x) - 9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */ 6189 #define CURSOR_FORMAT_SHIFT 24 6190 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) 6191 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) 6192 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) 6193 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) 6194 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) 6195 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) 6196 /* New style CUR*CNTR flags */ 6197 #define MCURSOR_MODE 0x27 6198 #define MCURSOR_MODE_DISABLE 0x00 6199 #define MCURSOR_MODE_128_32B_AX 0x02 6200 #define MCURSOR_MODE_256_32B_AX 0x03 6201 #define MCURSOR_MODE_64_32B_AX 0x07 6202 #define MCURSOR_MODE_128_ARGB_AX ((1 << 5) | MCURSOR_MODE_128_32B_AX) 6203 #define MCURSOR_MODE_256_ARGB_AX ((1 << 5) | MCURSOR_MODE_256_32B_AX) 6204 #define MCURSOR_MODE_64_ARGB_AX ((1 << 5) | MCURSOR_MODE_64_32B_AX) 6205 #define MCURSOR_PIPE_SELECT_MASK (0x3 << 28) 6206 #define MCURSOR_PIPE_SELECT_SHIFT 28 6207 #define MCURSOR_PIPE_SELECT(pipe) ((pipe) << 28) 6208 #define MCURSOR_GAMMA_ENABLE (1 << 26) 6209 #define MCURSOR_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */ 6210 #define MCURSOR_ROTATE_180 (1 << 15) 6211 #define MCURSOR_TRICKLE_FEED_DISABLE (1 << 14) 6212 #define _CURABASE 0x70084 6213 #define _CURAPOS 0x70088 6214 #define CURSOR_POS_MASK 0x007FF 6215 #define CURSOR_POS_SIGN 0x8000 6216 #define CURSOR_X_SHIFT 0 6217 #define CURSOR_Y_SHIFT 16 6218 #define CURSIZE _MMIO(0x700a0) /* 845/865 */ 6219 #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */ 6220 #define CUR_FBC_CTL_EN (1 << 31) 6221 #define _CURASURFLIVE 0x700ac /* g4x+ */ 6222 #define _CURBCNTR 0x700c0 6223 #define _CURBBASE 0x700c4 6224 #define _CURBPOS 0x700c8 6225 6226 #define _CURBCNTR_IVB 0x71080 6227 #define _CURBBASE_IVB 0x71084 6228 #define _CURBPOS_IVB 0x71088 6229 6230 #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR) 6231 #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE) 6232 #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS) 6233 #define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A) 6234 #define CURSURFLIVE(pipe) _CURSOR2(pipe, _CURASURFLIVE) 6235 6236 #define CURSOR_A_OFFSET 0x70080 6237 #define CURSOR_B_OFFSET 0x700c0 6238 #define CHV_CURSOR_C_OFFSET 0x700e0 6239 #define IVB_CURSOR_B_OFFSET 0x71080 6240 #define IVB_CURSOR_C_OFFSET 0x72080 6241 6242 /* Display A control */ 6243 #define _DSPACNTR 0x70180 6244 #define DISPLAY_PLANE_ENABLE (1 << 31) 6245 #define DISPLAY_PLANE_DISABLE 0 6246 #define DISPPLANE_GAMMA_ENABLE (1 << 30) 6247 #define DISPPLANE_GAMMA_DISABLE 0 6248 #define DISPPLANE_PIXFORMAT_MASK (0xf << 26) 6249 #define DISPPLANE_YUV422 (0x0 << 26) 6250 #define DISPPLANE_8BPP (0x2 << 26) 6251 #define DISPPLANE_BGRA555 (0x3 << 26) 6252 #define DISPPLANE_BGRX555 (0x4 << 26) 6253 #define DISPPLANE_BGRX565 (0x5 << 26) 6254 #define DISPPLANE_BGRX888 (0x6 << 26) 6255 #define DISPPLANE_BGRA888 (0x7 << 26) 6256 #define DISPPLANE_RGBX101010 (0x8 << 26) 6257 #define DISPPLANE_RGBA101010 (0x9 << 26) 6258 #define DISPPLANE_BGRX101010 (0xa << 26) 6259 #define DISPPLANE_RGBX161616 (0xc << 26) 6260 #define DISPPLANE_RGBX888 (0xe << 26) 6261 #define DISPPLANE_RGBA888 (0xf << 26) 6262 #define DISPPLANE_STEREO_ENABLE (1 << 25) 6263 #define DISPPLANE_STEREO_DISABLE 0 6264 #define DISPPLANE_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */ 6265 #define DISPPLANE_SEL_PIPE_SHIFT 24 6266 #define DISPPLANE_SEL_PIPE_MASK (3 << DISPPLANE_SEL_PIPE_SHIFT) 6267 #define DISPPLANE_SEL_PIPE(pipe) ((pipe) << DISPPLANE_SEL_PIPE_SHIFT) 6268 #define DISPPLANE_SRC_KEY_ENABLE (1 << 22) 6269 #define DISPPLANE_SRC_KEY_DISABLE 0 6270 #define DISPPLANE_LINE_DOUBLE (1 << 20) 6271 #define DISPPLANE_NO_LINE_DOUBLE 0 6272 #define DISPPLANE_STEREO_POLARITY_FIRST 0 6273 #define DISPPLANE_STEREO_POLARITY_SECOND (1 << 18) 6274 #define DISPPLANE_ALPHA_PREMULTIPLY (1 << 16) /* CHV pipe B */ 6275 #define DISPPLANE_ROTATE_180 (1 << 15) 6276 #define DISPPLANE_TRICKLE_FEED_DISABLE (1 << 14) /* Ironlake */ 6277 #define DISPPLANE_TILED (1 << 10) 6278 #define DISPPLANE_MIRROR (1 << 8) /* CHV pipe B */ 6279 #define _DSPAADDR 0x70184 6280 #define _DSPASTRIDE 0x70188 6281 #define _DSPAPOS 0x7018C /* reserved */ 6282 #define _DSPASIZE 0x70190 6283 #define _DSPASURF 0x7019C /* 965+ only */ 6284 #define _DSPATILEOFF 0x701A4 /* 965+ only */ 6285 #define _DSPAOFFSET 0x701A4 /* HSW */ 6286 #define _DSPASURFLIVE 0x701AC 6287 6288 #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR) 6289 #define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR) 6290 #define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE) 6291 #define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS) 6292 #define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE) 6293 #define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF) 6294 #define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF) 6295 #define DSPLINOFF(plane) DSPADDR(plane) 6296 #define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET) 6297 #define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE) 6298 6299 /* CHV pipe B blender and primary plane */ 6300 #define _CHV_BLEND_A 0x60a00 6301 #define CHV_BLEND_LEGACY (0 << 30) 6302 #define CHV_BLEND_ANDROID (1 << 30) 6303 #define CHV_BLEND_MPO (2 << 30) 6304 #define CHV_BLEND_MASK (3 << 30) 6305 #define _CHV_CANVAS_A 0x60a04 6306 #define _PRIMPOS_A 0x60a08 6307 #define _PRIMSIZE_A 0x60a0c 6308 #define _PRIMCNSTALPHA_A 0x60a10 6309 #define PRIM_CONST_ALPHA_ENABLE (1 << 31) 6310 6311 #define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A) 6312 #define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A) 6313 #define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A) 6314 #define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A) 6315 #define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A) 6316 6317 /* Display/Sprite base address macros */ 6318 #define DISP_BASEADDR_MASK (0xfffff000) 6319 #define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK) 6320 #define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK) 6321 6322 /* 6323 * VBIOS flags 6324 * gen2: 6325 * [00:06] alm,mgm 6326 * [10:16] all 6327 * [30:32] alm,mgm 6328 * gen3+: 6329 * [00:0f] all 6330 * [10:1f] all 6331 * [30:32] all 6332 */ 6333 #define SWF0(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4) 6334 #define SWF1(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4) 6335 #define SWF3(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4) 6336 #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) 6337 6338 /* Pipe B */ 6339 #define _PIPEBDSL (DISPLAY_MMIO_BASE(dev_priv) + 0x71000) 6340 #define _PIPEBCONF (DISPLAY_MMIO_BASE(dev_priv) + 0x71008) 6341 #define _PIPEBSTAT (DISPLAY_MMIO_BASE(dev_priv) + 0x71024) 6342 #define _PIPEBFRAMEHIGH 0x71040 6343 #define _PIPEBFRAMEPIXEL 0x71044 6344 #define _PIPEB_FRMCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71040) 6345 #define _PIPEB_FLIPCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71044) 6346 6347 6348 /* Display B control */ 6349 #define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180) 6350 #define DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15) 6351 #define DISPPLANE_ALPHA_TRANS_DISABLE 0 6352 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 6353 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 6354 #define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184) 6355 #define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188) 6356 #define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C) 6357 #define _DSPBSIZE (DISPLAY_MMIO_BASE(dev_priv) + 0x71190) 6358 #define _DSPBSURF (DISPLAY_MMIO_BASE(dev_priv) + 0x7119C) 6359 #define _DSPBTILEOFF (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) 6360 #define _DSPBOFFSET (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) 6361 #define _DSPBSURFLIVE (DISPLAY_MMIO_BASE(dev_priv) + 0x711AC) 6362 6363 /* ICL DSI 0 and 1 */ 6364 #define _PIPEDSI0CONF 0x7b008 6365 #define _PIPEDSI1CONF 0x7b808 6366 6367 /* Sprite A control */ 6368 #define _DVSACNTR 0x72180 6369 #define DVS_ENABLE (1 << 31) 6370 #define DVS_GAMMA_ENABLE (1 << 30) 6371 #define DVS_YUV_RANGE_CORRECTION_DISABLE (1 << 27) 6372 #define DVS_PIXFORMAT_MASK (3 << 25) 6373 #define DVS_FORMAT_YUV422 (0 << 25) 6374 #define DVS_FORMAT_RGBX101010 (1 << 25) 6375 #define DVS_FORMAT_RGBX888 (2 << 25) 6376 #define DVS_FORMAT_RGBX161616 (3 << 25) 6377 #define DVS_PIPE_CSC_ENABLE (1 << 24) 6378 #define DVS_SOURCE_KEY (1 << 22) 6379 #define DVS_RGB_ORDER_XBGR (1 << 20) 6380 #define DVS_YUV_FORMAT_BT709 (1 << 18) 6381 #define DVS_YUV_BYTE_ORDER_MASK (3 << 16) 6382 #define DVS_YUV_ORDER_YUYV (0 << 16) 6383 #define DVS_YUV_ORDER_UYVY (1 << 16) 6384 #define DVS_YUV_ORDER_YVYU (2 << 16) 6385 #define DVS_YUV_ORDER_VYUY (3 << 16) 6386 #define DVS_ROTATE_180 (1 << 15) 6387 #define DVS_DEST_KEY (1 << 2) 6388 #define DVS_TRICKLE_FEED_DISABLE (1 << 14) 6389 #define DVS_TILED (1 << 10) 6390 #define _DVSALINOFF 0x72184 6391 #define _DVSASTRIDE 0x72188 6392 #define _DVSAPOS 0x7218c 6393 #define _DVSASIZE 0x72190 6394 #define _DVSAKEYVAL 0x72194 6395 #define _DVSAKEYMSK 0x72198 6396 #define _DVSASURF 0x7219c 6397 #define _DVSAKEYMAXVAL 0x721a0 6398 #define _DVSATILEOFF 0x721a4 6399 #define _DVSASURFLIVE 0x721ac 6400 #define _DVSASCALE 0x72204 6401 #define DVS_SCALE_ENABLE (1 << 31) 6402 #define DVS_FILTER_MASK (3 << 29) 6403 #define DVS_FILTER_MEDIUM (0 << 29) 6404 #define DVS_FILTER_ENHANCING (1 << 29) 6405 #define DVS_FILTER_SOFTENING (2 << 29) 6406 #define DVS_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */ 6407 #define DVS_VERTICAL_OFFSET_ENABLE (1 << 27) 6408 #define _DVSAGAMC 0x72300 6409 6410 #define _DVSBCNTR 0x73180 6411 #define _DVSBLINOFF 0x73184 6412 #define _DVSBSTRIDE 0x73188 6413 #define _DVSBPOS 0x7318c 6414 #define _DVSBSIZE 0x73190 6415 #define _DVSBKEYVAL 0x73194 6416 #define _DVSBKEYMSK 0x73198 6417 #define _DVSBSURF 0x7319c 6418 #define _DVSBKEYMAXVAL 0x731a0 6419 #define _DVSBTILEOFF 0x731a4 6420 #define _DVSBSURFLIVE 0x731ac 6421 #define _DVSBSCALE 0x73204 6422 #define _DVSBGAMC 0x73300 6423 6424 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR) 6425 #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) 6426 #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) 6427 #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS) 6428 #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF) 6429 #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) 6430 #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE) 6431 #define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE) 6432 #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) 6433 #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) 6434 #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) 6435 #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) 6436 6437 #define _SPRA_CTL 0x70280 6438 #define SPRITE_ENABLE (1 << 31) 6439 #define SPRITE_GAMMA_ENABLE (1 << 30) 6440 #define SPRITE_YUV_RANGE_CORRECTION_DISABLE (1 << 28) 6441 #define SPRITE_PIXFORMAT_MASK (7 << 25) 6442 #define SPRITE_FORMAT_YUV422 (0 << 25) 6443 #define SPRITE_FORMAT_RGBX101010 (1 << 25) 6444 #define SPRITE_FORMAT_RGBX888 (2 << 25) 6445 #define SPRITE_FORMAT_RGBX161616 (3 << 25) 6446 #define SPRITE_FORMAT_YUV444 (4 << 25) 6447 #define SPRITE_FORMAT_XR_BGR101010 (5 << 25) /* Extended range */ 6448 #define SPRITE_PIPE_CSC_ENABLE (1 << 24) 6449 #define SPRITE_SOURCE_KEY (1 << 22) 6450 #define SPRITE_RGB_ORDER_RGBX (1 << 20) /* only for 888 and 161616 */ 6451 #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1 << 19) 6452 #define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18) /* 0 is BT601 */ 6453 #define SPRITE_YUV_BYTE_ORDER_MASK (3 << 16) 6454 #define SPRITE_YUV_ORDER_YUYV (0 << 16) 6455 #define SPRITE_YUV_ORDER_UYVY (1 << 16) 6456 #define SPRITE_YUV_ORDER_YVYU (2 << 16) 6457 #define SPRITE_YUV_ORDER_VYUY (3 << 16) 6458 #define SPRITE_ROTATE_180 (1 << 15) 6459 #define SPRITE_TRICKLE_FEED_DISABLE (1 << 14) 6460 #define SPRITE_INT_GAMMA_ENABLE (1 << 13) 6461 #define SPRITE_TILED (1 << 10) 6462 #define SPRITE_DEST_KEY (1 << 2) 6463 #define _SPRA_LINOFF 0x70284 6464 #define _SPRA_STRIDE 0x70288 6465 #define _SPRA_POS 0x7028c 6466 #define _SPRA_SIZE 0x70290 6467 #define _SPRA_KEYVAL 0x70294 6468 #define _SPRA_KEYMSK 0x70298 6469 #define _SPRA_SURF 0x7029c 6470 #define _SPRA_KEYMAX 0x702a0 6471 #define _SPRA_TILEOFF 0x702a4 6472 #define _SPRA_OFFSET 0x702a4 6473 #define _SPRA_SURFLIVE 0x702ac 6474 #define _SPRA_SCALE 0x70304 6475 #define SPRITE_SCALE_ENABLE (1 << 31) 6476 #define SPRITE_FILTER_MASK (3 << 29) 6477 #define SPRITE_FILTER_MEDIUM (0 << 29) 6478 #define SPRITE_FILTER_ENHANCING (1 << 29) 6479 #define SPRITE_FILTER_SOFTENING (2 << 29) 6480 #define SPRITE_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */ 6481 #define SPRITE_VERTICAL_OFFSET_ENABLE (1 << 27) 6482 #define _SPRA_GAMC 0x70400 6483 6484 #define _SPRB_CTL 0x71280 6485 #define _SPRB_LINOFF 0x71284 6486 #define _SPRB_STRIDE 0x71288 6487 #define _SPRB_POS 0x7128c 6488 #define _SPRB_SIZE 0x71290 6489 #define _SPRB_KEYVAL 0x71294 6490 #define _SPRB_KEYMSK 0x71298 6491 #define _SPRB_SURF 0x7129c 6492 #define _SPRB_KEYMAX 0x712a0 6493 #define _SPRB_TILEOFF 0x712a4 6494 #define _SPRB_OFFSET 0x712a4 6495 #define _SPRB_SURFLIVE 0x712ac 6496 #define _SPRB_SCALE 0x71304 6497 #define _SPRB_GAMC 0x71400 6498 6499 #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL) 6500 #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) 6501 #define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) 6502 #define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS) 6503 #define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) 6504 #define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) 6505 #define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) 6506 #define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF) 6507 #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) 6508 #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) 6509 #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) 6510 #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) 6511 #define SPRGAMC(pipe) _MMIO_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) 6512 #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) 6513 6514 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) 6515 #define SP_ENABLE (1 << 31) 6516 #define SP_GAMMA_ENABLE (1 << 30) 6517 #define SP_PIXFORMAT_MASK (0xf << 26) 6518 #define SP_FORMAT_YUV422 (0 << 26) 6519 #define SP_FORMAT_BGR565 (5 << 26) 6520 #define SP_FORMAT_BGRX8888 (6 << 26) 6521 #define SP_FORMAT_BGRA8888 (7 << 26) 6522 #define SP_FORMAT_RGBX1010102 (8 << 26) 6523 #define SP_FORMAT_RGBA1010102 (9 << 26) 6524 #define SP_FORMAT_RGBX8888 (0xe << 26) 6525 #define SP_FORMAT_RGBA8888 (0xf << 26) 6526 #define SP_ALPHA_PREMULTIPLY (1 << 23) /* CHV pipe B */ 6527 #define SP_SOURCE_KEY (1 << 22) 6528 #define SP_YUV_FORMAT_BT709 (1 << 18) 6529 #define SP_YUV_BYTE_ORDER_MASK (3 << 16) 6530 #define SP_YUV_ORDER_YUYV (0 << 16) 6531 #define SP_YUV_ORDER_UYVY (1 << 16) 6532 #define SP_YUV_ORDER_YVYU (2 << 16) 6533 #define SP_YUV_ORDER_VYUY (3 << 16) 6534 #define SP_ROTATE_180 (1 << 15) 6535 #define SP_TILED (1 << 10) 6536 #define SP_MIRROR (1 << 8) /* CHV pipe B */ 6537 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) 6538 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) 6539 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c) 6540 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190) 6541 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194) 6542 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198) 6543 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c) 6544 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0) 6545 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4) 6546 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) 6547 #define SP_CONST_ALPHA_ENABLE (1 << 31) 6548 #define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0) 6549 #define SP_CONTRAST(x) ((x) << 18) /* u3.6 */ 6550 #define SP_BRIGHTNESS(x) ((x) & 0xff) /* s8 */ 6551 #define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4) 6552 #define SP_SH_SIN(x) (((x) & 0x7ff) << 16) /* s4.7 */ 6553 #define SP_SH_COS(x) (x) /* u3.7 */ 6554 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4) 6555 6556 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) 6557 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) 6558 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) 6559 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c) 6560 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) 6561 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294) 6562 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) 6563 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) 6564 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) 6565 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) 6566 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) 6567 #define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0) 6568 #define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4) 6569 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4) 6570 6571 #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \ 6572 _MMIO_PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b)) 6573 6574 #define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR) 6575 #define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF) 6576 #define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE) 6577 #define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS) 6578 #define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE) 6579 #define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL) 6580 #define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK) 6581 #define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF) 6582 #define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL) 6583 #define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF) 6584 #define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA) 6585 #define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0) 6586 #define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1) 6587 #define SPGAMC(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) 6588 6589 /* 6590 * CHV pipe B sprite CSC 6591 * 6592 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff| 6593 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff| 6594 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff| 6595 */ 6596 #define _MMIO_CHV_SPCSC(plane_id, reg) \ 6597 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg)) 6598 6599 #define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900) 6600 #define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904) 6601 #define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908) 6602 #define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */ 6603 #define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */ 6604 6605 #define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c) 6606 #define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910) 6607 #define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914) 6608 #define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918) 6609 #define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c) 6610 #define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */ 6611 #define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */ 6612 6613 #define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920) 6614 #define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924) 6615 #define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928) 6616 #define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */ 6617 #define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */ 6618 6619 #define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c) 6620 #define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930) 6621 #define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934) 6622 #define SPCSC_OMAX(x) ((x) << 16) /* u10 */ 6623 #define SPCSC_OMIN(x) ((x) << 0) /* u10 */ 6624 6625 /* Skylake plane registers */ 6626 6627 #define _PLANE_CTL_1_A 0x70180 6628 #define _PLANE_CTL_2_A 0x70280 6629 #define _PLANE_CTL_3_A 0x70380 6630 #define PLANE_CTL_ENABLE (1 << 31) 6631 #define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-GLK */ 6632 #define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE (1 << 28) 6633 /* 6634 * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition 6635 * expanded to include bit 23 as well. However, the shift-24 based values 6636 * correctly map to the same formats in ICL, as long as bit 23 is set to 0 6637 */ 6638 #define PLANE_CTL_FORMAT_MASK (0xf << 24) 6639 #define PLANE_CTL_FORMAT_YUV422 (0 << 24) 6640 #define PLANE_CTL_FORMAT_NV12 (1 << 24) 6641 #define PLANE_CTL_FORMAT_XRGB_2101010 (2 << 24) 6642 #define PLANE_CTL_FORMAT_P010 (3 << 24) 6643 #define PLANE_CTL_FORMAT_XRGB_8888 (4 << 24) 6644 #define PLANE_CTL_FORMAT_P012 (5 << 24) 6645 #define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24) 6646 #define PLANE_CTL_FORMAT_P016 (7 << 24) 6647 #define PLANE_CTL_FORMAT_AYUV (8 << 24) 6648 #define PLANE_CTL_FORMAT_INDEXED (12 << 24) 6649 #define PLANE_CTL_FORMAT_RGB_565 (14 << 24) 6650 #define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23) 6651 #define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) /* Pre-GLK */ 6652 #define PLANE_CTL_FORMAT_Y210 (1 << 23) 6653 #define PLANE_CTL_FORMAT_Y212 (3 << 23) 6654 #define PLANE_CTL_FORMAT_Y216 (5 << 23) 6655 #define PLANE_CTL_FORMAT_Y410 (7 << 23) 6656 #define PLANE_CTL_FORMAT_Y412 (9 << 23) 6657 #define PLANE_CTL_FORMAT_Y416 (0xb << 23) 6658 #define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21) 6659 #define PLANE_CTL_KEY_ENABLE_SOURCE (1 << 21) 6660 #define PLANE_CTL_KEY_ENABLE_DESTINATION (2 << 21) 6661 #define PLANE_CTL_ORDER_BGRX (0 << 20) 6662 #define PLANE_CTL_ORDER_RGBX (1 << 20) 6663 #define PLANE_CTL_YUV420_Y_PLANE (1 << 19) 6664 #define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18) 6665 #define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16) 6666 #define PLANE_CTL_YUV422_YUYV (0 << 16) 6667 #define PLANE_CTL_YUV422_UYVY (1 << 16) 6668 #define PLANE_CTL_YUV422_YVYU (2 << 16) 6669 #define PLANE_CTL_YUV422_VYUY (3 << 16) 6670 #define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE (1 << 15) 6671 #define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14) 6672 #define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) /* Pre-GLK */ 6673 #define PLANE_CTL_TILED_MASK (0x7 << 10) 6674 #define PLANE_CTL_TILED_LINEAR (0 << 10) 6675 #define PLANE_CTL_TILED_X (1 << 10) 6676 #define PLANE_CTL_TILED_Y (4 << 10) 6677 #define PLANE_CTL_TILED_YF (5 << 10) 6678 #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8) 6679 #define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */ 6680 #define PLANE_CTL_ALPHA_DISABLE (0 << 4) 6681 #define PLANE_CTL_ALPHA_SW_PREMULTIPLY (2 << 4) 6682 #define PLANE_CTL_ALPHA_HW_PREMULTIPLY (3 << 4) 6683 #define PLANE_CTL_ROTATE_MASK 0x3 6684 #define PLANE_CTL_ROTATE_0 0x0 6685 #define PLANE_CTL_ROTATE_90 0x1 6686 #define PLANE_CTL_ROTATE_180 0x2 6687 #define PLANE_CTL_ROTATE_270 0x3 6688 #define _PLANE_STRIDE_1_A 0x70188 6689 #define _PLANE_STRIDE_2_A 0x70288 6690 #define _PLANE_STRIDE_3_A 0x70388 6691 #define _PLANE_POS_1_A 0x7018c 6692 #define _PLANE_POS_2_A 0x7028c 6693 #define _PLANE_POS_3_A 0x7038c 6694 #define _PLANE_SIZE_1_A 0x70190 6695 #define _PLANE_SIZE_2_A 0x70290 6696 #define _PLANE_SIZE_3_A 0x70390 6697 #define _PLANE_SURF_1_A 0x7019c 6698 #define _PLANE_SURF_2_A 0x7029c 6699 #define _PLANE_SURF_3_A 0x7039c 6700 #define _PLANE_OFFSET_1_A 0x701a4 6701 #define _PLANE_OFFSET_2_A 0x702a4 6702 #define _PLANE_OFFSET_3_A 0x703a4 6703 #define _PLANE_KEYVAL_1_A 0x70194 6704 #define _PLANE_KEYVAL_2_A 0x70294 6705 #define _PLANE_KEYMSK_1_A 0x70198 6706 #define _PLANE_KEYMSK_2_A 0x70298 6707 #define PLANE_KEYMSK_ALPHA_ENABLE (1 << 31) 6708 #define _PLANE_KEYMAX_1_A 0x701a0 6709 #define _PLANE_KEYMAX_2_A 0x702a0 6710 #define PLANE_KEYMAX_ALPHA(a) ((a) << 24) 6711 #define _PLANE_AUX_DIST_1_A 0x701c0 6712 #define _PLANE_AUX_DIST_2_A 0x702c0 6713 #define _PLANE_AUX_OFFSET_1_A 0x701c4 6714 #define _PLANE_AUX_OFFSET_2_A 0x702c4 6715 #define _PLANE_CUS_CTL_1_A 0x701c8 6716 #define _PLANE_CUS_CTL_2_A 0x702c8 6717 #define PLANE_CUS_ENABLE (1 << 31) 6718 #define PLANE_CUS_PLANE_6 (0 << 30) 6719 #define PLANE_CUS_PLANE_7 (1 << 30) 6720 #define PLANE_CUS_HPHASE_SIGN_NEGATIVE (1 << 19) 6721 #define PLANE_CUS_HPHASE_0 (0 << 16) 6722 #define PLANE_CUS_HPHASE_0_25 (1 << 16) 6723 #define PLANE_CUS_HPHASE_0_5 (2 << 16) 6724 #define PLANE_CUS_VPHASE_SIGN_NEGATIVE (1 << 15) 6725 #define PLANE_CUS_VPHASE_0 (0 << 12) 6726 #define PLANE_CUS_VPHASE_0_25 (1 << 12) 6727 #define PLANE_CUS_VPHASE_0_5 (2 << 12) 6728 #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */ 6729 #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */ 6730 #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */ 6731 #define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */ 6732 #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28) 6733 #define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */ 6734 #define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */ 6735 #define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17) 6736 #define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709 (1 << 17) 6737 #define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 (2 << 17) 6738 #define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 (3 << 17) 6739 #define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 (4 << 17) 6740 #define PLANE_COLOR_PLANE_GAMMA_DISABLE (1 << 13) 6741 #define PLANE_COLOR_ALPHA_MASK (0x3 << 4) 6742 #define PLANE_COLOR_ALPHA_DISABLE (0 << 4) 6743 #define PLANE_COLOR_ALPHA_SW_PREMULTIPLY (2 << 4) 6744 #define PLANE_COLOR_ALPHA_HW_PREMULTIPLY (3 << 4) 6745 #define _PLANE_BUF_CFG_1_A 0x7027c 6746 #define _PLANE_BUF_CFG_2_A 0x7037c 6747 #define _PLANE_NV12_BUF_CFG_1_A 0x70278 6748 #define _PLANE_NV12_BUF_CFG_2_A 0x70378 6749 6750 /* Input CSC Register Definitions */ 6751 #define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0 6752 #define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0 6753 6754 #define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0 6755 #define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0 6756 6757 #define _PLANE_INPUT_CSC_RY_GY_1(pipe) \ 6758 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \ 6759 _PLANE_INPUT_CSC_RY_GY_1_B) 6760 #define _PLANE_INPUT_CSC_RY_GY_2(pipe) \ 6761 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \ 6762 _PLANE_INPUT_CSC_RY_GY_2_B) 6763 6764 #define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \ 6765 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \ 6766 _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4) 6767 6768 #define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8 6769 #define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8 6770 6771 #define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8 6772 #define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8 6773 6774 #define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \ 6775 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \ 6776 _PLANE_INPUT_CSC_PREOFF_HI_1_B) 6777 #define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \ 6778 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \ 6779 _PLANE_INPUT_CSC_PREOFF_HI_2_B) 6780 #define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \ 6781 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \ 6782 _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4) 6783 6784 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204 6785 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304 6786 6787 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204 6788 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304 6789 6790 #define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \ 6791 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \ 6792 _PLANE_INPUT_CSC_POSTOFF_HI_1_B) 6793 #define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \ 6794 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \ 6795 _PLANE_INPUT_CSC_POSTOFF_HI_2_B) 6796 #define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \ 6797 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \ 6798 _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4) 6799 6800 #define _PLANE_CTL_1_B 0x71180 6801 #define _PLANE_CTL_2_B 0x71280 6802 #define _PLANE_CTL_3_B 0x71380 6803 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) 6804 #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) 6805 #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B) 6806 #define PLANE_CTL(pipe, plane) \ 6807 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) 6808 6809 #define _PLANE_STRIDE_1_B 0x71188 6810 #define _PLANE_STRIDE_2_B 0x71288 6811 #define _PLANE_STRIDE_3_B 0x71388 6812 #define _PLANE_STRIDE_1(pipe) \ 6813 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) 6814 #define _PLANE_STRIDE_2(pipe) \ 6815 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) 6816 #define _PLANE_STRIDE_3(pipe) \ 6817 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B) 6818 #define PLANE_STRIDE(pipe, plane) \ 6819 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) 6820 6821 #define _PLANE_POS_1_B 0x7118c 6822 #define _PLANE_POS_2_B 0x7128c 6823 #define _PLANE_POS_3_B 0x7138c 6824 #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) 6825 #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) 6826 #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B) 6827 #define PLANE_POS(pipe, plane) \ 6828 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) 6829 6830 #define _PLANE_SIZE_1_B 0x71190 6831 #define _PLANE_SIZE_2_B 0x71290 6832 #define _PLANE_SIZE_3_B 0x71390 6833 #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) 6834 #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) 6835 #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B) 6836 #define PLANE_SIZE(pipe, plane) \ 6837 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) 6838 6839 #define _PLANE_SURF_1_B 0x7119c 6840 #define _PLANE_SURF_2_B 0x7129c 6841 #define _PLANE_SURF_3_B 0x7139c 6842 #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B) 6843 #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B) 6844 #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) 6845 #define PLANE_SURF(pipe, plane) \ 6846 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) 6847 6848 #define _PLANE_OFFSET_1_B 0x711a4 6849 #define _PLANE_OFFSET_2_B 0x712a4 6850 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B) 6851 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B) 6852 #define PLANE_OFFSET(pipe, plane) \ 6853 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe)) 6854 6855 #define _PLANE_KEYVAL_1_B 0x71194 6856 #define _PLANE_KEYVAL_2_B 0x71294 6857 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B) 6858 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) 6859 #define PLANE_KEYVAL(pipe, plane) \ 6860 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe)) 6861 6862 #define _PLANE_KEYMSK_1_B 0x71198 6863 #define _PLANE_KEYMSK_2_B 0x71298 6864 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B) 6865 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B) 6866 #define PLANE_KEYMSK(pipe, plane) \ 6867 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe)) 6868 6869 #define _PLANE_KEYMAX_1_B 0x711a0 6870 #define _PLANE_KEYMAX_2_B 0x712a0 6871 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B) 6872 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B) 6873 #define PLANE_KEYMAX(pipe, plane) \ 6874 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe)) 6875 6876 #define _PLANE_BUF_CFG_1_B 0x7127c 6877 #define _PLANE_BUF_CFG_2_B 0x7137c 6878 #define DDB_ENTRY_MASK 0x7FF /* skl+: 10 bits, icl+ 11 bits */ 6879 #define DDB_ENTRY_END_SHIFT 16 6880 #define _PLANE_BUF_CFG_1(pipe) \ 6881 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B) 6882 #define _PLANE_BUF_CFG_2(pipe) \ 6883 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B) 6884 #define PLANE_BUF_CFG(pipe, plane) \ 6885 _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe)) 6886 6887 #define _PLANE_NV12_BUF_CFG_1_B 0x71278 6888 #define _PLANE_NV12_BUF_CFG_2_B 0x71378 6889 #define _PLANE_NV12_BUF_CFG_1(pipe) \ 6890 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B) 6891 #define _PLANE_NV12_BUF_CFG_2(pipe) \ 6892 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B) 6893 #define PLANE_NV12_BUF_CFG(pipe, plane) \ 6894 _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe)) 6895 6896 #define _PLANE_AUX_DIST_1_B 0x711c0 6897 #define _PLANE_AUX_DIST_2_B 0x712c0 6898 #define _PLANE_AUX_DIST_1(pipe) \ 6899 _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B) 6900 #define _PLANE_AUX_DIST_2(pipe) \ 6901 _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B) 6902 #define PLANE_AUX_DIST(pipe, plane) \ 6903 _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe)) 6904 6905 #define _PLANE_AUX_OFFSET_1_B 0x711c4 6906 #define _PLANE_AUX_OFFSET_2_B 0x712c4 6907 #define _PLANE_AUX_OFFSET_1(pipe) \ 6908 _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B) 6909 #define _PLANE_AUX_OFFSET_2(pipe) \ 6910 _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B) 6911 #define PLANE_AUX_OFFSET(pipe, plane) \ 6912 _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe)) 6913 6914 #define _PLANE_CUS_CTL_1_B 0x711c8 6915 #define _PLANE_CUS_CTL_2_B 0x712c8 6916 #define _PLANE_CUS_CTL_1(pipe) \ 6917 _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B) 6918 #define _PLANE_CUS_CTL_2(pipe) \ 6919 _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B) 6920 #define PLANE_CUS_CTL(pipe, plane) \ 6921 _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe)) 6922 6923 #define _PLANE_COLOR_CTL_1_B 0x711CC 6924 #define _PLANE_COLOR_CTL_2_B 0x712CC 6925 #define _PLANE_COLOR_CTL_3_B 0x713CC 6926 #define _PLANE_COLOR_CTL_1(pipe) \ 6927 _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B) 6928 #define _PLANE_COLOR_CTL_2(pipe) \ 6929 _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B) 6930 #define PLANE_COLOR_CTL(pipe, plane) \ 6931 _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe)) 6932 6933 #/* SKL new cursor registers */ 6934 #define _CUR_BUF_CFG_A 0x7017c 6935 #define _CUR_BUF_CFG_B 0x7117c 6936 #define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) 6937 6938 /* VBIOS regs */ 6939 #define VGACNTRL _MMIO(0x71400) 6940 # define VGA_DISP_DISABLE (1 << 31) 6941 # define VGA_2X_MODE (1 << 30) 6942 # define VGA_PIPE_B_SELECT (1 << 29) 6943 6944 #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400) 6945 6946 /* Ironlake */ 6947 6948 #define CPU_VGACNTRL _MMIO(0x41000) 6949 6950 #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030) 6951 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 6952 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */ 6953 #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */ 6954 #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */ 6955 #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */ 6956 #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */ 6957 #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0) 6958 #define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0) 6959 #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0) 6960 #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0) 6961 6962 /* refresh rate hardware control */ 6963 #define RR_HW_CTL _MMIO(0x45300) 6964 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff 6965 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 6966 6967 #define FDI_PLL_BIOS_0 _MMIO(0x46000) 6968 #define FDI_PLL_FB_CLOCK_MASK 0xff 6969 #define FDI_PLL_BIOS_1 _MMIO(0x46004) 6970 #define FDI_PLL_BIOS_2 _MMIO(0x46008) 6971 #define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c) 6972 #define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010) 6973 #define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014) 6974 6975 #define PCH_3DCGDIS0 _MMIO(0x46020) 6976 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) 6977 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) 6978 6979 #define PCH_3DCGDIS1 _MMIO(0x46024) 6980 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) 6981 6982 #define FDI_PLL_FREQ_CTL _MMIO(0x46030) 6983 #define FDI_PLL_FREQ_CHANGE_REQUEST (1 << 24) 6984 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 6985 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff 6986 6987 6988 #define _PIPEA_DATA_M1 0x60030 6989 #define PIPE_DATA_M1_OFFSET 0 6990 #define _PIPEA_DATA_N1 0x60034 6991 #define PIPE_DATA_N1_OFFSET 0 6992 6993 #define _PIPEA_DATA_M2 0x60038 6994 #define PIPE_DATA_M2_OFFSET 0 6995 #define _PIPEA_DATA_N2 0x6003c 6996 #define PIPE_DATA_N2_OFFSET 0 6997 6998 #define _PIPEA_LINK_M1 0x60040 6999 #define PIPE_LINK_M1_OFFSET 0 7000 #define _PIPEA_LINK_N1 0x60044 7001 #define PIPE_LINK_N1_OFFSET 0 7002 7003 #define _PIPEA_LINK_M2 0x60048 7004 #define PIPE_LINK_M2_OFFSET 0 7005 #define _PIPEA_LINK_N2 0x6004c 7006 #define PIPE_LINK_N2_OFFSET 0 7007 7008 /* PIPEB timing regs are same start from 0x61000 */ 7009 7010 #define _PIPEB_DATA_M1 0x61030 7011 #define _PIPEB_DATA_N1 0x61034 7012 #define _PIPEB_DATA_M2 0x61038 7013 #define _PIPEB_DATA_N2 0x6103c 7014 #define _PIPEB_LINK_M1 0x61040 7015 #define _PIPEB_LINK_N1 0x61044 7016 #define _PIPEB_LINK_M2 0x61048 7017 #define _PIPEB_LINK_N2 0x6104c 7018 7019 #define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1) 7020 #define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1) 7021 #define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2) 7022 #define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2) 7023 #define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1) 7024 #define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1) 7025 #define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2) 7026 #define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2) 7027 7028 /* CPU panel fitter */ 7029 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ 7030 #define _PFA_CTL_1 0x68080 7031 #define _PFB_CTL_1 0x68880 7032 #define PF_ENABLE (1 << 31) 7033 #define PF_PIPE_SEL_MASK_IVB (3 << 29) 7034 #define PF_PIPE_SEL_IVB(pipe) ((pipe) << 29) 7035 #define PF_FILTER_MASK (3 << 23) 7036 #define PF_FILTER_PROGRAMMED (0 << 23) 7037 #define PF_FILTER_MED_3x3 (1 << 23) 7038 #define PF_FILTER_EDGE_ENHANCE (2 << 23) 7039 #define PF_FILTER_EDGE_SOFTEN (3 << 23) 7040 #define _PFA_WIN_SZ 0x68074 7041 #define _PFB_WIN_SZ 0x68874 7042 #define _PFA_WIN_POS 0x68070 7043 #define _PFB_WIN_POS 0x68870 7044 #define _PFA_VSCALE 0x68084 7045 #define _PFB_VSCALE 0x68884 7046 #define _PFA_HSCALE 0x68090 7047 #define _PFB_HSCALE 0x68890 7048 7049 #define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) 7050 #define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) 7051 #define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) 7052 #define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) 7053 #define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) 7054 7055 #define _PSA_CTL 0x68180 7056 #define _PSB_CTL 0x68980 7057 #define PS_ENABLE (1 << 31) 7058 #define _PSA_WIN_SZ 0x68174 7059 #define _PSB_WIN_SZ 0x68974 7060 #define _PSA_WIN_POS 0x68170 7061 #define _PSB_WIN_POS 0x68970 7062 7063 #define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL) 7064 #define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ) 7065 #define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS) 7066 7067 /* 7068 * Skylake scalers 7069 */ 7070 #define _PS_1A_CTRL 0x68180 7071 #define _PS_2A_CTRL 0x68280 7072 #define _PS_1B_CTRL 0x68980 7073 #define _PS_2B_CTRL 0x68A80 7074 #define _PS_1C_CTRL 0x69180 7075 #define PS_SCALER_EN (1 << 31) 7076 #define SKL_PS_SCALER_MODE_MASK (3 << 28) 7077 #define SKL_PS_SCALER_MODE_DYN (0 << 28) 7078 #define SKL_PS_SCALER_MODE_HQ (1 << 28) 7079 #define SKL_PS_SCALER_MODE_NV12 (2 << 28) 7080 #define PS_SCALER_MODE_PLANAR (1 << 29) 7081 #define PS_SCALER_MODE_NORMAL (0 << 29) 7082 #define PS_PLANE_SEL_MASK (7 << 25) 7083 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25) 7084 #define PS_FILTER_MASK (3 << 23) 7085 #define PS_FILTER_MEDIUM (0 << 23) 7086 #define PS_FILTER_EDGE_ENHANCE (2 << 23) 7087 #define PS_FILTER_BILINEAR (3 << 23) 7088 #define PS_VERT3TAP (1 << 21) 7089 #define PS_VERT_INT_INVERT_FIELD1 (0 << 20) 7090 #define PS_VERT_INT_INVERT_FIELD0 (1 << 20) 7091 #define PS_PWRUP_PROGRESS (1 << 17) 7092 #define PS_V_FILTER_BYPASS (1 << 8) 7093 #define PS_VADAPT_EN (1 << 7) 7094 #define PS_VADAPT_MODE_MASK (3 << 5) 7095 #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5) 7096 #define PS_VADAPT_MODE_MOD_ADAPT (1 << 5) 7097 #define PS_VADAPT_MODE_MOST_ADAPT (3 << 5) 7098 #define PS_PLANE_Y_SEL_MASK (7 << 5) 7099 #define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5) 7100 7101 #define _PS_PWR_GATE_1A 0x68160 7102 #define _PS_PWR_GATE_2A 0x68260 7103 #define _PS_PWR_GATE_1B 0x68960 7104 #define _PS_PWR_GATE_2B 0x68A60 7105 #define _PS_PWR_GATE_1C 0x69160 7106 #define PS_PWR_GATE_DIS_OVERRIDE (1 << 31) 7107 #define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3) 7108 #define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3) 7109 #define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3) 7110 #define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3) 7111 #define PS_PWR_GATE_SLPEN_8 0 7112 #define PS_PWR_GATE_SLPEN_16 1 7113 #define PS_PWR_GATE_SLPEN_24 2 7114 #define PS_PWR_GATE_SLPEN_32 3 7115 7116 #define _PS_WIN_POS_1A 0x68170 7117 #define _PS_WIN_POS_2A 0x68270 7118 #define _PS_WIN_POS_1B 0x68970 7119 #define _PS_WIN_POS_2B 0x68A70 7120 #define _PS_WIN_POS_1C 0x69170 7121 7122 #define _PS_WIN_SZ_1A 0x68174 7123 #define _PS_WIN_SZ_2A 0x68274 7124 #define _PS_WIN_SZ_1B 0x68974 7125 #define _PS_WIN_SZ_2B 0x68A74 7126 #define _PS_WIN_SZ_1C 0x69174 7127 7128 #define _PS_VSCALE_1A 0x68184 7129 #define _PS_VSCALE_2A 0x68284 7130 #define _PS_VSCALE_1B 0x68984 7131 #define _PS_VSCALE_2B 0x68A84 7132 #define _PS_VSCALE_1C 0x69184 7133 7134 #define _PS_HSCALE_1A 0x68190 7135 #define _PS_HSCALE_2A 0x68290 7136 #define _PS_HSCALE_1B 0x68990 7137 #define _PS_HSCALE_2B 0x68A90 7138 #define _PS_HSCALE_1C 0x69190 7139 7140 #define _PS_VPHASE_1A 0x68188 7141 #define _PS_VPHASE_2A 0x68288 7142 #define _PS_VPHASE_1B 0x68988 7143 #define _PS_VPHASE_2B 0x68A88 7144 #define _PS_VPHASE_1C 0x69188 7145 #define PS_Y_PHASE(x) ((x) << 16) 7146 #define PS_UV_RGB_PHASE(x) ((x) << 0) 7147 #define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */ 7148 #define PS_PHASE_TRIP (1 << 0) 7149 7150 #define _PS_HPHASE_1A 0x68194 7151 #define _PS_HPHASE_2A 0x68294 7152 #define _PS_HPHASE_1B 0x68994 7153 #define _PS_HPHASE_2B 0x68A94 7154 #define _PS_HPHASE_1C 0x69194 7155 7156 #define _PS_ECC_STAT_1A 0x681D0 7157 #define _PS_ECC_STAT_2A 0x682D0 7158 #define _PS_ECC_STAT_1B 0x689D0 7159 #define _PS_ECC_STAT_2B 0x68AD0 7160 #define _PS_ECC_STAT_1C 0x691D0 7161 7162 #define _ID(id, a, b) _PICK_EVEN(id, a, b) 7163 #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \ 7164 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \ 7165 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL)) 7166 #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \ 7167 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \ 7168 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B)) 7169 #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \ 7170 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \ 7171 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B)) 7172 #define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \ 7173 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \ 7174 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B)) 7175 #define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \ 7176 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \ 7177 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B)) 7178 #define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \ 7179 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \ 7180 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B)) 7181 #define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \ 7182 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \ 7183 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B)) 7184 #define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \ 7185 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \ 7186 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B)) 7187 #define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \ 7188 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \ 7189 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)) 7190 7191 /* legacy palette */ 7192 #define _LGC_PALETTE_A 0x4a000 7193 #define _LGC_PALETTE_B 0x4a800 7194 #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4) 7195 7196 /* ilk/snb precision palette */ 7197 #define _PREC_PALETTE_A 0x4b000 7198 #define _PREC_PALETTE_B 0x4c000 7199 #define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4) 7200 7201 #define _PREC_PIPEAGCMAX 0x4d000 7202 #define _PREC_PIPEBGCMAX 0x4d010 7203 #define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4) 7204 7205 #define _GAMMA_MODE_A 0x4a480 7206 #define _GAMMA_MODE_B 0x4ac80 7207 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) 7208 #define PRE_CSC_GAMMA_ENABLE (1 << 31) 7209 #define POST_CSC_GAMMA_ENABLE (1 << 30) 7210 #define GAMMA_MODE_MODE_MASK (3 << 0) 7211 #define GAMMA_MODE_MODE_8BIT (0 << 0) 7212 #define GAMMA_MODE_MODE_10BIT (1 << 0) 7213 #define GAMMA_MODE_MODE_12BIT (2 << 0) 7214 #define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */ 7215 #define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */ 7216 7217 /* DMC/CSR */ 7218 #define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4) 7219 #define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0 7220 #define CSR_HTP_ADDR_SKL 0x00500034 7221 #define CSR_SSP_BASE _MMIO(0x8F074) 7222 #define CSR_HTP_SKL _MMIO(0x8F004) 7223 #define CSR_LAST_WRITE _MMIO(0x8F034) 7224 #define CSR_LAST_WRITE_VALUE 0xc003b400 7225 /* MMIO address range for CSR program (0x80000 - 0x82FFF) */ 7226 #define CSR_MMIO_START_RANGE 0x80000 7227 #define CSR_MMIO_END_RANGE 0x8FFFF 7228 #define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030) 7229 #define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C) 7230 #define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038) 7231 7232 /* interrupts */ 7233 #define DE_MASTER_IRQ_CONTROL (1 << 31) 7234 #define DE_SPRITEB_FLIP_DONE (1 << 29) 7235 #define DE_SPRITEA_FLIP_DONE (1 << 28) 7236 #define DE_PLANEB_FLIP_DONE (1 << 27) 7237 #define DE_PLANEA_FLIP_DONE (1 << 26) 7238 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane))) 7239 #define DE_PCU_EVENT (1 << 25) 7240 #define DE_GTT_FAULT (1 << 24) 7241 #define DE_POISON (1 << 23) 7242 #define DE_PERFORM_COUNTER (1 << 22) 7243 #define DE_PCH_EVENT (1 << 21) 7244 #define DE_AUX_CHANNEL_A (1 << 20) 7245 #define DE_DP_A_HOTPLUG (1 << 19) 7246 #define DE_GSE (1 << 18) 7247 #define DE_PIPEB_VBLANK (1 << 15) 7248 #define DE_PIPEB_EVEN_FIELD (1 << 14) 7249 #define DE_PIPEB_ODD_FIELD (1 << 13) 7250 #define DE_PIPEB_LINE_COMPARE (1 << 12) 7251 #define DE_PIPEB_VSYNC (1 << 11) 7252 #define DE_PIPEB_CRC_DONE (1 << 10) 7253 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) 7254 #define DE_PIPEA_VBLANK (1 << 7) 7255 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe))) 7256 #define DE_PIPEA_EVEN_FIELD (1 << 6) 7257 #define DE_PIPEA_ODD_FIELD (1 << 5) 7258 #define DE_PIPEA_LINE_COMPARE (1 << 4) 7259 #define DE_PIPEA_VSYNC (1 << 3) 7260 #define DE_PIPEA_CRC_DONE (1 << 2) 7261 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe))) 7262 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 7263 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe))) 7264 7265 /* More Ivybridge lolz */ 7266 #define DE_ERR_INT_IVB (1 << 30) 7267 #define DE_GSE_IVB (1 << 29) 7268 #define DE_PCH_EVENT_IVB (1 << 28) 7269 #define DE_DP_A_HOTPLUG_IVB (1 << 27) 7270 #define DE_AUX_CHANNEL_A_IVB (1 << 26) 7271 #define DE_EDP_PSR_INT_HSW (1 << 19) 7272 #define DE_SPRITEC_FLIP_DONE_IVB (1 << 14) 7273 #define DE_PLANEC_FLIP_DONE_IVB (1 << 13) 7274 #define DE_PIPEC_VBLANK_IVB (1 << 10) 7275 #define DE_SPRITEB_FLIP_DONE_IVB (1 << 9) 7276 #define DE_PLANEB_FLIP_DONE_IVB (1 << 8) 7277 #define DE_PIPEB_VBLANK_IVB (1 << 5) 7278 #define DE_SPRITEA_FLIP_DONE_IVB (1 << 4) 7279 #define DE_PLANEA_FLIP_DONE_IVB (1 << 3) 7280 #define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane))) 7281 #define DE_PIPEA_VBLANK_IVB (1 << 0) 7282 #define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5)) 7283 7284 #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */ 7285 #define MASTER_INTERRUPT_ENABLE (1 << 31) 7286 7287 #define DEISR _MMIO(0x44000) 7288 #define DEIMR _MMIO(0x44004) 7289 #define DEIIR _MMIO(0x44008) 7290 #define DEIER _MMIO(0x4400c) 7291 7292 #define GTISR _MMIO(0x44010) 7293 #define GTIMR _MMIO(0x44014) 7294 #define GTIIR _MMIO(0x44018) 7295 #define GTIER _MMIO(0x4401c) 7296 7297 #define GEN8_MASTER_IRQ _MMIO(0x44200) 7298 #define GEN8_MASTER_IRQ_CONTROL (1 << 31) 7299 #define GEN8_PCU_IRQ (1 << 30) 7300 #define GEN8_DE_PCH_IRQ (1 << 23) 7301 #define GEN8_DE_MISC_IRQ (1 << 22) 7302 #define GEN8_DE_PORT_IRQ (1 << 20) 7303 #define GEN8_DE_PIPE_C_IRQ (1 << 18) 7304 #define GEN8_DE_PIPE_B_IRQ (1 << 17) 7305 #define GEN8_DE_PIPE_A_IRQ (1 << 16) 7306 #define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe))) 7307 #define GEN8_GT_VECS_IRQ (1 << 6) 7308 #define GEN8_GT_GUC_IRQ (1 << 5) 7309 #define GEN8_GT_PM_IRQ (1 << 4) 7310 #define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */ 7311 #define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */ 7312 #define GEN8_GT_BCS_IRQ (1 << 1) 7313 #define GEN8_GT_RCS_IRQ (1 << 0) 7314 7315 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which))) 7316 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which))) 7317 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which))) 7318 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which))) 7319 7320 #define GEN9_GUC_TO_HOST_INT_EVENT (1 << 31) 7321 #define GEN9_GUC_EXEC_ERROR_EVENT (1 << 30) 7322 #define GEN9_GUC_DISPLAY_EVENT (1 << 29) 7323 #define GEN9_GUC_SEMA_SIGNAL_EVENT (1 << 28) 7324 #define GEN9_GUC_IOMMU_MSG_EVENT (1 << 27) 7325 #define GEN9_GUC_DB_RING_EVENT (1 << 26) 7326 #define GEN9_GUC_DMA_DONE_EVENT (1 << 25) 7327 #define GEN9_GUC_FATAL_ERROR_EVENT (1 << 24) 7328 #define GEN9_GUC_NOTIFICATION_EVENT (1 << 23) 7329 7330 #define GEN8_RCS_IRQ_SHIFT 0 7331 #define GEN8_BCS_IRQ_SHIFT 16 7332 #define GEN8_VCS0_IRQ_SHIFT 0 /* NB: VCS1 in bspec! */ 7333 #define GEN8_VCS1_IRQ_SHIFT 16 /* NB: VCS2 in bpsec! */ 7334 #define GEN8_VECS_IRQ_SHIFT 0 7335 #define GEN8_WD_IRQ_SHIFT 16 7336 7337 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe))) 7338 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe))) 7339 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe))) 7340 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe))) 7341 #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31) 7342 #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29) 7343 #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28) 7344 #define GEN8_PIPE_CURSOR_FAULT (1 << 10) 7345 #define GEN8_PIPE_SPRITE_FAULT (1 << 9) 7346 #define GEN8_PIPE_PRIMARY_FAULT (1 << 8) 7347 #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5) 7348 #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4) 7349 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) 7350 #define GEN8_PIPE_VSYNC (1 << 1) 7351 #define GEN8_PIPE_VBLANK (1 << 0) 7352 #define GEN9_PIPE_CURSOR_FAULT (1 << 11) 7353 #define GEN9_PIPE_PLANE4_FAULT (1 << 10) 7354 #define GEN9_PIPE_PLANE3_FAULT (1 << 9) 7355 #define GEN9_PIPE_PLANE2_FAULT (1 << 8) 7356 #define GEN9_PIPE_PLANE1_FAULT (1 << 7) 7357 #define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6) 7358 #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5) 7359 #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4) 7360 #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3) 7361 #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p))) 7362 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ 7363 (GEN8_PIPE_CURSOR_FAULT | \ 7364 GEN8_PIPE_SPRITE_FAULT | \ 7365 GEN8_PIPE_PRIMARY_FAULT) 7366 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \ 7367 (GEN9_PIPE_CURSOR_FAULT | \ 7368 GEN9_PIPE_PLANE4_FAULT | \ 7369 GEN9_PIPE_PLANE3_FAULT | \ 7370 GEN9_PIPE_PLANE2_FAULT | \ 7371 GEN9_PIPE_PLANE1_FAULT) 7372 7373 #define GEN8_DE_PORT_ISR _MMIO(0x44440) 7374 #define GEN8_DE_PORT_IMR _MMIO(0x44444) 7375 #define GEN8_DE_PORT_IIR _MMIO(0x44448) 7376 #define GEN8_DE_PORT_IER _MMIO(0x4444c) 7377 #define ICL_AUX_CHANNEL_E (1 << 29) 7378 #define CNL_AUX_CHANNEL_F (1 << 28) 7379 #define GEN9_AUX_CHANNEL_D (1 << 27) 7380 #define GEN9_AUX_CHANNEL_C (1 << 26) 7381 #define GEN9_AUX_CHANNEL_B (1 << 25) 7382 #define BXT_DE_PORT_HP_DDIC (1 << 5) 7383 #define BXT_DE_PORT_HP_DDIB (1 << 4) 7384 #define BXT_DE_PORT_HP_DDIA (1 << 3) 7385 #define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDIA | \ 7386 BXT_DE_PORT_HP_DDIB | \ 7387 BXT_DE_PORT_HP_DDIC) 7388 #define GEN8_PORT_DP_A_HOTPLUG (1 << 3) 7389 #define BXT_DE_PORT_GMBUS (1 << 1) 7390 #define GEN8_AUX_CHANNEL_A (1 << 0) 7391 7392 #define GEN8_DE_MISC_ISR _MMIO(0x44460) 7393 #define GEN8_DE_MISC_IMR _MMIO(0x44464) 7394 #define GEN8_DE_MISC_IIR _MMIO(0x44468) 7395 #define GEN8_DE_MISC_IER _MMIO(0x4446c) 7396 #define GEN8_DE_MISC_GSE (1 << 27) 7397 #define GEN8_DE_EDP_PSR (1 << 19) 7398 7399 #define GEN8_PCU_ISR _MMIO(0x444e0) 7400 #define GEN8_PCU_IMR _MMIO(0x444e4) 7401 #define GEN8_PCU_IIR _MMIO(0x444e8) 7402 #define GEN8_PCU_IER _MMIO(0x444ec) 7403 7404 #define GEN11_GU_MISC_ISR _MMIO(0x444f0) 7405 #define GEN11_GU_MISC_IMR _MMIO(0x444f4) 7406 #define GEN11_GU_MISC_IIR _MMIO(0x444f8) 7407 #define GEN11_GU_MISC_IER _MMIO(0x444fc) 7408 #define GEN11_GU_MISC_GSE (1 << 27) 7409 7410 #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010) 7411 #define GEN11_MASTER_IRQ (1 << 31) 7412 #define GEN11_PCU_IRQ (1 << 30) 7413 #define GEN11_GU_MISC_IRQ (1 << 29) 7414 #define GEN11_DISPLAY_IRQ (1 << 16) 7415 #define GEN11_GT_DW_IRQ(x) (1 << (x)) 7416 #define GEN11_GT_DW1_IRQ (1 << 1) 7417 #define GEN11_GT_DW0_IRQ (1 << 0) 7418 7419 #define GEN11_DISPLAY_INT_CTL _MMIO(0x44200) 7420 #define GEN11_DISPLAY_IRQ_ENABLE (1 << 31) 7421 #define GEN11_AUDIO_CODEC_IRQ (1 << 24) 7422 #define GEN11_DE_PCH_IRQ (1 << 23) 7423 #define GEN11_DE_MISC_IRQ (1 << 22) 7424 #define GEN11_DE_HPD_IRQ (1 << 21) 7425 #define GEN11_DE_PORT_IRQ (1 << 20) 7426 #define GEN11_DE_PIPE_C (1 << 18) 7427 #define GEN11_DE_PIPE_B (1 << 17) 7428 #define GEN11_DE_PIPE_A (1 << 16) 7429 7430 #define GEN11_DE_HPD_ISR _MMIO(0x44470) 7431 #define GEN11_DE_HPD_IMR _MMIO(0x44474) 7432 #define GEN11_DE_HPD_IIR _MMIO(0x44478) 7433 #define GEN11_DE_HPD_IER _MMIO(0x4447c) 7434 #define GEN11_TC4_HOTPLUG (1 << 19) 7435 #define GEN11_TC3_HOTPLUG (1 << 18) 7436 #define GEN11_TC2_HOTPLUG (1 << 17) 7437 #define GEN11_TC1_HOTPLUG (1 << 16) 7438 #define GEN11_TC_HOTPLUG(tc_port) (1 << ((tc_port) + 16)) 7439 #define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC4_HOTPLUG | \ 7440 GEN11_TC3_HOTPLUG | \ 7441 GEN11_TC2_HOTPLUG | \ 7442 GEN11_TC1_HOTPLUG) 7443 #define GEN11_TBT4_HOTPLUG (1 << 3) 7444 #define GEN11_TBT3_HOTPLUG (1 << 2) 7445 #define GEN11_TBT2_HOTPLUG (1 << 1) 7446 #define GEN11_TBT1_HOTPLUG (1 << 0) 7447 #define GEN11_TBT_HOTPLUG(tc_port) (1 << (tc_port)) 7448 #define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT4_HOTPLUG | \ 7449 GEN11_TBT3_HOTPLUG | \ 7450 GEN11_TBT2_HOTPLUG | \ 7451 GEN11_TBT1_HOTPLUG) 7452 7453 #define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030) 7454 #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038) 7455 #define GEN11_HOTPLUG_CTL_ENABLE(tc_port) (8 << (tc_port) * 4) 7456 #define GEN11_HOTPLUG_CTL_LONG_DETECT(tc_port) (2 << (tc_port) * 4) 7457 #define GEN11_HOTPLUG_CTL_SHORT_DETECT(tc_port) (1 << (tc_port) * 4) 7458 #define GEN11_HOTPLUG_CTL_NO_DETECT(tc_port) (0 << (tc_port) * 4) 7459 7460 #define GEN11_GT_INTR_DW0 _MMIO(0x190018) 7461 #define GEN11_CSME (31) 7462 #define GEN11_GUNIT (28) 7463 #define GEN11_GUC (25) 7464 #define GEN11_WDPERF (20) 7465 #define GEN11_KCR (19) 7466 #define GEN11_GTPM (16) 7467 #define GEN11_BCS (15) 7468 #define GEN11_RCS0 (0) 7469 7470 #define GEN11_GT_INTR_DW1 _MMIO(0x19001c) 7471 #define GEN11_VECS(x) (31 - (x)) 7472 #define GEN11_VCS(x) (x) 7473 7474 #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4)) 7475 7476 #define GEN11_INTR_IDENTITY_REG0 _MMIO(0x190060) 7477 #define GEN11_INTR_IDENTITY_REG1 _MMIO(0x190064) 7478 #define GEN11_INTR_DATA_VALID (1 << 31) 7479 #define GEN11_INTR_ENGINE_CLASS(x) (((x) & GENMASK(18, 16)) >> 16) 7480 #define GEN11_INTR_ENGINE_INSTANCE(x) (((x) & GENMASK(25, 20)) >> 20) 7481 #define GEN11_INTR_ENGINE_INTR(x) ((x) & 0xffff) 7482 7483 #define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4)) 7484 7485 #define GEN11_IIR_REG0_SELECTOR _MMIO(0x190070) 7486 #define GEN11_IIR_REG1_SELECTOR _MMIO(0x190074) 7487 7488 #define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + ((x) * 4)) 7489 7490 #define GEN11_RENDER_COPY_INTR_ENABLE _MMIO(0x190030) 7491 #define GEN11_VCS_VECS_INTR_ENABLE _MMIO(0x190034) 7492 #define GEN11_GUC_SG_INTR_ENABLE _MMIO(0x190038) 7493 #define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c) 7494 #define GEN11_CRYPTO_RSVD_INTR_ENABLE _MMIO(0x190040) 7495 #define GEN11_GUNIT_CSME_INTR_ENABLE _MMIO(0x190044) 7496 7497 #define GEN11_RCS0_RSVD_INTR_MASK _MMIO(0x190090) 7498 #define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0) 7499 #define GEN11_VCS0_VCS1_INTR_MASK _MMIO(0x1900a8) 7500 #define GEN11_VCS2_VCS3_INTR_MASK _MMIO(0x1900ac) 7501 #define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0) 7502 #define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8) 7503 #define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec) 7504 #define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0) 7505 #define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4) 7506 7507 #define ENGINE1_MASK REG_GENMASK(31, 16) 7508 #define ENGINE0_MASK REG_GENMASK(15, 0) 7509 7510 #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004) 7511 /* Required on all Ironlake and Sandybridge according to the B-Spec. */ 7512 #define ILK_ELPIN_409_SELECT (1 << 25) 7513 #define ILK_DPARB_GATE (1 << 22) 7514 #define ILK_VSDPFD_FULL (1 << 21) 7515 #define FUSE_STRAP _MMIO(0x42014) 7516 #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31) 7517 #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30) 7518 #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29) 7519 #define IVB_PIPE_C_DISABLE (1 << 28) 7520 #define ILK_HDCP_DISABLE (1 << 25) 7521 #define ILK_eDP_A_DISABLE (1 << 24) 7522 #define HSW_CDCLK_LIMIT (1 << 24) 7523 #define ILK_DESKTOP (1 << 23) 7524 #define HSW_CPU_SSC_ENABLE (1 << 21) 7525 7526 #define FUSE_STRAP3 _MMIO(0x42020) 7527 #define HSW_REF_CLK_SELECT (1 << 1) 7528 7529 #define ILK_DSPCLK_GATE_D _MMIO(0x42020) 7530 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) 7531 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) 7532 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) 7533 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7) 7534 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5) 7535 7536 #define IVB_CHICKEN3 _MMIO(0x4200c) 7537 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) 7538 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) 7539 7540 #define CHICKEN_PAR1_1 _MMIO(0x42080) 7541 #define SKL_DE_COMPRESSED_HASH_MODE (1 << 15) 7542 #define DPA_MASK_VBLANK_SRD (1 << 15) 7543 #define FORCE_ARB_IDLE_PLANES (1 << 14) 7544 #define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) 7545 7546 #define CHICKEN_PAR2_1 _MMIO(0x42090) 7547 #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14) 7548 7549 #define CHICKEN_MISC_2 _MMIO(0x42084) 7550 #define CNL_COMP_PWR_DOWN (1 << 23) 7551 #define GLK_CL2_PWR_DOWN (1 << 12) 7552 #define GLK_CL1_PWR_DOWN (1 << 11) 7553 #define GLK_CL0_PWR_DOWN (1 << 10) 7554 7555 #define CHICKEN_MISC_4 _MMIO(0x4208c) 7556 #define FBC_STRIDE_OVERRIDE (1 << 13) 7557 #define FBC_STRIDE_MASK 0x1FFF 7558 7559 #define _CHICKEN_PIPESL_1_A 0x420b0 7560 #define _CHICKEN_PIPESL_1_B 0x420b4 7561 #define HSW_FBCQ_DIS (1 << 22) 7562 #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0) 7563 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) 7564 7565 #define CHICKEN_TRANS_A _MMIO(0x420c0) 7566 #define CHICKEN_TRANS_B _MMIO(0x420c4) 7567 #define CHICKEN_TRANS_C _MMIO(0x420c8) 7568 #define CHICKEN_TRANS_EDP _MMIO(0x420cc) 7569 #define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and CNL+ */ 7570 #define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19) 7571 #define DDI_TRAINING_OVERRIDE_VALUE (1 << 18) 7572 #define DDIE_TRAINING_OVERRIDE_ENABLE (1 << 17) /* CHICKEN_TRANS_A only */ 7573 #define DDIE_TRAINING_OVERRIDE_VALUE (1 << 16) /* CHICKEN_TRANS_A only */ 7574 #define PSR2_ADD_VERTICAL_LINE_COUNT (1 << 15) 7575 #define PSR2_VSC_ENABLE_PROG_HEADER (1 << 12) 7576 7577 #define DISP_ARB_CTL _MMIO(0x45000) 7578 #define DISP_FBC_MEMORY_WAKE (1 << 31) 7579 #define DISP_TILE_SURFACE_SWIZZLING (1 << 13) 7580 #define DISP_FBC_WM_DIS (1 << 15) 7581 #define DISP_ARB_CTL2 _MMIO(0x45004) 7582 #define DISP_DATA_PARTITION_5_6 (1 << 6) 7583 #define DISP_IPC_ENABLE (1 << 3) 7584 #define DBUF_CTL _MMIO(0x45008) 7585 #define DBUF_CTL_S1 _MMIO(0x45008) 7586 #define DBUF_CTL_S2 _MMIO(0x44FE8) 7587 #define DBUF_POWER_REQUEST (1 << 31) 7588 #define DBUF_POWER_STATE (1 << 30) 7589 #define GEN7_MSG_CTL _MMIO(0x45010) 7590 #define WAIT_FOR_PCH_RESET_ACK (1 << 1) 7591 #define WAIT_FOR_PCH_FLR_ACK (1 << 0) 7592 #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) 7593 #define RESET_PCH_HANDSHAKE_ENABLE (1 << 4) 7594 7595 #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) 7596 #define SKL_SELECT_ALTERNATE_DC_EXIT (1 << 30) 7597 #define MASK_WAKEMEM (1 << 13) 7598 #define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7) 7599 7600 #define SKL_DFSM _MMIO(0x51000) 7601 #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23) 7602 #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23) 7603 #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23) 7604 #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23) 7605 #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23) 7606 #define SKL_DFSM_PIPE_A_DISABLE (1 << 30) 7607 #define SKL_DFSM_PIPE_B_DISABLE (1 << 21) 7608 #define SKL_DFSM_PIPE_C_DISABLE (1 << 28) 7609 7610 #define SKL_DSSM _MMIO(0x51004) 7611 #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31) 7612 #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29) 7613 #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29) 7614 #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29) 7615 #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29) 7616 7617 #define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0) 7618 #define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1 << 14) 7619 7620 #define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4) 7621 #define GEN9_TSG_BARRIER_ACK_DISABLE (1 << 8) 7622 #define GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE (1 << 10) 7623 7624 #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec) 7625 #define GEN9_CTX_PREEMPT_REG _MMIO(0x2248) 7626 #define GEN8_CS_CHICKEN1 _MMIO(0x2580) 7627 #define GEN9_PREEMPT_3D_OBJECT_LEVEL (1 << 0) 7628 #define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1)) 7629 #define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 0) 7630 #define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 1) 7631 #define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(1, 0) 7632 #define GEN9_PREEMPT_GPGPU_LEVEL_MASK GEN9_PREEMPT_GPGPU_LEVEL(1, 1) 7633 7634 /* GEN7 chicken */ 7635 #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010) 7636 #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1 << 10) | (1 << 26)) 7637 #define GEN9_RHWO_OPTIMIZATION_DISABLE (1 << 14) 7638 7639 #define COMMON_SLICE_CHICKEN2 _MMIO(0x7014) 7640 #define GEN9_PBE_COMPRESSED_HASH_SELECTION (1 << 13) 7641 #define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1 << 12) 7642 #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1 << 8) 7643 #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1 << 0) 7644 7645 #define GEN8_L3CNTLREG _MMIO(0x7034) 7646 #define GEN8_ERRDETBCTRL (1 << 9) 7647 7648 #define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304) 7649 #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC (1 << 11) 7650 7651 #define HIZ_CHICKEN _MMIO(0x7018) 7652 # define CHV_HZ_8X8_MODE_IN_1X (1 << 15) 7653 # define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1 << 3) 7654 7655 #define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308) 7656 #define DISABLE_PIXEL_MASK_CAMMING (1 << 14) 7657 7658 #define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c) 7659 #define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11) 7660 7661 #define GEN7_SARCHKMD _MMIO(0xB000) 7662 #define GEN7_DISABLE_DEMAND_PREFETCH (1 << 31) 7663 #define GEN7_DISABLE_SAMPLER_PREFETCH (1 << 30) 7664 7665 #define GEN7_L3SQCREG1 _MMIO(0xB010) 7666 #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 7667 7668 #define GEN8_L3SQCREG1 _MMIO(0xB100) 7669 /* 7670 * Note that on CHV the following has an off-by-one error wrt. to BSpec. 7671 * Using the formula in BSpec leads to a hang, while the formula here works 7672 * fine and matches the formulas for all other platforms. A BSpec change 7673 * request has been filed to clarify this. 7674 */ 7675 #define L3_GENERAL_PRIO_CREDITS(x) (((x) >> 1) << 19) 7676 #define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14) 7677 #define L3_PRIO_CREDITS_MASK ((0x1f << 19) | (0x1f << 14)) 7678 7679 #define GEN7_L3CNTLREG1 _MMIO(0xB01C) 7680 #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C 7681 #define GEN7_L3AGDIS (1 << 19) 7682 #define GEN7_L3CNTLREG2 _MMIO(0xB020) 7683 #define GEN7_L3CNTLREG3 _MMIO(0xB024) 7684 7685 #define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xB030) 7686 #define GEN7_WA_L3_CHICKEN_MODE 0x20000000 7687 #define GEN10_L3_CHICKEN_MODE_REGISTER _MMIO(0xB114) 7688 #define GEN11_I2M_WRITE_DISABLE (1 << 28) 7689 7690 #define GEN7_L3SQCREG4 _MMIO(0xb034) 7691 #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1 << 27) 7692 7693 #define GEN8_L3SQCREG4 _MMIO(0xb118) 7694 #define GEN11_LQSC_CLEAN_EVICT_DISABLE (1 << 6) 7695 #define GEN8_LQSC_RO_PERF_DIS (1 << 27) 7696 #define GEN8_LQSC_FLUSH_COHERENT_LINES (1 << 21) 7697 7698 /* GEN8 chicken */ 7699 #define HDC_CHICKEN0 _MMIO(0x7300) 7700 #define CNL_HDC_CHICKEN0 _MMIO(0xE5F0) 7701 #define ICL_HDC_MODE _MMIO(0xE5F4) 7702 #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1 << 15) 7703 #define HDC_FENCE_DEST_SLM_DISABLE (1 << 14) 7704 #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1 << 11) 7705 #define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1 << 5) 7706 #define HDC_FORCE_NON_COHERENT (1 << 4) 7707 #define HDC_BARRIER_PERFORMANCE_DISABLE (1 << 10) 7708 7709 #define GEN8_HDC_CHICKEN1 _MMIO(0x7304) 7710 7711 /* GEN9 chicken */ 7712 #define SLICE_ECO_CHICKEN0 _MMIO(0x7308) 7713 #define PIXEL_MASK_CAMMING_DISABLE (1 << 14) 7714 7715 #define GEN9_WM_CHICKEN3 _MMIO(0x5588) 7716 #define GEN9_FACTOR_IN_CLR_VAL_HIZ (1 << 9) 7717 7718 /* WaCatErrorRejectionIssue */ 7719 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030) 7720 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1 << 11) 7721 7722 #define HSW_SCRATCH1 _MMIO(0xb038) 7723 #define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1 << 27) 7724 7725 #define BDW_SCRATCH1 _MMIO(0xb11c) 7726 #define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1 << 2) 7727 7728 /*GEN11 chicken */ 7729 #define _PIPEA_CHICKEN 0x70038 7730 #define _PIPEB_CHICKEN 0x71038 7731 #define _PIPEC_CHICKEN 0x72038 7732 #define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\ 7733 _PIPEB_CHICKEN) 7734 #define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15) 7735 #define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7) 7736 7737 /* PCH */ 7738 7739 #define PCH_DISPLAY_BASE 0xc0000u 7740 7741 /* south display engine interrupt: IBX */ 7742 #define SDE_AUDIO_POWER_D (1 << 27) 7743 #define SDE_AUDIO_POWER_C (1 << 26) 7744 #define SDE_AUDIO_POWER_B (1 << 25) 7745 #define SDE_AUDIO_POWER_SHIFT (25) 7746 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) 7747 #define SDE_GMBUS (1 << 24) 7748 #define SDE_AUDIO_HDCP_TRANSB (1 << 23) 7749 #define SDE_AUDIO_HDCP_TRANSA (1 << 22) 7750 #define SDE_AUDIO_HDCP_MASK (3 << 22) 7751 #define SDE_AUDIO_TRANSB (1 << 21) 7752 #define SDE_AUDIO_TRANSA (1 << 20) 7753 #define SDE_AUDIO_TRANS_MASK (3 << 20) 7754 #define SDE_POISON (1 << 19) 7755 /* 18 reserved */ 7756 #define SDE_FDI_RXB (1 << 17) 7757 #define SDE_FDI_RXA (1 << 16) 7758 #define SDE_FDI_MASK (3 << 16) 7759 #define SDE_AUXD (1 << 15) 7760 #define SDE_AUXC (1 << 14) 7761 #define SDE_AUXB (1 << 13) 7762 #define SDE_AUX_MASK (7 << 13) 7763 /* 12 reserved */ 7764 #define SDE_CRT_HOTPLUG (1 << 11) 7765 #define SDE_PORTD_HOTPLUG (1 << 10) 7766 #define SDE_PORTC_HOTPLUG (1 << 9) 7767 #define SDE_PORTB_HOTPLUG (1 << 8) 7768 #define SDE_SDVOB_HOTPLUG (1 << 6) 7769 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \ 7770 SDE_SDVOB_HOTPLUG | \ 7771 SDE_PORTB_HOTPLUG | \ 7772 SDE_PORTC_HOTPLUG | \ 7773 SDE_PORTD_HOTPLUG) 7774 #define SDE_TRANSB_CRC_DONE (1 << 5) 7775 #define SDE_TRANSB_CRC_ERR (1 << 4) 7776 #define SDE_TRANSB_FIFO_UNDER (1 << 3) 7777 #define SDE_TRANSA_CRC_DONE (1 << 2) 7778 #define SDE_TRANSA_CRC_ERR (1 << 1) 7779 #define SDE_TRANSA_FIFO_UNDER (1 << 0) 7780 #define SDE_TRANS_MASK (0x3f) 7781 7782 /* south display engine interrupt: CPT - CNP */ 7783 #define SDE_AUDIO_POWER_D_CPT (1 << 31) 7784 #define SDE_AUDIO_POWER_C_CPT (1 << 30) 7785 #define SDE_AUDIO_POWER_B_CPT (1 << 29) 7786 #define SDE_AUDIO_POWER_SHIFT_CPT 29 7787 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29) 7788 #define SDE_AUXD_CPT (1 << 27) 7789 #define SDE_AUXC_CPT (1 << 26) 7790 #define SDE_AUXB_CPT (1 << 25) 7791 #define SDE_AUX_MASK_CPT (7 << 25) 7792 #define SDE_PORTE_HOTPLUG_SPT (1 << 25) 7793 #define SDE_PORTA_HOTPLUG_SPT (1 << 24) 7794 #define SDE_PORTD_HOTPLUG_CPT (1 << 23) 7795 #define SDE_PORTC_HOTPLUG_CPT (1 << 22) 7796 #define SDE_PORTB_HOTPLUG_CPT (1 << 21) 7797 #define SDE_CRT_HOTPLUG_CPT (1 << 19) 7798 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18) 7799 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ 7800 SDE_SDVOB_HOTPLUG_CPT | \ 7801 SDE_PORTD_HOTPLUG_CPT | \ 7802 SDE_PORTC_HOTPLUG_CPT | \ 7803 SDE_PORTB_HOTPLUG_CPT) 7804 #define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \ 7805 SDE_PORTD_HOTPLUG_CPT | \ 7806 SDE_PORTC_HOTPLUG_CPT | \ 7807 SDE_PORTB_HOTPLUG_CPT | \ 7808 SDE_PORTA_HOTPLUG_SPT) 7809 #define SDE_GMBUS_CPT (1 << 17) 7810 #define SDE_ERROR_CPT (1 << 16) 7811 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) 7812 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) 7813 #define SDE_FDI_RXC_CPT (1 << 8) 7814 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) 7815 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) 7816 #define SDE_FDI_RXB_CPT (1 << 4) 7817 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) 7818 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) 7819 #define SDE_FDI_RXA_CPT (1 << 0) 7820 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \ 7821 SDE_AUDIO_CP_REQ_B_CPT | \ 7822 SDE_AUDIO_CP_REQ_A_CPT) 7823 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \ 7824 SDE_AUDIO_CP_CHG_B_CPT | \ 7825 SDE_AUDIO_CP_CHG_A_CPT) 7826 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \ 7827 SDE_FDI_RXB_CPT | \ 7828 SDE_FDI_RXA_CPT) 7829 7830 /* south display engine interrupt: ICP */ 7831 #define SDE_TC4_HOTPLUG_ICP (1 << 27) 7832 #define SDE_TC3_HOTPLUG_ICP (1 << 26) 7833 #define SDE_TC2_HOTPLUG_ICP (1 << 25) 7834 #define SDE_TC1_HOTPLUG_ICP (1 << 24) 7835 #define SDE_GMBUS_ICP (1 << 23) 7836 #define SDE_DDIB_HOTPLUG_ICP (1 << 17) 7837 #define SDE_DDIA_HOTPLUG_ICP (1 << 16) 7838 #define SDE_TC_HOTPLUG_ICP(tc_port) (1 << ((tc_port) + 24)) 7839 #define SDE_DDI_HOTPLUG_ICP(port) (1 << ((port) + 16)) 7840 #define SDE_DDI_MASK_ICP (SDE_DDIB_HOTPLUG_ICP | \ 7841 SDE_DDIA_HOTPLUG_ICP) 7842 #define SDE_TC_MASK_ICP (SDE_TC4_HOTPLUG_ICP | \ 7843 SDE_TC3_HOTPLUG_ICP | \ 7844 SDE_TC2_HOTPLUG_ICP | \ 7845 SDE_TC1_HOTPLUG_ICP) 7846 7847 #define SDEISR _MMIO(0xc4000) 7848 #define SDEIMR _MMIO(0xc4004) 7849 #define SDEIIR _MMIO(0xc4008) 7850 #define SDEIER _MMIO(0xc400c) 7851 7852 #define SERR_INT _MMIO(0xc4040) 7853 #define SERR_INT_POISON (1 << 31) 7854 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) 7855 7856 /* digital port hotplug */ 7857 #define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */ 7858 #define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */ 7859 #define BXT_DDIA_HPD_INVERT (1 << 27) 7860 #define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */ 7861 #define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */ 7862 #define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */ 7863 #define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */ 7864 #define PORTD_HOTPLUG_ENABLE (1 << 20) 7865 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */ 7866 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */ 7867 #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */ 7868 #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */ 7869 #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */ 7870 #define PORTD_HOTPLUG_STATUS_MASK (3 << 16) 7871 #define PORTD_HOTPLUG_NO_DETECT (0 << 16) 7872 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) 7873 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16) 7874 #define PORTC_HOTPLUG_ENABLE (1 << 12) 7875 #define BXT_DDIC_HPD_INVERT (1 << 11) 7876 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */ 7877 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */ 7878 #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */ 7879 #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */ 7880 #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */ 7881 #define PORTC_HOTPLUG_STATUS_MASK (3 << 8) 7882 #define PORTC_HOTPLUG_NO_DETECT (0 << 8) 7883 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) 7884 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8) 7885 #define PORTB_HOTPLUG_ENABLE (1 << 4) 7886 #define BXT_DDIB_HPD_INVERT (1 << 3) 7887 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */ 7888 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */ 7889 #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */ 7890 #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */ 7891 #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */ 7892 #define PORTB_HOTPLUG_STATUS_MASK (3 << 0) 7893 #define PORTB_HOTPLUG_NO_DETECT (0 << 0) 7894 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) 7895 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0) 7896 #define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \ 7897 BXT_DDIB_HPD_INVERT | \ 7898 BXT_DDIC_HPD_INVERT) 7899 7900 #define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */ 7901 #define PORTE_HOTPLUG_ENABLE (1 << 4) 7902 #define PORTE_HOTPLUG_STATUS_MASK (3 << 0) 7903 #define PORTE_HOTPLUG_NO_DETECT (0 << 0) 7904 #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0) 7905 #define PORTE_HOTPLUG_LONG_DETECT (2 << 0) 7906 7907 /* This register is a reuse of PCH_PORT_HOTPLUG register. The 7908 * functionality covered in PCH_PORT_HOTPLUG is split into 7909 * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC. 7910 */ 7911 7912 #define SHOTPLUG_CTL_DDI _MMIO(0xc4030) 7913 #define ICP_DDIB_HPD_ENABLE (1 << 7) 7914 #define ICP_DDIB_HPD_STATUS_MASK (3 << 4) 7915 #define ICP_DDIB_HPD_NO_DETECT (0 << 4) 7916 #define ICP_DDIB_HPD_SHORT_DETECT (1 << 4) 7917 #define ICP_DDIB_HPD_LONG_DETECT (2 << 4) 7918 #define ICP_DDIB_HPD_SHORT_LONG_DETECT (3 << 4) 7919 #define ICP_DDIA_HPD_ENABLE (1 << 3) 7920 #define ICP_DDIA_HPD_OP_DRIVE_1 (1 << 2) 7921 #define ICP_DDIA_HPD_STATUS_MASK (3 << 0) 7922 #define ICP_DDIA_HPD_NO_DETECT (0 << 0) 7923 #define ICP_DDIA_HPD_SHORT_DETECT (1 << 0) 7924 #define ICP_DDIA_HPD_LONG_DETECT (2 << 0) 7925 #define ICP_DDIA_HPD_SHORT_LONG_DETECT (3 << 0) 7926 7927 #define SHOTPLUG_CTL_TC _MMIO(0xc4034) 7928 #define ICP_TC_HPD_ENABLE(tc_port) (8 << (tc_port) * 4) 7929 /* Icelake DSC Rate Control Range Parameter Registers */ 7930 #define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240) 7931 #define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4) 7932 #define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40) 7933 #define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4) 7934 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208) 7935 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4) 7936 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308) 7937 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4) 7938 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408) 7939 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4) 7940 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508) 7941 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4) 7942 #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7943 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \ 7944 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC) 7945 #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7946 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \ 7947 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC) 7948 #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7949 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \ 7950 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC) 7951 #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7952 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \ 7953 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC) 7954 #define RC_BPG_OFFSET_SHIFT 10 7955 #define RC_MAX_QP_SHIFT 5 7956 #define RC_MIN_QP_SHIFT 0 7957 7958 #define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248) 7959 #define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4) 7960 #define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48) 7961 #define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4) 7962 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210) 7963 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4) 7964 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310) 7965 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4) 7966 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410) 7967 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4) 7968 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510) 7969 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4) 7970 #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7971 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \ 7972 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC) 7973 #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7974 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \ 7975 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC) 7976 #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7977 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \ 7978 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC) 7979 #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7980 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \ 7981 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC) 7982 7983 #define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250) 7984 #define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4) 7985 #define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50) 7986 #define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4) 7987 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218) 7988 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4) 7989 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318) 7990 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4) 7991 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418) 7992 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4) 7993 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518) 7994 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4) 7995 #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7996 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \ 7997 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC) 7998 #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7999 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \ 8000 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC) 8001 #define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8002 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \ 8003 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC) 8004 #define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8005 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \ 8006 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC) 8007 8008 #define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258) 8009 #define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4) 8010 #define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58) 8011 #define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4) 8012 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220) 8013 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4) 8014 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320) 8015 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4) 8016 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420) 8017 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4) 8018 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520) 8019 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4) 8020 #define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8021 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \ 8022 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC) 8023 #define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8024 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \ 8025 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC) 8026 #define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8027 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \ 8028 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC) 8029 #define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8030 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \ 8031 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC) 8032 8033 #define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4) 8034 #define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4) 8035 8036 #define _PCH_DPLL_A 0xc6014 8037 #define _PCH_DPLL_B 0xc6018 8038 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) 8039 8040 #define _PCH_FPA0 0xc6040 8041 #define FP_CB_TUNE (0x3 << 22) 8042 #define _PCH_FPA1 0xc6044 8043 #define _PCH_FPB0 0xc6048 8044 #define _PCH_FPB1 0xc604c 8045 #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0) 8046 #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1) 8047 8048 #define PCH_DPLL_TEST _MMIO(0xc606c) 8049 8050 #define PCH_DREF_CONTROL _MMIO(0xC6200) 8051 #define DREF_CONTROL_MASK 0x7fc3 8052 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13) 8053 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13) 8054 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13) 8055 #define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13) 8056 #define DREF_SSC_SOURCE_DISABLE (0 << 11) 8057 #define DREF_SSC_SOURCE_ENABLE (2 << 11) 8058 #define DREF_SSC_SOURCE_MASK (3 << 11) 8059 #define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9) 8060 #define DREF_NONSPREAD_CK505_ENABLE (1 << 9) 8061 #define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9) 8062 #define DREF_NONSPREAD_SOURCE_MASK (3 << 9) 8063 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7) 8064 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7) 8065 #define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7) 8066 #define DREF_SSC4_DOWNSPREAD (0 << 6) 8067 #define DREF_SSC4_CENTERSPREAD (1 << 6) 8068 #define DREF_SSC1_DISABLE (0 << 1) 8069 #define DREF_SSC1_ENABLE (1 << 1) 8070 #define DREF_SSC4_DISABLE (0) 8071 #define DREF_SSC4_ENABLE (1) 8072 8073 #define PCH_RAWCLK_FREQ _MMIO(0xc6204) 8074 #define FDL_TP1_TIMER_SHIFT 12 8075 #define FDL_TP1_TIMER_MASK (3 << 12) 8076 #define FDL_TP2_TIMER_SHIFT 10 8077 #define FDL_TP2_TIMER_MASK (3 << 10) 8078 #define RAWCLK_FREQ_MASK 0x3ff 8079 #define CNP_RAWCLK_DIV_MASK (0x3ff << 16) 8080 #define CNP_RAWCLK_DIV(div) ((div) << 16) 8081 #define CNP_RAWCLK_FRAC_MASK (0xf << 26) 8082 #define CNP_RAWCLK_DEN(den) ((den) << 26) 8083 #define ICP_RAWCLK_NUM(num) ((num) << 11) 8084 8085 #define PCH_DPLL_TMR_CFG _MMIO(0xc6208) 8086 8087 #define PCH_SSC4_PARMS _MMIO(0xc6210) 8088 #define PCH_SSC4_AUX_PARMS _MMIO(0xc6214) 8089 8090 #define PCH_DPLL_SEL _MMIO(0xc7000) 8091 #define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4)) 8092 #define TRANS_DPLLA_SEL(pipe) 0 8093 #define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3)) 8094 8095 /* transcoder */ 8096 8097 #define _PCH_TRANS_HTOTAL_A 0xe0000 8098 #define TRANS_HTOTAL_SHIFT 16 8099 #define TRANS_HACTIVE_SHIFT 0 8100 #define _PCH_TRANS_HBLANK_A 0xe0004 8101 #define TRANS_HBLANK_END_SHIFT 16 8102 #define TRANS_HBLANK_START_SHIFT 0 8103 #define _PCH_TRANS_HSYNC_A 0xe0008 8104 #define TRANS_HSYNC_END_SHIFT 16 8105 #define TRANS_HSYNC_START_SHIFT 0 8106 #define _PCH_TRANS_VTOTAL_A 0xe000c 8107 #define TRANS_VTOTAL_SHIFT 16 8108 #define TRANS_VACTIVE_SHIFT 0 8109 #define _PCH_TRANS_VBLANK_A 0xe0010 8110 #define TRANS_VBLANK_END_SHIFT 16 8111 #define TRANS_VBLANK_START_SHIFT 0 8112 #define _PCH_TRANS_VSYNC_A 0xe0014 8113 #define TRANS_VSYNC_END_SHIFT 16 8114 #define TRANS_VSYNC_START_SHIFT 0 8115 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028 8116 8117 #define _PCH_TRANSA_DATA_M1 0xe0030 8118 #define _PCH_TRANSA_DATA_N1 0xe0034 8119 #define _PCH_TRANSA_DATA_M2 0xe0038 8120 #define _PCH_TRANSA_DATA_N2 0xe003c 8121 #define _PCH_TRANSA_LINK_M1 0xe0040 8122 #define _PCH_TRANSA_LINK_N1 0xe0044 8123 #define _PCH_TRANSA_LINK_M2 0xe0048 8124 #define _PCH_TRANSA_LINK_N2 0xe004c 8125 8126 /* Per-transcoder DIP controls (PCH) */ 8127 #define _VIDEO_DIP_CTL_A 0xe0200 8128 #define _VIDEO_DIP_DATA_A 0xe0208 8129 #define _VIDEO_DIP_GCP_A 0xe0210 8130 #define GCP_COLOR_INDICATION (1 << 2) 8131 #define GCP_DEFAULT_PHASE_ENABLE (1 << 1) 8132 #define GCP_AV_MUTE (1 << 0) 8133 8134 #define _VIDEO_DIP_CTL_B 0xe1200 8135 #define _VIDEO_DIP_DATA_B 0xe1208 8136 #define _VIDEO_DIP_GCP_B 0xe1210 8137 8138 #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) 8139 #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) 8140 #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) 8141 8142 /* Per-transcoder DIP controls (VLV) */ 8143 #define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200) 8144 #define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208) 8145 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210) 8146 8147 #define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170) 8148 #define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174) 8149 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178) 8150 8151 #define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0) 8152 #define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4) 8153 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8) 8154 8155 #define VLV_TVIDEO_DIP_CTL(pipe) \ 8156 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \ 8157 _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C) 8158 #define VLV_TVIDEO_DIP_DATA(pipe) \ 8159 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \ 8160 _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C) 8161 #define VLV_TVIDEO_DIP_GCP(pipe) \ 8162 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \ 8163 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C) 8164 8165 /* Haswell DIP controls */ 8166 8167 #define _HSW_VIDEO_DIP_CTL_A 0x60200 8168 #define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220 8169 #define _HSW_VIDEO_DIP_VS_DATA_A 0x60260 8170 #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 8171 #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 8172 #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320 8173 #define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440 8174 #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240 8175 #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280 8176 #define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 8177 #define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300 8178 #define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344 8179 #define _HSW_VIDEO_DIP_GCP_A 0x60210 8180 8181 #define _HSW_VIDEO_DIP_CTL_B 0x61200 8182 #define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220 8183 #define _HSW_VIDEO_DIP_VS_DATA_B 0x61260 8184 #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 8185 #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 8186 #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320 8187 #define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440 8188 #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240 8189 #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280 8190 #define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 8191 #define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300 8192 #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344 8193 #define _HSW_VIDEO_DIP_GCP_B 0x61210 8194 8195 /* Icelake PPS_DATA and _ECC DIP Registers. 8196 * These are available for transcoders B,C and eDP. 8197 * Adding the _A so as to reuse the _MMIO_TRANS2 8198 * definition, with which it offsets to the right location. 8199 */ 8200 8201 #define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350 8202 #define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350 8203 #define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4 8204 #define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4 8205 8206 #define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A) 8207 #define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A) 8208 #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4) 8209 #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4) 8210 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) 8211 #define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4) 8212 #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) 8213 #define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4) 8214 #define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4) 8215 #define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4) 8216 8217 #define _HSW_STEREO_3D_CTL_A 0x70020 8218 #define S3D_ENABLE (1 << 31) 8219 #define _HSW_STEREO_3D_CTL_B 0x71020 8220 8221 #define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A) 8222 8223 #define _PCH_TRANS_HTOTAL_B 0xe1000 8224 #define _PCH_TRANS_HBLANK_B 0xe1004 8225 #define _PCH_TRANS_HSYNC_B 0xe1008 8226 #define _PCH_TRANS_VTOTAL_B 0xe100c 8227 #define _PCH_TRANS_VBLANK_B 0xe1010 8228 #define _PCH_TRANS_VSYNC_B 0xe1014 8229 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 8230 8231 #define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B) 8232 #define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B) 8233 #define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B) 8234 #define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B) 8235 #define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B) 8236 #define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B) 8237 #define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B) 8238 8239 #define _PCH_TRANSB_DATA_M1 0xe1030 8240 #define _PCH_TRANSB_DATA_N1 0xe1034 8241 #define _PCH_TRANSB_DATA_M2 0xe1038 8242 #define _PCH_TRANSB_DATA_N2 0xe103c 8243 #define _PCH_TRANSB_LINK_M1 0xe1040 8244 #define _PCH_TRANSB_LINK_N1 0xe1044 8245 #define _PCH_TRANSB_LINK_M2 0xe1048 8246 #define _PCH_TRANSB_LINK_N2 0xe104c 8247 8248 #define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1) 8249 #define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1) 8250 #define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2) 8251 #define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2) 8252 #define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1) 8253 #define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1) 8254 #define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2) 8255 #define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2) 8256 8257 #define _PCH_TRANSACONF 0xf0008 8258 #define _PCH_TRANSBCONF 0xf1008 8259 #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF) 8260 #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */ 8261 #define TRANS_DISABLE (0 << 31) 8262 #define TRANS_ENABLE (1 << 31) 8263 #define TRANS_STATE_MASK (1 << 30) 8264 #define TRANS_STATE_DISABLE (0 << 30) 8265 #define TRANS_STATE_ENABLE (1 << 30) 8266 #define TRANS_FSYNC_DELAY_HB1 (0 << 27) 8267 #define TRANS_FSYNC_DELAY_HB2 (1 << 27) 8268 #define TRANS_FSYNC_DELAY_HB3 (2 << 27) 8269 #define TRANS_FSYNC_DELAY_HB4 (3 << 27) 8270 #define TRANS_INTERLACE_MASK (7 << 21) 8271 #define TRANS_PROGRESSIVE (0 << 21) 8272 #define TRANS_INTERLACED (3 << 21) 8273 #define TRANS_LEGACY_INTERLACED_ILK (2 << 21) 8274 #define TRANS_8BPC (0 << 5) 8275 #define TRANS_10BPC (1 << 5) 8276 #define TRANS_6BPC (2 << 5) 8277 #define TRANS_12BPC (3 << 5) 8278 8279 #define _TRANSA_CHICKEN1 0xf0060 8280 #define _TRANSB_CHICKEN1 0xf1060 8281 #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) 8282 #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1 << 10) 8283 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1 << 4) 8284 #define _TRANSA_CHICKEN2 0xf0064 8285 #define _TRANSB_CHICKEN2 0xf1064 8286 #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) 8287 #define TRANS_CHICKEN2_TIMING_OVERRIDE (1 << 31) 8288 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1 << 29) 8289 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3 << 27) 8290 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1 << 26) 8291 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1 << 25) 8292 8293 #define SOUTH_CHICKEN1 _MMIO(0xc2000) 8294 #define FDIA_PHASE_SYNC_SHIFT_OVR 19 8295 #define FDIA_PHASE_SYNC_SHIFT_EN 18 8296 #define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) 8297 #define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) 8298 #define FDI_BC_BIFURCATION_SELECT (1 << 12) 8299 #define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8) 8300 #define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8) 8301 #define SPT_PWM_GRANULARITY (1 << 0) 8302 #define SOUTH_CHICKEN2 _MMIO(0xc2004) 8303 #define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13) 8304 #define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12) 8305 #define LPT_PWM_GRANULARITY (1 << 5) 8306 #define DPLS_EDP_PPS_FIX_DIS (1 << 0) 8307 8308 #define _FDI_RXA_CHICKEN 0xc200c 8309 #define _FDI_RXB_CHICKEN 0xc2010 8310 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1 << 1) 8311 #define FDI_RX_PHASE_SYNC_POINTER_EN (1 << 0) 8312 #define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) 8313 8314 #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020) 8315 #define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31) 8316 #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30) 8317 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29) 8318 #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14) 8319 #define CNP_PWM_CGE_GATING_DISABLE (1 << 13) 8320 #define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12) 8321 8322 /* CPU: FDI_TX */ 8323 #define _FDI_TXA_CTL 0x60100 8324 #define _FDI_TXB_CTL 0x61100 8325 #define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) 8326 #define FDI_TX_DISABLE (0 << 31) 8327 #define FDI_TX_ENABLE (1 << 31) 8328 #define FDI_LINK_TRAIN_PATTERN_1 (0 << 28) 8329 #define FDI_LINK_TRAIN_PATTERN_2 (1 << 28) 8330 #define FDI_LINK_TRAIN_PATTERN_IDLE (2 << 28) 8331 #define FDI_LINK_TRAIN_NONE (3 << 28) 8332 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0 << 25) 8333 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1 << 25) 8334 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2 << 25) 8335 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3 << 25) 8336 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22) 8337 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22) 8338 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22) 8339 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22) 8340 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. 8341 SNB has different settings. */ 8342 /* SNB A-stepping */ 8343 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) 8344 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) 8345 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) 8346 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22) 8347 /* SNB B-stepping */ 8348 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0 << 22) 8349 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a << 22) 8350 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39 << 22) 8351 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38 << 22) 8352 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f << 22) 8353 #define FDI_DP_PORT_WIDTH_SHIFT 19 8354 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT) 8355 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT) 8356 #define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18) 8357 /* Ironlake: hardwired to 1 */ 8358 #define FDI_TX_PLL_ENABLE (1 << 14) 8359 8360 /* Ivybridge has different bits for lolz */ 8361 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0 << 8) 8362 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1 << 8) 8363 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2 << 8) 8364 #define FDI_LINK_TRAIN_NONE_IVB (3 << 8) 8365 8366 /* both Tx and Rx */ 8367 #define FDI_COMPOSITE_SYNC (1 << 11) 8368 #define FDI_LINK_TRAIN_AUTO (1 << 10) 8369 #define FDI_SCRAMBLING_ENABLE (0 << 7) 8370 #define FDI_SCRAMBLING_DISABLE (1 << 7) 8371 8372 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */ 8373 #define _FDI_RXA_CTL 0xf000c 8374 #define _FDI_RXB_CTL 0xf100c 8375 #define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) 8376 #define FDI_RX_ENABLE (1 << 31) 8377 /* train, dp width same as FDI_TX */ 8378 #define FDI_FS_ERRC_ENABLE (1 << 27) 8379 #define FDI_FE_ERRC_ENABLE (1 << 26) 8380 #define FDI_RX_POLARITY_REVERSED_LPT (1 << 16) 8381 #define FDI_8BPC (0 << 16) 8382 #define FDI_10BPC (1 << 16) 8383 #define FDI_6BPC (2 << 16) 8384 #define FDI_12BPC (3 << 16) 8385 #define FDI_RX_LINK_REVERSAL_OVERRIDE (1 << 15) 8386 #define FDI_DMI_LINK_REVERSE_MASK (1 << 14) 8387 #define FDI_RX_PLL_ENABLE (1 << 13) 8388 #define FDI_FS_ERR_CORRECT_ENABLE (1 << 11) 8389 #define FDI_FE_ERR_CORRECT_ENABLE (1 << 10) 8390 #define FDI_FS_ERR_REPORT_ENABLE (1 << 9) 8391 #define FDI_FE_ERR_REPORT_ENABLE (1 << 8) 8392 #define FDI_RX_ENHANCE_FRAME_ENABLE (1 << 6) 8393 #define FDI_PCDCLK (1 << 4) 8394 /* CPT */ 8395 #define FDI_AUTO_TRAINING (1 << 10) 8396 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0 << 8) 8397 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1 << 8) 8398 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2 << 8) 8399 #define FDI_LINK_TRAIN_NORMAL_CPT (3 << 8) 8400 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3 << 8) 8401 8402 #define _FDI_RXA_MISC 0xf0010 8403 #define _FDI_RXB_MISC 0xf1010 8404 #define FDI_RX_PWRDN_LANE1_MASK (3 << 26) 8405 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x) << 26) 8406 #define FDI_RX_PWRDN_LANE0_MASK (3 << 24) 8407 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x) << 24) 8408 #define FDI_RX_TP1_TO_TP2_48 (2 << 20) 8409 #define FDI_RX_TP1_TO_TP2_64 (3 << 20) 8410 #define FDI_RX_FDI_DELAY_90 (0x90 << 0) 8411 #define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) 8412 8413 #define _FDI_RXA_TUSIZE1 0xf0030 8414 #define _FDI_RXA_TUSIZE2 0xf0038 8415 #define _FDI_RXB_TUSIZE1 0xf1030 8416 #define _FDI_RXB_TUSIZE2 0xf1038 8417 #define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) 8418 #define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) 8419 8420 /* FDI_RX interrupt register format */ 8421 #define FDI_RX_INTER_LANE_ALIGN (1 << 10) 8422 #define FDI_RX_SYMBOL_LOCK (1 << 9) /* train 2 */ 8423 #define FDI_RX_BIT_LOCK (1 << 8) /* train 1 */ 8424 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1 << 7) 8425 #define FDI_RX_FS_CODE_ERR (1 << 6) 8426 #define FDI_RX_FE_CODE_ERR (1 << 5) 8427 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1 << 4) 8428 #define FDI_RX_HDCP_LINK_FAIL (1 << 3) 8429 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1 << 2) 8430 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1 << 1) 8431 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1 << 0) 8432 8433 #define _FDI_RXA_IIR 0xf0014 8434 #define _FDI_RXA_IMR 0xf0018 8435 #define _FDI_RXB_IIR 0xf1014 8436 #define _FDI_RXB_IMR 0xf1018 8437 #define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) 8438 #define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) 8439 8440 #define FDI_PLL_CTL_1 _MMIO(0xfe000) 8441 #define FDI_PLL_CTL_2 _MMIO(0xfe004) 8442 8443 #define PCH_LVDS _MMIO(0xe1180) 8444 #define LVDS_DETECTED (1 << 1) 8445 8446 #define _PCH_DP_B 0xe4100 8447 #define PCH_DP_B _MMIO(_PCH_DP_B) 8448 #define _PCH_DPB_AUX_CH_CTL 0xe4110 8449 #define _PCH_DPB_AUX_CH_DATA1 0xe4114 8450 #define _PCH_DPB_AUX_CH_DATA2 0xe4118 8451 #define _PCH_DPB_AUX_CH_DATA3 0xe411c 8452 #define _PCH_DPB_AUX_CH_DATA4 0xe4120 8453 #define _PCH_DPB_AUX_CH_DATA5 0xe4124 8454 8455 #define _PCH_DP_C 0xe4200 8456 #define PCH_DP_C _MMIO(_PCH_DP_C) 8457 #define _PCH_DPC_AUX_CH_CTL 0xe4210 8458 #define _PCH_DPC_AUX_CH_DATA1 0xe4214 8459 #define _PCH_DPC_AUX_CH_DATA2 0xe4218 8460 #define _PCH_DPC_AUX_CH_DATA3 0xe421c 8461 #define _PCH_DPC_AUX_CH_DATA4 0xe4220 8462 #define _PCH_DPC_AUX_CH_DATA5 0xe4224 8463 8464 #define _PCH_DP_D 0xe4300 8465 #define PCH_DP_D _MMIO(_PCH_DP_D) 8466 #define _PCH_DPD_AUX_CH_CTL 0xe4310 8467 #define _PCH_DPD_AUX_CH_DATA1 0xe4314 8468 #define _PCH_DPD_AUX_CH_DATA2 0xe4318 8469 #define _PCH_DPD_AUX_CH_DATA3 0xe431c 8470 #define _PCH_DPD_AUX_CH_DATA4 0xe4320 8471 #define _PCH_DPD_AUX_CH_DATA5 0xe4324 8472 8473 #define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL) 8474 #define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ 8475 8476 /* CPT */ 8477 #define _TRANS_DP_CTL_A 0xe0300 8478 #define _TRANS_DP_CTL_B 0xe1300 8479 #define _TRANS_DP_CTL_C 0xe2300 8480 #define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B) 8481 #define TRANS_DP_OUTPUT_ENABLE (1 << 31) 8482 #define TRANS_DP_PORT_SEL_MASK (3 << 29) 8483 #define TRANS_DP_PORT_SEL_NONE (3 << 29) 8484 #define TRANS_DP_PORT_SEL(port) (((port) - PORT_B) << 29) 8485 #define TRANS_DP_AUDIO_ONLY (1 << 26) 8486 #define TRANS_DP_ENH_FRAMING (1 << 18) 8487 #define TRANS_DP_8BPC (0 << 9) 8488 #define TRANS_DP_10BPC (1 << 9) 8489 #define TRANS_DP_6BPC (2 << 9) 8490 #define TRANS_DP_12BPC (3 << 9) 8491 #define TRANS_DP_BPC_MASK (3 << 9) 8492 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1 << 4) 8493 #define TRANS_DP_VSYNC_ACTIVE_LOW 0 8494 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1 << 3) 8495 #define TRANS_DP_HSYNC_ACTIVE_LOW 0 8496 #define TRANS_DP_SYNC_MASK (3 << 3) 8497 8498 /* SNB eDP training params */ 8499 /* SNB A-stepping */ 8500 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) 8501 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) 8502 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) 8503 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22) 8504 /* SNB B-stepping */ 8505 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22) 8506 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22) 8507 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22) 8508 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22) 8509 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22) 8510 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22) 8511 8512 /* IVB */ 8513 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22) 8514 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22) 8515 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22) 8516 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22) 8517 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22) 8518 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22) 8519 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22) 8520 8521 /* legacy values */ 8522 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22) 8523 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22) 8524 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22) 8525 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22) 8526 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22) 8527 8528 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22) 8529 8530 #define VLV_PMWGICZ _MMIO(0x1300a4) 8531 8532 #define RC6_LOCATION _MMIO(0xD40) 8533 #define RC6_CTX_IN_DRAM (1 << 0) 8534 #define RC6_CTX_BASE _MMIO(0xD48) 8535 #define RC6_CTX_BASE_MASK 0xFFFFFFF0 8536 #define PWRCTX_MAXCNT_RCSUNIT _MMIO(0x2054) 8537 #define PWRCTX_MAXCNT_VCSUNIT0 _MMIO(0x12054) 8538 #define PWRCTX_MAXCNT_BCSUNIT _MMIO(0x22054) 8539 #define PWRCTX_MAXCNT_VECSUNIT _MMIO(0x1A054) 8540 #define PWRCTX_MAXCNT_VCSUNIT1 _MMIO(0x1C054) 8541 #define IDLE_TIME_MASK 0xFFFFF 8542 #define FORCEWAKE _MMIO(0xA18C) 8543 #define FORCEWAKE_VLV _MMIO(0x1300b0) 8544 #define FORCEWAKE_ACK_VLV _MMIO(0x1300b4) 8545 #define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8) 8546 #define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc) 8547 #define FORCEWAKE_ACK_HSW _MMIO(0x130044) 8548 #define FORCEWAKE_ACK _MMIO(0x130090) 8549 #define VLV_GTLC_WAKE_CTRL _MMIO(0x130090) 8550 #define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25) 8551 #define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24) 8552 #define VLV_GTLC_ALLOWWAKEREQ (1 << 0) 8553 8554 #define VLV_GTLC_PW_STATUS _MMIO(0x130094) 8555 #define VLV_GTLC_ALLOWWAKEACK (1 << 0) 8556 #define VLV_GTLC_ALLOWWAKEERR (1 << 1) 8557 #define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5) 8558 #define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7) 8559 #define FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded */ 8560 #define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270) 8561 #define FORCEWAKE_MEDIA_VDBOX_GEN11(n) _MMIO(0xa540 + (n) * 4) 8562 #define FORCEWAKE_MEDIA_VEBOX_GEN11(n) _MMIO(0xa560 + (n) * 4) 8563 #define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278) 8564 #define FORCEWAKE_BLITTER_GEN9 _MMIO(0xa188) 8565 #define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0x0D88) 8566 #define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n) _MMIO(0x0D50 + (n) * 4) 8567 #define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n) _MMIO(0x0D70 + (n) * 4) 8568 #define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0x0D84) 8569 #define FORCEWAKE_ACK_BLITTER_GEN9 _MMIO(0x130044) 8570 #define FORCEWAKE_KERNEL BIT(0) 8571 #define FORCEWAKE_USER BIT(1) 8572 #define FORCEWAKE_KERNEL_FALLBACK BIT(15) 8573 #define FORCEWAKE_MT_ACK _MMIO(0x130040) 8574 #define ECOBUS _MMIO(0xa180) 8575 #define FORCEWAKE_MT_ENABLE (1 << 5) 8576 #define VLV_SPAREG2H _MMIO(0xA194) 8577 #define GEN9_PWRGT_DOMAIN_STATUS _MMIO(0xA2A0) 8578 #define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0) 8579 #define GEN9_PWRGT_RENDER_STATUS_MASK (1 << 1) 8580 8581 #define GTFIFODBG _MMIO(0x120000) 8582 #define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20) 8583 #define GT_FIFO_FREE_ENTRIES_CHV (0x7f << 13) 8584 #define GT_FIFO_SBDROPERR (1 << 6) 8585 #define GT_FIFO_BLOBDROPERR (1 << 5) 8586 #define GT_FIFO_SB_READ_ABORTERR (1 << 4) 8587 #define GT_FIFO_DROPERR (1 << 3) 8588 #define GT_FIFO_OVFERR (1 << 2) 8589 #define GT_FIFO_IAWRERR (1 << 1) 8590 #define GT_FIFO_IARDERR (1 << 0) 8591 8592 #define GTFIFOCTL _MMIO(0x120008) 8593 #define GT_FIFO_FREE_ENTRIES_MASK 0x7f 8594 #define GT_FIFO_NUM_RESERVED_ENTRIES 20 8595 #define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12) 8596 #define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11) 8597 8598 #define HSW_IDICR _MMIO(0x9008) 8599 #define IDIHASHMSK(x) (((x) & 0x3f) << 16) 8600 #define HSW_EDRAM_CAP _MMIO(0x120010) 8601 #define EDRAM_ENABLED 0x1 8602 #define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf) 8603 #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7) 8604 #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3) 8605 8606 #define GEN6_UCGCTL1 _MMIO(0x9400) 8607 # define GEN6_GAMUNIT_CLOCK_GATE_DISABLE (1 << 22) 8608 # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16) 8609 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) 8610 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7) 8611 8612 #define GEN6_UCGCTL2 _MMIO(0x9404) 8613 # define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31) 8614 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30) 8615 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22) 8616 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) 8617 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) 8618 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11) 8619 8620 #define GEN6_UCGCTL3 _MMIO(0x9408) 8621 # define GEN6_OACSUNIT_CLOCK_GATE_DISABLE (1 << 20) 8622 8623 #define GEN7_UCGCTL4 _MMIO(0x940c) 8624 #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1 << 25) 8625 #define GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE (1 << 14) 8626 8627 #define GEN6_RCGCTL1 _MMIO(0x9410) 8628 #define GEN6_RCGCTL2 _MMIO(0x9414) 8629 #define GEN6_RSTCTL _MMIO(0x9420) 8630 8631 #define GEN8_UCGCTL6 _MMIO(0x9430) 8632 #define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1 << 24) 8633 #define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1 << 14) 8634 #define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1 << 28) 8635 8636 #define GEN6_GFXPAUSE _MMIO(0xA000) 8637 #define GEN6_RPNSWREQ _MMIO(0xA008) 8638 #define GEN6_TURBO_DISABLE (1 << 31) 8639 #define GEN6_FREQUENCY(x) ((x) << 25) 8640 #define HSW_FREQUENCY(x) ((x) << 24) 8641 #define GEN9_FREQUENCY(x) ((x) << 23) 8642 #define GEN6_OFFSET(x) ((x) << 19) 8643 #define GEN6_AGGRESSIVE_TURBO (0 << 15) 8644 #define GEN6_RC_VIDEO_FREQ _MMIO(0xA00C) 8645 #define GEN6_RC_CONTROL _MMIO(0xA090) 8646 #define GEN6_RC_CTL_RC6pp_ENABLE (1 << 16) 8647 #define GEN6_RC_CTL_RC6p_ENABLE (1 << 17) 8648 #define GEN6_RC_CTL_RC6_ENABLE (1 << 18) 8649 #define GEN6_RC_CTL_RC1e_ENABLE (1 << 20) 8650 #define GEN6_RC_CTL_RC7_ENABLE (1 << 22) 8651 #define VLV_RC_CTL_CTX_RST_PARALLEL (1 << 24) 8652 #define GEN7_RC_CTL_TO_MODE (1 << 28) 8653 #define GEN6_RC_CTL_EI_MODE(x) ((x) << 27) 8654 #define GEN6_RC_CTL_HW_ENABLE (1 << 31) 8655 #define GEN6_RP_DOWN_TIMEOUT _MMIO(0xA010) 8656 #define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xA014) 8657 #define GEN6_RPSTAT1 _MMIO(0xA01C) 8658 #define GEN6_CAGF_SHIFT 8 8659 #define HSW_CAGF_SHIFT 7 8660 #define GEN9_CAGF_SHIFT 23 8661 #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) 8662 #define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT) 8663 #define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT) 8664 #define GEN6_RP_CONTROL _MMIO(0xA024) 8665 #define GEN6_RP_MEDIA_TURBO (1 << 11) 8666 #define GEN6_RP_MEDIA_MODE_MASK (3 << 9) 8667 #define GEN6_RP_MEDIA_HW_TURBO_MODE (3 << 9) 8668 #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2 << 9) 8669 #define GEN6_RP_MEDIA_HW_MODE (1 << 9) 8670 #define GEN6_RP_MEDIA_SW_MODE (0 << 9) 8671 #define GEN6_RP_MEDIA_IS_GFX (1 << 8) 8672 #define GEN6_RP_ENABLE (1 << 7) 8673 #define GEN6_RP_UP_IDLE_MIN (0x1 << 3) 8674 #define GEN6_RP_UP_BUSY_AVG (0x2 << 3) 8675 #define GEN6_RP_UP_BUSY_CONT (0x4 << 3) 8676 #define GEN6_RP_DOWN_IDLE_AVG (0x2 << 0) 8677 #define GEN6_RP_DOWN_IDLE_CONT (0x1 << 0) 8678 #define GEN6_RP_UP_THRESHOLD _MMIO(0xA02C) 8679 #define GEN6_RP_DOWN_THRESHOLD _MMIO(0xA030) 8680 #define GEN6_RP_CUR_UP_EI _MMIO(0xA050) 8681 #define GEN6_RP_EI_MASK 0xffffff 8682 #define GEN6_CURICONT_MASK GEN6_RP_EI_MASK 8683 #define GEN6_RP_CUR_UP _MMIO(0xA054) 8684 #define GEN6_CURBSYTAVG_MASK GEN6_RP_EI_MASK 8685 #define GEN6_RP_PREV_UP _MMIO(0xA058) 8686 #define GEN6_RP_CUR_DOWN_EI _MMIO(0xA05C) 8687 #define GEN6_CURIAVG_MASK GEN6_RP_EI_MASK 8688 #define GEN6_RP_CUR_DOWN _MMIO(0xA060) 8689 #define GEN6_RP_PREV_DOWN _MMIO(0xA064) 8690 #define GEN6_RP_UP_EI _MMIO(0xA068) 8691 #define GEN6_RP_DOWN_EI _MMIO(0xA06C) 8692 #define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xA070) 8693 #define GEN6_RPDEUHWTC _MMIO(0xA080) 8694 #define GEN6_RPDEUC _MMIO(0xA084) 8695 #define GEN6_RPDEUCSW _MMIO(0xA088) 8696 #define GEN6_RC_STATE _MMIO(0xA094) 8697 #define RC_SW_TARGET_STATE_SHIFT 16 8698 #define RC_SW_TARGET_STATE_MASK (7 << RC_SW_TARGET_STATE_SHIFT) 8699 #define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098) 8700 #define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C) 8701 #define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0) 8702 #define GEN10_MEDIA_WAKE_RATE_LIMIT _MMIO(0xA0A0) 8703 #define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8) 8704 #define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC) 8705 #define GEN6_RC_SLEEP _MMIO(0xA0B0) 8706 #define GEN6_RCUBMABDTMR _MMIO(0xA0B0) 8707 #define GEN6_RC1e_THRESHOLD _MMIO(0xA0B4) 8708 #define GEN6_RC6_THRESHOLD _MMIO(0xA0B8) 8709 #define GEN6_RC6p_THRESHOLD _MMIO(0xA0BC) 8710 #define VLV_RCEDATA _MMIO(0xA0BC) 8711 #define GEN6_RC6pp_THRESHOLD _MMIO(0xA0C0) 8712 #define GEN6_PMINTRMSK _MMIO(0xA168) 8713 #define GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC (1 << 31) 8714 #define ARAT_EXPIRED_INTRMSK (1 << 9) 8715 #define GEN8_MISC_CTRL0 _MMIO(0xA180) 8716 #define VLV_PWRDWNUPCTL _MMIO(0xA294) 8717 #define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4) 8718 #define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8) 8719 #define GEN9_PG_ENABLE _MMIO(0xA210) 8720 #define GEN9_RENDER_PG_ENABLE REG_BIT(0) 8721 #define GEN9_MEDIA_PG_ENABLE REG_BIT(1) 8722 #define GEN11_MEDIA_SAMPLER_PG_ENABLE REG_BIT(2) 8723 #define GEN8_PUSHBUS_CONTROL _MMIO(0xA248) 8724 #define GEN8_PUSHBUS_ENABLE _MMIO(0xA250) 8725 #define GEN8_PUSHBUS_SHIFT _MMIO(0xA25C) 8726 8727 #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C) 8728 #define PIXEL_OVERLAP_CNT_MASK (3 << 30) 8729 #define PIXEL_OVERLAP_CNT_SHIFT 30 8730 8731 #define GEN6_PMISR _MMIO(0x44020) 8732 #define GEN6_PMIMR _MMIO(0x44024) /* rps_lock */ 8733 #define GEN6_PMIIR _MMIO(0x44028) 8734 #define GEN6_PMIER _MMIO(0x4402C) 8735 #define GEN6_PM_MBOX_EVENT (1 << 25) 8736 #define GEN6_PM_THERMAL_EVENT (1 << 24) 8737 8738 /* 8739 * For Gen11 these are in the upper word of the GPM_WGBOXPERF 8740 * registers. Shifting is handled on accessing the imr and ier. 8741 */ 8742 #define GEN6_PM_RP_DOWN_TIMEOUT (1 << 6) 8743 #define GEN6_PM_RP_UP_THRESHOLD (1 << 5) 8744 #define GEN6_PM_RP_DOWN_THRESHOLD (1 << 4) 8745 #define GEN6_PM_RP_UP_EI_EXPIRED (1 << 2) 8746 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1 << 1) 8747 #define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_EI_EXPIRED | \ 8748 GEN6_PM_RP_UP_THRESHOLD | \ 8749 GEN6_PM_RP_DOWN_EI_EXPIRED | \ 8750 GEN6_PM_RP_DOWN_THRESHOLD | \ 8751 GEN6_PM_RP_DOWN_TIMEOUT) 8752 8753 #define GEN7_GT_SCRATCH(i) _MMIO(0x4F100 + (i) * 4) 8754 #define GEN7_GT_SCRATCH_REG_NUM 8 8755 8756 #define VLV_GTLC_SURVIVABILITY_REG _MMIO(0x130098) 8757 #define VLV_GFX_CLK_STATUS_BIT (1 << 3) 8758 #define VLV_GFX_CLK_FORCE_ON_BIT (1 << 2) 8759 8760 #define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104) 8761 #define VLV_COUNTER_CONTROL _MMIO(0x138104) 8762 #define VLV_COUNT_RANGE_HIGH (1 << 15) 8763 #define VLV_MEDIA_RC0_COUNT_EN (1 << 5) 8764 #define VLV_RENDER_RC0_COUNT_EN (1 << 4) 8765 #define VLV_MEDIA_RC6_COUNT_EN (1 << 1) 8766 #define VLV_RENDER_RC6_COUNT_EN (1 << 0) 8767 #define GEN6_GT_GFX_RC6 _MMIO(0x138108) 8768 #define VLV_GT_RENDER_RC6 _MMIO(0x138108) 8769 #define VLV_GT_MEDIA_RC6 _MMIO(0x13810C) 8770 8771 #define GEN6_GT_GFX_RC6p _MMIO(0x13810C) 8772 #define GEN6_GT_GFX_RC6pp _MMIO(0x138110) 8773 #define VLV_RENDER_C0_COUNT _MMIO(0x138118) 8774 #define VLV_MEDIA_C0_COUNT _MMIO(0x13811C) 8775 8776 #define GEN6_PCODE_MAILBOX _MMIO(0x138124) 8777 #define GEN6_PCODE_READY (1 << 31) 8778 #define GEN6_PCODE_ERROR_MASK 0xFF 8779 #define GEN6_PCODE_SUCCESS 0x0 8780 #define GEN6_PCODE_ILLEGAL_CMD 0x1 8781 #define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2 8782 #define GEN6_PCODE_TIMEOUT 0x3 8783 #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF 8784 #define GEN7_PCODE_TIMEOUT 0x2 8785 #define GEN7_PCODE_ILLEGAL_DATA 0x3 8786 #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10 8787 #define GEN6_PCODE_WRITE_RC6VIDS 0x4 8788 #define GEN6_PCODE_READ_RC6VIDS 0x5 8789 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) 8790 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) 8791 #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18 8792 #define GEN9_PCODE_READ_MEM_LATENCY 0x6 8793 #define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF 8794 #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8 8795 #define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16 8796 #define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24 8797 #define SKL_PCODE_LOAD_HDCP_KEYS 0x5 8798 #define SKL_PCODE_CDCLK_CONTROL 0x7 8799 #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3 8800 #define SKL_CDCLK_READY_FOR_CHANGE 0x1 8801 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 8802 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 8803 #define GEN6_READ_OC_PARAMS 0xc 8804 #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd 8805 #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8) 8806 #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8)) 8807 #define GEN6_PCODE_READ_D_COMP 0x10 8808 #define GEN6_PCODE_WRITE_D_COMP 0x11 8809 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17 8810 #define DISPLAY_IPS_CONTROL 0x19 8811 /* See also IPS_CTL */ 8812 #define IPS_PCODE_CONTROL (1 << 30) 8813 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A 8814 #define GEN9_PCODE_SAGV_CONTROL 0x21 8815 #define GEN9_SAGV_DISABLE 0x0 8816 #define GEN9_SAGV_IS_DISABLED 0x1 8817 #define GEN9_SAGV_ENABLE 0x3 8818 #define GEN6_PCODE_DATA _MMIO(0x138128) 8819 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 8820 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 8821 #define GEN6_PCODE_DATA1 _MMIO(0x13812C) 8822 8823 #define GEN6_GT_CORE_STATUS _MMIO(0x138060) 8824 #define GEN6_CORE_CPD_STATE_MASK (7 << 4) 8825 #define GEN6_RCn_MASK 7 8826 #define GEN6_RC0 0 8827 #define GEN6_RC3 2 8828 #define GEN6_RC6 3 8829 #define GEN6_RC7 4 8830 8831 #define GEN8_GT_SLICE_INFO _MMIO(0x138064) 8832 #define GEN8_LSLICESTAT_MASK 0x7 8833 8834 #define CHV_POWER_SS0_SIG1 _MMIO(0xa720) 8835 #define CHV_POWER_SS1_SIG1 _MMIO(0xa728) 8836 #define CHV_SS_PG_ENABLE (1 << 1) 8837 #define CHV_EU08_PG_ENABLE (1 << 9) 8838 #define CHV_EU19_PG_ENABLE (1 << 17) 8839 #define CHV_EU210_PG_ENABLE (1 << 25) 8840 8841 #define CHV_POWER_SS0_SIG2 _MMIO(0xa724) 8842 #define CHV_POWER_SS1_SIG2 _MMIO(0xa72c) 8843 #define CHV_EU311_PG_ENABLE (1 << 1) 8844 8845 #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4) 8846 #define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \ 8847 ((slice) % 3) * 0x4) 8848 #define GEN9_PGCTL_SLICE_ACK (1 << 0) 8849 #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice) * 2)) 8850 #define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F) 8851 8852 #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8) 8853 #define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \ 8854 ((slice) % 3) * 0x8) 8855 #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8) 8856 #define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \ 8857 ((slice) % 3) * 0x8) 8858 #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0) 8859 #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2) 8860 #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4) 8861 #define GEN9_PGCTL_SSA_EU311_ACK (1 << 6) 8862 #define GEN9_PGCTL_SSB_EU08_ACK (1 << 8) 8863 #define GEN9_PGCTL_SSB_EU19_ACK (1 << 10) 8864 #define GEN9_PGCTL_SSB_EU210_ACK (1 << 12) 8865 #define GEN9_PGCTL_SSB_EU311_ACK (1 << 14) 8866 8867 #define GEN7_MISCCPCTL _MMIO(0x9424) 8868 #define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0) 8869 #define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1 << 2) 8870 #define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1 << 4) 8871 #define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1 << 6) 8872 8873 #define GEN8_GARBCNTL _MMIO(0xB004) 8874 #define GEN9_GAPS_TSV_CREDIT_DISABLE (1 << 7) 8875 #define GEN11_ARBITRATION_PRIO_ORDER_MASK (0x3f << 22) 8876 #define GEN11_HASH_CTRL_EXCL_MASK (0x7f << 0) 8877 #define GEN11_HASH_CTRL_EXCL_BIT0 (1 << 0) 8878 8879 #define GEN11_GLBLINVL _MMIO(0xB404) 8880 #define GEN11_BANK_HASH_ADDR_EXCL_MASK (0x7f << 5) 8881 #define GEN11_BANK_HASH_ADDR_EXCL_BIT0 (1 << 5) 8882 8883 #define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550) 8884 #define DFR_DISABLE (1 << 9) 8885 8886 #define GEN11_GACB_PERF_CTRL _MMIO(0x4B80) 8887 #define GEN11_HASH_CTRL_MASK (0x3 << 12 | 0xf << 0) 8888 #define GEN11_HASH_CTRL_BIT0 (1 << 0) 8889 #define GEN11_HASH_CTRL_BIT4 (1 << 12) 8890 8891 #define GEN11_LSN_UNSLCVC _MMIO(0xB43C) 8892 #define GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC (1 << 9) 8893 #define GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC (1 << 7) 8894 8895 #define GEN10_SAMPLER_MODE _MMIO(0xE18C) 8896 #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5) 8897 8898 /* IVYBRIDGE DPF */ 8899 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */ 8900 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14) 8901 #define GEN7_PARITY_ERROR_VALID (1 << 13) 8902 #define GEN7_L3CDERRST1_BANK_MASK (3 << 11) 8903 #define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8) 8904 #define GEN7_PARITY_ERROR_ROW(reg) \ 8905 (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14) 8906 #define GEN7_PARITY_ERROR_BANK(reg) \ 8907 (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11) 8908 #define GEN7_PARITY_ERROR_SUBBANK(reg) \ 8909 (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) 8910 #define GEN7_L3CDERRST1_ENABLE (1 << 7) 8911 8912 #define GEN7_L3LOG(slice, i) _MMIO(0xB070 + (slice) * 0x200 + (i) * 4) 8913 #define GEN7_L3LOG_SIZE 0x80 8914 8915 #define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */ 8916 #define GEN7_HALF_SLICE_CHICKEN1_GT2 _MMIO(0xf100) 8917 #define GEN7_MAX_PS_THREAD_DEP (8 << 12) 8918 #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1 << 10) 8919 #define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1 << 4) 8920 #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1 << 3) 8921 8922 #define GEN9_HALF_SLICE_CHICKEN5 _MMIO(0xe188) 8923 #define GEN9_DG_MIRROR_FIX_ENABLE (1 << 5) 8924 #define GEN9_CCS_TLB_PREFETCH_ENABLE (1 << 3) 8925 8926 #define GEN8_ROW_CHICKEN _MMIO(0xe4f0) 8927 #define FLOW_CONTROL_ENABLE (1 << 15) 8928 #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1 << 8) 8929 #define STALL_DOP_GATING_DISABLE (1 << 5) 8930 #define THROTTLE_12_5 (7 << 2) 8931 #define DISABLE_EARLY_EOT (1 << 1) 8932 8933 #define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4) 8934 #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4) 8935 #define DOP_CLOCK_GATING_DISABLE (1 << 0) 8936 #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8) 8937 #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1) 8938 8939 #define HSW_ROW_CHICKEN3 _MMIO(0xe49c) 8940 #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) 8941 8942 #define HALF_SLICE_CHICKEN2 _MMIO(0xe180) 8943 #define GEN8_ST_PO_DISABLE (1 << 13) 8944 8945 #define HALF_SLICE_CHICKEN3 _MMIO(0xe184) 8946 #define HSW_SAMPLE_C_PERFORMANCE (1 << 9) 8947 #define GEN8_CENTROID_PIXEL_OPT_DIS (1 << 8) 8948 #define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1 << 5) 8949 #define CNL_FAST_ANISO_L1_BANKING_FIX (1 << 4) 8950 #define GEN8_SAMPLER_POWER_BYPASS_DIS (1 << 1) 8951 8952 #define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194) 8953 #define GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR (1 << 8) 8954 #define GEN9_ENABLE_YV12_BUGFIX (1 << 4) 8955 #define GEN9_ENABLE_GPGPU_PREEMPTION (1 << 2) 8956 8957 /* Audio */ 8958 #define G4X_AUD_VID_DID _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020) 8959 #define INTEL_AUDIO_DEVCL 0x808629FB 8960 #define INTEL_AUDIO_DEVBLC 0x80862801 8961 #define INTEL_AUDIO_DEVCTG 0x80862802 8962 8963 #define G4X_AUD_CNTL_ST _MMIO(0x620B4) 8964 #define G4X_ELDV_DEVCL_DEVBLC (1 << 13) 8965 #define G4X_ELDV_DEVCTG (1 << 14) 8966 #define G4X_ELD_ADDR_MASK (0xf << 5) 8967 #define G4X_ELD_ACK (1 << 4) 8968 #define G4X_HDMIW_HDMIEDID _MMIO(0x6210C) 8969 8970 #define _IBX_HDMIW_HDMIEDID_A 0xE2050 8971 #define _IBX_HDMIW_HDMIEDID_B 0xE2150 8972 #define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \ 8973 _IBX_HDMIW_HDMIEDID_B) 8974 #define _IBX_AUD_CNTL_ST_A 0xE20B4 8975 #define _IBX_AUD_CNTL_ST_B 0xE21B4 8976 #define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \ 8977 _IBX_AUD_CNTL_ST_B) 8978 #define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10) 8979 #define IBX_ELD_ADDRESS_MASK (0x1f << 5) 8980 #define IBX_ELD_ACK (1 << 4) 8981 #define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0) 8982 #define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4)) 8983 #define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4)) 8984 8985 #define _CPT_HDMIW_HDMIEDID_A 0xE5050 8986 #define _CPT_HDMIW_HDMIEDID_B 0xE5150 8987 #define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B) 8988 #define _CPT_AUD_CNTL_ST_A 0xE50B4 8989 #define _CPT_AUD_CNTL_ST_B 0xE51B4 8990 #define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B) 8991 #define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0) 8992 8993 #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050) 8994 #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150) 8995 #define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B) 8996 #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4) 8997 #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4) 8998 #define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B) 8999 #define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0) 9000 9001 /* These are the 4 32-bit write offset registers for each stream 9002 * output buffer. It determines the offset from the 9003 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. 9004 */ 9005 #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4) 9006 9007 #define _IBX_AUD_CONFIG_A 0xe2000 9008 #define _IBX_AUD_CONFIG_B 0xe2100 9009 #define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B) 9010 #define _CPT_AUD_CONFIG_A 0xe5000 9011 #define _CPT_AUD_CONFIG_B 0xe5100 9012 #define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B) 9013 #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000) 9014 #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100) 9015 #define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B) 9016 9017 #define AUD_CONFIG_N_VALUE_INDEX (1 << 29) 9018 #define AUD_CONFIG_N_PROG_ENABLE (1 << 28) 9019 #define AUD_CONFIG_UPPER_N_SHIFT 20 9020 #define AUD_CONFIG_UPPER_N_MASK (0xff << 20) 9021 #define AUD_CONFIG_LOWER_N_SHIFT 4 9022 #define AUD_CONFIG_LOWER_N_MASK (0xfff << 4) 9023 #define AUD_CONFIG_N_MASK (AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK) 9024 #define AUD_CONFIG_N(n) \ 9025 (((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) | \ 9026 (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT)) 9027 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 9028 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16) 9029 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16) 9030 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16) 9031 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16) 9032 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16) 9033 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16) 9034 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16) 9035 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16) 9036 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16) 9037 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16) 9038 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16) 9039 #define AUD_CONFIG_DISABLE_NCTS (1 << 3) 9040 9041 /* HSW Audio */ 9042 #define _HSW_AUD_CONFIG_A 0x65000 9043 #define _HSW_AUD_CONFIG_B 0x65100 9044 #define HSW_AUD_CFG(trans) _MMIO_TRANS(trans, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B) 9045 9046 #define _HSW_AUD_MISC_CTRL_A 0x65010 9047 #define _HSW_AUD_MISC_CTRL_B 0x65110 9048 #define HSW_AUD_MISC_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B) 9049 9050 #define _HSW_AUD_M_CTS_ENABLE_A 0x65028 9051 #define _HSW_AUD_M_CTS_ENABLE_B 0x65128 9052 #define HSW_AUD_M_CTS_ENABLE(trans) _MMIO_TRANS(trans, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B) 9053 #define AUD_M_CTS_M_VALUE_INDEX (1 << 21) 9054 #define AUD_M_CTS_M_PROG_ENABLE (1 << 20) 9055 #define AUD_CONFIG_M_MASK 0xfffff 9056 9057 #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 9058 #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 9059 #define HSW_AUD_DIP_ELD_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B) 9060 9061 /* Audio Digital Converter */ 9062 #define _HSW_AUD_DIG_CNVT_1 0x65080 9063 #define _HSW_AUD_DIG_CNVT_2 0x65180 9064 #define AUD_DIG_CNVT(trans) _MMIO_TRANS(trans, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2) 9065 #define DIP_PORT_SEL_MASK 0x3 9066 9067 #define _HSW_AUD_EDID_DATA_A 0x65050 9068 #define _HSW_AUD_EDID_DATA_B 0x65150 9069 #define HSW_AUD_EDID_DATA(trans) _MMIO_TRANS(trans, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B) 9070 9071 #define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c) 9072 #define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0) 9073 #define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4)) 9074 #define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4)) 9075 #define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4)) 9076 #define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4)) 9077 9078 #define HSW_AUD_CHICKENBIT _MMIO(0x65f10) 9079 #define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15) 9080 9081 /* 9082 * HSW - ICL power wells 9083 * 9084 * Platforms have up to 3 power well control register sets, each set 9085 * controlling up to 16 power wells via a request/status HW flag tuple: 9086 * - main (HSW_PWR_WELL_CTL[1-4]) 9087 * - AUX (ICL_PWR_WELL_CTL_AUX[1-4]) 9088 * - DDI (ICL_PWR_WELL_CTL_DDI[1-4]) 9089 * Each control register set consists of up to 4 registers used by different 9090 * sources that can request a power well to be enabled: 9091 * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1) 9092 * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2) 9093 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set) 9094 * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4) 9095 */ 9096 #define HSW_PWR_WELL_CTL1 _MMIO(0x45400) 9097 #define HSW_PWR_WELL_CTL2 _MMIO(0x45404) 9098 #define HSW_PWR_WELL_CTL3 _MMIO(0x45408) 9099 #define HSW_PWR_WELL_CTL4 _MMIO(0x4540C) 9100 #define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2)) 9101 #define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2)) 9102 9103 /* HSW/BDW power well */ 9104 #define HSW_PW_CTL_IDX_GLOBAL 15 9105 9106 /* SKL/BXT/GLK/CNL power wells */ 9107 #define SKL_PW_CTL_IDX_PW_2 15 9108 #define SKL_PW_CTL_IDX_PW_1 14 9109 #define CNL_PW_CTL_IDX_AUX_F 12 9110 #define CNL_PW_CTL_IDX_AUX_D 11 9111 #define GLK_PW_CTL_IDX_AUX_C 10 9112 #define GLK_PW_CTL_IDX_AUX_B 9 9113 #define GLK_PW_CTL_IDX_AUX_A 8 9114 #define CNL_PW_CTL_IDX_DDI_F 6 9115 #define SKL_PW_CTL_IDX_DDI_D 4 9116 #define SKL_PW_CTL_IDX_DDI_C 3 9117 #define SKL_PW_CTL_IDX_DDI_B 2 9118 #define SKL_PW_CTL_IDX_DDI_A_E 1 9119 #define GLK_PW_CTL_IDX_DDI_A 1 9120 #define SKL_PW_CTL_IDX_MISC_IO 0 9121 9122 /* ICL - power wells */ 9123 #define ICL_PW_CTL_IDX_PW_4 3 9124 #define ICL_PW_CTL_IDX_PW_3 2 9125 #define ICL_PW_CTL_IDX_PW_2 1 9126 #define ICL_PW_CTL_IDX_PW_1 0 9127 9128 #define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440) 9129 #define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444) 9130 #define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C) 9131 #define ICL_PW_CTL_IDX_AUX_TBT4 11 9132 #define ICL_PW_CTL_IDX_AUX_TBT3 10 9133 #define ICL_PW_CTL_IDX_AUX_TBT2 9 9134 #define ICL_PW_CTL_IDX_AUX_TBT1 8 9135 #define ICL_PW_CTL_IDX_AUX_F 5 9136 #define ICL_PW_CTL_IDX_AUX_E 4 9137 #define ICL_PW_CTL_IDX_AUX_D 3 9138 #define ICL_PW_CTL_IDX_AUX_C 2 9139 #define ICL_PW_CTL_IDX_AUX_B 1 9140 #define ICL_PW_CTL_IDX_AUX_A 0 9141 9142 #define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450) 9143 #define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454) 9144 #define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C) 9145 #define ICL_PW_CTL_IDX_DDI_F 5 9146 #define ICL_PW_CTL_IDX_DDI_E 4 9147 #define ICL_PW_CTL_IDX_DDI_D 3 9148 #define ICL_PW_CTL_IDX_DDI_C 2 9149 #define ICL_PW_CTL_IDX_DDI_B 1 9150 #define ICL_PW_CTL_IDX_DDI_A 0 9151 9152 /* HSW - power well misc debug registers */ 9153 #define HSW_PWR_WELL_CTL5 _MMIO(0x45410) 9154 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31) 9155 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20) 9156 #define HSW_PWR_WELL_FORCE_ON (1 << 19) 9157 #define HSW_PWR_WELL_CTL6 _MMIO(0x45414) 9158 9159 /* SKL Fuse Status */ 9160 enum skl_power_gate { 9161 SKL_PG0, 9162 SKL_PG1, 9163 SKL_PG2, 9164 ICL_PG3, 9165 ICL_PG4, 9166 }; 9167 9168 #define SKL_FUSE_STATUS _MMIO(0x42000) 9169 #define SKL_FUSE_DOWNLOAD_STATUS (1 << 31) 9170 /* 9171 * PG0 is HW controlled, so doesn't have a corresponding power well control knob 9172 * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2 9173 */ 9174 #define SKL_PW_CTL_IDX_TO_PG(pw_idx) \ 9175 ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1) 9176 /* 9177 * PG0 is HW controlled, so doesn't have a corresponding power well control knob 9178 * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4 9179 */ 9180 #define ICL_PW_CTL_IDX_TO_PG(pw_idx) \ 9181 ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1) 9182 #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg))) 9183 9184 #define _CNL_AUX_REG_IDX(pw_idx) ((pw_idx) - GLK_PW_CTL_IDX_AUX_B) 9185 #define _CNL_AUX_ANAOVRD1_B 0x162250 9186 #define _CNL_AUX_ANAOVRD1_C 0x162210 9187 #define _CNL_AUX_ANAOVRD1_D 0x1622D0 9188 #define _CNL_AUX_ANAOVRD1_F 0x162A90 9189 #define CNL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw_idx), \ 9190 _CNL_AUX_ANAOVRD1_B, \ 9191 _CNL_AUX_ANAOVRD1_C, \ 9192 _CNL_AUX_ANAOVRD1_D, \ 9193 _CNL_AUX_ANAOVRD1_F)) 9194 #define CNL_AUX_ANAOVRD1_ENABLE (1 << 16) 9195 #define CNL_AUX_ANAOVRD1_LDO_BYPASS (1 << 23) 9196 9197 #define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A) 9198 #define _ICL_AUX_ANAOVRD1_A 0x162398 9199 #define _ICL_AUX_ANAOVRD1_B 0x6C398 9200 #define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \ 9201 _ICL_AUX_ANAOVRD1_A, \ 9202 _ICL_AUX_ANAOVRD1_B)) 9203 #define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7) 9204 #define ICL_AUX_ANAOVRD1_ENABLE (1 << 0) 9205 9206 /* HDCP Key Registers */ 9207 #define HDCP_KEY_CONF _MMIO(0x66c00) 9208 #define HDCP_AKSV_SEND_TRIGGER BIT(31) 9209 #define HDCP_CLEAR_KEYS_TRIGGER BIT(30) 9210 #define HDCP_KEY_LOAD_TRIGGER BIT(8) 9211 #define HDCP_KEY_STATUS _MMIO(0x66c04) 9212 #define HDCP_FUSE_IN_PROGRESS BIT(7) 9213 #define HDCP_FUSE_ERROR BIT(6) 9214 #define HDCP_FUSE_DONE BIT(5) 9215 #define HDCP_KEY_LOAD_STATUS BIT(1) 9216 #define HDCP_KEY_LOAD_DONE BIT(0) 9217 #define HDCP_AKSV_LO _MMIO(0x66c10) 9218 #define HDCP_AKSV_HI _MMIO(0x66c14) 9219 9220 /* HDCP Repeater Registers */ 9221 #define HDCP_REP_CTL _MMIO(0x66d00) 9222 #define HDCP_DDIB_REP_PRESENT BIT(30) 9223 #define HDCP_DDIA_REP_PRESENT BIT(29) 9224 #define HDCP_DDIC_REP_PRESENT BIT(28) 9225 #define HDCP_DDID_REP_PRESENT BIT(27) 9226 #define HDCP_DDIF_REP_PRESENT BIT(26) 9227 #define HDCP_DDIE_REP_PRESENT BIT(25) 9228 #define HDCP_DDIB_SHA1_M0 (1 << 20) 9229 #define HDCP_DDIA_SHA1_M0 (2 << 20) 9230 #define HDCP_DDIC_SHA1_M0 (3 << 20) 9231 #define HDCP_DDID_SHA1_M0 (4 << 20) 9232 #define HDCP_DDIF_SHA1_M0 (5 << 20) 9233 #define HDCP_DDIE_SHA1_M0 (6 << 20) /* Bspec says 5? */ 9234 #define HDCP_SHA1_BUSY BIT(16) 9235 #define HDCP_SHA1_READY BIT(17) 9236 #define HDCP_SHA1_COMPLETE BIT(18) 9237 #define HDCP_SHA1_V_MATCH BIT(19) 9238 #define HDCP_SHA1_TEXT_32 (1 << 1) 9239 #define HDCP_SHA1_COMPLETE_HASH (2 << 1) 9240 #define HDCP_SHA1_TEXT_24 (4 << 1) 9241 #define HDCP_SHA1_TEXT_16 (5 << 1) 9242 #define HDCP_SHA1_TEXT_8 (6 << 1) 9243 #define HDCP_SHA1_TEXT_0 (7 << 1) 9244 #define HDCP_SHA_V_PRIME_H0 _MMIO(0x66d04) 9245 #define HDCP_SHA_V_PRIME_H1 _MMIO(0x66d08) 9246 #define HDCP_SHA_V_PRIME_H2 _MMIO(0x66d0C) 9247 #define HDCP_SHA_V_PRIME_H3 _MMIO(0x66d10) 9248 #define HDCP_SHA_V_PRIME_H4 _MMIO(0x66d14) 9249 #define HDCP_SHA_V_PRIME(h) _MMIO((0x66d04 + (h) * 4)) 9250 #define HDCP_SHA_TEXT _MMIO(0x66d18) 9251 9252 /* HDCP Auth Registers */ 9253 #define _PORTA_HDCP_AUTHENC 0x66800 9254 #define _PORTB_HDCP_AUTHENC 0x66500 9255 #define _PORTC_HDCP_AUTHENC 0x66600 9256 #define _PORTD_HDCP_AUTHENC 0x66700 9257 #define _PORTE_HDCP_AUTHENC 0x66A00 9258 #define _PORTF_HDCP_AUTHENC 0x66900 9259 #define _PORT_HDCP_AUTHENC(port, x) _MMIO(_PICK(port, \ 9260 _PORTA_HDCP_AUTHENC, \ 9261 _PORTB_HDCP_AUTHENC, \ 9262 _PORTC_HDCP_AUTHENC, \ 9263 _PORTD_HDCP_AUTHENC, \ 9264 _PORTE_HDCP_AUTHENC, \ 9265 _PORTF_HDCP_AUTHENC) + (x)) 9266 #define PORT_HDCP_CONF(port) _PORT_HDCP_AUTHENC(port, 0x0) 9267 #define HDCP_CONF_CAPTURE_AN BIT(0) 9268 #define HDCP_CONF_AUTH_AND_ENC (BIT(1) | BIT(0)) 9269 #define PORT_HDCP_ANINIT(port) _PORT_HDCP_AUTHENC(port, 0x4) 9270 #define PORT_HDCP_ANLO(port) _PORT_HDCP_AUTHENC(port, 0x8) 9271 #define PORT_HDCP_ANHI(port) _PORT_HDCP_AUTHENC(port, 0xC) 9272 #define PORT_HDCP_BKSVLO(port) _PORT_HDCP_AUTHENC(port, 0x10) 9273 #define PORT_HDCP_BKSVHI(port) _PORT_HDCP_AUTHENC(port, 0x14) 9274 #define PORT_HDCP_RPRIME(port) _PORT_HDCP_AUTHENC(port, 0x18) 9275 #define PORT_HDCP_STATUS(port) _PORT_HDCP_AUTHENC(port, 0x1C) 9276 #define HDCP_STATUS_STREAM_A_ENC BIT(31) 9277 #define HDCP_STATUS_STREAM_B_ENC BIT(30) 9278 #define HDCP_STATUS_STREAM_C_ENC BIT(29) 9279 #define HDCP_STATUS_STREAM_D_ENC BIT(28) 9280 #define HDCP_STATUS_AUTH BIT(21) 9281 #define HDCP_STATUS_ENC BIT(20) 9282 #define HDCP_STATUS_RI_MATCH BIT(19) 9283 #define HDCP_STATUS_R0_READY BIT(18) 9284 #define HDCP_STATUS_AN_READY BIT(17) 9285 #define HDCP_STATUS_CIPHER BIT(16) 9286 #define HDCP_STATUS_FRAME_CNT(x) (((x) >> 8) & 0xff) 9287 9288 /* HDCP2.2 Registers */ 9289 #define _PORTA_HDCP2_BASE 0x66800 9290 #define _PORTB_HDCP2_BASE 0x66500 9291 #define _PORTC_HDCP2_BASE 0x66600 9292 #define _PORTD_HDCP2_BASE 0x66700 9293 #define _PORTE_HDCP2_BASE 0x66A00 9294 #define _PORTF_HDCP2_BASE 0x66900 9295 #define _PORT_HDCP2_BASE(port, x) _MMIO(_PICK((port), \ 9296 _PORTA_HDCP2_BASE, \ 9297 _PORTB_HDCP2_BASE, \ 9298 _PORTC_HDCP2_BASE, \ 9299 _PORTD_HDCP2_BASE, \ 9300 _PORTE_HDCP2_BASE, \ 9301 _PORTF_HDCP2_BASE) + (x)) 9302 9303 #define HDCP2_AUTH_DDI(port) _PORT_HDCP2_BASE(port, 0x98) 9304 #define AUTH_LINK_AUTHENTICATED BIT(31) 9305 #define AUTH_LINK_TYPE BIT(30) 9306 #define AUTH_FORCE_CLR_INPUTCTR BIT(19) 9307 #define AUTH_CLR_KEYS BIT(18) 9308 9309 #define HDCP2_CTL_DDI(port) _PORT_HDCP2_BASE(port, 0xB0) 9310 #define CTL_LINK_ENCRYPTION_REQ BIT(31) 9311 9312 #define HDCP2_STATUS_DDI(port) _PORT_HDCP2_BASE(port, 0xB4) 9313 #define STREAM_ENCRYPTION_STATUS_A BIT(31) 9314 #define STREAM_ENCRYPTION_STATUS_B BIT(30) 9315 #define STREAM_ENCRYPTION_STATUS_C BIT(29) 9316 #define LINK_TYPE_STATUS BIT(22) 9317 #define LINK_AUTH_STATUS BIT(21) 9318 #define LINK_ENCRYPTION_STATUS BIT(20) 9319 9320 /* Per-pipe DDI Function Control */ 9321 #define _TRANS_DDI_FUNC_CTL_A 0x60400 9322 #define _TRANS_DDI_FUNC_CTL_B 0x61400 9323 #define _TRANS_DDI_FUNC_CTL_C 0x62400 9324 #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400 9325 #define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400 9326 #define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00 9327 #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A) 9328 9329 #define TRANS_DDI_FUNC_ENABLE (1 << 31) 9330 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ 9331 #define TRANS_DDI_PORT_MASK (7 << 28) 9332 #define TRANS_DDI_PORT_SHIFT 28 9333 #define TRANS_DDI_SELECT_PORT(x) ((x) << 28) 9334 #define TRANS_DDI_PORT_NONE (0 << 28) 9335 #define TRANS_DDI_MODE_SELECT_MASK (7 << 24) 9336 #define TRANS_DDI_MODE_SELECT_HDMI (0 << 24) 9337 #define TRANS_DDI_MODE_SELECT_DVI (1 << 24) 9338 #define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24) 9339 #define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24) 9340 #define TRANS_DDI_MODE_SELECT_FDI (4 << 24) 9341 #define TRANS_DDI_BPC_MASK (7 << 20) 9342 #define TRANS_DDI_BPC_8 (0 << 20) 9343 #define TRANS_DDI_BPC_10 (1 << 20) 9344 #define TRANS_DDI_BPC_6 (2 << 20) 9345 #define TRANS_DDI_BPC_12 (3 << 20) 9346 #define TRANS_DDI_PVSYNC (1 << 17) 9347 #define TRANS_DDI_PHSYNC (1 << 16) 9348 #define TRANS_DDI_EDP_INPUT_MASK (7 << 12) 9349 #define TRANS_DDI_EDP_INPUT_A_ON (0 << 12) 9350 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12) 9351 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12) 9352 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12) 9353 #define TRANS_DDI_HDCP_SIGNALLING (1 << 9) 9354 #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8) 9355 #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7) 9356 #define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6) 9357 #define TRANS_DDI_BFI_ENABLE (1 << 4) 9358 #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4) 9359 #define TRANS_DDI_HDMI_SCRAMBLING (1 << 0) 9360 #define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \ 9361 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \ 9362 | TRANS_DDI_HDMI_SCRAMBLING) 9363 9364 #define _TRANS_DDI_FUNC_CTL2_A 0x60404 9365 #define _TRANS_DDI_FUNC_CTL2_B 0x61404 9366 #define _TRANS_DDI_FUNC_CTL2_C 0x62404 9367 #define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404 9368 #define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404 9369 #define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04 9370 #define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(tran, \ 9371 _TRANS_DDI_FUNC_CTL2_A) 9372 #define PORT_SYNC_MODE_ENABLE (1 << 4) 9373 #define PORT_SYNC_MODE_MASTER_SELECT(x) ((x) << 0) 9374 #define PORT_SYNC_MODE_MASTER_SELECT_MASK (0x7 << 0) 9375 #define PORT_SYNC_MODE_MASTER_SELECT_SHIFT 0 9376 9377 /* DisplayPort Transport Control */ 9378 #define _DP_TP_CTL_A 0x64040 9379 #define _DP_TP_CTL_B 0x64140 9380 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) 9381 #define DP_TP_CTL_ENABLE (1 << 31) 9382 #define DP_TP_CTL_FEC_ENABLE (1 << 30) 9383 #define DP_TP_CTL_MODE_SST (0 << 27) 9384 #define DP_TP_CTL_MODE_MST (1 << 27) 9385 #define DP_TP_CTL_FORCE_ACT (1 << 25) 9386 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18) 9387 #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15) 9388 #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8) 9389 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8) 9390 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1 << 8) 9391 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4 << 8) 9392 #define DP_TP_CTL_LINK_TRAIN_PAT4 (5 << 8) 9393 #define DP_TP_CTL_LINK_TRAIN_IDLE (2 << 8) 9394 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3 << 8) 9395 #define DP_TP_CTL_SCRAMBLE_DISABLE (1 << 7) 9396 9397 /* DisplayPort Transport Status */ 9398 #define _DP_TP_STATUS_A 0x64044 9399 #define _DP_TP_STATUS_B 0x64144 9400 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B) 9401 #define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28) 9402 #define DP_TP_STATUS_IDLE_DONE (1 << 25) 9403 #define DP_TP_STATUS_ACT_SENT (1 << 24) 9404 #define DP_TP_STATUS_MODE_STATUS_MST (1 << 23) 9405 #define DP_TP_STATUS_AUTOTRAIN_DONE (1 << 12) 9406 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8) 9407 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4) 9408 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0) 9409 9410 /* DDI Buffer Control */ 9411 #define _DDI_BUF_CTL_A 0x64000 9412 #define _DDI_BUF_CTL_B 0x64100 9413 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B) 9414 #define DDI_BUF_CTL_ENABLE (1 << 31) 9415 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24) 9416 #define DDI_BUF_EMP_MASK (0xf << 24) 9417 #define DDI_BUF_PORT_REVERSAL (1 << 16) 9418 #define DDI_BUF_IS_IDLE (1 << 7) 9419 #define DDI_A_4_LANES (1 << 4) 9420 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) 9421 #define DDI_PORT_WIDTH_MASK (7 << 1) 9422 #define DDI_PORT_WIDTH_SHIFT 1 9423 #define DDI_INIT_DISPLAY_DETECTED (1 << 0) 9424 9425 /* DDI Buffer Translations */ 9426 #define _DDI_BUF_TRANS_A 0x64E00 9427 #define _DDI_BUF_TRANS_B 0x64E60 9428 #define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8) 9429 #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31) 9430 #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4) 9431 9432 /* Sideband Interface (SBI) is programmed indirectly, via 9433 * SBI_ADDR, which contains the register offset; and SBI_DATA, 9434 * which contains the payload */ 9435 #define SBI_ADDR _MMIO(0xC6000) 9436 #define SBI_DATA _MMIO(0xC6004) 9437 #define SBI_CTL_STAT _MMIO(0xC6008) 9438 #define SBI_CTL_DEST_ICLK (0x0 << 16) 9439 #define SBI_CTL_DEST_MPHY (0x1 << 16) 9440 #define SBI_CTL_OP_IORD (0x2 << 8) 9441 #define SBI_CTL_OP_IOWR (0x3 << 8) 9442 #define SBI_CTL_OP_CRRD (0x6 << 8) 9443 #define SBI_CTL_OP_CRWR (0x7 << 8) 9444 #define SBI_RESPONSE_FAIL (0x1 << 1) 9445 #define SBI_RESPONSE_SUCCESS (0x0 << 1) 9446 #define SBI_BUSY (0x1 << 0) 9447 #define SBI_READY (0x0 << 0) 9448 9449 /* SBI offsets */ 9450 #define SBI_SSCDIVINTPHASE 0x0200 9451 #define SBI_SSCDIVINTPHASE6 0x0600 9452 #define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1 9453 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1) 9454 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1) 9455 #define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8 9456 #define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8) 9457 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8) 9458 #define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15) 9459 #define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0) 9460 #define SBI_SSCDITHPHASE 0x0204 9461 #define SBI_SSCCTL 0x020c 9462 #define SBI_SSCCTL6 0x060C 9463 #define SBI_SSCCTL_PATHALT (1 << 3) 9464 #define SBI_SSCCTL_DISABLE (1 << 0) 9465 #define SBI_SSCAUXDIV6 0x0610 9466 #define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4 9467 #define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4) 9468 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4) 9469 #define SBI_DBUFF0 0x2a00 9470 #define SBI_GEN0 0x1f00 9471 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0) 9472 9473 /* LPT PIXCLK_GATE */ 9474 #define PIXCLK_GATE _MMIO(0xC6020) 9475 #define PIXCLK_GATE_UNGATE (1 << 0) 9476 #define PIXCLK_GATE_GATE (0 << 0) 9477 9478 /* SPLL */ 9479 #define SPLL_CTL _MMIO(0x46020) 9480 #define SPLL_PLL_ENABLE (1 << 31) 9481 #define SPLL_REF_BCLK (0 << 28) 9482 #define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */ 9483 #define SPLL_REF_NON_SSC_HSW (2 << 28) 9484 #define SPLL_REF_PCH_SSC_BDW (2 << 28) 9485 #define SPLL_REF_LCPLL (3 << 28) 9486 #define SPLL_REF_MASK (3 << 28) 9487 #define SPLL_FREQ_810MHz (0 << 26) 9488 #define SPLL_FREQ_1350MHz (1 << 26) 9489 #define SPLL_FREQ_2700MHz (2 << 26) 9490 #define SPLL_FREQ_MASK (3 << 26) 9491 9492 /* WRPLL */ 9493 #define _WRPLL_CTL1 0x46040 9494 #define _WRPLL_CTL2 0x46060 9495 #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2) 9496 #define WRPLL_PLL_ENABLE (1 << 31) 9497 #define WRPLL_REF_BCLK (0 << 28) 9498 #define WRPLL_REF_PCH_SSC (1 << 28) 9499 #define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */ 9500 #define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */ 9501 #define WRPLL_REF_LCPLL (3 << 28) 9502 #define WRPLL_REF_MASK (3 << 28) 9503 /* WRPLL divider programming */ 9504 #define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0) 9505 #define WRPLL_DIVIDER_REF_MASK (0xff) 9506 #define WRPLL_DIVIDER_POST(x) ((x) << 8) 9507 #define WRPLL_DIVIDER_POST_MASK (0x3f << 8) 9508 #define WRPLL_DIVIDER_POST_SHIFT 8 9509 #define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16) 9510 #define WRPLL_DIVIDER_FB_SHIFT 16 9511 #define WRPLL_DIVIDER_FB_MASK (0xff << 16) 9512 9513 /* Port clock selection */ 9514 #define _PORT_CLK_SEL_A 0x46100 9515 #define _PORT_CLK_SEL_B 0x46104 9516 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B) 9517 #define PORT_CLK_SEL_LCPLL_2700 (0 << 29) 9518 #define PORT_CLK_SEL_LCPLL_1350 (1 << 29) 9519 #define PORT_CLK_SEL_LCPLL_810 (2 << 29) 9520 #define PORT_CLK_SEL_SPLL (3 << 29) 9521 #define PORT_CLK_SEL_WRPLL(pll) (((pll) + 4) << 29) 9522 #define PORT_CLK_SEL_WRPLL1 (4 << 29) 9523 #define PORT_CLK_SEL_WRPLL2 (5 << 29) 9524 #define PORT_CLK_SEL_NONE (7 << 29) 9525 #define PORT_CLK_SEL_MASK (7 << 29) 9526 9527 /* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */ 9528 #define DDI_CLK_SEL(port) PORT_CLK_SEL(port) 9529 #define DDI_CLK_SEL_NONE (0x0 << 28) 9530 #define DDI_CLK_SEL_MG (0x8 << 28) 9531 #define DDI_CLK_SEL_TBT_162 (0xC << 28) 9532 #define DDI_CLK_SEL_TBT_270 (0xD << 28) 9533 #define DDI_CLK_SEL_TBT_540 (0xE << 28) 9534 #define DDI_CLK_SEL_TBT_810 (0xF << 28) 9535 #define DDI_CLK_SEL_MASK (0xF << 28) 9536 9537 /* Transcoder clock selection */ 9538 #define _TRANS_CLK_SEL_A 0x46140 9539 #define _TRANS_CLK_SEL_B 0x46144 9540 #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B) 9541 /* For each transcoder, we need to select the corresponding port clock */ 9542 #define TRANS_CLK_SEL_DISABLED (0x0 << 29) 9543 #define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29) 9544 9545 #define CDCLK_FREQ _MMIO(0x46200) 9546 9547 #define _TRANSA_MSA_MISC 0x60410 9548 #define _TRANSB_MSA_MISC 0x61410 9549 #define _TRANSC_MSA_MISC 0x62410 9550 #define _TRANS_EDP_MSA_MISC 0x6f410 9551 #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC) 9552 9553 #define TRANS_MSA_SYNC_CLK (1 << 0) 9554 #define TRANS_MSA_SAMPLING_444 (2 << 1) 9555 #define TRANS_MSA_CLRSP_YCBCR (2 << 3) 9556 #define TRANS_MSA_6_BPC (0 << 5) 9557 #define TRANS_MSA_8_BPC (1 << 5) 9558 #define TRANS_MSA_10_BPC (2 << 5) 9559 #define TRANS_MSA_12_BPC (3 << 5) 9560 #define TRANS_MSA_16_BPC (4 << 5) 9561 #define TRANS_MSA_CEA_RANGE (1 << 3) 9562 #define TRANS_MSA_USE_VSC_SDP (1 << 14) 9563 9564 /* LCPLL Control */ 9565 #define LCPLL_CTL _MMIO(0x130040) 9566 #define LCPLL_PLL_DISABLE (1 << 31) 9567 #define LCPLL_PLL_LOCK (1 << 30) 9568 #define LCPLL_REF_NON_SSC (0 << 28) 9569 #define LCPLL_REF_BCLK (2 << 28) 9570 #define LCPLL_REF_PCH_SSC (3 << 28) 9571 #define LCPLL_REF_MASK (3 << 28) 9572 #define LCPLL_CLK_FREQ_MASK (3 << 26) 9573 #define LCPLL_CLK_FREQ_450 (0 << 26) 9574 #define LCPLL_CLK_FREQ_54O_BDW (1 << 26) 9575 #define LCPLL_CLK_FREQ_337_5_BDW (2 << 26) 9576 #define LCPLL_CLK_FREQ_675_BDW (3 << 26) 9577 #define LCPLL_CD_CLOCK_DISABLE (1 << 25) 9578 #define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24) 9579 #define LCPLL_CD2X_CLOCK_DISABLE (1 << 23) 9580 #define LCPLL_POWER_DOWN_ALLOW (1 << 22) 9581 #define LCPLL_CD_SOURCE_FCLK (1 << 21) 9582 #define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19) 9583 9584 /* 9585 * SKL Clocks 9586 */ 9587 9588 /* CDCLK_CTL */ 9589 #define CDCLK_CTL _MMIO(0x46000) 9590 #define CDCLK_FREQ_SEL_MASK (3 << 26) 9591 #define CDCLK_FREQ_450_432 (0 << 26) 9592 #define CDCLK_FREQ_540 (1 << 26) 9593 #define CDCLK_FREQ_337_308 (2 << 26) 9594 #define CDCLK_FREQ_675_617 (3 << 26) 9595 #define BXT_CDCLK_CD2X_DIV_SEL_MASK (3 << 22) 9596 #define BXT_CDCLK_CD2X_DIV_SEL_1 (0 << 22) 9597 #define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1 << 22) 9598 #define BXT_CDCLK_CD2X_DIV_SEL_2 (2 << 22) 9599 #define BXT_CDCLK_CD2X_DIV_SEL_4 (3 << 22) 9600 #define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20) 9601 #define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19) 9602 #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3) 9603 #define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19) 9604 #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16) 9605 #define CDCLK_FREQ_DECIMAL_MASK (0x7ff) 9606 9607 /* LCPLL_CTL */ 9608 #define LCPLL1_CTL _MMIO(0x46010) 9609 #define LCPLL2_CTL _MMIO(0x46014) 9610 #define LCPLL_PLL_ENABLE (1 << 31) 9611 9612 /* DPLL control1 */ 9613 #define DPLL_CTRL1 _MMIO(0x6C058) 9614 #define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5)) 9615 #define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4)) 9616 #define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1)) 9617 #define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1) 9618 #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1)) 9619 #define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6)) 9620 #define DPLL_CTRL1_LINK_RATE_2700 0 9621 #define DPLL_CTRL1_LINK_RATE_1350 1 9622 #define DPLL_CTRL1_LINK_RATE_810 2 9623 #define DPLL_CTRL1_LINK_RATE_1620 3 9624 #define DPLL_CTRL1_LINK_RATE_1080 4 9625 #define DPLL_CTRL1_LINK_RATE_2160 5 9626 9627 /* DPLL control2 */ 9628 #define DPLL_CTRL2 _MMIO(0x6C05C) 9629 #define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15)) 9630 #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1)) 9631 #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1) 9632 #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1)) 9633 #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3)) 9634 9635 /* DPLL Status */ 9636 #define DPLL_STATUS _MMIO(0x6C060) 9637 #define DPLL_LOCK(id) (1 << ((id) * 8)) 9638 9639 /* DPLL cfg */ 9640 #define _DPLL1_CFGCR1 0x6C040 9641 #define _DPLL2_CFGCR1 0x6C048 9642 #define _DPLL3_CFGCR1 0x6C050 9643 #define DPLL_CFGCR1_FREQ_ENABLE (1 << 31) 9644 #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9) 9645 #define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9) 9646 #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff) 9647 9648 #define _DPLL1_CFGCR2 0x6C044 9649 #define _DPLL2_CFGCR2 0x6C04C 9650 #define _DPLL3_CFGCR2 0x6C054 9651 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8) 9652 #define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8) 9653 #define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7) 9654 #define DPLL_CFGCR2_KDIV_MASK (3 << 5) 9655 #define DPLL_CFGCR2_KDIV(x) ((x) << 5) 9656 #define DPLL_CFGCR2_KDIV_5 (0 << 5) 9657 #define DPLL_CFGCR2_KDIV_2 (1 << 5) 9658 #define DPLL_CFGCR2_KDIV_3 (2 << 5) 9659 #define DPLL_CFGCR2_KDIV_1 (3 << 5) 9660 #define DPLL_CFGCR2_PDIV_MASK (7 << 2) 9661 #define DPLL_CFGCR2_PDIV(x) ((x) << 2) 9662 #define DPLL_CFGCR2_PDIV_1 (0 << 2) 9663 #define DPLL_CFGCR2_PDIV_2 (1 << 2) 9664 #define DPLL_CFGCR2_PDIV_3 (2 << 2) 9665 #define DPLL_CFGCR2_PDIV_7 (4 << 2) 9666 #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3) 9667 9668 #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1) 9669 #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2) 9670 9671 /* 9672 * CNL Clocks 9673 */ 9674 #define DPCLKA_CFGCR0 _MMIO(0x6C200) 9675 #define DPCLKA_CFGCR0_ICL _MMIO(0x164280) 9676 #define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \ 9677 (port) + 10)) 9678 #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) + 10)) 9679 #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \ 9680 21 : (tc_port) + 12)) 9681 #define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \ 9682 (port) * 2) 9683 #define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)) 9684 #define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)) 9685 9686 /* CNL PLL */ 9687 #define DPLL0_ENABLE 0x46010 9688 #define DPLL1_ENABLE 0x46014 9689 #define PLL_ENABLE (1 << 31) 9690 #define PLL_LOCK (1 << 30) 9691 #define PLL_POWER_ENABLE (1 << 27) 9692 #define PLL_POWER_STATE (1 << 26) 9693 #define CNL_DPLL_ENABLE(pll) _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE) 9694 9695 #define TBT_PLL_ENABLE _MMIO(0x46020) 9696 9697 #define _MG_PLL1_ENABLE 0x46030 9698 #define _MG_PLL2_ENABLE 0x46034 9699 #define _MG_PLL3_ENABLE 0x46038 9700 #define _MG_PLL4_ENABLE 0x4603C 9701 /* Bits are the same as DPLL0_ENABLE */ 9702 #define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \ 9703 _MG_PLL2_ENABLE) 9704 9705 #define _MG_REFCLKIN_CTL_PORT1 0x16892C 9706 #define _MG_REFCLKIN_CTL_PORT2 0x16992C 9707 #define _MG_REFCLKIN_CTL_PORT3 0x16A92C 9708 #define _MG_REFCLKIN_CTL_PORT4 0x16B92C 9709 #define MG_REFCLKIN_CTL_OD_2_MUX(x) ((x) << 8) 9710 #define MG_REFCLKIN_CTL_OD_2_MUX_MASK (0x7 << 8) 9711 #define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \ 9712 _MG_REFCLKIN_CTL_PORT1, \ 9713 _MG_REFCLKIN_CTL_PORT2) 9714 9715 #define _MG_CLKTOP2_CORECLKCTL1_PORT1 0x1688D8 9716 #define _MG_CLKTOP2_CORECLKCTL1_PORT2 0x1698D8 9717 #define _MG_CLKTOP2_CORECLKCTL1_PORT3 0x16A8D8 9718 #define _MG_CLKTOP2_CORECLKCTL1_PORT4 0x16B8D8 9719 #define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x) ((x) << 16) 9720 #define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK (0xff << 16) 9721 #define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8) 9722 #define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK (0xff << 8) 9723 #define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \ 9724 _MG_CLKTOP2_CORECLKCTL1_PORT1, \ 9725 _MG_CLKTOP2_CORECLKCTL1_PORT2) 9726 9727 #define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4 9728 #define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4 9729 #define _MG_CLKTOP2_HSCLKCTL_PORT3 0x16A8D4 9730 #define _MG_CLKTOP2_HSCLKCTL_PORT4 0x16B8D4 9731 #define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x) ((x) << 16) 9732 #define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK (0x1 << 16) 9733 #define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14) 9734 #define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK (0x3 << 14) 9735 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK (0x3 << 12) 9736 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2 (0 << 12) 9737 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3 (1 << 12) 9738 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5 (2 << 12) 9739 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7 (3 << 12) 9740 #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8) 9741 #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT 8 9742 #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << 8) 9743 #define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \ 9744 _MG_CLKTOP2_HSCLKCTL_PORT1, \ 9745 _MG_CLKTOP2_HSCLKCTL_PORT2) 9746 9747 #define _MG_PLL_DIV0_PORT1 0x168A00 9748 #define _MG_PLL_DIV0_PORT2 0x169A00 9749 #define _MG_PLL_DIV0_PORT3 0x16AA00 9750 #define _MG_PLL_DIV0_PORT4 0x16BA00 9751 #define MG_PLL_DIV0_FRACNEN_H (1 << 30) 9752 #define MG_PLL_DIV0_FBDIV_FRAC_MASK (0x3fffff << 8) 9753 #define MG_PLL_DIV0_FBDIV_FRAC_SHIFT 8 9754 #define MG_PLL_DIV0_FBDIV_FRAC(x) ((x) << 8) 9755 #define MG_PLL_DIV0_FBDIV_INT_MASK (0xff << 0) 9756 #define MG_PLL_DIV0_FBDIV_INT(x) ((x) << 0) 9757 #define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \ 9758 _MG_PLL_DIV0_PORT2) 9759 9760 #define _MG_PLL_DIV1_PORT1 0x168A04 9761 #define _MG_PLL_DIV1_PORT2 0x169A04 9762 #define _MG_PLL_DIV1_PORT3 0x16AA04 9763 #define _MG_PLL_DIV1_PORT4 0x16BA04 9764 #define MG_PLL_DIV1_IREF_NDIVRATIO(x) ((x) << 16) 9765 #define MG_PLL_DIV1_DITHER_DIV_1 (0 << 12) 9766 #define MG_PLL_DIV1_DITHER_DIV_2 (1 << 12) 9767 #define MG_PLL_DIV1_DITHER_DIV_4 (2 << 12) 9768 #define MG_PLL_DIV1_DITHER_DIV_8 (3 << 12) 9769 #define MG_PLL_DIV1_NDIVRATIO(x) ((x) << 4) 9770 #define MG_PLL_DIV1_FBPREDIV_MASK (0xf << 0) 9771 #define MG_PLL_DIV1_FBPREDIV(x) ((x) << 0) 9772 #define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \ 9773 _MG_PLL_DIV1_PORT2) 9774 9775 #define _MG_PLL_LF_PORT1 0x168A08 9776 #define _MG_PLL_LF_PORT2 0x169A08 9777 #define _MG_PLL_LF_PORT3 0x16AA08 9778 #define _MG_PLL_LF_PORT4 0x16BA08 9779 #define MG_PLL_LF_TDCTARGETCNT(x) ((x) << 24) 9780 #define MG_PLL_LF_AFCCNTSEL_256 (0 << 20) 9781 #define MG_PLL_LF_AFCCNTSEL_512 (1 << 20) 9782 #define MG_PLL_LF_GAINCTRL(x) ((x) << 16) 9783 #define MG_PLL_LF_INT_COEFF(x) ((x) << 8) 9784 #define MG_PLL_LF_PROP_COEFF(x) ((x) << 0) 9785 #define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \ 9786 _MG_PLL_LF_PORT2) 9787 9788 #define _MG_PLL_FRAC_LOCK_PORT1 0x168A0C 9789 #define _MG_PLL_FRAC_LOCK_PORT2 0x169A0C 9790 #define _MG_PLL_FRAC_LOCK_PORT3 0x16AA0C 9791 #define _MG_PLL_FRAC_LOCK_PORT4 0x16BA0C 9792 #define MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 (1 << 18) 9793 #define MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 (1 << 16) 9794 #define MG_PLL_FRAC_LOCK_LOCKTHRESH(x) ((x) << 11) 9795 #define MG_PLL_FRAC_LOCK_DCODITHEREN (1 << 10) 9796 #define MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN (1 << 8) 9797 #define MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x) ((x) << 0) 9798 #define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \ 9799 _MG_PLL_FRAC_LOCK_PORT1, \ 9800 _MG_PLL_FRAC_LOCK_PORT2) 9801 9802 #define _MG_PLL_SSC_PORT1 0x168A10 9803 #define _MG_PLL_SSC_PORT2 0x169A10 9804 #define _MG_PLL_SSC_PORT3 0x16AA10 9805 #define _MG_PLL_SSC_PORT4 0x16BA10 9806 #define MG_PLL_SSC_EN (1 << 28) 9807 #define MG_PLL_SSC_TYPE(x) ((x) << 26) 9808 #define MG_PLL_SSC_STEPLENGTH(x) ((x) << 16) 9809 #define MG_PLL_SSC_STEPNUM(x) ((x) << 10) 9810 #define MG_PLL_SSC_FLLEN (1 << 9) 9811 #define MG_PLL_SSC_STEPSIZE(x) ((x) << 0) 9812 #define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \ 9813 _MG_PLL_SSC_PORT2) 9814 9815 #define _MG_PLL_BIAS_PORT1 0x168A14 9816 #define _MG_PLL_BIAS_PORT2 0x169A14 9817 #define _MG_PLL_BIAS_PORT3 0x16AA14 9818 #define _MG_PLL_BIAS_PORT4 0x16BA14 9819 #define MG_PLL_BIAS_BIAS_GB_SEL(x) ((x) << 30) 9820 #define MG_PLL_BIAS_BIAS_GB_SEL_MASK (0x3 << 30) 9821 #define MG_PLL_BIAS_INIT_DCOAMP(x) ((x) << 24) 9822 #define MG_PLL_BIAS_INIT_DCOAMP_MASK (0x3f << 24) 9823 #define MG_PLL_BIAS_BIAS_BONUS(x) ((x) << 16) 9824 #define MG_PLL_BIAS_BIAS_BONUS_MASK (0xff << 16) 9825 #define MG_PLL_BIAS_BIASCAL_EN (1 << 15) 9826 #define MG_PLL_BIAS_CTRIM(x) ((x) << 8) 9827 #define MG_PLL_BIAS_CTRIM_MASK (0x1f << 8) 9828 #define MG_PLL_BIAS_VREF_RDAC(x) ((x) << 5) 9829 #define MG_PLL_BIAS_VREF_RDAC_MASK (0x7 << 5) 9830 #define MG_PLL_BIAS_IREFTRIM(x) ((x) << 0) 9831 #define MG_PLL_BIAS_IREFTRIM_MASK (0x1f << 0) 9832 #define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \ 9833 _MG_PLL_BIAS_PORT2) 9834 9835 #define _MG_PLL_TDC_COLDST_BIAS_PORT1 0x168A18 9836 #define _MG_PLL_TDC_COLDST_BIAS_PORT2 0x169A18 9837 #define _MG_PLL_TDC_COLDST_BIAS_PORT3 0x16AA18 9838 #define _MG_PLL_TDC_COLDST_BIAS_PORT4 0x16BA18 9839 #define MG_PLL_TDC_COLDST_IREFINT_EN (1 << 27) 9840 #define MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x) ((x) << 17) 9841 #define MG_PLL_TDC_COLDST_COLDSTART (1 << 16) 9842 #define MG_PLL_TDC_TDCOVCCORR_EN (1 << 2) 9843 #define MG_PLL_TDC_TDCSEL(x) ((x) << 0) 9844 #define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \ 9845 _MG_PLL_TDC_COLDST_BIAS_PORT1, \ 9846 _MG_PLL_TDC_COLDST_BIAS_PORT2) 9847 9848 #define _CNL_DPLL0_CFGCR0 0x6C000 9849 #define _CNL_DPLL1_CFGCR0 0x6C080 9850 #define DPLL_CFGCR0_HDMI_MODE (1 << 30) 9851 #define DPLL_CFGCR0_SSC_ENABLE (1 << 29) 9852 #define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25) 9853 #define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25) 9854 #define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25) 9855 #define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25) 9856 #define DPLL_CFGCR0_LINK_RATE_810 (2 << 25) 9857 #define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25) 9858 #define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25) 9859 #define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25) 9860 #define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25) 9861 #define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25) 9862 #define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10) 9863 #define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10) 9864 #define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10) 9865 #define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff) 9866 #define CNL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0) 9867 9868 #define _CNL_DPLL0_CFGCR1 0x6C004 9869 #define _CNL_DPLL1_CFGCR1 0x6C084 9870 #define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10) 9871 #define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10) 9872 #define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10) 9873 #define DPLL_CFGCR1_QDIV_MODE_SHIFT (9) 9874 #define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9) 9875 #define DPLL_CFGCR1_KDIV_MASK (7 << 6) 9876 #define DPLL_CFGCR1_KDIV_SHIFT (6) 9877 #define DPLL_CFGCR1_KDIV(x) ((x) << 6) 9878 #define DPLL_CFGCR1_KDIV_1 (1 << 6) 9879 #define DPLL_CFGCR1_KDIV_2 (2 << 6) 9880 #define DPLL_CFGCR1_KDIV_3 (4 << 6) 9881 #define DPLL_CFGCR1_PDIV_MASK (0xf << 2) 9882 #define DPLL_CFGCR1_PDIV_SHIFT (2) 9883 #define DPLL_CFGCR1_PDIV(x) ((x) << 2) 9884 #define DPLL_CFGCR1_PDIV_2 (1 << 2) 9885 #define DPLL_CFGCR1_PDIV_3 (2 << 2) 9886 #define DPLL_CFGCR1_PDIV_5 (4 << 2) 9887 #define DPLL_CFGCR1_PDIV_7 (8 << 2) 9888 #define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0) 9889 #define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0) 9890 #define CNL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1) 9891 9892 #define _ICL_DPLL0_CFGCR0 0x164000 9893 #define _ICL_DPLL1_CFGCR0 0x164080 9894 #define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \ 9895 _ICL_DPLL1_CFGCR0) 9896 9897 #define _ICL_DPLL0_CFGCR1 0x164004 9898 #define _ICL_DPLL1_CFGCR1 0x164084 9899 #define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \ 9900 _ICL_DPLL1_CFGCR1) 9901 9902 /* BXT display engine PLL */ 9903 #define BXT_DE_PLL_CTL _MMIO(0x6d000) 9904 #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */ 9905 #define BXT_DE_PLL_RATIO_MASK 0xff 9906 9907 #define BXT_DE_PLL_ENABLE _MMIO(0x46070) 9908 #define BXT_DE_PLL_PLL_ENABLE (1 << 31) 9909 #define BXT_DE_PLL_LOCK (1 << 30) 9910 #define CNL_CDCLK_PLL_RATIO(x) (x) 9911 #define CNL_CDCLK_PLL_RATIO_MASK 0xff 9912 9913 /* GEN9 DC */ 9914 #define DC_STATE_EN _MMIO(0x45504) 9915 #define DC_STATE_DISABLE 0 9916 #define DC_STATE_EN_UPTO_DC5 (1 << 0) 9917 #define DC_STATE_EN_DC9 (1 << 3) 9918 #define DC_STATE_EN_UPTO_DC6 (2 << 0) 9919 #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3 9920 9921 #define DC_STATE_DEBUG _MMIO(0x45520) 9922 #define DC_STATE_DEBUG_MASK_CORES (1 << 0) 9923 #define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1) 9924 9925 #define BXT_P_CR_MC_BIOS_REQ_0_0_0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7114) 9926 #define BXT_REQ_DATA_MASK 0x3F 9927 #define BXT_DRAM_CHANNEL_ACTIVE_SHIFT 12 9928 #define BXT_DRAM_CHANNEL_ACTIVE_MASK (0xF << 12) 9929 #define BXT_MEMORY_FREQ_MULTIPLIER_HZ 133333333 9930 9931 #define BXT_D_CR_DRP0_DUNIT8 0x1000 9932 #define BXT_D_CR_DRP0_DUNIT9 0x1200 9933 #define BXT_D_CR_DRP0_DUNIT_START 8 9934 #define BXT_D_CR_DRP0_DUNIT_END 11 9935 #define BXT_D_CR_DRP0_DUNIT(x) _MMIO(MCHBAR_MIRROR_BASE_SNB + \ 9936 _PICK_EVEN((x) - 8, BXT_D_CR_DRP0_DUNIT8,\ 9937 BXT_D_CR_DRP0_DUNIT9)) 9938 #define BXT_DRAM_RANK_MASK 0x3 9939 #define BXT_DRAM_RANK_SINGLE 0x1 9940 #define BXT_DRAM_RANK_DUAL 0x3 9941 #define BXT_DRAM_WIDTH_MASK (0x3 << 4) 9942 #define BXT_DRAM_WIDTH_SHIFT 4 9943 #define BXT_DRAM_WIDTH_X8 (0x0 << 4) 9944 #define BXT_DRAM_WIDTH_X16 (0x1 << 4) 9945 #define BXT_DRAM_WIDTH_X32 (0x2 << 4) 9946 #define BXT_DRAM_WIDTH_X64 (0x3 << 4) 9947 #define BXT_DRAM_SIZE_MASK (0x7 << 6) 9948 #define BXT_DRAM_SIZE_SHIFT 6 9949 #define BXT_DRAM_SIZE_4GBIT (0x0 << 6) 9950 #define BXT_DRAM_SIZE_6GBIT (0x1 << 6) 9951 #define BXT_DRAM_SIZE_8GBIT (0x2 << 6) 9952 #define BXT_DRAM_SIZE_12GBIT (0x3 << 6) 9953 #define BXT_DRAM_SIZE_16GBIT (0x4 << 6) 9954 #define BXT_DRAM_TYPE_MASK (0x7 << 22) 9955 #define BXT_DRAM_TYPE_SHIFT 22 9956 #define BXT_DRAM_TYPE_DDR3 (0x0 << 22) 9957 #define BXT_DRAM_TYPE_LPDDR3 (0x1 << 22) 9958 #define BXT_DRAM_TYPE_LPDDR4 (0x2 << 22) 9959 #define BXT_DRAM_TYPE_DDR4 (0x4 << 22) 9960 9961 #define SKL_MEMORY_FREQ_MULTIPLIER_HZ 266666666 9962 #define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04) 9963 #define SKL_REQ_DATA_MASK (0xF << 0) 9964 9965 #define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000) 9966 #define SKL_DRAM_DDR_TYPE_MASK (0x3 << 0) 9967 #define SKL_DRAM_DDR_TYPE_DDR4 (0 << 0) 9968 #define SKL_DRAM_DDR_TYPE_DDR3 (1 << 0) 9969 #define SKL_DRAM_DDR_TYPE_LPDDR3 (2 << 0) 9970 #define SKL_DRAM_DDR_TYPE_LPDDR4 (3 << 0) 9971 9972 #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C) 9973 #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010) 9974 #define SKL_DRAM_S_SHIFT 16 9975 #define SKL_DRAM_SIZE_MASK 0x3F 9976 #define SKL_DRAM_WIDTH_MASK (0x3 << 8) 9977 #define SKL_DRAM_WIDTH_SHIFT 8 9978 #define SKL_DRAM_WIDTH_X8 (0x0 << 8) 9979 #define SKL_DRAM_WIDTH_X16 (0x1 << 8) 9980 #define SKL_DRAM_WIDTH_X32 (0x2 << 8) 9981 #define SKL_DRAM_RANK_MASK (0x1 << 10) 9982 #define SKL_DRAM_RANK_SHIFT 10 9983 #define SKL_DRAM_RANK_1 (0x0 << 10) 9984 #define SKL_DRAM_RANK_2 (0x1 << 10) 9985 #define SKL_DRAM_RANK_MASK (0x1 << 10) 9986 #define CNL_DRAM_SIZE_MASK 0x7F 9987 #define CNL_DRAM_WIDTH_MASK (0x3 << 7) 9988 #define CNL_DRAM_WIDTH_SHIFT 7 9989 #define CNL_DRAM_WIDTH_X8 (0x0 << 7) 9990 #define CNL_DRAM_WIDTH_X16 (0x1 << 7) 9991 #define CNL_DRAM_WIDTH_X32 (0x2 << 7) 9992 #define CNL_DRAM_RANK_MASK (0x3 << 9) 9993 #define CNL_DRAM_RANK_SHIFT 9 9994 #define CNL_DRAM_RANK_1 (0x0 << 9) 9995 #define CNL_DRAM_RANK_2 (0x1 << 9) 9996 #define CNL_DRAM_RANK_3 (0x2 << 9) 9997 #define CNL_DRAM_RANK_4 (0x3 << 9) 9998 9999 /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, 10000 * since on HSW we can't write to it using I915_WRITE. */ 10001 #define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C) 10002 #define D_COMP_BDW _MMIO(0x138144) 10003 #define D_COMP_RCOMP_IN_PROGRESS (1 << 9) 10004 #define D_COMP_COMP_FORCE (1 << 8) 10005 #define D_COMP_COMP_DISABLE (1 << 0) 10006 10007 /* Pipe WM_LINETIME - watermark line time */ 10008 #define _PIPE_WM_LINETIME_A 0x45270 10009 #define _PIPE_WM_LINETIME_B 0x45274 10010 #define PIPE_WM_LINETIME(pipe) _MMIO_PIPE(pipe, _PIPE_WM_LINETIME_A, _PIPE_WM_LINETIME_B) 10011 #define PIPE_WM_LINETIME_MASK (0x1ff) 10012 #define PIPE_WM_LINETIME_TIME(x) ((x)) 10013 #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff << 16) 10014 #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x) << 16) 10015 10016 /* SFUSE_STRAP */ 10017 #define SFUSE_STRAP _MMIO(0xc2014) 10018 #define SFUSE_STRAP_FUSE_LOCK (1 << 13) 10019 #define SFUSE_STRAP_RAW_FREQUENCY (1 << 8) 10020 #define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7) 10021 #define SFUSE_STRAP_CRT_DISABLED (1 << 6) 10022 #define SFUSE_STRAP_DDIF_DETECTED (1 << 3) 10023 #define SFUSE_STRAP_DDIB_DETECTED (1 << 2) 10024 #define SFUSE_STRAP_DDIC_DETECTED (1 << 1) 10025 #define SFUSE_STRAP_DDID_DETECTED (1 << 0) 10026 10027 #define WM_MISC _MMIO(0x45260) 10028 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0) 10029 10030 #define WM_DBG _MMIO(0x45280) 10031 #define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0) 10032 #define WM_DBG_DISALLOW_MAXFIFO (1 << 1) 10033 #define WM_DBG_DISALLOW_SPRITE (1 << 2) 10034 10035 /* pipe CSC */ 10036 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010 10037 #define _PIPE_A_CSC_COEFF_BY 0x49014 10038 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018 10039 #define _PIPE_A_CSC_COEFF_BU 0x4901c 10040 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020 10041 #define _PIPE_A_CSC_COEFF_BV 0x49024 10042 10043 #define _PIPE_A_CSC_MODE 0x49028 10044 #define ICL_CSC_ENABLE (1 << 31) 10045 #define ICL_OUTPUT_CSC_ENABLE (1 << 30) 10046 #define CSC_BLACK_SCREEN_OFFSET (1 << 2) 10047 #define CSC_POSITION_BEFORE_GAMMA (1 << 1) 10048 #define CSC_MODE_YUV_TO_RGB (1 << 0) 10049 10050 #define _PIPE_A_CSC_PREOFF_HI 0x49030 10051 #define _PIPE_A_CSC_PREOFF_ME 0x49034 10052 #define _PIPE_A_CSC_PREOFF_LO 0x49038 10053 #define _PIPE_A_CSC_POSTOFF_HI 0x49040 10054 #define _PIPE_A_CSC_POSTOFF_ME 0x49044 10055 #define _PIPE_A_CSC_POSTOFF_LO 0x49048 10056 10057 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110 10058 #define _PIPE_B_CSC_COEFF_BY 0x49114 10059 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118 10060 #define _PIPE_B_CSC_COEFF_BU 0x4911c 10061 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120 10062 #define _PIPE_B_CSC_COEFF_BV 0x49124 10063 #define _PIPE_B_CSC_MODE 0x49128 10064 #define _PIPE_B_CSC_PREOFF_HI 0x49130 10065 #define _PIPE_B_CSC_PREOFF_ME 0x49134 10066 #define _PIPE_B_CSC_PREOFF_LO 0x49138 10067 #define _PIPE_B_CSC_POSTOFF_HI 0x49140 10068 #define _PIPE_B_CSC_POSTOFF_ME 0x49144 10069 #define _PIPE_B_CSC_POSTOFF_LO 0x49148 10070 10071 #define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY) 10072 #define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY) 10073 #define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU) 10074 #define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU) 10075 #define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV) 10076 #define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV) 10077 #define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE) 10078 #define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI) 10079 #define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME) 10080 #define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO) 10081 #define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI) 10082 #define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) 10083 #define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) 10084 10085 /* Pipe Output CSC */ 10086 #define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY 0x49050 10087 #define _PIPE_A_OUTPUT_CSC_COEFF_BY 0x49054 10088 #define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU 0x49058 10089 #define _PIPE_A_OUTPUT_CSC_COEFF_BU 0x4905c 10090 #define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV 0x49060 10091 #define _PIPE_A_OUTPUT_CSC_COEFF_BV 0x49064 10092 #define _PIPE_A_OUTPUT_CSC_PREOFF_HI 0x49068 10093 #define _PIPE_A_OUTPUT_CSC_PREOFF_ME 0x4906c 10094 #define _PIPE_A_OUTPUT_CSC_PREOFF_LO 0x49070 10095 #define _PIPE_A_OUTPUT_CSC_POSTOFF_HI 0x49074 10096 #define _PIPE_A_OUTPUT_CSC_POSTOFF_ME 0x49078 10097 #define _PIPE_A_OUTPUT_CSC_POSTOFF_LO 0x4907c 10098 10099 #define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY 0x49150 10100 #define _PIPE_B_OUTPUT_CSC_COEFF_BY 0x49154 10101 #define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU 0x49158 10102 #define _PIPE_B_OUTPUT_CSC_COEFF_BU 0x4915c 10103 #define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV 0x49160 10104 #define _PIPE_B_OUTPUT_CSC_COEFF_BV 0x49164 10105 #define _PIPE_B_OUTPUT_CSC_PREOFF_HI 0x49168 10106 #define _PIPE_B_OUTPUT_CSC_PREOFF_ME 0x4916c 10107 #define _PIPE_B_OUTPUT_CSC_PREOFF_LO 0x49170 10108 #define _PIPE_B_OUTPUT_CSC_POSTOFF_HI 0x49174 10109 #define _PIPE_B_OUTPUT_CSC_POSTOFF_ME 0x49178 10110 #define _PIPE_B_OUTPUT_CSC_POSTOFF_LO 0x4917c 10111 10112 #define PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe,\ 10113 _PIPE_A_OUTPUT_CSC_COEFF_RY_GY,\ 10114 _PIPE_B_OUTPUT_CSC_COEFF_RY_GY) 10115 #define PIPE_CSC_OUTPUT_COEFF_BY(pipe) _MMIO_PIPE(pipe, \ 10116 _PIPE_A_OUTPUT_CSC_COEFF_BY, \ 10117 _PIPE_B_OUTPUT_CSC_COEFF_BY) 10118 #define PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, \ 10119 _PIPE_A_OUTPUT_CSC_COEFF_RU_GU, \ 10120 _PIPE_B_OUTPUT_CSC_COEFF_RU_GU) 10121 #define PIPE_CSC_OUTPUT_COEFF_BU(pipe) _MMIO_PIPE(pipe, \ 10122 _PIPE_A_OUTPUT_CSC_COEFF_BU, \ 10123 _PIPE_B_OUTPUT_CSC_COEFF_BU) 10124 #define PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, \ 10125 _PIPE_A_OUTPUT_CSC_COEFF_RV_GV, \ 10126 _PIPE_B_OUTPUT_CSC_COEFF_RV_GV) 10127 #define PIPE_CSC_OUTPUT_COEFF_BV(pipe) _MMIO_PIPE(pipe, \ 10128 _PIPE_A_OUTPUT_CSC_COEFF_BV, \ 10129 _PIPE_B_OUTPUT_CSC_COEFF_BV) 10130 #define PIPE_CSC_OUTPUT_PREOFF_HI(pipe) _MMIO_PIPE(pipe, \ 10131 _PIPE_A_OUTPUT_CSC_PREOFF_HI, \ 10132 _PIPE_B_OUTPUT_CSC_PREOFF_HI) 10133 #define PIPE_CSC_OUTPUT_PREOFF_ME(pipe) _MMIO_PIPE(pipe, \ 10134 _PIPE_A_OUTPUT_CSC_PREOFF_ME, \ 10135 _PIPE_B_OUTPUT_CSC_PREOFF_ME) 10136 #define PIPE_CSC_OUTPUT_PREOFF_LO(pipe) _MMIO_PIPE(pipe, \ 10137 _PIPE_A_OUTPUT_CSC_PREOFF_LO, \ 10138 _PIPE_B_OUTPUT_CSC_PREOFF_LO) 10139 #define PIPE_CSC_OUTPUT_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, \ 10140 _PIPE_A_OUTPUT_CSC_POSTOFF_HI, \ 10141 _PIPE_B_OUTPUT_CSC_POSTOFF_HI) 10142 #define PIPE_CSC_OUTPUT_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, \ 10143 _PIPE_A_OUTPUT_CSC_POSTOFF_ME, \ 10144 _PIPE_B_OUTPUT_CSC_POSTOFF_ME) 10145 #define PIPE_CSC_OUTPUT_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, \ 10146 _PIPE_A_OUTPUT_CSC_POSTOFF_LO, \ 10147 _PIPE_B_OUTPUT_CSC_POSTOFF_LO) 10148 10149 /* pipe degamma/gamma LUTs on IVB+ */ 10150 #define _PAL_PREC_INDEX_A 0x4A400 10151 #define _PAL_PREC_INDEX_B 0x4AC00 10152 #define _PAL_PREC_INDEX_C 0x4B400 10153 #define PAL_PREC_10_12_BIT (0 << 31) 10154 #define PAL_PREC_SPLIT_MODE (1 << 31) 10155 #define PAL_PREC_AUTO_INCREMENT (1 << 15) 10156 #define PAL_PREC_INDEX_VALUE_MASK (0x3ff << 0) 10157 #define PAL_PREC_INDEX_VALUE(x) ((x) << 0) 10158 #define _PAL_PREC_DATA_A 0x4A404 10159 #define _PAL_PREC_DATA_B 0x4AC04 10160 #define _PAL_PREC_DATA_C 0x4B404 10161 #define _PAL_PREC_GC_MAX_A 0x4A410 10162 #define _PAL_PREC_GC_MAX_B 0x4AC10 10163 #define _PAL_PREC_GC_MAX_C 0x4B410 10164 #define _PAL_PREC_EXT_GC_MAX_A 0x4A420 10165 #define _PAL_PREC_EXT_GC_MAX_B 0x4AC20 10166 #define _PAL_PREC_EXT_GC_MAX_C 0x4B420 10167 #define _PAL_PREC_EXT2_GC_MAX_A 0x4A430 10168 #define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30 10169 #define _PAL_PREC_EXT2_GC_MAX_C 0x4B430 10170 10171 #define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B) 10172 #define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B) 10173 #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4) 10174 #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4) 10175 #define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4) 10176 10177 #define _PRE_CSC_GAMC_INDEX_A 0x4A484 10178 #define _PRE_CSC_GAMC_INDEX_B 0x4AC84 10179 #define _PRE_CSC_GAMC_INDEX_C 0x4B484 10180 #define PRE_CSC_GAMC_AUTO_INCREMENT (1 << 10) 10181 #define _PRE_CSC_GAMC_DATA_A 0x4A488 10182 #define _PRE_CSC_GAMC_DATA_B 0x4AC88 10183 #define _PRE_CSC_GAMC_DATA_C 0x4B488 10184 10185 #define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B) 10186 #define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B) 10187 10188 /* ICL Multi segmented gamma */ 10189 #define _PAL_PREC_MULTI_SEG_INDEX_A 0x4A408 10190 #define _PAL_PREC_MULTI_SEG_INDEX_B 0x4AC08 10191 #define PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT REG_BIT(15) 10192 #define PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK REG_GENMASK(4, 0) 10193 10194 #define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C 10195 #define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C 10196 10197 #define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \ 10198 _PAL_PREC_MULTI_SEG_INDEX_A, \ 10199 _PAL_PREC_MULTI_SEG_INDEX_B) 10200 #define PREC_PAL_MULTI_SEG_DATA(pipe) _MMIO_PIPE(pipe, \ 10201 _PAL_PREC_MULTI_SEG_DATA_A, \ 10202 _PAL_PREC_MULTI_SEG_DATA_B) 10203 10204 /* pipe CSC & degamma/gamma LUTs on CHV */ 10205 #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900) 10206 #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904) 10207 #define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908) 10208 #define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C) 10209 #define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910) 10210 #define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000) 10211 #define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000) 10212 #define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00) 10213 #define CGM_PIPE_MODE_GAMMA (1 << 2) 10214 #define CGM_PIPE_MODE_CSC (1 << 1) 10215 #define CGM_PIPE_MODE_DEGAMMA (1 << 0) 10216 10217 #define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900) 10218 #define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904) 10219 #define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908) 10220 #define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C) 10221 #define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910) 10222 #define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000) 10223 #define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000) 10224 #define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00) 10225 10226 #define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01) 10227 #define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23) 10228 #define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45) 10229 #define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67) 10230 #define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8) 10231 #define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4) 10232 #define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4) 10233 #define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE) 10234 10235 /* MIPI DSI registers */ 10236 10237 #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */ 10238 #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c)) 10239 10240 /* Gen11 DSI */ 10241 #define _MMIO_DSI(tc, dsi0, dsi1) _MMIO_TRANS((tc) - TRANSCODER_DSI_0, \ 10242 dsi0, dsi1) 10243 10244 #define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004) 10245 #define GLK_TX_ESC_CLK_DIV1_MASK 0x3FF 10246 #define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008) 10247 #define GLK_TX_ESC_CLK_DIV2_MASK 0x3FF 10248 10249 #define _ICL_DSI_ESC_CLK_DIV0 0x6b090 10250 #define _ICL_DSI_ESC_CLK_DIV1 0x6b890 10251 #define ICL_DSI_ESC_CLK_DIV(port) _MMIO_PORT((port), \ 10252 _ICL_DSI_ESC_CLK_DIV0, \ 10253 _ICL_DSI_ESC_CLK_DIV1) 10254 #define _ICL_DPHY_ESC_CLK_DIV0 0x162190 10255 #define _ICL_DPHY_ESC_CLK_DIV1 0x6C190 10256 #define ICL_DPHY_ESC_CLK_DIV(port) _MMIO_PORT((port), \ 10257 _ICL_DPHY_ESC_CLK_DIV0, \ 10258 _ICL_DPHY_ESC_CLK_DIV1) 10259 #define ICL_BYTE_CLK_PER_ESC_CLK_MASK (0x1f << 16) 10260 #define ICL_BYTE_CLK_PER_ESC_CLK_SHIFT 16 10261 #define ICL_ESC_CLK_DIV_MASK 0x1ff 10262 #define ICL_ESC_CLK_DIV_SHIFT 0 10263 #define DSI_MAX_ESC_CLK 20000 /* in KHz */ 10264 10265 /* Gen4+ Timestamp and Pipe Frame time stamp registers */ 10266 #define GEN4_TIMESTAMP _MMIO(0x2358) 10267 #define ILK_TIMESTAMP_HI _MMIO(0x70070) 10268 #define IVB_TIMESTAMP_CTR _MMIO(0x44070) 10269 10270 #define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074) 10271 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0 10272 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff 10273 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12 10274 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12) 10275 10276 #define _PIPE_FRMTMSTMP_A 0x70048 10277 #define PIPE_FRMTMSTMP(pipe) \ 10278 _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A) 10279 10280 /* BXT MIPI clock controls */ 10281 #define BXT_MAX_VAR_OUTPUT_KHZ 39500 10282 10283 #define BXT_MIPI_CLOCK_CTL _MMIO(0x46090) 10284 #define BXT_MIPI1_DIV_SHIFT 26 10285 #define BXT_MIPI2_DIV_SHIFT 10 10286 #define BXT_MIPI_DIV_SHIFT(port) \ 10287 _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \ 10288 BXT_MIPI2_DIV_SHIFT) 10289 10290 /* TX control divider to select actual TX clock output from (8x/var) */ 10291 #define BXT_MIPI1_TX_ESCLK_SHIFT 26 10292 #define BXT_MIPI2_TX_ESCLK_SHIFT 10 10293 #define BXT_MIPI_TX_ESCLK_SHIFT(port) \ 10294 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \ 10295 BXT_MIPI2_TX_ESCLK_SHIFT) 10296 #define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (0x3F << 26) 10297 #define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (0x3F << 10) 10298 #define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \ 10299 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \ 10300 BXT_MIPI2_TX_ESCLK_FIXDIV_MASK) 10301 #define BXT_MIPI_TX_ESCLK_DIVIDER(port, val) \ 10302 (((val) & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port)) 10303 /* RX upper control divider to select actual RX clock output from 8x */ 10304 #define BXT_MIPI1_RX_ESCLK_UPPER_SHIFT 21 10305 #define BXT_MIPI2_RX_ESCLK_UPPER_SHIFT 5 10306 #define BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port) \ 10307 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \ 10308 BXT_MIPI2_RX_ESCLK_UPPER_SHIFT) 10309 #define BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 21) 10310 #define BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 5) 10311 #define BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port) \ 10312 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \ 10313 BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK) 10314 #define BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val) \ 10315 (((val) & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port)) 10316 /* 8/3X divider to select the actual 8/3X clock output from 8x */ 10317 #define BXT_MIPI1_8X_BY3_SHIFT 19 10318 #define BXT_MIPI2_8X_BY3_SHIFT 3 10319 #define BXT_MIPI_8X_BY3_SHIFT(port) \ 10320 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \ 10321 BXT_MIPI2_8X_BY3_SHIFT) 10322 #define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19) 10323 #define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3) 10324 #define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \ 10325 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \ 10326 BXT_MIPI2_8X_BY3_DIVIDER_MASK) 10327 #define BXT_MIPI_8X_BY3_DIVIDER(port, val) \ 10328 (((val) & 3) << BXT_MIPI_8X_BY3_SHIFT(port)) 10329 /* RX lower control divider to select actual RX clock output from 8x */ 10330 #define BXT_MIPI1_RX_ESCLK_LOWER_SHIFT 16 10331 #define BXT_MIPI2_RX_ESCLK_LOWER_SHIFT 0 10332 #define BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port) \ 10333 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \ 10334 BXT_MIPI2_RX_ESCLK_LOWER_SHIFT) 10335 #define BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 16) 10336 #define BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 0) 10337 #define BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port) \ 10338 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \ 10339 BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK) 10340 #define BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val) \ 10341 (((val) & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port)) 10342 10343 #define RX_DIVIDER_BIT_1_2 0x3 10344 #define RX_DIVIDER_BIT_3_4 0xC 10345 10346 /* BXT MIPI mode configure */ 10347 #define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8 10348 #define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8 10349 #define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(tc, \ 10350 _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE) 10351 10352 #define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC 10353 #define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC 10354 #define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(tc, \ 10355 _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE) 10356 10357 #define _BXT_MIPIA_TRANS_VTOTAL 0x6B100 10358 #define _BXT_MIPIC_TRANS_VTOTAL 0x6B900 10359 #define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(tc, \ 10360 _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL) 10361 10362 #define BXT_DSI_PLL_CTL _MMIO(0x161000) 10363 #define BXT_DSI_PLL_PVD_RATIO_SHIFT 16 10364 #define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT) 10365 #define BXT_DSI_PLL_PVD_RATIO_1 (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT) 10366 #define BXT_DSIC_16X_BY1 (0 << 10) 10367 #define BXT_DSIC_16X_BY2 (1 << 10) 10368 #define BXT_DSIC_16X_BY3 (2 << 10) 10369 #define BXT_DSIC_16X_BY4 (3 << 10) 10370 #define BXT_DSIC_16X_MASK (3 << 10) 10371 #define BXT_DSIA_16X_BY1 (0 << 8) 10372 #define BXT_DSIA_16X_BY2 (1 << 8) 10373 #define BXT_DSIA_16X_BY3 (2 << 8) 10374 #define BXT_DSIA_16X_BY4 (3 << 8) 10375 #define BXT_DSIA_16X_MASK (3 << 8) 10376 #define BXT_DSI_FREQ_SEL_SHIFT 8 10377 #define BXT_DSI_FREQ_SEL_MASK (0xF << BXT_DSI_FREQ_SEL_SHIFT) 10378 10379 #define BXT_DSI_PLL_RATIO_MAX 0x7D 10380 #define BXT_DSI_PLL_RATIO_MIN 0x22 10381 #define GLK_DSI_PLL_RATIO_MAX 0x6F 10382 #define GLK_DSI_PLL_RATIO_MIN 0x22 10383 #define BXT_DSI_PLL_RATIO_MASK 0xFF 10384 #define BXT_REF_CLOCK_KHZ 19200 10385 10386 #define BXT_DSI_PLL_ENABLE _MMIO(0x46080) 10387 #define BXT_DSI_PLL_DO_ENABLE (1 << 31) 10388 #define BXT_DSI_PLL_LOCKED (1 << 30) 10389 10390 #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) 10391 #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) 10392 #define MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL) 10393 10394 /* BXT port control */ 10395 #define _BXT_MIPIA_PORT_CTRL 0x6B0C0 10396 #define _BXT_MIPIC_PORT_CTRL 0x6B8C0 10397 #define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL) 10398 10399 /* ICL DSI MODE control */ 10400 #define _ICL_DSI_IO_MODECTL_0 0x6B094 10401 #define _ICL_DSI_IO_MODECTL_1 0x6B894 10402 #define ICL_DSI_IO_MODECTL(port) _MMIO_PORT(port, \ 10403 _ICL_DSI_IO_MODECTL_0, \ 10404 _ICL_DSI_IO_MODECTL_1) 10405 #define COMBO_PHY_MODE_DSI (1 << 0) 10406 10407 /* Display Stream Splitter Control */ 10408 #define DSS_CTL1 _MMIO(0x67400) 10409 #define SPLITTER_ENABLE (1 << 31) 10410 #define JOINER_ENABLE (1 << 30) 10411 #define DUAL_LINK_MODE_INTERLEAVE (1 << 24) 10412 #define DUAL_LINK_MODE_FRONTBACK (0 << 24) 10413 #define OVERLAP_PIXELS_MASK (0xf << 16) 10414 #define OVERLAP_PIXELS(pixels) ((pixels) << 16) 10415 #define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) 10416 #define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) 10417 #define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0 10418 10419 #define DSS_CTL2 _MMIO(0x67404) 10420 #define LEFT_BRANCH_VDSC_ENABLE (1 << 31) 10421 #define RIGHT_BRANCH_VDSC_ENABLE (1 << 15) 10422 #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) 10423 #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) 10424 10425 #define _ICL_PIPE_DSS_CTL1_PB 0x78200 10426 #define _ICL_PIPE_DSS_CTL1_PC 0x78400 10427 #define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 10428 _ICL_PIPE_DSS_CTL1_PB, \ 10429 _ICL_PIPE_DSS_CTL1_PC) 10430 #define BIG_JOINER_ENABLE (1 << 29) 10431 #define MASTER_BIG_JOINER_ENABLE (1 << 28) 10432 #define VGA_CENTERING_ENABLE (1 << 27) 10433 10434 #define _ICL_PIPE_DSS_CTL2_PB 0x78204 10435 #define _ICL_PIPE_DSS_CTL2_PC 0x78404 10436 #define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 10437 _ICL_PIPE_DSS_CTL2_PB, \ 10438 _ICL_PIPE_DSS_CTL2_PC) 10439 10440 #define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020) 10441 #define STAP_SELECT (1 << 0) 10442 10443 #define BXT_P_DSI_REGULATOR_TX_CTRL _MMIO(0x160054) 10444 #define HS_IO_CTRL_SELECT (1 << 0) 10445 10446 #define DPI_ENABLE (1 << 31) /* A + C */ 10447 #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 10448 #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27) 10449 #define DUAL_LINK_MODE_SHIFT 26 10450 #define DUAL_LINK_MODE_MASK (1 << 26) 10451 #define DUAL_LINK_MODE_FRONT_BACK (0 << 26) 10452 #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26) 10453 #define DITHERING_ENABLE (1 << 25) /* A + C */ 10454 #define FLOPPED_HSTX (1 << 23) 10455 #define DE_INVERT (1 << 19) /* XXX */ 10456 #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18 10457 #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18) 10458 #define AFE_LATCHOUT (1 << 17) 10459 #define LP_OUTPUT_HOLD (1 << 16) 10460 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15 10461 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15) 10462 #define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11 10463 #define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11) 10464 #define CSB_SHIFT 9 10465 #define CSB_MASK (3 << 9) 10466 #define CSB_20MHZ (0 << 9) 10467 #define CSB_10MHZ (1 << 9) 10468 #define CSB_40MHZ (2 << 9) 10469 #define BANDGAP_MASK (1 << 8) 10470 #define BANDGAP_PNW_CIRCUIT (0 << 8) 10471 #define BANDGAP_LNC_CIRCUIT (1 << 8) 10472 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5 10473 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5) 10474 #define TEARING_EFFECT_DELAY (1 << 4) /* A + C */ 10475 #define TEARING_EFFECT_SHIFT 2 /* A + C */ 10476 #define TEARING_EFFECT_MASK (3 << 2) 10477 #define TEARING_EFFECT_OFF (0 << 2) 10478 #define TEARING_EFFECT_DSI (1 << 2) 10479 #define TEARING_EFFECT_GPIO (2 << 2) 10480 #define LANE_CONFIGURATION_SHIFT 0 10481 #define LANE_CONFIGURATION_MASK (3 << 0) 10482 #define LANE_CONFIGURATION_4LANE (0 << 0) 10483 #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0) 10484 #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0) 10485 10486 #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) 10487 #define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) 10488 #define MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) 10489 #define TEARING_EFFECT_DELAY_SHIFT 0 10490 #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) 10491 10492 /* XXX: all bits reserved */ 10493 #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0) 10494 10495 /* MIPI DSI Controller and D-PHY registers */ 10496 10497 #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000) 10498 #define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800) 10499 #define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY) 10500 #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */ 10501 #define ULPS_STATE_MASK (3 << 1) 10502 #define ULPS_STATE_ENTER (2 << 1) 10503 #define ULPS_STATE_EXIT (1 << 1) 10504 #define ULPS_STATE_NORMAL_OPERATION (0 << 1) 10505 #define DEVICE_READY (1 << 0) 10506 10507 #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004) 10508 #define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804) 10509 #define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT) 10510 #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008) 10511 #define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808) 10512 #define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN) 10513 #define TEARING_EFFECT (1 << 31) 10514 #define SPL_PKT_SENT_INTERRUPT (1 << 30) 10515 #define GEN_READ_DATA_AVAIL (1 << 29) 10516 #define LP_GENERIC_WR_FIFO_FULL (1 << 28) 10517 #define HS_GENERIC_WR_FIFO_FULL (1 << 27) 10518 #define RX_PROT_VIOLATION (1 << 26) 10519 #define RX_INVALID_TX_LENGTH (1 << 25) 10520 #define ACK_WITH_NO_ERROR (1 << 24) 10521 #define TURN_AROUND_ACK_TIMEOUT (1 << 23) 10522 #define LP_RX_TIMEOUT (1 << 22) 10523 #define HS_TX_TIMEOUT (1 << 21) 10524 #define DPI_FIFO_UNDERRUN (1 << 20) 10525 #define LOW_CONTENTION (1 << 19) 10526 #define HIGH_CONTENTION (1 << 18) 10527 #define TXDSI_VC_ID_INVALID (1 << 17) 10528 #define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16) 10529 #define TXCHECKSUM_ERROR (1 << 15) 10530 #define TXECC_MULTIBIT_ERROR (1 << 14) 10531 #define TXECC_SINGLE_BIT_ERROR (1 << 13) 10532 #define TXFALSE_CONTROL_ERROR (1 << 12) 10533 #define RXDSI_VC_ID_INVALID (1 << 11) 10534 #define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10) 10535 #define RXCHECKSUM_ERROR (1 << 9) 10536 #define RXECC_MULTIBIT_ERROR (1 << 8) 10537 #define RXECC_SINGLE_BIT_ERROR (1 << 7) 10538 #define RXFALSE_CONTROL_ERROR (1 << 6) 10539 #define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5) 10540 #define RX_LP_TX_SYNC_ERROR (1 << 4) 10541 #define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3) 10542 #define RXEOT_SYNC_ERROR (1 << 2) 10543 #define RXSOT_SYNC_ERROR (1 << 1) 10544 #define RXSOT_ERROR (1 << 0) 10545 10546 #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c) 10547 #define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c) 10548 #define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG) 10549 #define CMD_MODE_DATA_WIDTH_MASK (7 << 13) 10550 #define CMD_MODE_NOT_SUPPORTED (0 << 13) 10551 #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13) 10552 #define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13) 10553 #define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13) 10554 #define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13) 10555 #define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13) 10556 #define VID_MODE_FORMAT_MASK (0xf << 7) 10557 #define VID_MODE_NOT_SUPPORTED (0 << 7) 10558 #define VID_MODE_FORMAT_RGB565 (1 << 7) 10559 #define VID_MODE_FORMAT_RGB666_PACKED (2 << 7) 10560 #define VID_MODE_FORMAT_RGB666 (3 << 7) 10561 #define VID_MODE_FORMAT_RGB888 (4 << 7) 10562 #define CMD_MODE_CHANNEL_NUMBER_SHIFT 5 10563 #define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5) 10564 #define VID_MODE_CHANNEL_NUMBER_SHIFT 3 10565 #define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3) 10566 #define DATA_LANES_PRG_REG_SHIFT 0 10567 #define DATA_LANES_PRG_REG_MASK (7 << 0) 10568 10569 #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010) 10570 #define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810) 10571 #define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT) 10572 #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff 10573 10574 #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014) 10575 #define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814) 10576 #define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT) 10577 #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff 10578 10579 #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018) 10580 #define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818) 10581 #define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT) 10582 #define TURN_AROUND_TIMEOUT_MASK 0x3f 10583 10584 #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c) 10585 #define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c) 10586 #define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER) 10587 #define DEVICE_RESET_TIMER_MASK 0xffff 10588 10589 #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020) 10590 #define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820) 10591 #define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION) 10592 #define VERTICAL_ADDRESS_SHIFT 16 10593 #define VERTICAL_ADDRESS_MASK (0xffff << 16) 10594 #define HORIZONTAL_ADDRESS_SHIFT 0 10595 #define HORIZONTAL_ADDRESS_MASK 0xffff 10596 10597 #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024) 10598 #define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824) 10599 #define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE) 10600 #define DBI_FIFO_EMPTY_HALF (0 << 0) 10601 #define DBI_FIFO_EMPTY_QUARTER (1 << 0) 10602 #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0) 10603 10604 /* regs below are bits 15:0 */ 10605 #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028) 10606 #define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828) 10607 #define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT) 10608 10609 #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c) 10610 #define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c) 10611 #define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT) 10612 10613 #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030) 10614 #define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830) 10615 #define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT) 10616 10617 #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034) 10618 #define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834) 10619 #define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT) 10620 10621 #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038) 10622 #define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838) 10623 #define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT) 10624 10625 #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c) 10626 #define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c) 10627 #define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT) 10628 10629 #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040) 10630 #define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840) 10631 #define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT) 10632 10633 #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044) 10634 #define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844) 10635 #define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT) 10636 10637 /* regs above are bits 15:0 */ 10638 10639 #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048) 10640 #define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848) 10641 #define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL) 10642 #define DPI_LP_MODE (1 << 6) 10643 #define BACKLIGHT_OFF (1 << 5) 10644 #define BACKLIGHT_ON (1 << 4) 10645 #define COLOR_MODE_OFF (1 << 3) 10646 #define COLOR_MODE_ON (1 << 2) 10647 #define TURN_ON (1 << 1) 10648 #define SHUTDOWN (1 << 0) 10649 10650 #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c) 10651 #define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c) 10652 #define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA) 10653 #define COMMAND_BYTE_SHIFT 0 10654 #define COMMAND_BYTE_MASK (0x3f << 0) 10655 10656 #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050) 10657 #define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850) 10658 #define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT) 10659 #define MASTER_INIT_TIMER_SHIFT 0 10660 #define MASTER_INIT_TIMER_MASK (0xffff << 0) 10661 10662 #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054) 10663 #define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854) 10664 #define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \ 10665 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE) 10666 #define MAX_RETURN_PKT_SIZE_SHIFT 0 10667 #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) 10668 10669 #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058) 10670 #define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858) 10671 #define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT) 10672 #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) 10673 #define DISABLE_VIDEO_BTA (1 << 3) 10674 #define IP_TG_CONFIG (1 << 2) 10675 #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0) 10676 #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0) 10677 #define VIDEO_MODE_BURST (3 << 0) 10678 10679 #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c) 10680 #define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c) 10681 #define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE) 10682 #define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9) 10683 #define BXT_DPHY_DEFEATURE_EN (1 << 8) 10684 #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) 10685 #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6) 10686 #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5) 10687 #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4) 10688 #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3) 10689 #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2) 10690 #define CLOCKSTOP (1 << 1) 10691 #define EOT_DISABLE (1 << 0) 10692 10693 #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060) 10694 #define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860) 10695 #define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK) 10696 #define LP_BYTECLK_SHIFT 0 10697 #define LP_BYTECLK_MASK (0xffff << 0) 10698 10699 #define _MIPIA_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb0a4) 10700 #define _MIPIC_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb8a4) 10701 #define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT) 10702 10703 #define _MIPIA_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb098) 10704 #define _MIPIC_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb898) 10705 #define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING) 10706 10707 /* bits 31:0 */ 10708 #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064) 10709 #define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864) 10710 #define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA) 10711 10712 /* bits 31:0 */ 10713 #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068) 10714 #define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868) 10715 #define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA) 10716 10717 #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c) 10718 #define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c) 10719 #define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL) 10720 #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070) 10721 #define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870) 10722 #define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL) 10723 #define LONG_PACKET_WORD_COUNT_SHIFT 8 10724 #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8) 10725 #define SHORT_PACKET_PARAM_SHIFT 8 10726 #define SHORT_PACKET_PARAM_MASK (0xffff << 8) 10727 #define VIRTUAL_CHANNEL_SHIFT 6 10728 #define VIRTUAL_CHANNEL_MASK (3 << 6) 10729 #define DATA_TYPE_SHIFT 0 10730 #define DATA_TYPE_MASK (0x3f << 0) 10731 /* data type values, see include/video/mipi_display.h */ 10732 10733 #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074) 10734 #define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874) 10735 #define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT) 10736 #define DPI_FIFO_EMPTY (1 << 28) 10737 #define DBI_FIFO_EMPTY (1 << 27) 10738 #define LP_CTRL_FIFO_EMPTY (1 << 26) 10739 #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25) 10740 #define LP_CTRL_FIFO_FULL (1 << 24) 10741 #define HS_CTRL_FIFO_EMPTY (1 << 18) 10742 #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17) 10743 #define HS_CTRL_FIFO_FULL (1 << 16) 10744 #define LP_DATA_FIFO_EMPTY (1 << 10) 10745 #define LP_DATA_FIFO_HALF_EMPTY (1 << 9) 10746 #define LP_DATA_FIFO_FULL (1 << 8) 10747 #define HS_DATA_FIFO_EMPTY (1 << 2) 10748 #define HS_DATA_FIFO_HALF_EMPTY (1 << 1) 10749 #define HS_DATA_FIFO_FULL (1 << 0) 10750 10751 #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078) 10752 #define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878) 10753 #define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE) 10754 #define DBI_HS_LP_MODE_MASK (1 << 0) 10755 #define DBI_LP_MODE (1 << 0) 10756 #define DBI_HS_MODE (0 << 0) 10757 10758 #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080) 10759 #define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880) 10760 #define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM) 10761 #define EXIT_ZERO_COUNT_SHIFT 24 10762 #define EXIT_ZERO_COUNT_MASK (0x3f << 24) 10763 #define TRAIL_COUNT_SHIFT 16 10764 #define TRAIL_COUNT_MASK (0x1f << 16) 10765 #define CLK_ZERO_COUNT_SHIFT 8 10766 #define CLK_ZERO_COUNT_MASK (0xff << 8) 10767 #define PREPARE_COUNT_SHIFT 0 10768 #define PREPARE_COUNT_MASK (0x3f << 0) 10769 10770 #define _ICL_DSI_T_INIT_MASTER_0 0x6b088 10771 #define _ICL_DSI_T_INIT_MASTER_1 0x6b888 10772 #define ICL_DSI_T_INIT_MASTER(port) _MMIO_PORT(port, \ 10773 _ICL_DSI_T_INIT_MASTER_0,\ 10774 _ICL_DSI_T_INIT_MASTER_1) 10775 10776 #define _DPHY_CLK_TIMING_PARAM_0 0x162180 10777 #define _DPHY_CLK_TIMING_PARAM_1 0x6c180 10778 #define DPHY_CLK_TIMING_PARAM(port) _MMIO_PORT(port, \ 10779 _DPHY_CLK_TIMING_PARAM_0,\ 10780 _DPHY_CLK_TIMING_PARAM_1) 10781 #define _DSI_CLK_TIMING_PARAM_0 0x6b080 10782 #define _DSI_CLK_TIMING_PARAM_1 0x6b880 10783 #define DSI_CLK_TIMING_PARAM(port) _MMIO_PORT(port, \ 10784 _DSI_CLK_TIMING_PARAM_0,\ 10785 _DSI_CLK_TIMING_PARAM_1) 10786 #define CLK_PREPARE_OVERRIDE (1 << 31) 10787 #define CLK_PREPARE(x) ((x) << 28) 10788 #define CLK_PREPARE_MASK (0x7 << 28) 10789 #define CLK_PREPARE_SHIFT 28 10790 #define CLK_ZERO_OVERRIDE (1 << 27) 10791 #define CLK_ZERO(x) ((x) << 20) 10792 #define CLK_ZERO_MASK (0xf << 20) 10793 #define CLK_ZERO_SHIFT 20 10794 #define CLK_PRE_OVERRIDE (1 << 19) 10795 #define CLK_PRE(x) ((x) << 16) 10796 #define CLK_PRE_MASK (0x3 << 16) 10797 #define CLK_PRE_SHIFT 16 10798 #define CLK_POST_OVERRIDE (1 << 15) 10799 #define CLK_POST(x) ((x) << 8) 10800 #define CLK_POST_MASK (0x7 << 8) 10801 #define CLK_POST_SHIFT 8 10802 #define CLK_TRAIL_OVERRIDE (1 << 7) 10803 #define CLK_TRAIL(x) ((x) << 0) 10804 #define CLK_TRAIL_MASK (0xf << 0) 10805 #define CLK_TRAIL_SHIFT 0 10806 10807 #define _DPHY_DATA_TIMING_PARAM_0 0x162184 10808 #define _DPHY_DATA_TIMING_PARAM_1 0x6c184 10809 #define DPHY_DATA_TIMING_PARAM(port) _MMIO_PORT(port, \ 10810 _DPHY_DATA_TIMING_PARAM_0,\ 10811 _DPHY_DATA_TIMING_PARAM_1) 10812 #define _DSI_DATA_TIMING_PARAM_0 0x6B084 10813 #define _DSI_DATA_TIMING_PARAM_1 0x6B884 10814 #define DSI_DATA_TIMING_PARAM(port) _MMIO_PORT(port, \ 10815 _DSI_DATA_TIMING_PARAM_0,\ 10816 _DSI_DATA_TIMING_PARAM_1) 10817 #define HS_PREPARE_OVERRIDE (1 << 31) 10818 #define HS_PREPARE(x) ((x) << 24) 10819 #define HS_PREPARE_MASK (0x7 << 24) 10820 #define HS_PREPARE_SHIFT 24 10821 #define HS_ZERO_OVERRIDE (1 << 23) 10822 #define HS_ZERO(x) ((x) << 16) 10823 #define HS_ZERO_MASK (0xf << 16) 10824 #define HS_ZERO_SHIFT 16 10825 #define HS_TRAIL_OVERRIDE (1 << 15) 10826 #define HS_TRAIL(x) ((x) << 8) 10827 #define HS_TRAIL_MASK (0x7 << 8) 10828 #define HS_TRAIL_SHIFT 8 10829 #define HS_EXIT_OVERRIDE (1 << 7) 10830 #define HS_EXIT(x) ((x) << 0) 10831 #define HS_EXIT_MASK (0x7 << 0) 10832 #define HS_EXIT_SHIFT 0 10833 10834 #define _DPHY_TA_TIMING_PARAM_0 0x162188 10835 #define _DPHY_TA_TIMING_PARAM_1 0x6c188 10836 #define DPHY_TA_TIMING_PARAM(port) _MMIO_PORT(port, \ 10837 _DPHY_TA_TIMING_PARAM_0,\ 10838 _DPHY_TA_TIMING_PARAM_1) 10839 #define _DSI_TA_TIMING_PARAM_0 0x6b098 10840 #define _DSI_TA_TIMING_PARAM_1 0x6b898 10841 #define DSI_TA_TIMING_PARAM(port) _MMIO_PORT(port, \ 10842 _DSI_TA_TIMING_PARAM_0,\ 10843 _DSI_TA_TIMING_PARAM_1) 10844 #define TA_SURE_OVERRIDE (1 << 31) 10845 #define TA_SURE(x) ((x) << 16) 10846 #define TA_SURE_MASK (0x1f << 16) 10847 #define TA_SURE_SHIFT 16 10848 #define TA_GO_OVERRIDE (1 << 15) 10849 #define TA_GO(x) ((x) << 8) 10850 #define TA_GO_MASK (0xf << 8) 10851 #define TA_GO_SHIFT 8 10852 #define TA_GET_OVERRIDE (1 << 7) 10853 #define TA_GET(x) ((x) << 0) 10854 #define TA_GET_MASK (0xf << 0) 10855 #define TA_GET_SHIFT 0 10856 10857 /* DSI transcoder configuration */ 10858 #define _DSI_TRANS_FUNC_CONF_0 0x6b030 10859 #define _DSI_TRANS_FUNC_CONF_1 0x6b830 10860 #define DSI_TRANS_FUNC_CONF(tc) _MMIO_DSI(tc, \ 10861 _DSI_TRANS_FUNC_CONF_0,\ 10862 _DSI_TRANS_FUNC_CONF_1) 10863 #define OP_MODE_MASK (0x3 << 28) 10864 #define OP_MODE_SHIFT 28 10865 #define CMD_MODE_NO_GATE (0x0 << 28) 10866 #define CMD_MODE_TE_GATE (0x1 << 28) 10867 #define VIDEO_MODE_SYNC_EVENT (0x2 << 28) 10868 #define VIDEO_MODE_SYNC_PULSE (0x3 << 28) 10869 #define LINK_READY (1 << 20) 10870 #define PIX_FMT_MASK (0x3 << 16) 10871 #define PIX_FMT_SHIFT 16 10872 #define PIX_FMT_RGB565 (0x0 << 16) 10873 #define PIX_FMT_RGB666_PACKED (0x1 << 16) 10874 #define PIX_FMT_RGB666_LOOSE (0x2 << 16) 10875 #define PIX_FMT_RGB888 (0x3 << 16) 10876 #define PIX_FMT_RGB101010 (0x4 << 16) 10877 #define PIX_FMT_RGB121212 (0x5 << 16) 10878 #define PIX_FMT_COMPRESSED (0x6 << 16) 10879 #define BGR_TRANSMISSION (1 << 15) 10880 #define PIX_VIRT_CHAN(x) ((x) << 12) 10881 #define PIX_VIRT_CHAN_MASK (0x3 << 12) 10882 #define PIX_VIRT_CHAN_SHIFT 12 10883 #define PIX_BUF_THRESHOLD_MASK (0x3 << 10) 10884 #define PIX_BUF_THRESHOLD_SHIFT 10 10885 #define PIX_BUF_THRESHOLD_1_4 (0x0 << 10) 10886 #define PIX_BUF_THRESHOLD_1_2 (0x1 << 10) 10887 #define PIX_BUF_THRESHOLD_3_4 (0x2 << 10) 10888 #define PIX_BUF_THRESHOLD_FULL (0x3 << 10) 10889 #define CONTINUOUS_CLK_MASK (0x3 << 8) 10890 #define CONTINUOUS_CLK_SHIFT 8 10891 #define CLK_ENTER_LP_AFTER_DATA (0x0 << 8) 10892 #define CLK_HS_OR_LP (0x2 << 8) 10893 #define CLK_HS_CONTINUOUS (0x3 << 8) 10894 #define LINK_CALIBRATION_MASK (0x3 << 4) 10895 #define LINK_CALIBRATION_SHIFT 4 10896 #define CALIBRATION_DISABLED (0x0 << 4) 10897 #define CALIBRATION_ENABLED_INITIAL_ONLY (0x2 << 4) 10898 #define CALIBRATION_ENABLED_INITIAL_PERIODIC (0x3 << 4) 10899 #define S3D_ORIENTATION_LANDSCAPE (1 << 1) 10900 #define EOTP_DISABLED (1 << 0) 10901 10902 #define _DSI_CMD_RXCTL_0 0x6b0d4 10903 #define _DSI_CMD_RXCTL_1 0x6b8d4 10904 #define DSI_CMD_RXCTL(tc) _MMIO_DSI(tc, \ 10905 _DSI_CMD_RXCTL_0,\ 10906 _DSI_CMD_RXCTL_1) 10907 #define READ_UNLOADS_DW (1 << 16) 10908 #define RECEIVED_UNASSIGNED_TRIGGER (1 << 15) 10909 #define RECEIVED_ACKNOWLEDGE_TRIGGER (1 << 14) 10910 #define RECEIVED_TEAR_EFFECT_TRIGGER (1 << 13) 10911 #define RECEIVED_RESET_TRIGGER (1 << 12) 10912 #define RECEIVED_PAYLOAD_WAS_LOST (1 << 11) 10913 #define RECEIVED_CRC_WAS_LOST (1 << 10) 10914 #define NUMBER_RX_PLOAD_DW_MASK (0xff << 0) 10915 #define NUMBER_RX_PLOAD_DW_SHIFT 0 10916 10917 #define _DSI_CMD_TXCTL_0 0x6b0d0 10918 #define _DSI_CMD_TXCTL_1 0x6b8d0 10919 #define DSI_CMD_TXCTL(tc) _MMIO_DSI(tc, \ 10920 _DSI_CMD_TXCTL_0,\ 10921 _DSI_CMD_TXCTL_1) 10922 #define KEEP_LINK_IN_HS (1 << 24) 10923 #define FREE_HEADER_CREDIT_MASK (0x1f << 8) 10924 #define FREE_HEADER_CREDIT_SHIFT 0x8 10925 #define FREE_PLOAD_CREDIT_MASK (0xff << 0) 10926 #define FREE_PLOAD_CREDIT_SHIFT 0 10927 #define MAX_HEADER_CREDIT 0x10 10928 #define MAX_PLOAD_CREDIT 0x40 10929 10930 #define _DSI_CMD_TXHDR_0 0x6b100 10931 #define _DSI_CMD_TXHDR_1 0x6b900 10932 #define DSI_CMD_TXHDR(tc) _MMIO_DSI(tc, \ 10933 _DSI_CMD_TXHDR_0,\ 10934 _DSI_CMD_TXHDR_1) 10935 #define PAYLOAD_PRESENT (1 << 31) 10936 #define LP_DATA_TRANSFER (1 << 30) 10937 #define VBLANK_FENCE (1 << 29) 10938 #define PARAM_WC_MASK (0xffff << 8) 10939 #define PARAM_WC_LOWER_SHIFT 8 10940 #define PARAM_WC_UPPER_SHIFT 16 10941 #define VC_MASK (0x3 << 6) 10942 #define VC_SHIFT 6 10943 #define DT_MASK (0x3f << 0) 10944 #define DT_SHIFT 0 10945 10946 #define _DSI_CMD_TXPYLD_0 0x6b104 10947 #define _DSI_CMD_TXPYLD_1 0x6b904 10948 #define DSI_CMD_TXPYLD(tc) _MMIO_DSI(tc, \ 10949 _DSI_CMD_TXPYLD_0,\ 10950 _DSI_CMD_TXPYLD_1) 10951 10952 #define _DSI_LP_MSG_0 0x6b0d8 10953 #define _DSI_LP_MSG_1 0x6b8d8 10954 #define DSI_LP_MSG(tc) _MMIO_DSI(tc, \ 10955 _DSI_LP_MSG_0,\ 10956 _DSI_LP_MSG_1) 10957 #define LPTX_IN_PROGRESS (1 << 17) 10958 #define LINK_IN_ULPS (1 << 16) 10959 #define LINK_ULPS_TYPE_LP11 (1 << 8) 10960 #define LINK_ENTER_ULPS (1 << 0) 10961 10962 /* DSI timeout registers */ 10963 #define _DSI_HSTX_TO_0 0x6b044 10964 #define _DSI_HSTX_TO_1 0x6b844 10965 #define DSI_HSTX_TO(tc) _MMIO_DSI(tc, \ 10966 _DSI_HSTX_TO_0,\ 10967 _DSI_HSTX_TO_1) 10968 #define HSTX_TIMEOUT_VALUE_MASK (0xffff << 16) 10969 #define HSTX_TIMEOUT_VALUE_SHIFT 16 10970 #define HSTX_TIMEOUT_VALUE(x) ((x) << 16) 10971 #define HSTX_TIMED_OUT (1 << 0) 10972 10973 #define _DSI_LPRX_HOST_TO_0 0x6b048 10974 #define _DSI_LPRX_HOST_TO_1 0x6b848 10975 #define DSI_LPRX_HOST_TO(tc) _MMIO_DSI(tc, \ 10976 _DSI_LPRX_HOST_TO_0,\ 10977 _DSI_LPRX_HOST_TO_1) 10978 #define LPRX_TIMED_OUT (1 << 16) 10979 #define LPRX_TIMEOUT_VALUE_MASK (0xffff << 0) 10980 #define LPRX_TIMEOUT_VALUE_SHIFT 0 10981 #define LPRX_TIMEOUT_VALUE(x) ((x) << 0) 10982 10983 #define _DSI_PWAIT_TO_0 0x6b040 10984 #define _DSI_PWAIT_TO_1 0x6b840 10985 #define DSI_PWAIT_TO(tc) _MMIO_DSI(tc, \ 10986 _DSI_PWAIT_TO_0,\ 10987 _DSI_PWAIT_TO_1) 10988 #define PRESET_TIMEOUT_VALUE_MASK (0xffff << 16) 10989 #define PRESET_TIMEOUT_VALUE_SHIFT 16 10990 #define PRESET_TIMEOUT_VALUE(x) ((x) << 16) 10991 #define PRESPONSE_TIMEOUT_VALUE_MASK (0xffff << 0) 10992 #define PRESPONSE_TIMEOUT_VALUE_SHIFT 0 10993 #define PRESPONSE_TIMEOUT_VALUE(x) ((x) << 0) 10994 10995 #define _DSI_TA_TO_0 0x6b04c 10996 #define _DSI_TA_TO_1 0x6b84c 10997 #define DSI_TA_TO(tc) _MMIO_DSI(tc, \ 10998 _DSI_TA_TO_0,\ 10999 _DSI_TA_TO_1) 11000 #define TA_TIMED_OUT (1 << 16) 11001 #define TA_TIMEOUT_VALUE_MASK (0xffff << 0) 11002 #define TA_TIMEOUT_VALUE_SHIFT 0 11003 #define TA_TIMEOUT_VALUE(x) ((x) << 0) 11004 11005 /* bits 31:0 */ 11006 #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084) 11007 #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884) 11008 #define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL) 11009 11010 #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb088) 11011 #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb888) 11012 #define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT) 11013 #define LP_HS_SSW_CNT_SHIFT 16 11014 #define LP_HS_SSW_CNT_MASK (0xffff << 16) 11015 #define HS_LP_PWR_SW_CNT_SHIFT 0 11016 #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0) 11017 11018 #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c) 11019 #define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c) 11020 #define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL) 11021 #define STOP_STATE_STALL_COUNTER_SHIFT 0 11022 #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) 11023 11024 #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090) 11025 #define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890) 11026 #define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1) 11027 #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094) 11028 #define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894) 11029 #define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1) 11030 #define RX_CONTENTION_DETECTED (1 << 0) 11031 11032 /* XXX: only pipe A ?!? */ 11033 #define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100) 11034 #define DBI_TYPEC_ENABLE (1 << 31) 11035 #define DBI_TYPEC_WIP (1 << 30) 11036 #define DBI_TYPEC_OPTION_SHIFT 28 11037 #define DBI_TYPEC_OPTION_MASK (3 << 28) 11038 #define DBI_TYPEC_FREQ_SHIFT 24 11039 #define DBI_TYPEC_FREQ_MASK (0xf << 24) 11040 #define DBI_TYPEC_OVERRIDE (1 << 8) 11041 #define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0 11042 #define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0) 11043 11044 11045 /* MIPI adapter registers */ 11046 11047 #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104) 11048 #define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904) 11049 #define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL) 11050 #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */ 11051 #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) 11052 #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5) 11053 #define ESCAPE_CLOCK_DIVIDER_2 (1 << 5) 11054 #define ESCAPE_CLOCK_DIVIDER_4 (2 << 5) 11055 #define READ_REQUEST_PRIORITY_SHIFT 3 11056 #define READ_REQUEST_PRIORITY_MASK (3 << 3) 11057 #define READ_REQUEST_PRIORITY_LOW (0 << 3) 11058 #define READ_REQUEST_PRIORITY_HIGH (3 << 3) 11059 #define RGB_FLIP_TO_BGR (1 << 2) 11060 11061 #define BXT_PIPE_SELECT_SHIFT 7 11062 #define BXT_PIPE_SELECT_MASK (7 << 7) 11063 #define BXT_PIPE_SELECT(pipe) ((pipe) << 7) 11064 #define GLK_PHY_STATUS_PORT_READY (1 << 31) /* RO */ 11065 #define GLK_ULPS_NOT_ACTIVE (1 << 30) /* RO */ 11066 #define GLK_MIPIIO_RESET_RELEASED (1 << 28) 11067 #define GLK_CLOCK_LANE_STOP_STATE (1 << 27) /* RO */ 11068 #define GLK_DATA_LANE_STOP_STATE (1 << 26) /* RO */ 11069 #define GLK_LP_WAKE (1 << 22) 11070 #define GLK_LP11_LOW_PWR_MODE (1 << 21) 11071 #define GLK_LP00_LOW_PWR_MODE (1 << 20) 11072 #define GLK_FIREWALL_ENABLE (1 << 16) 11073 #define BXT_PIXEL_OVERLAP_CNT_MASK (0xf << 10) 11074 #define BXT_PIXEL_OVERLAP_CNT_SHIFT 10 11075 #define BXT_DSC_ENABLE (1 << 3) 11076 #define BXT_RGB_FLIP (1 << 2) 11077 #define GLK_MIPIIO_PORT_POWERED (1 << 1) /* RO */ 11078 #define GLK_MIPIIO_ENABLE (1 << 0) 11079 11080 #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108) 11081 #define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908) 11082 #define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS) 11083 #define DATA_MEM_ADDRESS_SHIFT 5 11084 #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) 11085 #define DATA_VALID (1 << 0) 11086 11087 #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c) 11088 #define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c) 11089 #define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH) 11090 #define DATA_LENGTH_SHIFT 0 11091 #define DATA_LENGTH_MASK (0xfffff << 0) 11092 11093 #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110) 11094 #define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910) 11095 #define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS) 11096 #define COMMAND_MEM_ADDRESS_SHIFT 5 11097 #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) 11098 #define AUTO_PWG_ENABLE (1 << 2) 11099 #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1) 11100 #define COMMAND_VALID (1 << 0) 11101 11102 #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114) 11103 #define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914) 11104 #define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH) 11105 #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */ 11106 #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n))) 11107 11108 #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118) 11109 #define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918) 11110 #define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */ 11111 11112 #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138) 11113 #define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938) 11114 #define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID) 11115 #define READ_DATA_VALID(n) (1 << (n)) 11116 11117 /* MOCS (Memory Object Control State) registers */ 11118 #define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */ 11119 11120 #define GEN9_GFX_MOCS(i) _MMIO(0xc800 + (i) * 4) /* Graphics MOCS registers */ 11121 #define GEN9_MFX0_MOCS(i) _MMIO(0xc900 + (i) * 4) /* Media 0 MOCS registers */ 11122 #define GEN9_MFX1_MOCS(i) _MMIO(0xca00 + (i) * 4) /* Media 1 MOCS registers */ 11123 #define GEN9_VEBOX_MOCS(i) _MMIO(0xcb00 + (i) * 4) /* Video MOCS registers */ 11124 #define GEN9_BLT_MOCS(i) _MMIO(0xcc00 + (i) * 4) /* Blitter MOCS registers */ 11125 /* Media decoder 2 MOCS registers */ 11126 #define GEN11_MFX2_MOCS(i) _MMIO(0x10000 + (i) * 4) 11127 11128 #define GEN10_SCRATCH_LNCF2 _MMIO(0xb0a0) 11129 #define PMFLUSHDONE_LNICRSDROP (1 << 20) 11130 #define PMFLUSH_GAPL3UNBLOCK (1 << 21) 11131 #define PMFLUSHDONE_LNEBLK (1 << 22) 11132 11133 /* gamt regs */ 11134 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4) 11135 #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */ 11136 #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF /* max/min for LRA1/2 */ 11137 #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F /* " " */ 11138 #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF /* " " */ 11139 11140 #define MMCD_MISC_CTRL _MMIO(0x4ddc) /* skl+ */ 11141 #define MMCD_PCLA (1 << 31) 11142 #define MMCD_HOTSPOT_EN (1 << 27) 11143 11144 #define _ICL_PHY_MISC_A 0x64C00 11145 #define _ICL_PHY_MISC_B 0x64C04 11146 #define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, \ 11147 _ICL_PHY_MISC_B) 11148 #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23) 11149 11150 /* Icelake Display Stream Compression Registers */ 11151 #define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200) 11152 #define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00) 11153 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270 11154 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370 11155 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470 11156 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570 11157 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11158 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \ 11159 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC) 11160 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11161 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \ 11162 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC) 11163 #define DSC_VBR_ENABLE (1 << 19) 11164 #define DSC_422_ENABLE (1 << 18) 11165 #define DSC_COLOR_SPACE_CONVERSION (1 << 17) 11166 #define DSC_BLOCK_PREDICTION (1 << 16) 11167 #define DSC_LINE_BUF_DEPTH_SHIFT 12 11168 #define DSC_BPC_SHIFT 8 11169 #define DSC_VER_MIN_SHIFT 4 11170 #define DSC_VER_MAJ (0x1 << 0) 11171 11172 #define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204) 11173 #define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04) 11174 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274 11175 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374 11176 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474 11177 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC 0x78574 11178 #define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11179 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \ 11180 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC) 11181 #define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11182 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \ 11183 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC) 11184 #define DSC_BPP(bpp) ((bpp) << 0) 11185 11186 #define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208) 11187 #define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08) 11188 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278 11189 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378 11190 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478 11191 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC 0x78578 11192 #define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11193 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \ 11194 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC) 11195 #define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11196 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \ 11197 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC) 11198 #define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16) 11199 #define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0) 11200 11201 #define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C) 11202 #define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C) 11203 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C 11204 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C 11205 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C 11206 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC 0x7857C 11207 #define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11208 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \ 11209 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC) 11210 #define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11211 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \ 11212 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC) 11213 #define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16) 11214 #define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0) 11215 11216 #define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210) 11217 #define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10) 11218 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280 11219 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380 11220 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480 11221 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC 0x78580 11222 #define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11223 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \ 11224 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC) 11225 #define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11226 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \ 11227 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC) 11228 #define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16) 11229 #define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0) 11230 11231 #define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214) 11232 #define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14) 11233 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284 11234 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384 11235 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484 11236 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC 0x78584 11237 #define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11238 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \ 11239 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC) 11240 #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11241 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \ 11242 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC) 11243 #define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16) 11244 #define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0) 11245 11246 #define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218) 11247 #define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18) 11248 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288 11249 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388 11250 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488 11251 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC 0x78588 11252 #define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11253 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \ 11254 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC) 11255 #define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11256 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \ 11257 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC) 11258 #define DSC_FLATNESS_MAX_QP(max_qp) ((max_qp) << 24) 11259 #define DSC_FLATNESS_MIN_QP(min_qp) ((min_qp) << 16) 11260 #define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8) 11261 #define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0) 11262 11263 #define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C) 11264 #define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C) 11265 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C 11266 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C 11267 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C 11268 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC 0x7858C 11269 #define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11270 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \ 11271 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC) 11272 #define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11273 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \ 11274 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC) 11275 #define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16) 11276 #define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0) 11277 11278 #define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220) 11279 #define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20) 11280 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290 11281 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390 11282 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490 11283 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC 0x78590 11284 #define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11285 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \ 11286 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC) 11287 #define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11288 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \ 11289 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC) 11290 #define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16) 11291 #define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0) 11292 11293 #define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224) 11294 #define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24) 11295 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294 11296 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394 11297 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494 11298 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC 0x78594 11299 #define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11300 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \ 11301 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC) 11302 #define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11303 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \ 11304 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC) 11305 #define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16) 11306 #define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0) 11307 11308 #define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228) 11309 #define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28) 11310 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298 11311 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398 11312 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498 11313 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC 0x78598 11314 #define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11315 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \ 11316 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC) 11317 #define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11318 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \ 11319 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC) 11320 #define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low) ((rc_tgt_off_low) << 20) 11321 #define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) ((rc_tgt_off_high) << 16) 11322 #define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8) 11323 #define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0) 11324 11325 #define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C) 11326 #define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C) 11327 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C 11328 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C 11329 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C 11330 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC 0x7859C 11331 #define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11332 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \ 11333 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC) 11334 #define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11335 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \ 11336 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC) 11337 11338 #define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260) 11339 #define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60) 11340 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0 11341 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0 11342 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0 11343 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC 0x785A0 11344 #define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11345 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \ 11346 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC) 11347 #define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11348 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \ 11349 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC) 11350 11351 #define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264) 11352 #define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64) 11353 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4 11354 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4 11355 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4 11356 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC 0x785A4 11357 #define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11358 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \ 11359 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC) 11360 #define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11361 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \ 11362 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC) 11363 11364 #define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268) 11365 #define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68) 11366 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8 11367 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8 11368 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8 11369 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC 0x785A8 11370 #define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11371 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \ 11372 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC) 11373 #define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11374 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \ 11375 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC) 11376 11377 #define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C) 11378 #define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C) 11379 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC 11380 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC 11381 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC 11382 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC 0x785AC 11383 #define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11384 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \ 11385 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC) 11386 #define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11387 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \ 11388 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC) 11389 11390 #define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270) 11391 #define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70) 11392 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0 11393 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0 11394 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0 11395 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC 0x785B0 11396 #define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11397 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \ 11398 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC) 11399 #define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11400 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \ 11401 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC) 11402 #define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame) << 20) 11403 #define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16) 11404 #define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0) 11405 11406 /* Icelake Rate Control Buffer Threshold Registers */ 11407 #define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230) 11408 #define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4) 11409 #define DSCC_RC_BUF_THRESH_0 _MMIO(0x6BA30) 11410 #define DSCC_RC_BUF_THRESH_0_UDW _MMIO(0x6BA30 + 4) 11411 #define _ICL_DSC0_RC_BUF_THRESH_0_PB (0x78254) 11412 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB (0x78254 + 4) 11413 #define _ICL_DSC1_RC_BUF_THRESH_0_PB (0x78354) 11414 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB (0x78354 + 4) 11415 #define _ICL_DSC0_RC_BUF_THRESH_0_PC (0x78454) 11416 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC (0x78454 + 4) 11417 #define _ICL_DSC1_RC_BUF_THRESH_0_PC (0x78554) 11418 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC (0x78554 + 4) 11419 #define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11420 _ICL_DSC0_RC_BUF_THRESH_0_PB, \ 11421 _ICL_DSC0_RC_BUF_THRESH_0_PC) 11422 #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11423 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \ 11424 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC) 11425 #define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11426 _ICL_DSC1_RC_BUF_THRESH_0_PB, \ 11427 _ICL_DSC1_RC_BUF_THRESH_0_PC) 11428 #define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11429 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \ 11430 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC) 11431 11432 #define DSCA_RC_BUF_THRESH_1 _MMIO(0x6B238) 11433 #define DSCA_RC_BUF_THRESH_1_UDW _MMIO(0x6B238 + 4) 11434 #define DSCC_RC_BUF_THRESH_1 _MMIO(0x6BA38) 11435 #define DSCC_RC_BUF_THRESH_1_UDW _MMIO(0x6BA38 + 4) 11436 #define _ICL_DSC0_RC_BUF_THRESH_1_PB (0x7825C) 11437 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB (0x7825C + 4) 11438 #define _ICL_DSC1_RC_BUF_THRESH_1_PB (0x7835C) 11439 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB (0x7835C + 4) 11440 #define _ICL_DSC0_RC_BUF_THRESH_1_PC (0x7845C) 11441 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC (0x7845C + 4) 11442 #define _ICL_DSC1_RC_BUF_THRESH_1_PC (0x7855C) 11443 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC (0x7855C + 4) 11444 #define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11445 _ICL_DSC0_RC_BUF_THRESH_1_PB, \ 11446 _ICL_DSC0_RC_BUF_THRESH_1_PC) 11447 #define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11448 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \ 11449 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC) 11450 #define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11451 _ICL_DSC1_RC_BUF_THRESH_1_PB, \ 11452 _ICL_DSC1_RC_BUF_THRESH_1_PC) 11453 #define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11454 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \ 11455 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC) 11456 11457 #define PORT_TX_DFLEXDPSP _MMIO(FIA1_BASE + 0x008A0) 11458 #define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6)) 11459 #define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5)) 11460 #define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8) 11461 #define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8)) 11462 #define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8)) 11463 11464 #define PORT_TX_DFLEXDPPMS _MMIO(FIA1_BASE + 0x00890) 11465 #define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 << (tc_port)) 11466 11467 #define PORT_TX_DFLEXDPCSSS _MMIO(FIA1_BASE + 0x00894) 11468 #define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port)) 11469 11470 #endif /* _I915_REG_H_ */ 11471