1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 2 * All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef _I915_REG_H_ 26 #define _I915_REG_H_ 27 28 #include "i915_reg_defs.h" 29 #include "display/intel_display_reg_defs.h" 30 31 /** 32 * DOC: The i915 register macro definition style guide 33 * 34 * Follow the style described here for new macros, and while changing existing 35 * macros. Do **not** mass change existing definitions just to update the style. 36 * 37 * File Layout 38 * ~~~~~~~~~~~ 39 * 40 * Keep helper macros near the top. For example, _PIPE() and friends. 41 * 42 * Prefix macros that generally should not be used outside of this file with 43 * underscore '_'. For example, _PIPE() and friends, single instances of 44 * registers that are defined solely for the use by function-like macros. 45 * 46 * Avoid using the underscore prefixed macros outside of this file. There are 47 * exceptions, but keep them to a minimum. 48 * 49 * There are two basic types of register definitions: Single registers and 50 * register groups. Register groups are registers which have two or more 51 * instances, for example one per pipe, port, transcoder, etc. Register groups 52 * should be defined using function-like macros. 53 * 54 * For single registers, define the register offset first, followed by register 55 * contents. 56 * 57 * For register groups, define the register instance offsets first, prefixed 58 * with underscore, followed by a function-like macro choosing the right 59 * instance based on the parameter, followed by register contents. 60 * 61 * Define the register contents (i.e. bit and bit field macros) from most 62 * significant to least significant bit. Indent the register content macros 63 * using two extra spaces between ``#define`` and the macro name. 64 * 65 * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents 66 * using ``REG_FIELD_PREP(mask, value)``. This will define the values already 67 * shifted in place, so they can be directly OR'd together. For convenience, 68 * function-like macros may be used to define bit fields, but do note that the 69 * macros may be needed to read as well as write the register contents. 70 * 71 * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name. 72 * 73 * Group the register and its contents together without blank lines, separate 74 * from other registers and their contents with one blank line. 75 * 76 * Indent macro values from macro names using TABs. Align values vertically. Use 77 * braces in macro values as needed to avoid unintended precedence after macro 78 * substitution. Use spaces in macro values according to kernel coding 79 * style. Use lower case in hexadecimal values. 80 * 81 * Naming 82 * ~~~~~~ 83 * 84 * Try to name registers according to the specs. If the register name changes in 85 * the specs from platform to another, stick to the original name. 86 * 87 * Try to re-use existing register macro definitions. Only add new macros for 88 * new register offsets, or when the register contents have changed enough to 89 * warrant a full redefinition. 90 * 91 * When a register macro changes for a new platform, prefix the new macro using 92 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The 93 * prefix signifies the start platform/generation using the register. 94 * 95 * When a bit (field) macro changes or gets added for a new platform, while 96 * retaining the existing register macro, add a platform acronym or generation 97 * suffix to the name. For example, ``_SKL`` or ``_GEN8``. 98 * 99 * Examples 100 * ~~~~~~~~ 101 * 102 * (Note that the values in the example are indented using spaces instead of 103 * TABs to avoid misalignment in generated documentation. Use TABs in the 104 * definitions.):: 105 * 106 * #define _FOO_A 0xf000 107 * #define _FOO_B 0xf001 108 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B) 109 * #define FOO_ENABLE REG_BIT(31) 110 * #define FOO_MODE_MASK REG_GENMASK(19, 16) 111 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0) 112 * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1) 113 * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2) 114 * 115 * #define BAR _MMIO(0xb000) 116 * #define GEN8_BAR _MMIO(0xb888) 117 */ 118 119 #define GU_CNTL_PROTECTED _MMIO(0x10100C) 120 #define DEPRESENT REG_BIT(9) 121 122 #define GU_CNTL _MMIO(0x101010) 123 #define LMEM_INIT REG_BIT(7) 124 #define DRIVERFLR REG_BIT(31) 125 #define GU_DEBUG _MMIO(0x101018) 126 #define DRIVERFLR_STATUS REG_BIT(31) 127 128 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0) 129 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20) 130 #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18) 131 #define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4) 132 #define GEN6_STOLEN_RESERVED_1M (0 << 4) 133 #define GEN6_STOLEN_RESERVED_512K (1 << 4) 134 #define GEN6_STOLEN_RESERVED_256K (2 << 4) 135 #define GEN6_STOLEN_RESERVED_128K (3 << 4) 136 #define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5) 137 #define GEN7_STOLEN_RESERVED_1M (0 << 5) 138 #define GEN7_STOLEN_RESERVED_256K (1 << 5) 139 #define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7) 140 #define GEN8_STOLEN_RESERVED_1M (0 << 7) 141 #define GEN8_STOLEN_RESERVED_2M (1 << 7) 142 #define GEN8_STOLEN_RESERVED_4M (2 << 7) 143 #define GEN8_STOLEN_RESERVED_8M (3 << 7) 144 #define GEN6_STOLEN_RESERVED_ENABLE (1 << 0) 145 #define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20) 146 147 #define _VGA_MSR_WRITE _MMIO(0x3c2) 148 149 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 150 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 151 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL) 152 153 /* 154 * Reset registers 155 */ 156 #define DEBUG_RESET_I830 _MMIO(0x6070) 157 #define DEBUG_RESET_FULL (1 << 7) 158 #define DEBUG_RESET_RENDER (1 << 8) 159 #define DEBUG_RESET_DISPLAY (1 << 9) 160 161 /* 162 * IOSF sideband 163 */ 164 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100) 165 #define IOSF_DEVFN_SHIFT 24 166 #define IOSF_OPCODE_SHIFT 16 167 #define IOSF_PORT_SHIFT 8 168 #define IOSF_BYTE_ENABLES_SHIFT 4 169 #define IOSF_BAR_SHIFT 1 170 #define IOSF_SB_BUSY (1 << 0) 171 #define IOSF_PORT_BUNIT 0x03 172 #define IOSF_PORT_PUNIT 0x04 173 #define IOSF_PORT_NC 0x11 174 #define IOSF_PORT_DPIO 0x12 175 #define IOSF_PORT_GPIO_NC 0x13 176 #define IOSF_PORT_CCK 0x14 177 #define IOSF_PORT_DPIO_2 0x1a 178 #define IOSF_PORT_FLISDSI 0x1b 179 #define IOSF_PORT_GPIO_SC 0x48 180 #define IOSF_PORT_GPIO_SUS 0xa8 181 #define IOSF_PORT_CCU 0xa9 182 #define CHV_IOSF_PORT_GPIO_N 0x13 183 #define CHV_IOSF_PORT_GPIO_SE 0x48 184 #define CHV_IOSF_PORT_GPIO_E 0xa8 185 #define CHV_IOSF_PORT_GPIO_SW 0xb2 186 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104) 187 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108) 188 189 /* DPIO registers */ 190 #define DPIO_DEVFN 0 191 192 #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110) 193 #define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */ 194 #define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */ 195 #define DPIO_SFR_BYPASS (1 << 1) 196 #define DPIO_CMNRST (1 << 0) 197 198 /* 199 * Per pipe/PLL DPIO regs 200 */ 201 #define _VLV_PLL_DW3_CH0 0x800c 202 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ 203 #define DPIO_POST_DIV_DAC 0 204 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ 205 #define DPIO_POST_DIV_LVDS1 2 206 #define DPIO_POST_DIV_LVDS2 3 207 #define DPIO_K_SHIFT (24) /* 4 bits */ 208 #define DPIO_P1_SHIFT (21) /* 3 bits */ 209 #define DPIO_P2_SHIFT (16) /* 5 bits */ 210 #define DPIO_N_SHIFT (12) /* 4 bits */ 211 #define DPIO_ENABLE_CALIBRATION (1 << 11) 212 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ 213 #define DPIO_M2DIV_MASK 0xff 214 #define _VLV_PLL_DW3_CH1 0x802c 215 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1) 216 217 #define _VLV_PLL_DW5_CH0 0x8014 218 #define DPIO_REFSEL_OVERRIDE 27 219 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ 220 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ 221 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ 222 #define DPIO_PLL_REFCLK_SEL_MASK 3 223 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ 224 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ 225 #define _VLV_PLL_DW5_CH1 0x8034 226 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1) 227 228 #define _VLV_PLL_DW7_CH0 0x801c 229 #define _VLV_PLL_DW7_CH1 0x803c 230 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1) 231 232 #define _VLV_PLL_DW8_CH0 0x8040 233 #define _VLV_PLL_DW8_CH1 0x8060 234 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1) 235 236 #define VLV_PLL_DW9_BCAST 0xc044 237 #define _VLV_PLL_DW9_CH0 0x8044 238 #define _VLV_PLL_DW9_CH1 0x8064 239 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1) 240 241 #define _VLV_PLL_DW10_CH0 0x8048 242 #define _VLV_PLL_DW10_CH1 0x8068 243 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1) 244 245 #define _VLV_PLL_DW11_CH0 0x804c 246 #define _VLV_PLL_DW11_CH1 0x806c 247 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1) 248 249 /* Spec for ref block start counts at DW10 */ 250 #define VLV_REF_DW13 0x80ac 251 252 #define VLV_CMN_DW0 0x8100 253 254 /* 255 * Per DDI channel DPIO regs 256 */ 257 258 #define _VLV_PCS_DW0_CH0 0x8200 259 #define _VLV_PCS_DW0_CH1 0x8400 260 #define DPIO_PCS_TX_LANE2_RESET (1 << 16) 261 #define DPIO_PCS_TX_LANE1_RESET (1 << 7) 262 #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4) 263 #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3) 264 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1) 265 266 #define _VLV_PCS01_DW0_CH0 0x200 267 #define _VLV_PCS23_DW0_CH0 0x400 268 #define _VLV_PCS01_DW0_CH1 0x2600 269 #define _VLV_PCS23_DW0_CH1 0x2800 270 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1) 271 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1) 272 273 #define _VLV_PCS_DW1_CH0 0x8204 274 #define _VLV_PCS_DW1_CH1 0x8404 275 #define CHV_PCS_REQ_SOFTRESET_EN (1 << 23) 276 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22) 277 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21) 278 #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) 279 #define DPIO_PCS_CLK_SOFT_RESET (1 << 5) 280 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1) 281 282 #define _VLV_PCS01_DW1_CH0 0x204 283 #define _VLV_PCS23_DW1_CH0 0x404 284 #define _VLV_PCS01_DW1_CH1 0x2604 285 #define _VLV_PCS23_DW1_CH1 0x2804 286 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1) 287 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1) 288 289 #define _VLV_PCS_DW8_CH0 0x8220 290 #define _VLV_PCS_DW8_CH1 0x8420 291 #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20) 292 #define CHV_PCS_USEDCLKCHANNEL (1 << 21) 293 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1) 294 295 #define _VLV_PCS01_DW8_CH0 0x0220 296 #define _VLV_PCS23_DW8_CH0 0x0420 297 #define _VLV_PCS01_DW8_CH1 0x2620 298 #define _VLV_PCS23_DW8_CH1 0x2820 299 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1) 300 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1) 301 302 #define _VLV_PCS_DW9_CH0 0x8224 303 #define _VLV_PCS_DW9_CH1 0x8424 304 #define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13) 305 #define DPIO_PCS_TX2MARGIN_000 (0 << 13) 306 #define DPIO_PCS_TX2MARGIN_101 (1 << 13) 307 #define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10) 308 #define DPIO_PCS_TX1MARGIN_000 (0 << 10) 309 #define DPIO_PCS_TX1MARGIN_101 (1 << 10) 310 #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1) 311 312 #define _VLV_PCS01_DW9_CH0 0x224 313 #define _VLV_PCS23_DW9_CH0 0x424 314 #define _VLV_PCS01_DW9_CH1 0x2624 315 #define _VLV_PCS23_DW9_CH1 0x2824 316 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1) 317 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1) 318 319 #define _CHV_PCS_DW10_CH0 0x8228 320 #define _CHV_PCS_DW10_CH1 0x8428 321 #define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30) 322 #define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31) 323 #define DPIO_PCS_TX2DEEMP_MASK (0xf << 24) 324 #define DPIO_PCS_TX2DEEMP_9P5 (0 << 24) 325 #define DPIO_PCS_TX2DEEMP_6P0 (2 << 24) 326 #define DPIO_PCS_TX1DEEMP_MASK (0xf << 16) 327 #define DPIO_PCS_TX1DEEMP_9P5 (0 << 16) 328 #define DPIO_PCS_TX1DEEMP_6P0 (2 << 16) 329 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1) 330 331 #define _VLV_PCS01_DW10_CH0 0x0228 332 #define _VLV_PCS23_DW10_CH0 0x0428 333 #define _VLV_PCS01_DW10_CH1 0x2628 334 #define _VLV_PCS23_DW10_CH1 0x2828 335 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1) 336 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1) 337 338 #define _VLV_PCS_DW11_CH0 0x822c 339 #define _VLV_PCS_DW11_CH1 0x842c 340 #define DPIO_TX2_STAGGER_MASK(x) ((x) << 24) 341 #define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3) 342 #define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1) 343 #define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0) 344 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1) 345 346 #define _VLV_PCS01_DW11_CH0 0x022c 347 #define _VLV_PCS23_DW11_CH0 0x042c 348 #define _VLV_PCS01_DW11_CH1 0x262c 349 #define _VLV_PCS23_DW11_CH1 0x282c 350 #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1) 351 #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1) 352 353 #define _VLV_PCS01_DW12_CH0 0x0230 354 #define _VLV_PCS23_DW12_CH0 0x0430 355 #define _VLV_PCS01_DW12_CH1 0x2630 356 #define _VLV_PCS23_DW12_CH1 0x2830 357 #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1) 358 #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1) 359 360 #define _VLV_PCS_DW12_CH0 0x8230 361 #define _VLV_PCS_DW12_CH1 0x8430 362 #define DPIO_TX2_STAGGER_MULT(x) ((x) << 20) 363 #define DPIO_TX1_STAGGER_MULT(x) ((x) << 16) 364 #define DPIO_TX1_STAGGER_MASK(x) ((x) << 8) 365 #define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6) 366 #define DPIO_LANESTAGGER_STRAP(x) ((x) << 0) 367 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1) 368 369 #define _VLV_PCS_DW14_CH0 0x8238 370 #define _VLV_PCS_DW14_CH1 0x8438 371 #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1) 372 373 #define _VLV_PCS_DW23_CH0 0x825c 374 #define _VLV_PCS_DW23_CH1 0x845c 375 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1) 376 377 #define _VLV_TX_DW2_CH0 0x8288 378 #define _VLV_TX_DW2_CH1 0x8488 379 #define DPIO_SWING_MARGIN000_SHIFT 16 380 #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT) 381 #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8 382 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1) 383 384 #define _VLV_TX_DW3_CH0 0x828c 385 #define _VLV_TX_DW3_CH1 0x848c 386 /* The following bit for CHV phy */ 387 #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27) 388 #define DPIO_SWING_MARGIN101_SHIFT 16 389 #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT) 390 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1) 391 392 #define _VLV_TX_DW4_CH0 0x8290 393 #define _VLV_TX_DW4_CH1 0x8490 394 #define DPIO_SWING_DEEMPH9P5_SHIFT 24 395 #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT) 396 #define DPIO_SWING_DEEMPH6P0_SHIFT 16 397 #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT) 398 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1) 399 400 #define _VLV_TX3_DW4_CH0 0x690 401 #define _VLV_TX3_DW4_CH1 0x2a90 402 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1) 403 404 #define _VLV_TX_DW5_CH0 0x8294 405 #define _VLV_TX_DW5_CH1 0x8494 406 #define DPIO_TX_OCALINIT_EN (1 << 31) 407 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1) 408 409 #define _VLV_TX_DW11_CH0 0x82ac 410 #define _VLV_TX_DW11_CH1 0x84ac 411 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1) 412 413 #define _VLV_TX_DW14_CH0 0x82b8 414 #define _VLV_TX_DW14_CH1 0x84b8 415 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1) 416 417 /* CHV dpPhy registers */ 418 #define _CHV_PLL_DW0_CH0 0x8000 419 #define _CHV_PLL_DW0_CH1 0x8180 420 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1) 421 422 #define _CHV_PLL_DW1_CH0 0x8004 423 #define _CHV_PLL_DW1_CH1 0x8184 424 #define DPIO_CHV_N_DIV_SHIFT 8 425 #define DPIO_CHV_M1_DIV_BY_2 (0 << 0) 426 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1) 427 428 #define _CHV_PLL_DW2_CH0 0x8008 429 #define _CHV_PLL_DW2_CH1 0x8188 430 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1) 431 432 #define _CHV_PLL_DW3_CH0 0x800c 433 #define _CHV_PLL_DW3_CH1 0x818c 434 #define DPIO_CHV_FRAC_DIV_EN (1 << 16) 435 #define DPIO_CHV_FIRST_MOD (0 << 8) 436 #define DPIO_CHV_SECOND_MOD (1 << 8) 437 #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0 438 #define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0) 439 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1) 440 441 #define _CHV_PLL_DW6_CH0 0x8018 442 #define _CHV_PLL_DW6_CH1 0x8198 443 #define DPIO_CHV_GAIN_CTRL_SHIFT 16 444 #define DPIO_CHV_INT_COEFF_SHIFT 8 445 #define DPIO_CHV_PROP_COEFF_SHIFT 0 446 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1) 447 448 #define _CHV_PLL_DW8_CH0 0x8020 449 #define _CHV_PLL_DW8_CH1 0x81A0 450 #define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0 451 #define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0) 452 #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1) 453 454 #define _CHV_PLL_DW9_CH0 0x8024 455 #define _CHV_PLL_DW9_CH1 0x81A4 456 #define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */ 457 #define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1) 458 #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */ 459 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1) 460 461 #define _CHV_CMN_DW0_CH0 0x8100 462 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19 463 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18 464 #define DPIO_ALLDL_POWERDOWN (1 << 1) 465 #define DPIO_ANYDL_POWERDOWN (1 << 0) 466 467 #define _CHV_CMN_DW5_CH0 0x8114 468 #define CHV_BUFRIGHTENA1_DISABLE (0 << 20) 469 #define CHV_BUFRIGHTENA1_NORMAL (1 << 20) 470 #define CHV_BUFRIGHTENA1_FORCE (3 << 20) 471 #define CHV_BUFRIGHTENA1_MASK (3 << 20) 472 #define CHV_BUFLEFTENA1_DISABLE (0 << 22) 473 #define CHV_BUFLEFTENA1_NORMAL (1 << 22) 474 #define CHV_BUFLEFTENA1_FORCE (3 << 22) 475 #define CHV_BUFLEFTENA1_MASK (3 << 22) 476 477 #define _CHV_CMN_DW13_CH0 0x8134 478 #define _CHV_CMN_DW0_CH1 0x8080 479 #define DPIO_CHV_S1_DIV_SHIFT 21 480 #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */ 481 #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */ 482 #define DPIO_CHV_K_DIV_SHIFT 4 483 #define DPIO_PLL_FREQLOCK (1 << 1) 484 #define DPIO_PLL_LOCK (1 << 0) 485 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1) 486 487 #define _CHV_CMN_DW14_CH0 0x8138 488 #define _CHV_CMN_DW1_CH1 0x8084 489 #define DPIO_AFC_RECAL (1 << 14) 490 #define DPIO_DCLKP_EN (1 << 13) 491 #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */ 492 #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */ 493 #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */ 494 #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */ 495 #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */ 496 #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */ 497 #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */ 498 #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */ 499 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1) 500 501 #define _CHV_CMN_DW19_CH0 0x814c 502 #define _CHV_CMN_DW6_CH1 0x8098 503 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */ 504 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */ 505 #define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */ 506 #define CHV_CMN_USEDCLKCHANNEL (1 << 13) 507 508 #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1) 509 510 #define CHV_CMN_DW28 0x8170 511 #define DPIO_CL1POWERDOWNEN (1 << 23) 512 #define DPIO_DYNPWRDOWNEN_CH0 (1 << 22) 513 #define DPIO_SUS_CLK_CONFIG_ON (0 << 0) 514 #define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0) 515 #define DPIO_SUS_CLK_CONFIG_GATE (2 << 0) 516 #define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0) 517 518 #define CHV_CMN_DW30 0x8178 519 #define DPIO_CL2_LDOFUSE_PWRENB (1 << 6) 520 #define DPIO_LRC_BYPASS (1 << 3) 521 522 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \ 523 (lane) * 0x200 + (offset)) 524 525 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80) 526 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84) 527 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88) 528 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c) 529 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90) 530 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94) 531 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98) 532 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c) 533 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0) 534 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4) 535 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8) 536 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac) 537 #define DPIO_FRC_LATENCY_SHFIT 8 538 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8) 539 #define DPIO_UPAR_SHIFT 30 540 541 #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090) 542 #define MIPIO_RST_CTRL (1 << 2) 543 544 #define _BXT_PHY_CTL_DDI_A 0x64C00 545 #define _BXT_PHY_CTL_DDI_B 0x64C10 546 #define _BXT_PHY_CTL_DDI_C 0x64C20 547 #define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10) 548 #define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9) 549 #define BXT_PHY_LANE_ENABLED (1 << 8) 550 #define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \ 551 _BXT_PHY_CTL_DDI_B) 552 553 #define _PHY_CTL_FAMILY_DDI 0x64C90 554 #define _PHY_CTL_FAMILY_EDP 0x64C80 555 #define _PHY_CTL_FAMILY_DDI_C 0x64CA0 556 #define COMMON_RESET_DIS (1 << 31) 557 #define BXT_PHY_CTL_FAMILY(phy) \ 558 _MMIO(_PICK_EVEN_2RANGES(phy, 1, \ 559 _PHY_CTL_FAMILY_DDI, _PHY_CTL_FAMILY_DDI, \ 560 _PHY_CTL_FAMILY_EDP, _PHY_CTL_FAMILY_DDI_C)) 561 562 /* UAIMI scratch pad register 1 */ 563 #define UAIMI_SPR1 _MMIO(0x4F074) 564 /* SKL VccIO mask */ 565 #define SKL_VCCIO_MASK 0x1 566 /* SKL balance leg register */ 567 #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C) 568 /* I_boost values */ 569 #define BALANCE_LEG_SHIFT(port) (8 + 3 * (port)) 570 #define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port))) 571 /* Balance leg disable bits */ 572 #define BALANCE_LEG_DISABLE_SHIFT 23 573 #define BALANCE_LEG_DISABLE(port) (1 << (23 + (port))) 574 575 /* 576 * Fence registers 577 * [0-7] @ 0x2000 gen2,gen3 578 * [8-15] @ 0x3000 945,g33,pnv 579 * 580 * [0-15] @ 0x3000 gen4,gen5 581 * 582 * [0-15] @ 0x100000 gen6,vlv,chv 583 * [0-31] @ 0x100000 gen7+ 584 */ 585 #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4) 586 #define I830_FENCE_START_MASK 0x07f80000 587 #define I830_FENCE_TILING_Y_SHIFT 12 588 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 589 #define I830_FENCE_PITCH_SHIFT 4 590 #define I830_FENCE_REG_VALID (1 << 0) 591 #define I915_FENCE_MAX_PITCH_VAL 4 592 #define I830_FENCE_MAX_PITCH_VAL 6 593 #define I830_FENCE_MAX_SIZE_VAL (1 << 8) 594 595 #define I915_FENCE_START_MASK 0x0ff00000 596 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) 597 598 #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8) 599 #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4) 600 #define I965_FENCE_PITCH_SHIFT 2 601 #define I965_FENCE_TILING_Y_SHIFT 1 602 #define I965_FENCE_REG_VALID (1 << 0) 603 #define I965_FENCE_MAX_PITCH_VAL 0x0400 604 605 #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8) 606 #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4) 607 #define GEN6_FENCE_PITCH_SHIFT 32 608 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 609 610 611 /* control register for cpu gtt access */ 612 #define TILECTL _MMIO(0x101000) 613 #define TILECTL_SWZCTL (1 << 0) 614 #define TILECTL_TLBPF (1 << 1) 615 #define TILECTL_TLB_PREFETCH_DIS (1 << 2) 616 #define TILECTL_BACKSNOOP_DIS (1 << 3) 617 618 /* 619 * Instruction and interrupt control regs 620 */ 621 #define PGTBL_CTL _MMIO(0x02020) 622 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ 623 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ 624 #define PGTBL_ER _MMIO(0x02024) 625 #define PRB0_BASE (0x2030 - 0x30) 626 #define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */ 627 #define PRB2_BASE (0x2050 - 0x30) /* gen3 */ 628 #define SRB0_BASE (0x2100 - 0x30) /* gen2 */ 629 #define SRB1_BASE (0x2110 - 0x30) /* gen2 */ 630 #define SRB2_BASE (0x2120 - 0x30) /* 830 */ 631 #define SRB3_BASE (0x2130 - 0x30) /* 830 */ 632 #define RENDER_RING_BASE 0x02000 633 #define BSD_RING_BASE 0x04000 634 #define GEN6_BSD_RING_BASE 0x12000 635 #define GEN8_BSD2_RING_BASE 0x1c000 636 #define GEN11_BSD_RING_BASE 0x1c0000 637 #define GEN11_BSD2_RING_BASE 0x1c4000 638 #define GEN11_BSD3_RING_BASE 0x1d0000 639 #define GEN11_BSD4_RING_BASE 0x1d4000 640 #define XEHP_BSD5_RING_BASE 0x1e0000 641 #define XEHP_BSD6_RING_BASE 0x1e4000 642 #define XEHP_BSD7_RING_BASE 0x1f0000 643 #define XEHP_BSD8_RING_BASE 0x1f4000 644 #define VEBOX_RING_BASE 0x1a000 645 #define GEN11_VEBOX_RING_BASE 0x1c8000 646 #define GEN11_VEBOX2_RING_BASE 0x1d8000 647 #define XEHP_VEBOX3_RING_BASE 0x1e8000 648 #define XEHP_VEBOX4_RING_BASE 0x1f8000 649 #define MTL_GSC_RING_BASE 0x11a000 650 #define GEN12_COMPUTE0_RING_BASE 0x1a000 651 #define GEN12_COMPUTE1_RING_BASE 0x1c000 652 #define GEN12_COMPUTE2_RING_BASE 0x1e000 653 #define GEN12_COMPUTE3_RING_BASE 0x26000 654 #define BLT_RING_BASE 0x22000 655 #define XEHPC_BCS1_RING_BASE 0x3e0000 656 #define XEHPC_BCS2_RING_BASE 0x3e2000 657 #define XEHPC_BCS3_RING_BASE 0x3e4000 658 #define XEHPC_BCS4_RING_BASE 0x3e6000 659 #define XEHPC_BCS5_RING_BASE 0x3e8000 660 #define XEHPC_BCS6_RING_BASE 0x3ea000 661 #define XEHPC_BCS7_RING_BASE 0x3ec000 662 #define XEHPC_BCS8_RING_BASE 0x3ee000 663 #define DG1_GSC_HECI1_BASE 0x00258000 664 #define DG1_GSC_HECI2_BASE 0x00259000 665 #define DG2_GSC_HECI1_BASE 0x00373000 666 #define DG2_GSC_HECI2_BASE 0x00374000 667 #define MTL_GSC_HECI1_BASE 0x00116000 668 #define MTL_GSC_HECI2_BASE 0x00117000 669 670 #define HECI_H_CSR(base) _MMIO((base) + 0x4) 671 #define HECI_H_CSR_IE REG_BIT(0) 672 #define HECI_H_CSR_IS REG_BIT(1) 673 #define HECI_H_CSR_IG REG_BIT(2) 674 #define HECI_H_CSR_RDY REG_BIT(3) 675 #define HECI_H_CSR_RST REG_BIT(4) 676 677 #define HECI_H_GS1(base) _MMIO((base) + 0xc4c) 678 #define HECI_H_GS1_ER_PREP REG_BIT(0) 679 680 /* 681 * The FWSTS register values are FW defined and can be different between 682 * HECI1 and HECI2 683 */ 684 #define HECI_FWSTS1 0xc40 685 #define HECI1_FWSTS1_CURRENT_STATE REG_GENMASK(3, 0) 686 #define HECI1_FWSTS1_CURRENT_STATE_RESET 0 687 #define HECI1_FWSTS1_PROXY_STATE_NORMAL 5 688 #define HECI1_FWSTS1_INIT_COMPLETE REG_BIT(9) 689 #define HECI_FWSTS2 0xc48 690 #define HECI_FWSTS3 0xc60 691 #define HECI_FWSTS4 0xc64 692 #define HECI_FWSTS5 0xc68 693 #define HECI1_FWSTS5_HUC_AUTH_DONE (1 << 19) 694 #define HECI_FWSTS6 0xc6c 695 696 /* the FWSTS regs are 1-based, so we use -base for index 0 to get an invalid reg */ 697 #define HECI_FWSTS(base, x) _MMIO((base) + _PICK(x, -(base), \ 698 HECI_FWSTS1, \ 699 HECI_FWSTS2, \ 700 HECI_FWSTS3, \ 701 HECI_FWSTS4, \ 702 HECI_FWSTS5, \ 703 HECI_FWSTS6)) 704 705 #define HSW_GTT_CACHE_EN _MMIO(0x4024) 706 #define GTT_CACHE_EN_ALL 0xF0007FFF 707 #define GEN7_WR_WATERMARK _MMIO(0x4028) 708 #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C) 709 #define ARB_MODE _MMIO(0x4030) 710 #define ARB_MODE_SWIZZLE_SNB (1 << 4) 711 #define ARB_MODE_SWIZZLE_IVB (1 << 5) 712 #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034) 713 #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038) 714 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ 715 #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4) 716 #define GEN7_LRA_LIMITS_REG_NUM 13 717 #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070) 718 #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074) 719 720 #define GEN7_ERR_INT _MMIO(0x44040) 721 #define ERR_INT_POISON (1 << 31) 722 #define ERR_INT_MMIO_UNCLAIMED (1 << 13) 723 #define ERR_INT_PIPE_CRC_DONE_C (1 << 8) 724 #define ERR_INT_FIFO_UNDERRUN_C (1 << 6) 725 #define ERR_INT_PIPE_CRC_DONE_B (1 << 5) 726 #define ERR_INT_FIFO_UNDERRUN_B (1 << 3) 727 #define ERR_INT_PIPE_CRC_DONE_A (1 << 2) 728 #define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3)) 729 #define ERR_INT_FIFO_UNDERRUN_A (1 << 0) 730 #define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) 731 732 #define FPGA_DBG _MMIO(0x42300) 733 #define FPGA_DBG_RM_NOCLAIM REG_BIT(31) 734 735 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028) 736 #define CLAIM_ER_CLR REG_BIT(31) 737 #define CLAIM_ER_OVERFLOW REG_BIT(16) 738 #define CLAIM_ER_CTR_MASK REG_GENMASK(15, 0) 739 740 #define DERRMR _MMIO(0x44050) 741 /* Note that HBLANK events are reserved on bdw+ */ 742 #define DERRMR_PIPEA_SCANLINE (1 << 0) 743 #define DERRMR_PIPEA_PRI_FLIP_DONE (1 << 1) 744 #define DERRMR_PIPEA_SPR_FLIP_DONE (1 << 2) 745 #define DERRMR_PIPEA_VBLANK (1 << 3) 746 #define DERRMR_PIPEA_HBLANK (1 << 5) 747 #define DERRMR_PIPEB_SCANLINE (1 << 8) 748 #define DERRMR_PIPEB_PRI_FLIP_DONE (1 << 9) 749 #define DERRMR_PIPEB_SPR_FLIP_DONE (1 << 10) 750 #define DERRMR_PIPEB_VBLANK (1 << 11) 751 #define DERRMR_PIPEB_HBLANK (1 << 13) 752 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */ 753 #define DERRMR_PIPEC_SCANLINE (1 << 14) 754 #define DERRMR_PIPEC_PRI_FLIP_DONE (1 << 15) 755 #define DERRMR_PIPEC_SPR_FLIP_DONE (1 << 20) 756 #define DERRMR_PIPEC_VBLANK (1 << 21) 757 #define DERRMR_PIPEC_HBLANK (1 << 22) 758 759 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030) 760 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034) 761 #define SCPD0 _MMIO(0x209c) /* 915+ only */ 762 #define SCPD_FBC_IGNORE_3D (1 << 6) 763 #define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5) 764 #define GEN2_IER _MMIO(0x20a0) 765 #define GEN2_IIR _MMIO(0x20a4) 766 #define GEN2_IMR _MMIO(0x20a8) 767 #define GEN2_ISR _MMIO(0x20ac) 768 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060) 769 #define GINT_DIS (1 << 22) 770 #define GCFG_DIS (1 << 8) 771 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064) 772 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084) 773 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0) 774 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4) 775 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8) 776 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac) 777 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120) 778 #define VLV_PCBR_ADDR_SHIFT 12 779 780 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */ 781 #define EIR _MMIO(0x20b0) 782 #define EMR _MMIO(0x20b4) 783 #define ESR _MMIO(0x20b8) 784 #define GM45_ERROR_PAGE_TABLE (1 << 5) 785 #define GM45_ERROR_MEM_PRIV (1 << 4) 786 #define I915_ERROR_PAGE_TABLE (1 << 4) 787 #define GM45_ERROR_CP_PRIV (1 << 3) 788 #define I915_ERROR_MEMORY_REFRESH (1 << 1) 789 #define I915_ERROR_INSTRUCTION (1 << 0) 790 #define INSTPM _MMIO(0x20c0) 791 #define INSTPM_SELF_EN (1 << 12) /* 915GM only */ 792 #define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts 793 will not assert AGPBUSY# and will only 794 be delivered when out of C3. */ 795 #define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */ 796 #define INSTPM_TLB_INVALIDATE (1 << 9) 797 #define INSTPM_SYNC_FLUSH (1 << 5) 798 #define MEM_MODE _MMIO(0x20cc) 799 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */ 800 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */ 801 #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */ 802 #define FW_BLC _MMIO(0x20d8) 803 #define FW_BLC2 _MMIO(0x20dc) 804 #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */ 805 #define FW_BLC_SELF_EN_MASK (1 << 31) 806 #define FW_BLC_SELF_FIFO_MASK (1 << 16) /* 945 only */ 807 #define FW_BLC_SELF_EN (1 << 15) /* 945 only */ 808 #define MM_BURST_LENGTH 0x00700000 809 #define MM_FIFO_WATERMARK 0x0001F000 810 #define LM_BURST_LENGTH 0x00000700 811 #define LM_FIFO_WATERMARK 0x0000001F 812 #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */ 813 814 #define _MBUS_ABOX0_CTL 0x45038 815 #define _MBUS_ABOX1_CTL 0x45048 816 #define _MBUS_ABOX2_CTL 0x4504C 817 #define MBUS_ABOX_CTL(x) \ 818 _MMIO(_PICK_EVEN_2RANGES(x, 2, \ 819 _MBUS_ABOX0_CTL, _MBUS_ABOX1_CTL, \ 820 _MBUS_ABOX2_CTL, _MBUS_ABOX2_CTL)) 821 822 #define MBUS_ABOX_BW_CREDIT_MASK (3 << 20) 823 #define MBUS_ABOX_BW_CREDIT(x) ((x) << 20) 824 #define MBUS_ABOX_B_CREDIT_MASK (0xF << 16) 825 #define MBUS_ABOX_B_CREDIT(x) ((x) << 16) 826 #define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8) 827 #define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8) 828 #define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0) 829 #define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0) 830 831 /* Make render/texture TLB fetches lower priorty than associated data 832 * fetches. This is not turned on by default 833 */ 834 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) 835 836 /* Isoch request wait on GTT enable (Display A/B/C streams). 837 * Make isoch requests stall on the TLB update. May cause 838 * display underruns (test mode only) 839 */ 840 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) 841 842 /* Block grant count for isoch requests when block count is 843 * set to a finite value. 844 */ 845 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) 846 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ 847 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ 848 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ 849 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ 850 851 /* Enable render writes to complete in C2/C3/C4 power states. 852 * If this isn't enabled, render writes are prevented in low 853 * power states. That seems bad to me. 854 */ 855 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) 856 857 /* This acknowledges an async flip immediately instead 858 * of waiting for 2TLB fetches. 859 */ 860 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) 861 862 /* Enables non-sequential data reads through arbiter 863 */ 864 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) 865 866 /* Disable FSB snooping of cacheable write cycles from binner/render 867 * command stream 868 */ 869 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) 870 871 /* Arbiter time slice for non-isoch streams */ 872 #define MI_ARB_TIME_SLICE_MASK (7 << 5) 873 #define MI_ARB_TIME_SLICE_1 (0 << 5) 874 #define MI_ARB_TIME_SLICE_2 (1 << 5) 875 #define MI_ARB_TIME_SLICE_4 (2 << 5) 876 #define MI_ARB_TIME_SLICE_6 (3 << 5) 877 #define MI_ARB_TIME_SLICE_8 (4 << 5) 878 #define MI_ARB_TIME_SLICE_10 (5 << 5) 879 #define MI_ARB_TIME_SLICE_14 (6 << 5) 880 #define MI_ARB_TIME_SLICE_16 (7 << 5) 881 882 /* Low priority grace period page size */ 883 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ 884 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) 885 886 /* Disable display A/B trickle feed */ 887 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) 888 889 /* Set display plane priority */ 890 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ 891 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ 892 893 #define MI_STATE _MMIO(0x20e4) /* gen2 only */ 894 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */ 895 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */ 896 897 /* On modern GEN architectures interrupt control consists of two sets 898 * of registers. The first set pertains to the ring generating the 899 * interrupt. The second control is for the functional block generating the 900 * interrupt. These are PM, GT, DE, etc. 901 * 902 * Luckily *knocks on wood* all the ring interrupt bits match up with the 903 * GT interrupt bits, so we don't need to duplicate the defines. 904 * 905 * These defines should cover us well from SNB->HSW with minor exceptions 906 * it can also work on ILK. 907 */ 908 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) 909 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25) 910 #define GT_BLT_USER_INTERRUPT (1 << 22) 911 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15) 912 #define GT_BSD_USER_INTERRUPT (1 << 12) 913 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */ 914 #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) /* bdw+ */ 915 #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8) 916 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */ 917 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) 918 #define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3) 919 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2) 920 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1) 921 #define GT_RENDER_USER_INTERRUPT (1 << 0) 922 923 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */ 924 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */ 925 926 #define GT_PARITY_ERROR(dev_priv) \ 927 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \ 928 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0)) 929 930 /* These are all the "old" interrupts */ 931 #define ILK_BSD_USER_INTERRUPT (1 << 5) 932 933 #define I915_PM_INTERRUPT (1 << 31) 934 #define I915_ISP_INTERRUPT (1 << 22) 935 #define I915_LPE_PIPE_B_INTERRUPT (1 << 21) 936 #define I915_LPE_PIPE_A_INTERRUPT (1 << 20) 937 #define I915_MIPIC_INTERRUPT (1 << 19) 938 #define I915_MIPIA_INTERRUPT (1 << 18) 939 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18) 940 #define I915_DISPLAY_PORT_INTERRUPT (1 << 17) 941 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16) 942 #define I915_MASTER_ERROR_INTERRUPT (1 << 15) 943 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14) 944 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */ 945 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13) 946 #define I915_HWB_OOM_INTERRUPT (1 << 13) 947 #define I915_LPE_PIPE_C_INTERRUPT (1 << 12) 948 #define I915_SYNC_STATUS_INTERRUPT (1 << 12) 949 #define I915_MISC_INTERRUPT (1 << 11) 950 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11) 951 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10) 952 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10) 953 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9) 954 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9) 955 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8) 956 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8) 957 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7) 958 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6) 959 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5) 960 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4) 961 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3) 962 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2) 963 #define I915_DEBUG_INTERRUPT (1 << 2) 964 #define I915_WINVALID_INTERRUPT (1 << 1) 965 #define I915_USER_INTERRUPT (1 << 1) 966 #define I915_ASLE_INTERRUPT (1 << 0) 967 #define I915_BSD_USER_INTERRUPT (1 << 25) 968 969 #define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000) 970 #define I915_HDMI_LPE_AUDIO_SIZE 0x1000 971 972 /* DisplayPort Audio w/ LPE */ 973 #define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38) 974 #define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0) 975 976 #define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20) 977 #define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30) 978 #define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34) 979 #define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \ 980 _VLV_AUD_PORT_EN_B_DBG, \ 981 _VLV_AUD_PORT_EN_C_DBG, \ 982 _VLV_AUD_PORT_EN_D_DBG) 983 #define VLV_AMP_MUTE (1 << 1) 984 985 #define GEN6_BSD_RNCID _MMIO(0x12198) 986 987 #define GEN7_FF_THREAD_MODE _MMIO(0x20a0) 988 #define GEN7_FF_SCHED_MASK 0x0077070 989 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19) 990 #define GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19) 991 #define GEN7_FF_TS_SCHED_HS1 (0x5 << 16) 992 #define GEN7_FF_TS_SCHED_HS0 (0x3 << 16) 993 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16) 994 #define GEN7_FF_TS_SCHED_HW (0x0 << 16) /* Default */ 995 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15) 996 #define GEN7_FF_VS_SCHED_HS1 (0x5 << 12) 997 #define GEN7_FF_VS_SCHED_HS0 (0x3 << 12) 998 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */ 999 #define GEN7_FF_VS_SCHED_HW (0x0 << 12) 1000 #define GEN7_FF_DS_SCHED_HS1 (0x5 << 4) 1001 #define GEN7_FF_DS_SCHED_HS0 (0x3 << 4) 1002 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */ 1003 #define GEN7_FF_DS_SCHED_HW (0x0 << 4) 1004 1005 /* 1006 * Framebuffer compression (915+ only) 1007 */ 1008 1009 #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */ 1010 #define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */ 1011 #define FBC_CONTROL _MMIO(0x3208) 1012 #define FBC_CTL_EN REG_BIT(31) 1013 #define FBC_CTL_PERIODIC REG_BIT(30) 1014 #define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16) 1015 #define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x)) 1016 #define FBC_CTL_STOP_ON_MOD REG_BIT(15) 1017 #define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */ 1018 #define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm only */ 1019 #define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5) 1020 #define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x)) 1021 #define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0) 1022 #define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x)) 1023 #define FBC_COMMAND _MMIO(0x320c) 1024 #define FBC_CMD_COMPRESS REG_BIT(0) 1025 #define FBC_STATUS _MMIO(0x3210) 1026 #define FBC_STAT_COMPRESSING REG_BIT(31) 1027 #define FBC_STAT_COMPRESSED REG_BIT(30) 1028 #define FBC_STAT_MODIFIED REG_BIT(29) 1029 #define FBC_STAT_CURRENT_LINE_MASK REG_GENMASK(10, 0) 1030 #define FBC_CONTROL2 _MMIO(0x3214) /* i965gm only */ 1031 #define FBC_CTL_FENCE_DBL REG_BIT(4) 1032 #define FBC_CTL_IDLE_MASK REG_GENMASK(3, 2) 1033 #define FBC_CTL_IDLE_IMM REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0) 1034 #define FBC_CTL_IDLE_FULL REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 1) 1035 #define FBC_CTL_IDLE_LINE REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 2) 1036 #define FBC_CTL_IDLE_DEBUG REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 3) 1037 #define FBC_CTL_CPU_FENCE_EN REG_BIT(1) 1038 #define FBC_CTL_PLANE_MASK REG_GENMASK(1, 0) 1039 #define FBC_CTL_PLANE(i9xx_plane) REG_FIELD_PREP(FBC_CTL_PLANE_MASK, (i9xx_plane)) 1040 #define FBC_FENCE_OFF _MMIO(0x3218) /* i965gm only, BSpec typo has 321Bh */ 1041 #define FBC_MOD_NUM _MMIO(0x3220) /* i965gm only */ 1042 #define FBC_MOD_NUM_MASK REG_GENMASK(31, 1) 1043 #define FBC_MOD_NUM_VALID REG_BIT(0) 1044 #define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) /* 49 reisters */ 1045 #define FBC_TAG_MASK REG_GENMASK(1, 0) /* 16 tags per register */ 1046 #define FBC_TAG_MODIFIED REG_FIELD_PREP(FBC_TAG_MASK, 0) 1047 #define FBC_TAG_UNCOMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 1) 1048 #define FBC_TAG_UNCOMPRESSIBLE REG_FIELD_PREP(FBC_TAG_MASK, 2) 1049 #define FBC_TAG_COMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 3) 1050 1051 #define FBC_LL_SIZE (1536) 1052 1053 /* Framebuffer compression for GM45+ */ 1054 #define DPFC_CB_BASE _MMIO(0x3200) 1055 #define ILK_DPFC_CB_BASE(fbc_id) _MMIO_PIPE((fbc_id), 0x43200, 0x43240) 1056 #define DPFC_CONTROL _MMIO(0x3208) 1057 #define ILK_DPFC_CONTROL(fbc_id) _MMIO_PIPE((fbc_id), 0x43208, 0x43248) 1058 #define DPFC_CTL_EN REG_BIT(31) 1059 #define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */ 1060 #define DPFC_CTL_PLANE_G4X(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane)) 1061 #define DPFC_CTL_FENCE_EN_G4X REG_BIT(29) /* g4x-snb */ 1062 #define DPFC_CTL_PLANE_MASK_IVB REG_GENMASK(30, 29) /* ivb only */ 1063 #define DPFC_CTL_PLANE_IVB(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_IVB, (i9xx_plane)) 1064 #define DPFC_CTL_FENCE_EN_IVB REG_BIT(28) /* ivb+ */ 1065 #define DPFC_CTL_PERSISTENT_MODE REG_BIT(25) /* g4x-snb */ 1066 #define DPFC_CTL_PLANE_BINDING_MASK REG_GENMASK(12, 11) /* lnl+ */ 1067 #define DPFC_CTL_PLANE_BINDING(plane_id) REG_FIELD_PREP(DPFC_CTL_PLANE_BINDING_MASK, (plane_id)) 1068 #define DPFC_CTL_FALSE_COLOR REG_BIT(10) /* ivb+ */ 1069 #define DPFC_CTL_SR_EN REG_BIT(10) /* g4x only */ 1070 #define DPFC_CTL_SR_EXIT_DIS REG_BIT(9) /* g4x only */ 1071 #define DPFC_CTL_LIMIT_MASK REG_GENMASK(7, 6) 1072 #define DPFC_CTL_LIMIT_1X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 0) 1073 #define DPFC_CTL_LIMIT_2X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 1) 1074 #define DPFC_CTL_LIMIT_4X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2) 1075 #define DPFC_CTL_FENCENO_MASK REG_GENMASK(3, 0) 1076 #define DPFC_CTL_FENCENO(fence) REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence)) 1077 #define DPFC_RECOMP_CTL _MMIO(0x320c) 1078 #define ILK_DPFC_RECOMP_CTL(fbc_id) _MMIO_PIPE((fbc_id), 0x4320c, 0x4324c) 1079 #define DPFC_RECOMP_STALL_EN REG_BIT(27) 1080 #define DPFC_RECOMP_STALL_WM_MASK REG_GENMASK(26, 16) 1081 #define DPFC_RECOMP_TIMER_COUNT_MASK REG_GENMASK(5, 0) 1082 #define DPFC_STATUS _MMIO(0x3210) 1083 #define ILK_DPFC_STATUS(fbc_id) _MMIO_PIPE((fbc_id), 0x43210, 0x43250) 1084 #define DPFC_INVAL_SEG_MASK REG_GENMASK(26, 16) 1085 #define DPFC_COMP_SEG_MASK REG_GENMASK(10, 0) 1086 #define DPFC_STATUS2 _MMIO(0x3214) 1087 #define ILK_DPFC_STATUS2(fbc_id) _MMIO_PIPE((fbc_id), 0x43214, 0x43254) 1088 #define DPFC_COMP_SEG_MASK_IVB REG_GENMASK(11, 0) 1089 #define DPFC_FENCE_YOFF _MMIO(0x3218) 1090 #define ILK_DPFC_FENCE_YOFF(fbc_id) _MMIO_PIPE((fbc_id), 0x43218, 0x43258) 1091 #define DPFC_CHICKEN _MMIO(0x3224) 1092 #define ILK_DPFC_CHICKEN(fbc_id) _MMIO_PIPE((fbc_id), 0x43224, 0x43264) 1093 #define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */ 1094 #define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */ 1095 #define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */ 1096 #define DPFC_CHICKEN_FORCE_SLB_INVALIDATION REG_BIT(13) /* icl+ */ 1097 #define DPFC_DISABLE_DUMMY0 REG_BIT(8) /* ivb+ */ 1098 1099 #define GLK_FBC_STRIDE(fbc_id) _MMIO_PIPE((fbc_id), 0x43228, 0x43268) 1100 #define FBC_STRIDE_OVERRIDE REG_BIT(15) 1101 #define FBC_STRIDE_MASK REG_GENMASK(14, 0) 1102 #define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x)) 1103 1104 #define ILK_FBC_RT_BASE _MMIO(0x2128) 1105 #define ILK_FBC_RT_VALID REG_BIT(0) 1106 #define SNB_FBC_FRONT_BUFFER REG_BIT(1) 1107 1108 #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000) 1109 #define ILK_FBCQ_DIS REG_BIT(22) 1110 #define ILK_PABSTRETCH_DIS REG_BIT(21) 1111 #define ILK_SABSTRETCH_DIS REG_BIT(20) 1112 #define IVB_PRI_STRETCH_MAX_MASK REG_GENMASK(21, 20) 1113 #define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0) 1114 #define IVB_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1) 1115 #define IVB_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2) 1116 #define IVB_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3) 1117 #define IVB_SPR_STRETCH_MAX_MASK REG_GENMASK(19, 18) 1118 #define IVB_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0) 1119 #define IVB_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1) 1120 #define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2) 1121 #define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3) 1122 1123 1124 /* 1125 * Framebuffer compression for Sandybridge 1126 * 1127 * The following two registers are of type GTTMMADR 1128 */ 1129 #define SNB_DPFC_CTL_SA _MMIO(0x100100) 1130 #define SNB_DPFC_FENCE_EN REG_BIT(29) 1131 #define SNB_DPFC_FENCENO_MASK REG_GENMASK(4, 0) 1132 #define SNB_DPFC_FENCENO(fence) REG_FIELD_PREP(SNB_DPFC_FENCENO_MASK, (fence)) 1133 #define SNB_DPFC_CPU_FENCE_OFFSET _MMIO(0x100104) 1134 1135 /* Framebuffer compression for Ivybridge */ 1136 #define IVB_FBC_RT_BASE _MMIO(0x7020) 1137 #define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024) 1138 1139 #define IPS_CTL _MMIO(0x43408) 1140 #define IPS_ENABLE REG_BIT(31) 1141 #define IPS_FALSE_COLOR REG_BIT(4) 1142 1143 #define MSG_FBC_REND_STATE(fbc_id) _MMIO_PIPE((fbc_id), 0x50380, 0x50384) 1144 #define FBC_REND_NUKE REG_BIT(2) 1145 #define FBC_REND_CACHE_CLEAN REG_BIT(1) 1146 1147 /* 1148 * Clock control & power management 1149 */ 1150 #define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014) 1151 #define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018) 1152 #define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030) 1153 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) 1154 1155 #define VGA0 _MMIO(0x6000) 1156 #define VGA1 _MMIO(0x6004) 1157 #define VGA_PD _MMIO(0x6010) 1158 #define VGA0_PD_P2_DIV_4 (1 << 7) 1159 #define VGA0_PD_P1_DIV_2 (1 << 5) 1160 #define VGA0_PD_P1_SHIFT 0 1161 #define VGA0_PD_P1_MASK (0x1f << 0) 1162 #define VGA1_PD_P2_DIV_4 (1 << 15) 1163 #define VGA1_PD_P1_DIV_2 (1 << 13) 1164 #define VGA1_PD_P1_SHIFT 8 1165 #define VGA1_PD_P1_MASK (0x1f << 8) 1166 #define DPLL_VCO_ENABLE (1 << 31) 1167 #define DPLL_SDVO_HIGH_SPEED (1 << 30) 1168 #define DPLL_DVO_2X_MODE (1 << 30) 1169 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) 1170 #define DPLL_SYNCLOCK_ENABLE (1 << 29) 1171 #define DPLL_REF_CLK_ENABLE_VLV (1 << 29) 1172 #define DPLL_VGA_MODE_DIS (1 << 28) 1173 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 1174 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 1175 #define DPLL_MODE_MASK (3 << 26) 1176 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 1177 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 1178 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 1179 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 1180 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 1181 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 1182 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ 1183 #define DPLL_LOCK_VLV (1 << 15) 1184 #define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14) 1185 #define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13) 1186 #define DPLL_SSC_REF_CLK_CHV (1 << 13) 1187 #define DPLL_PORTC_READY_MASK (0xf << 4) 1188 #define DPLL_PORTB_READY_MASK (0xf) 1189 1190 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 1191 1192 /* Additional CHV pll/phy registers */ 1193 #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240) 1194 #define DPLL_PORTD_READY_MASK (0xf) 1195 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100) 1196 #define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27)) 1197 #define PHY_LDO_DELAY_0NS 0x0 1198 #define PHY_LDO_DELAY_200NS 0x1 1199 #define PHY_LDO_DELAY_600NS 0x2 1200 #define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23)) 1201 #define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11)) 1202 #define PHY_CH_SU_PSR 0x1 1203 #define PHY_CH_DEEP_PSR 0x7 1204 #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2)) 1205 #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy)) 1206 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104) 1207 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30)) 1208 #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch)))) 1209 #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline)))) 1210 1211 /* 1212 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 1213 * this field (only one bit may be set). 1214 */ 1215 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 1216 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 1217 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 1218 /* i830, required in DVO non-gang */ 1219 #define PLL_P2_DIVIDE_BY_4 (1 << 23) 1220 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 1221 #define PLL_REF_INPUT_DREFCLK (0 << 13) 1222 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 1223 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 1224 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 1225 #define PLL_REF_INPUT_MASK (3 << 13) 1226 #define PLL_LOAD_PULSE_PHASE_SHIFT 9 1227 /* Ironlake */ 1228 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 1229 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) 1230 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9) 1231 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 1232 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff 1233 1234 /* 1235 * Parallel to Serial Load Pulse phase selection. 1236 * Selects the phase for the 10X DPLL clock for the PCIe 1237 * digital display port. The range is 4 to 13; 10 or more 1238 * is just a flip delay. The default is 6 1239 */ 1240 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 1241 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 1242 /* 1243 * SDVO multiplier for 945G/GM. Not used on 965. 1244 */ 1245 #define SDVO_MULTIPLIER_MASK 0x000000ff 1246 #define SDVO_MULTIPLIER_SHIFT_HIRES 4 1247 #define SDVO_MULTIPLIER_SHIFT_VGA 0 1248 1249 #define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c) 1250 #define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020) 1251 #define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c) 1252 #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) 1253 1254 /* 1255 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 1256 * 1257 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 1258 */ 1259 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 1260 #define DPLL_MD_UDI_DIVIDER_SHIFT 24 1261 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 1262 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 1263 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 1264 /* 1265 * SDVO/UDI pixel multiplier. 1266 * 1267 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 1268 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 1269 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 1270 * dummy bytes in the datastream at an increased clock rate, with both sides of 1271 * the link knowing how many bytes are fill. 1272 * 1273 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 1274 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 1275 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 1276 * through an SDVO command. 1277 * 1278 * This register field has values of multiplication factor minus 1, with 1279 * a maximum multiplier of 5 for SDVO. 1280 */ 1281 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 1282 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 1283 /* 1284 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 1285 * This best be set to the default value (3) or the CRT won't work. No, 1286 * I don't entirely understand what this does... 1287 */ 1288 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 1289 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 1290 1291 #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024) 1292 1293 #define _FPA0 0x6040 1294 #define _FPA1 0x6044 1295 #define _FPB0 0x6048 1296 #define _FPB1 0x604c 1297 #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0) 1298 #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1) 1299 #define FP_N_DIV_MASK 0x003f0000 1300 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 1301 #define FP_N_DIV_SHIFT 16 1302 #define FP_M1_DIV_MASK 0x00003f00 1303 #define FP_M1_DIV_SHIFT 8 1304 #define FP_M2_DIV_MASK 0x0000003f 1305 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff 1306 #define FP_M2_DIV_SHIFT 0 1307 #define DPLL_TEST _MMIO(0x606c) 1308 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 1309 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 1310 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 1311 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 1312 #define DPLLB_TEST_N_BYPASS (1 << 19) 1313 #define DPLLB_TEST_M_BYPASS (1 << 18) 1314 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 1315 #define DPLLA_TEST_N_BYPASS (1 << 3) 1316 #define DPLLA_TEST_M_BYPASS (1 << 2) 1317 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 1318 #define D_STATE _MMIO(0x6104) 1319 #define DSTATE_GFX_RESET_I830 (1 << 6) 1320 #define DSTATE_PLL_D3_OFF (1 << 3) 1321 #define DSTATE_GFX_CLOCK_GATING (1 << 1) 1322 #define DSTATE_DOT_CLOCK_GATING (1 << 0) 1323 #define DSPCLK_GATE_D(__i915) _MMIO(DISPLAY_MMIO_BASE(__i915) + 0x6200) 1324 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 1325 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 1326 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 1327 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ 1328 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ 1329 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ 1330 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ 1331 # define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */ 1332 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ 1333 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ 1334 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ 1335 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ 1336 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ 1337 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ 1338 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ 1339 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ 1340 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ 1341 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ 1342 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ 1343 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ 1344 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 1345 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) 1346 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) 1347 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) 1348 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ 1349 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ 1350 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ 1351 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) 1352 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) 1353 /* 1354 * This bit must be set on the 830 to prevent hangs when turning off the 1355 * overlay scaler. 1356 */ 1357 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 1358 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) 1359 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) 1360 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ 1361 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ 1362 1363 #define RENCLK_GATE_D1 _MMIO(0x6204) 1364 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ 1365 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ 1366 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) 1367 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) 1368 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) 1369 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) 1370 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) 1371 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) 1372 # define MAG_CLOCK_GATE_DISABLE (1 << 5) 1373 /* This bit must be unset on 855,865 */ 1374 # define MECI_CLOCK_GATE_DISABLE (1 << 4) 1375 # define DCMP_CLOCK_GATE_DISABLE (1 << 3) 1376 # define MEC_CLOCK_GATE_DISABLE (1 << 2) 1377 # define MECO_CLOCK_GATE_DISABLE (1 << 1) 1378 /* This bit must be set on 855,865. */ 1379 # define SV_CLOCK_GATE_DISABLE (1 << 0) 1380 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) 1381 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) 1382 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) 1383 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) 1384 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) 1385 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) 1386 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) 1387 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) 1388 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) 1389 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) 1390 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) 1391 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) 1392 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) 1393 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) 1394 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) 1395 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) 1396 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) 1397 1398 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) 1399 /* This bit must always be set on 965G/965GM */ 1400 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) 1401 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) 1402 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) 1403 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) 1404 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) 1405 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) 1406 /* This bit must always be set on 965G */ 1407 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) 1408 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) 1409 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) 1410 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) 1411 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) 1412 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) 1413 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) 1414 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) 1415 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) 1416 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) 1417 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) 1418 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) 1419 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) 1420 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) 1421 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) 1422 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) 1423 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) 1424 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) 1425 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) 1426 1427 #define RENCLK_GATE_D2 _MMIO(0x6208) 1428 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) 1429 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) 1430 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) 1431 1432 #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */ 1433 #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4) 1434 1435 #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */ 1436 #define DEUC _MMIO(0x6214) /* CRL only */ 1437 1438 #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500) 1439 #define FW_CSPWRDWNEN (1 << 15) 1440 1441 #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504) 1442 1443 #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508) 1444 #define CDCLK_FREQ_SHIFT 4 1445 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT) 1446 #define CZCLK_FREQ_MASK 0xf 1447 1448 #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C) 1449 #define PFI_CREDIT_63 (9 << 28) /* chv only */ 1450 #define PFI_CREDIT_31 (8 << 28) /* chv only */ 1451 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */ 1452 #define PFI_CREDIT_RESEND (1 << 27) 1453 #define VGA_FAST_MODE_DISABLE (1 << 14) 1454 1455 #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510) 1456 1457 /* 1458 * Palette regs 1459 */ 1460 #define _PALETTE_A 0xa000 1461 #define _PALETTE_B 0xa800 1462 #define _CHV_PALETTE_C 0xc000 1463 /* 8bit mode / i965+ 10.6 interpolated mode ldw/udw */ 1464 #define PALETTE_RED_MASK REG_GENMASK(23, 16) 1465 #define PALETTE_GREEN_MASK REG_GENMASK(15, 8) 1466 #define PALETTE_BLUE_MASK REG_GENMASK(7, 0) 1467 /* pre-i965 10bit interpolated mode ldw */ 1468 #define PALETTE_10BIT_RED_LDW_MASK REG_GENMASK(23, 16) 1469 #define PALETTE_10BIT_GREEN_LDW_MASK REG_GENMASK(15, 8) 1470 #define PALETTE_10BIT_BLUE_LDW_MASK REG_GENMASK(7, 0) 1471 /* pre-i965 10bit interpolated mode udw */ 1472 #define PALETTE_10BIT_RED_EXP_MASK REG_GENMASK(23, 22) 1473 #define PALETTE_10BIT_RED_MANT_MASK REG_GENMASK(21, 18) 1474 #define PALETTE_10BIT_RED_UDW_MASK REG_GENMASK(17, 16) 1475 #define PALETTE_10BIT_GREEN_EXP_MASK REG_GENMASK(15, 14) 1476 #define PALETTE_10BIT_GREEN_MANT_MASK REG_GENMASK(13, 10) 1477 #define PALETTE_10BIT_GREEN_UDW_MASK REG_GENMASK(9, 8) 1478 #define PALETTE_10BIT_BLUE_EXP_MASK REG_GENMASK(7, 6) 1479 #define PALETTE_10BIT_BLUE_MANT_MASK REG_GENMASK(5, 2) 1480 #define PALETTE_10BIT_BLUE_UDW_MASK REG_GENMASK(1, 0) 1481 #define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \ 1482 _PICK_EVEN_2RANGES(pipe, 2, \ 1483 _PALETTE_A, _PALETTE_B, \ 1484 _CHV_PALETTE_C, _CHV_PALETTE_C) + \ 1485 (i) * 4) 1486 1487 #define PEG_BAND_GAP_DATA _MMIO(0x14d68) 1488 1489 #define BXT_RP_STATE_CAP _MMIO(0x138170) 1490 #define GEN9_RP_STATE_LIMITS _MMIO(0x138148) 1491 1492 #define MTL_RP_STATE_CAP _MMIO(0x138000) 1493 #define MTL_MEDIAP_STATE_CAP _MMIO(0x138020) 1494 #define MTL_RP0_CAP_MASK REG_GENMASK(8, 0) 1495 #define MTL_RPN_CAP_MASK REG_GENMASK(24, 16) 1496 1497 #define MTL_GT_RPE_FREQUENCY _MMIO(0x13800c) 1498 #define MTL_MPE_FREQUENCY _MMIO(0x13802c) 1499 #define MTL_RPE_MASK REG_GENMASK(8, 0) 1500 1501 #define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8) 1502 #define GT0_PERF_LIMIT_REASONS_MASK 0xde3 1503 #define PROCHOT_MASK REG_BIT(0) 1504 #define THERMAL_LIMIT_MASK REG_BIT(1) 1505 #define RATL_MASK REG_BIT(5) 1506 #define VR_THERMALERT_MASK REG_BIT(6) 1507 #define VR_TDC_MASK REG_BIT(7) 1508 #define POWER_LIMIT_4_MASK REG_BIT(8) 1509 #define POWER_LIMIT_1_MASK REG_BIT(10) 1510 #define POWER_LIMIT_2_MASK REG_BIT(11) 1511 #define GT0_PERF_LIMIT_REASONS_LOG_MASK REG_GENMASK(31, 16) 1512 #define MTL_MEDIA_PERF_LIMIT_REASONS _MMIO(0x138030) 1513 1514 #define CHV_CLK_CTL1 _MMIO(0x101100) 1515 #define VLV_CLK_CTL2 _MMIO(0x101104) 1516 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28 1517 1518 /* 1519 * Overlay regs 1520 */ 1521 1522 #define OVADD _MMIO(0x30000) 1523 #define DOVSTA _MMIO(0x30008) 1524 #define OC_BUF (0x3 << 20) 1525 #define OGAMC5 _MMIO(0x30010) 1526 #define OGAMC4 _MMIO(0x30014) 1527 #define OGAMC3 _MMIO(0x30018) 1528 #define OGAMC2 _MMIO(0x3001c) 1529 #define OGAMC1 _MMIO(0x30020) 1530 #define OGAMC0 _MMIO(0x30024) 1531 1532 /* 1533 * GEN9 clock gating regs 1534 */ 1535 #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530) 1536 #define DARBF_GATING_DIS REG_BIT(27) 1537 #define MTL_PIPEDMC_GATING_DIS_A REG_BIT(15) 1538 #define MTL_PIPEDMC_GATING_DIS_B REG_BIT(14) 1539 #define PWM2_GATING_DIS REG_BIT(14) 1540 #define PWM1_GATING_DIS REG_BIT(13) 1541 1542 #define GEN9_CLKGATE_DIS_3 _MMIO(0x46538) 1543 #define TGL_VRH_GATING_DIS REG_BIT(31) 1544 #define DPT_GATING_DIS REG_BIT(22) 1545 1546 #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C) 1547 #define BXT_GMBUS_GATING_DIS (1 << 14) 1548 1549 #define GEN9_CLKGATE_DIS_5 _MMIO(0x46540) 1550 #define DPCE_GATING_DIS REG_BIT(17) 1551 1552 #define _CLKGATE_DIS_PSL_A 0x46520 1553 #define _CLKGATE_DIS_PSL_B 0x46524 1554 #define _CLKGATE_DIS_PSL_C 0x46528 1555 #define DUPS1_GATING_DIS (1 << 15) 1556 #define DUPS2_GATING_DIS (1 << 19) 1557 #define DUPS3_GATING_DIS (1 << 23) 1558 #define CURSOR_GATING_DIS REG_BIT(28) 1559 #define DPF_GATING_DIS (1 << 10) 1560 #define DPF_RAM_GATING_DIS (1 << 9) 1561 #define DPFR_GATING_DIS (1 << 8) 1562 1563 #define CLKGATE_DIS_PSL(pipe) \ 1564 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B) 1565 1566 #define _CLKGATE_DIS_PSL_EXT_A 0x4654C 1567 #define _CLKGATE_DIS_PSL_EXT_B 0x46550 1568 #define PIPEDMC_GATING_DIS REG_BIT(12) 1569 1570 #define CLKGATE_DIS_PSL_EXT(pipe) \ 1571 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_EXT_A, _CLKGATE_DIS_PSL_EXT_B) 1572 1573 /* DDI Buffer Control */ 1574 #define _DDI_CLK_VALFREQ_A 0x64030 1575 #define _DDI_CLK_VALFREQ_B 0x64130 1576 #define DDI_CLK_VALFREQ(port) _MMIO_PORT(port, _DDI_CLK_VALFREQ_A, _DDI_CLK_VALFREQ_B) 1577 1578 /* 1579 * Display engine regs 1580 */ 1581 1582 /* Pipe A CRC regs */ 1583 #define _PIPE_CRC_CTL_A 0x60050 1584 #define PIPE_CRC_ENABLE REG_BIT(31) 1585 /* skl+ source selection */ 1586 #define PIPE_CRC_SOURCE_MASK_SKL REG_GENMASK(30, 28) 1587 #define PIPE_CRC_SOURCE_PLANE_1_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 0) 1588 #define PIPE_CRC_SOURCE_PLANE_2_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 2) 1589 #define PIPE_CRC_SOURCE_DMUX_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 4) 1590 #define PIPE_CRC_SOURCE_PLANE_3_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 6) 1591 #define PIPE_CRC_SOURCE_PLANE_4_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 7) 1592 #define PIPE_CRC_SOURCE_PLANE_5_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 5) 1593 #define PIPE_CRC_SOURCE_PLANE_6_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 3) 1594 #define PIPE_CRC_SOURCE_PLANE_7_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 1) 1595 /* ivb+ source selection */ 1596 #define PIPE_CRC_SOURCE_MASK_IVB REG_GENMASK(30, 29) 1597 #define PIPE_CRC_SOURCE_PRIMARY_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 0) 1598 #define PIPE_CRC_SOURCE_SPRITE_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 1) 1599 #define PIPE_CRC_SOURCE_PF_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 2) 1600 /* ilk+ source selection */ 1601 #define PIPE_CRC_SOURCE_MASK_ILK REG_GENMASK(30, 28) 1602 #define PIPE_CRC_SOURCE_PRIMARY_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 0) 1603 #define PIPE_CRC_SOURCE_SPRITE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 1) 1604 #define PIPE_CRC_SOURCE_PIPE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 2) 1605 /* embedded DP port on the north display block */ 1606 #define PIPE_CRC_SOURCE_PORT_A_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 4) 1607 #define PIPE_CRC_SOURCE_FDI_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 5) 1608 /* vlv source selection */ 1609 #define PIPE_CRC_SOURCE_MASK_VLV REG_GENMASK(30, 27) 1610 #define PIPE_CRC_SOURCE_PIPE_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 0) 1611 #define PIPE_CRC_SOURCE_HDMIB_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 1) 1612 #define PIPE_CRC_SOURCE_HDMIC_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 2) 1613 /* with DP port the pipe source is invalid */ 1614 #define PIPE_CRC_SOURCE_DP_D_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 3) 1615 #define PIPE_CRC_SOURCE_DP_B_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 6) 1616 #define PIPE_CRC_SOURCE_DP_C_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 7) 1617 /* gen3+ source selection */ 1618 #define PIPE_CRC_SOURCE_MASK_I9XX REG_GENMASK(30, 28) 1619 #define PIPE_CRC_SOURCE_PIPE_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 0) 1620 #define PIPE_CRC_SOURCE_SDVOB_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 1) 1621 #define PIPE_CRC_SOURCE_SDVOC_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 2) 1622 /* with DP/TV port the pipe source is invalid */ 1623 #define PIPE_CRC_SOURCE_DP_D_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 3) 1624 #define PIPE_CRC_SOURCE_TV_PRE REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 4) 1625 #define PIPE_CRC_SOURCE_TV_POST REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 5) 1626 #define PIPE_CRC_SOURCE_DP_B_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 6) 1627 #define PIPE_CRC_SOURCE_DP_C_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 7) 1628 /* gen2 doesn't have source selection bits */ 1629 #define PIPE_CRC_INCLUDE_BORDER_I8XX REG_BIT(30) 1630 1631 #define _PIPE_CRC_RES_1_A_IVB 0x60064 1632 #define _PIPE_CRC_RES_2_A_IVB 0x60068 1633 #define _PIPE_CRC_RES_3_A_IVB 0x6006c 1634 #define _PIPE_CRC_RES_4_A_IVB 0x60070 1635 #define _PIPE_CRC_RES_5_A_IVB 0x60074 1636 1637 #define _PIPE_CRC_RES_RED_A 0x60060 1638 #define _PIPE_CRC_RES_GREEN_A 0x60064 1639 #define _PIPE_CRC_RES_BLUE_A 0x60068 1640 #define _PIPE_CRC_RES_RES1_A_I915 0x6006c 1641 #define _PIPE_CRC_RES_RES2_A_G4X 0x60080 1642 1643 /* Pipe B CRC regs */ 1644 #define _PIPE_CRC_RES_1_B_IVB 0x61064 1645 #define _PIPE_CRC_RES_2_B_IVB 0x61068 1646 #define _PIPE_CRC_RES_3_B_IVB 0x6106c 1647 #define _PIPE_CRC_RES_4_B_IVB 0x61070 1648 #define _PIPE_CRC_RES_5_B_IVB 0x61074 1649 1650 #define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A) 1651 #define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB) 1652 #define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB) 1653 #define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB) 1654 #define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB) 1655 #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB) 1656 1657 #define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A) 1658 #define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A) 1659 #define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A) 1660 #define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915) 1661 #define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X) 1662 1663 /* Pipe/transcoder A timing regs */ 1664 #define _TRANS_HTOTAL_A 0x60000 1665 #define HTOTAL_MASK REG_GENMASK(31, 16) 1666 #define HTOTAL(htotal) REG_FIELD_PREP(HTOTAL_MASK, (htotal)) 1667 #define HACTIVE_MASK REG_GENMASK(15, 0) 1668 #define HACTIVE(hdisplay) REG_FIELD_PREP(HACTIVE_MASK, (hdisplay)) 1669 #define _TRANS_HBLANK_A 0x60004 1670 #define HBLANK_END_MASK REG_GENMASK(31, 16) 1671 #define HBLANK_END(hblank_end) REG_FIELD_PREP(HBLANK_END_MASK, (hblank_end)) 1672 #define HBLANK_START_MASK REG_GENMASK(15, 0) 1673 #define HBLANK_START(hblank_start) REG_FIELD_PREP(HBLANK_START_MASK, (hblank_start)) 1674 #define _TRANS_HSYNC_A 0x60008 1675 #define HSYNC_END_MASK REG_GENMASK(31, 16) 1676 #define HSYNC_END(hsync_end) REG_FIELD_PREP(HSYNC_END_MASK, (hsync_end)) 1677 #define HSYNC_START_MASK REG_GENMASK(15, 0) 1678 #define HSYNC_START(hsync_start) REG_FIELD_PREP(HSYNC_START_MASK, (hsync_start)) 1679 #define _TRANS_VTOTAL_A 0x6000c 1680 #define VTOTAL_MASK REG_GENMASK(31, 16) 1681 #define VTOTAL(vtotal) REG_FIELD_PREP(VTOTAL_MASK, (vtotal)) 1682 #define VACTIVE_MASK REG_GENMASK(15, 0) 1683 #define VACTIVE(vdisplay) REG_FIELD_PREP(VACTIVE_MASK, (vdisplay)) 1684 #define _TRANS_VBLANK_A 0x60010 1685 #define VBLANK_END_MASK REG_GENMASK(31, 16) 1686 #define VBLANK_END(vblank_end) REG_FIELD_PREP(VBLANK_END_MASK, (vblank_end)) 1687 #define VBLANK_START_MASK REG_GENMASK(15, 0) 1688 #define VBLANK_START(vblank_start) REG_FIELD_PREP(VBLANK_START_MASK, (vblank_start)) 1689 #define _TRANS_VSYNC_A 0x60014 1690 #define VSYNC_END_MASK REG_GENMASK(31, 16) 1691 #define VSYNC_END(vsync_end) REG_FIELD_PREP(VSYNC_END_MASK, (vsync_end)) 1692 #define VSYNC_START_MASK REG_GENMASK(15, 0) 1693 #define VSYNC_START(vsync_start) REG_FIELD_PREP(VSYNC_START_MASK, (vsync_start)) 1694 #define _TRANS_EXITLINE_A 0x60018 1695 #define _PIPEASRC 0x6001c 1696 #define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16) 1697 #define PIPESRC_WIDTH(w) REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w)) 1698 #define PIPESRC_HEIGHT_MASK REG_GENMASK(15, 0) 1699 #define PIPESRC_HEIGHT(h) REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h)) 1700 #define _BCLRPAT_A 0x60020 1701 #define _TRANS_VSYNCSHIFT_A 0x60028 1702 #define _TRANS_MULT_A 0x6002c 1703 1704 /* Pipe/transcoder B timing regs */ 1705 #define _TRANS_HTOTAL_B 0x61000 1706 #define _TRANS_HBLANK_B 0x61004 1707 #define _TRANS_HSYNC_B 0x61008 1708 #define _TRANS_VTOTAL_B 0x6100c 1709 #define _TRANS_VBLANK_B 0x61010 1710 #define _TRANS_VSYNC_B 0x61014 1711 #define _PIPEBSRC 0x6101c 1712 #define _BCLRPAT_B 0x61020 1713 #define _TRANS_VSYNCSHIFT_B 0x61028 1714 #define _TRANS_MULT_B 0x6102c 1715 1716 /* DSI 0 timing regs */ 1717 #define _TRANS_HTOTAL_DSI0 0x6b000 1718 #define _TRANS_HSYNC_DSI0 0x6b008 1719 #define _TRANS_VTOTAL_DSI0 0x6b00c 1720 #define _TRANS_VSYNC_DSI0 0x6b014 1721 #define _TRANS_VSYNCSHIFT_DSI0 0x6b028 1722 1723 /* DSI 1 timing regs */ 1724 #define _TRANS_HTOTAL_DSI1 0x6b800 1725 #define _TRANS_HSYNC_DSI1 0x6b808 1726 #define _TRANS_VTOTAL_DSI1 0x6b80c 1727 #define _TRANS_VSYNC_DSI1 0x6b814 1728 #define _TRANS_VSYNCSHIFT_DSI1 0x6b828 1729 1730 #define TRANS_HTOTAL(trans) _MMIO_TRANS2((trans), _TRANS_HTOTAL_A) 1731 #define TRANS_HBLANK(trans) _MMIO_TRANS2((trans), _TRANS_HBLANK_A) 1732 #define TRANS_HSYNC(trans) _MMIO_TRANS2((trans), _TRANS_HSYNC_A) 1733 #define TRANS_VTOTAL(trans) _MMIO_TRANS2((trans), _TRANS_VTOTAL_A) 1734 #define TRANS_VBLANK(trans) _MMIO_TRANS2((trans), _TRANS_VBLANK_A) 1735 #define TRANS_VSYNC(trans) _MMIO_TRANS2((trans), _TRANS_VSYNC_A) 1736 #define BCLRPAT(trans) _MMIO_TRANS2((trans), _BCLRPAT_A) 1737 #define TRANS_VSYNCSHIFT(trans) _MMIO_TRANS2((trans), _TRANS_VSYNCSHIFT_A) 1738 #define PIPESRC(pipe) _MMIO_TRANS2((pipe), _PIPEASRC) 1739 #define TRANS_MULT(trans) _MMIO_TRANS2((trans), _TRANS_MULT_A) 1740 1741 /* VRR registers */ 1742 #define _TRANS_VRR_CTL_A 0x60420 1743 #define _TRANS_VRR_CTL_B 0x61420 1744 #define _TRANS_VRR_CTL_C 0x62420 1745 #define _TRANS_VRR_CTL_D 0x63420 1746 #define TRANS_VRR_CTL(trans) _MMIO_TRANS2(trans, _TRANS_VRR_CTL_A) 1747 #define VRR_CTL_VRR_ENABLE REG_BIT(31) 1748 #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) 1749 #define VRR_CTL_FLIP_LINE_EN REG_BIT(29) 1750 #define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3) 1751 #define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x)) 1752 #define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0) 1753 #define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0) 1754 #define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x)) 1755 1756 #define _TRANS_VRR_VMAX_A 0x60424 1757 #define _TRANS_VRR_VMAX_B 0x61424 1758 #define _TRANS_VRR_VMAX_C 0x62424 1759 #define _TRANS_VRR_VMAX_D 0x63424 1760 #define TRANS_VRR_VMAX(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMAX_A) 1761 #define VRR_VMAX_MASK REG_GENMASK(19, 0) 1762 1763 #define _TRANS_VRR_VMIN_A 0x60434 1764 #define _TRANS_VRR_VMIN_B 0x61434 1765 #define _TRANS_VRR_VMIN_C 0x62434 1766 #define _TRANS_VRR_VMIN_D 0x63434 1767 #define TRANS_VRR_VMIN(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMIN_A) 1768 #define VRR_VMIN_MASK REG_GENMASK(15, 0) 1769 1770 #define _TRANS_VRR_VMAXSHIFT_A 0x60428 1771 #define _TRANS_VRR_VMAXSHIFT_B 0x61428 1772 #define _TRANS_VRR_VMAXSHIFT_C 0x62428 1773 #define _TRANS_VRR_VMAXSHIFT_D 0x63428 1774 #define TRANS_VRR_VMAXSHIFT(trans) _MMIO_TRANS2(trans, \ 1775 _TRANS_VRR_VMAXSHIFT_A) 1776 #define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16) 1777 #define VRR_VMAXSHIFT_DEC REG_BIT(16) 1778 #define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0) 1779 1780 #define _TRANS_VRR_STATUS_A 0x6042C 1781 #define _TRANS_VRR_STATUS_B 0x6142C 1782 #define _TRANS_VRR_STATUS_C 0x6242C 1783 #define _TRANS_VRR_STATUS_D 0x6342C 1784 #define TRANS_VRR_STATUS(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS_A) 1785 #define VRR_STATUS_VMAX_REACHED REG_BIT(31) 1786 #define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30) 1787 #define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29) 1788 #define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28) 1789 #define VRR_STATUS_VRR_EN_LIVE REG_BIT(27) 1790 #define VRR_STATUS_FLIPS_SERVICED REG_BIT(26) 1791 #define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20) 1792 #define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0) 1793 #define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1) 1794 #define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2) 1795 #define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3) 1796 #define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4) 1797 #define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5) 1798 #define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6) 1799 1800 #define _TRANS_VRR_VTOTAL_PREV_A 0x60480 1801 #define _TRANS_VRR_VTOTAL_PREV_B 0x61480 1802 #define _TRANS_VRR_VTOTAL_PREV_C 0x62480 1803 #define _TRANS_VRR_VTOTAL_PREV_D 0x63480 1804 #define TRANS_VRR_VTOTAL_PREV(trans) _MMIO_TRANS2(trans, \ 1805 _TRANS_VRR_VTOTAL_PREV_A) 1806 #define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31) 1807 #define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30) 1808 #define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29) 1809 #define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0) 1810 1811 #define _TRANS_VRR_FLIPLINE_A 0x60438 1812 #define _TRANS_VRR_FLIPLINE_B 0x61438 1813 #define _TRANS_VRR_FLIPLINE_C 0x62438 1814 #define _TRANS_VRR_FLIPLINE_D 0x63438 1815 #define TRANS_VRR_FLIPLINE(trans) _MMIO_TRANS2(trans, \ 1816 _TRANS_VRR_FLIPLINE_A) 1817 #define VRR_FLIPLINE_MASK REG_GENMASK(19, 0) 1818 1819 #define _TRANS_VRR_STATUS2_A 0x6043C 1820 #define _TRANS_VRR_STATUS2_B 0x6143C 1821 #define _TRANS_VRR_STATUS2_C 0x6243C 1822 #define _TRANS_VRR_STATUS2_D 0x6343C 1823 #define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A) 1824 #define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0) 1825 1826 #define _TRANS_PUSH_A 0x60A70 1827 #define _TRANS_PUSH_B 0x61A70 1828 #define _TRANS_PUSH_C 0x62A70 1829 #define _TRANS_PUSH_D 0x63A70 1830 #define TRANS_PUSH(trans) _MMIO_TRANS2(trans, _TRANS_PUSH_A) 1831 #define TRANS_PUSH_EN REG_BIT(31) 1832 #define TRANS_PUSH_SEND REG_BIT(30) 1833 1834 #define _TRANS_VRR_VSYNC_A 0x60078 1835 #define TRANS_VRR_VSYNC(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VSYNC_A) 1836 #define VRR_VSYNC_END_MASK REG_GENMASK(28, 16) 1837 #define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end)) 1838 #define VRR_VSYNC_START_MASK REG_GENMASK(12, 0) 1839 #define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start)) 1840 1841 /* VGA port control */ 1842 #define ADPA _MMIO(0x61100) 1843 #define PCH_ADPA _MMIO(0xe1100) 1844 #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100) 1845 1846 #define ADPA_DAC_ENABLE (1 << 31) 1847 #define ADPA_DAC_DISABLE 0 1848 #define ADPA_PIPE_SEL_SHIFT 30 1849 #define ADPA_PIPE_SEL_MASK (1 << 30) 1850 #define ADPA_PIPE_SEL(pipe) ((pipe) << 30) 1851 #define ADPA_PIPE_SEL_SHIFT_CPT 29 1852 #define ADPA_PIPE_SEL_MASK_CPT (3 << 29) 1853 #define ADPA_PIPE_SEL_CPT(pipe) ((pipe) << 29) 1854 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ 1855 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0 << 24) 1856 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3 << 24) 1857 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24) 1858 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2 << 24) 1859 #define ADPA_CRT_HOTPLUG_ENABLE (1 << 23) 1860 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0 << 22) 1861 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1 << 22) 1862 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0 << 21) 1863 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1 << 21) 1864 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0 << 20) 1865 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1 << 20) 1866 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0 << 18) 1867 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1 << 18) 1868 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2 << 18) 1869 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3 << 18) 1870 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0 << 17) 1871 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1 << 17) 1872 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16) 1873 #define ADPA_USE_VGA_HVPOLARITY (1 << 15) 1874 #define ADPA_SETS_HVPOLARITY 0 1875 #define ADPA_VSYNC_CNTL_DISABLE (1 << 10) 1876 #define ADPA_VSYNC_CNTL_ENABLE 0 1877 #define ADPA_HSYNC_CNTL_DISABLE (1 << 11) 1878 #define ADPA_HSYNC_CNTL_ENABLE 0 1879 #define ADPA_VSYNC_ACTIVE_HIGH (1 << 4) 1880 #define ADPA_VSYNC_ACTIVE_LOW 0 1881 #define ADPA_HSYNC_ACTIVE_HIGH (1 << 3) 1882 #define ADPA_HSYNC_ACTIVE_LOW 0 1883 #define ADPA_DPMS_MASK (~(3 << 10)) 1884 #define ADPA_DPMS_ON (0 << 10) 1885 #define ADPA_DPMS_SUSPEND (1 << 10) 1886 #define ADPA_DPMS_STANDBY (2 << 10) 1887 #define ADPA_DPMS_OFF (3 << 10) 1888 1889 1890 /* Hotplug control (945+ only) */ 1891 #define PORT_HOTPLUG_EN _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110) 1892 #define PORTB_HOTPLUG_INT_EN (1 << 29) 1893 #define PORTC_HOTPLUG_INT_EN (1 << 28) 1894 #define PORTD_HOTPLUG_INT_EN (1 << 27) 1895 #define SDVOB_HOTPLUG_INT_EN (1 << 26) 1896 #define SDVOC_HOTPLUG_INT_EN (1 << 25) 1897 #define TV_HOTPLUG_INT_EN (1 << 18) 1898 #define CRT_HOTPLUG_INT_EN (1 << 9) 1899 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \ 1900 PORTC_HOTPLUG_INT_EN | \ 1901 PORTD_HOTPLUG_INT_EN | \ 1902 SDVOC_HOTPLUG_INT_EN | \ 1903 SDVOB_HOTPLUG_INT_EN | \ 1904 CRT_HOTPLUG_INT_EN) 1905 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 1906 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 1907 /* must use period 64 on GM45 according to docs */ 1908 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 1909 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 1910 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 1911 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 1912 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 1913 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 1914 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 1915 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 1916 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 1917 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 1918 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 1919 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 1920 1921 #define PORT_HOTPLUG_STAT _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114) 1922 /* HDMI/DP bits are g4x+ */ 1923 #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27) 1924 #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) 1925 #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29) 1926 #define PORTD_HOTPLUG_INT_STATUS (3 << 21) 1927 #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21) 1928 #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21) 1929 #define PORTC_HOTPLUG_INT_STATUS (3 << 19) 1930 #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19) 1931 #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19) 1932 #define PORTB_HOTPLUG_INT_STATUS (3 << 17) 1933 #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17) 1934 #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17) 1935 /* CRT/TV common between gen3+ */ 1936 #define CRT_HOTPLUG_INT_STATUS (1 << 11) 1937 #define TV_HOTPLUG_INT_STATUS (1 << 10) 1938 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 1939 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 1940 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 1941 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 1942 #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6) 1943 #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5) 1944 #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4) 1945 #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4) 1946 1947 /* SDVO is different across gen3/4 */ 1948 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) 1949 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) 1950 /* 1951 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, 1952 * since reality corrobates that they're the same as on gen3. But keep these 1953 * bits here (and the comment!) to help any other lost wanderers back onto the 1954 * right tracks. 1955 */ 1956 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) 1957 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) 1958 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) 1959 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) 1960 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \ 1961 SDVOB_HOTPLUG_INT_STATUS_G4X | \ 1962 SDVOC_HOTPLUG_INT_STATUS_G4X | \ 1963 PORTB_HOTPLUG_INT_STATUS | \ 1964 PORTC_HOTPLUG_INT_STATUS | \ 1965 PORTD_HOTPLUG_INT_STATUS) 1966 1967 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \ 1968 SDVOB_HOTPLUG_INT_STATUS_I915 | \ 1969 SDVOC_HOTPLUG_INT_STATUS_I915 | \ 1970 PORTB_HOTPLUG_INT_STATUS | \ 1971 PORTC_HOTPLUG_INT_STATUS | \ 1972 PORTD_HOTPLUG_INT_STATUS) 1973 1974 /* SDVO and HDMI port control. 1975 * The same register may be used for SDVO or HDMI */ 1976 #define _GEN3_SDVOB 0x61140 1977 #define _GEN3_SDVOC 0x61160 1978 #define GEN3_SDVOB _MMIO(_GEN3_SDVOB) 1979 #define GEN3_SDVOC _MMIO(_GEN3_SDVOC) 1980 #define GEN4_HDMIB GEN3_SDVOB 1981 #define GEN4_HDMIC GEN3_SDVOC 1982 #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140) 1983 #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160) 1984 #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C) 1985 #define PCH_SDVOB _MMIO(0xe1140) 1986 #define PCH_HDMIB PCH_SDVOB 1987 #define PCH_HDMIC _MMIO(0xe1150) 1988 #define PCH_HDMID _MMIO(0xe1160) 1989 1990 #define PORT_DFT_I9XX _MMIO(0x61150) 1991 #define DC_BALANCE_RESET (1 << 25) 1992 #define PORT_DFT2_G4X _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154) 1993 #define DC_BALANCE_RESET_VLV (1 << 31) 1994 #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0)) 1995 #define PIPE_C_SCRAMBLE_RESET REG_BIT(14) /* chv */ 1996 #define PIPE_B_SCRAMBLE_RESET REG_BIT(1) 1997 #define PIPE_A_SCRAMBLE_RESET REG_BIT(0) 1998 1999 /* Gen 3 SDVO bits: */ 2000 #define SDVO_ENABLE (1 << 31) 2001 #define SDVO_PIPE_SEL_SHIFT 30 2002 #define SDVO_PIPE_SEL_MASK (1 << 30) 2003 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30) 2004 #define SDVO_STALL_SELECT (1 << 29) 2005 #define SDVO_INTERRUPT_ENABLE (1 << 26) 2006 /* 2007 * 915G/GM SDVO pixel multiplier. 2008 * Programmed value is multiplier - 1, up to 5x. 2009 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 2010 */ 2011 #define SDVO_PORT_MULTIPLY_MASK (7 << 23) 2012 #define SDVO_PORT_MULTIPLY_SHIFT 23 2013 #define SDVO_PHASE_SELECT_MASK (15 << 19) 2014 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 2015 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 2016 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */ 2017 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */ 2018 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */ 2019 #define SDVO_DETECTED (1 << 2) 2020 /* Bits to be preserved when writing */ 2021 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \ 2022 SDVO_INTERRUPT_ENABLE) 2023 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE) 2024 2025 /* Gen 4 SDVO/HDMI bits: */ 2026 #define SDVO_COLOR_FORMAT_8bpc (0 << 26) 2027 #define SDVO_COLOR_FORMAT_MASK (7 << 26) 2028 #define SDVO_ENCODING_SDVO (0 << 10) 2029 #define SDVO_ENCODING_HDMI (2 << 10) 2030 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */ 2031 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */ 2032 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */ 2033 #define HDMI_AUDIO_ENABLE (1 << 6) /* HDMI only */ 2034 /* VSYNC/HSYNC bits new with 965, default is to be set */ 2035 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) 2036 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) 2037 2038 /* Gen 5 (IBX) SDVO/HDMI bits: */ 2039 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */ 2040 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */ 2041 2042 /* Gen 6 (CPT) SDVO/HDMI bits: */ 2043 #define SDVO_PIPE_SEL_SHIFT_CPT 29 2044 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29) 2045 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29) 2046 2047 /* CHV SDVO/HDMI bits: */ 2048 #define SDVO_PIPE_SEL_SHIFT_CHV 24 2049 #define SDVO_PIPE_SEL_MASK_CHV (3 << 24) 2050 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24) 2051 2052 /* Video Data Island Packet control */ 2053 #define VIDEO_DIP_DATA _MMIO(0x61178) 2054 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC 2055 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte 2056 * of the infoframe structure specified by CEA-861. */ 2057 #define VIDEO_DIP_DATA_SIZE 32 2058 #define VIDEO_DIP_ASYNC_DATA_SIZE 36 2059 #define VIDEO_DIP_GMP_DATA_SIZE 36 2060 #define VIDEO_DIP_VSC_DATA_SIZE 36 2061 #define VIDEO_DIP_PPS_DATA_SIZE 132 2062 #define VIDEO_DIP_CTL _MMIO(0x61170) 2063 /* Pre HSW: */ 2064 #define VIDEO_DIP_ENABLE (1 << 31) 2065 #define VIDEO_DIP_PORT(port) ((port) << 29) 2066 #define VIDEO_DIP_PORT_MASK (3 << 29) 2067 #define VIDEO_DIP_ENABLE_GCP (1 << 25) /* ilk+ */ 2068 #define VIDEO_DIP_ENABLE_AVI (1 << 21) 2069 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) 2070 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) /* ilk+ */ 2071 #define VIDEO_DIP_ENABLE_SPD (8 << 21) 2072 #define VIDEO_DIP_SELECT_AVI (0 << 19) 2073 #define VIDEO_DIP_SELECT_VENDOR (1 << 19) 2074 #define VIDEO_DIP_SELECT_GAMUT (2 << 19) 2075 #define VIDEO_DIP_SELECT_SPD (3 << 19) 2076 #define VIDEO_DIP_SELECT_MASK (3 << 19) 2077 #define VIDEO_DIP_FREQ_ONCE (0 << 16) 2078 #define VIDEO_DIP_FREQ_VSYNC (1 << 16) 2079 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) 2080 #define VIDEO_DIP_FREQ_MASK (3 << 16) 2081 /* HSW and later: */ 2082 #define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28) 2083 #define PSR_VSC_BIT_7_SET (1 << 27) 2084 #define VSC_SELECT_MASK (0x3 << 25) 2085 #define VSC_SELECT_SHIFT 25 2086 #define VSC_DIP_HW_HEA_DATA (0 << 25) 2087 #define VSC_DIP_HW_HEA_SW_DATA (1 << 25) 2088 #define VSC_DIP_HW_DATA_SW_HEA (2 << 25) 2089 #define VSC_DIP_SW_HEA_DATA (3 << 25) 2090 #define VDIP_ENABLE_PPS (1 << 24) 2091 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) 2092 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) 2093 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) 2094 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) 2095 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) 2096 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) 2097 /* ADL and later: */ 2098 #define VIDEO_DIP_ENABLE_AS_ADL REG_BIT(23) 2099 2100 /* Panel fitting */ 2101 #define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230) 2102 #define PFIT_ENABLE REG_BIT(31) 2103 #define PFIT_PIPE_MASK REG_GENMASK(30, 29) /* 965+ */ 2104 #define PFIT_PIPE(pipe) REG_FIELD_PREP(PFIT_PIPE_MASK, (pipe)) 2105 #define PFIT_SCALING_MASK REG_GENMASK(28, 26) /* 965+ */ 2106 #define PFIT_SCALING_AUTO REG_FIELD_PREP(PFIT_SCALING_MASK, 0) 2107 #define PFIT_SCALING_PROGRAMMED REG_FIELD_PREP(PFIT_SCALING_MASK, 1) 2108 #define PFIT_SCALING_PILLAR REG_FIELD_PREP(PFIT_SCALING_MASK, 2) 2109 #define PFIT_SCALING_LETTER REG_FIELD_PREP(PFIT_SCALING_MASK, 3) 2110 #define PFIT_FILTER_MASK REG_GENMASK(25, 24) /* 965+ */ 2111 #define PFIT_FILTER_FUZZY REG_FIELD_PREP(PFIT_FILTER_MASK, 0) 2112 #define PFIT_FILTER_CRISP REG_FIELD_PREP(PFIT_FILTER_MASK, 1) 2113 #define PFIT_FILTER_MEDIAN REG_FIELD_PREP(PFIT_FILTER_MASK, 2) 2114 #define PFIT_VERT_INTERP_MASK REG_GENMASK(11, 10) /* pre-965 */ 2115 #define PFIT_VERT_INTERP_BILINEAR REG_FIELD_PREP(PFIT_VERT_INTERP_MASK, 1) 2116 #define PFIT_VERT_AUTO_SCALE REG_BIT(9) /* pre-965 */ 2117 #define PFIT_HORIZ_INTERP_MASK REG_GENMASK(7, 6) /* pre-965 */ 2118 #define PFIT_HORIZ_INTERP_BILINEAR REG_FIELD_PREP(PFIT_HORIZ_INTERP_MASK, 1) 2119 #define PFIT_HORIZ_AUTO_SCALE REG_BIT(5) /* pre-965 */ 2120 #define PFIT_PANEL_8TO6_DITHER_ENABLE REG_BIT(3) /* pre-965 */ 2121 2122 #define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234) 2123 #define PFIT_VERT_SCALE_MASK REG_GENMASK(31, 20) /* pre-965 */ 2124 #define PFIT_VERT_SCALE(x) REG_FIELD_PREP(PFIT_VERT_SCALE_MASK, (x)) 2125 #define PFIT_HORIZ_SCALE_MASK REG_GENMASK(15, 4) /* pre-965 */ 2126 #define PFIT_HORIZ_SCALE(x) REG_FIELD_PREP(PFIT_HORIZ_SCALE_MASK, (x)) 2127 #define PFIT_VERT_SCALE_MASK_965 REG_GENMASK(28, 16) /* 965+ */ 2128 #define PFIT_HORIZ_SCALE_MASK_965 REG_GENMASK(12, 0) /* 965+ */ 2129 2130 #define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238) 2131 2132 #define PCH_GTC_CTL _MMIO(0xe7000) 2133 #define PCH_GTC_ENABLE (1 << 31) 2134 2135 /* Display Port */ 2136 #define DP_A _MMIO(0x64000) /* eDP */ 2137 #define DP_B _MMIO(0x64100) 2138 #define DP_C _MMIO(0x64200) 2139 #define DP_D _MMIO(0x64300) 2140 2141 #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100) 2142 #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200) 2143 #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300) 2144 2145 #define DP_PORT_EN (1 << 31) 2146 #define DP_PIPE_SEL_SHIFT 30 2147 #define DP_PIPE_SEL_MASK (1 << 30) 2148 #define DP_PIPE_SEL(pipe) ((pipe) << 30) 2149 #define DP_PIPE_SEL_SHIFT_IVB 29 2150 #define DP_PIPE_SEL_MASK_IVB (3 << 29) 2151 #define DP_PIPE_SEL_IVB(pipe) ((pipe) << 29) 2152 #define DP_PIPE_SEL_SHIFT_CHV 16 2153 #define DP_PIPE_SEL_MASK_CHV (3 << 16) 2154 #define DP_PIPE_SEL_CHV(pipe) ((pipe) << 16) 2155 2156 /* Link training mode - select a suitable mode for each stage */ 2157 #define DP_LINK_TRAIN_PAT_1 (0 << 28) 2158 #define DP_LINK_TRAIN_PAT_2 (1 << 28) 2159 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) 2160 #define DP_LINK_TRAIN_OFF (3 << 28) 2161 #define DP_LINK_TRAIN_MASK (3 << 28) 2162 #define DP_LINK_TRAIN_SHIFT 28 2163 2164 /* CPT Link training mode */ 2165 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) 2166 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) 2167 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) 2168 #define DP_LINK_TRAIN_OFF_CPT (3 << 8) 2169 #define DP_LINK_TRAIN_MASK_CPT (7 << 8) 2170 #define DP_LINK_TRAIN_SHIFT_CPT 8 2171 2172 /* Signal voltages. These are mostly controlled by the other end */ 2173 #define DP_VOLTAGE_0_4 (0 << 25) 2174 #define DP_VOLTAGE_0_6 (1 << 25) 2175 #define DP_VOLTAGE_0_8 (2 << 25) 2176 #define DP_VOLTAGE_1_2 (3 << 25) 2177 #define DP_VOLTAGE_MASK (7 << 25) 2178 #define DP_VOLTAGE_SHIFT 25 2179 2180 /* Signal pre-emphasis levels, like voltages, the other end tells us what 2181 * they want 2182 */ 2183 #define DP_PRE_EMPHASIS_0 (0 << 22) 2184 #define DP_PRE_EMPHASIS_3_5 (1 << 22) 2185 #define DP_PRE_EMPHASIS_6 (2 << 22) 2186 #define DP_PRE_EMPHASIS_9_5 (3 << 22) 2187 #define DP_PRE_EMPHASIS_MASK (7 << 22) 2188 #define DP_PRE_EMPHASIS_SHIFT 22 2189 2190 /* How many wires to use. I guess 3 was too hard */ 2191 #define DP_PORT_WIDTH(width) (((width) - 1) << 19) 2192 #define DP_PORT_WIDTH_MASK (7 << 19) 2193 #define DP_PORT_WIDTH_SHIFT 19 2194 2195 /* Mystic DPCD version 1.1 special mode */ 2196 #define DP_ENHANCED_FRAMING (1 << 18) 2197 2198 /* eDP */ 2199 #define DP_PLL_FREQ_270MHZ (0 << 16) 2200 #define DP_PLL_FREQ_162MHZ (1 << 16) 2201 #define DP_PLL_FREQ_MASK (3 << 16) 2202 2203 /* locked once port is enabled */ 2204 #define DP_PORT_REVERSAL (1 << 15) 2205 2206 /* eDP */ 2207 #define DP_PLL_ENABLE (1 << 14) 2208 2209 /* sends the clock on lane 15 of the PEG for debug */ 2210 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 2211 2212 #define DP_SCRAMBLING_DISABLE (1 << 12) 2213 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) 2214 2215 /* limit RGB values to avoid confusing TVs */ 2216 #define DP_COLOR_RANGE_16_235 (1 << 8) 2217 2218 /* Turn on the audio link */ 2219 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) 2220 2221 /* vs and hs sync polarity */ 2222 #define DP_SYNC_VS_HIGH (1 << 4) 2223 #define DP_SYNC_HS_HIGH (1 << 3) 2224 2225 /* A fantasy */ 2226 #define DP_DETECTED (1 << 2) 2227 2228 /* 2229 * Computing GMCH M and N values for the Display Port link 2230 * 2231 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes 2232 * 2233 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) 2234 * 2235 * The GMCH value is used internally 2236 * 2237 * bytes_per_pixel is the number of bytes coming out of the plane, 2238 * which is after the LUTs, so we want the bytes for our color format. 2239 * For our current usage, this is always 3, one byte for R, G and B. 2240 */ 2241 #define _PIPEA_DATA_M_G4X 0x70050 2242 #define _PIPEB_DATA_M_G4X 0x71050 2243 2244 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 2245 #define TU_SIZE_MASK REG_GENMASK(30, 25) 2246 #define TU_SIZE(x) REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */ 2247 2248 #define DATA_LINK_M_N_MASK REG_GENMASK(23, 0) 2249 #define DATA_LINK_N_MAX (0x800000) 2250 2251 #define _PIPEA_DATA_N_G4X 0x70054 2252 #define _PIPEB_DATA_N_G4X 0x71054 2253 2254 /* 2255 * Computing Link M and N values for the Display Port link 2256 * 2257 * Link M / N = pixel_clock / ls_clk 2258 * 2259 * (the DP spec calls pixel_clock the 'strm_clk') 2260 * 2261 * The Link value is transmitted in the Main Stream 2262 * Attributes and VB-ID. 2263 */ 2264 2265 #define _PIPEA_LINK_M_G4X 0x70060 2266 #define _PIPEB_LINK_M_G4X 0x71060 2267 #define _PIPEA_LINK_N_G4X 0x70064 2268 #define _PIPEB_LINK_N_G4X 0x71064 2269 2270 #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X) 2271 #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X) 2272 #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X) 2273 #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X) 2274 2275 /* Display & cursor control */ 2276 2277 /* Pipe A */ 2278 #define _PIPEADSL 0x70000 2279 #define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */ 2280 #define PIPEDSL_LINE_MASK REG_GENMASK(19, 0) 2281 #define _TRANSACONF 0x70008 2282 #define TRANSCONF_ENABLE REG_BIT(31) 2283 #define TRANSCONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */ 2284 #define TRANSCONF_STATE_ENABLE REG_BIT(30) /* i965+ */ 2285 #define TRANSCONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv & pipe A only */ 2286 #define TRANSCONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */ 2287 #define TRANSCONF_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANSCONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */ 2288 #define TRANSCONF_PIPE_LOCKED REG_BIT(25) 2289 #define TRANSCONF_FORCE_BORDER REG_BIT(25) 2290 #define TRANSCONF_GAMMA_MODE_MASK_I9XX REG_BIT(24) /* gmch */ 2291 #define TRANSCONF_GAMMA_MODE_MASK_ILK REG_GENMASK(25, 24) /* ilk-ivb */ 2292 #define TRANSCONF_GAMMA_MODE_8BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 0) 2293 #define TRANSCONF_GAMMA_MODE_10BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 1) 2294 #define TRANSCONF_GAMMA_MODE_12BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */ 2295 #define TRANSCONF_GAMMA_MODE_SPLIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */ 2296 #define TRANSCONF_GAMMA_MODE(x) REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */ 2297 #define TRANSCONF_INTERLACE_MASK REG_GENMASK(23, 21) /* gen3+ */ 2298 #define TRANSCONF_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 0) 2299 #define TRANSCONF_INTERLACE_W_SYNC_SHIFT_PANEL REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 4) /* gen4 only */ 2300 #define TRANSCONF_INTERLACE_W_SYNC_SHIFT REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 5) /* gen4 only */ 2301 #define TRANSCONF_INTERLACE_W_FIELD_INDICATION REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 6) 2302 #define TRANSCONF_INTERLACE_FIELD_0_ONLY REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 7) /* gen3 only */ 2303 /* 2304 * ilk+: PF/D=progressive fetch/display, IF/D=interlaced fetch/display, 2305 * DBL=power saving pixel doubling, PF-ID* requires panel fitter 2306 */ 2307 #define TRANSCONF_INTERLACE_MASK_ILK REG_GENMASK(23, 21) /* ilk+ */ 2308 #define TRANSCONF_INTERLACE_MASK_HSW REG_GENMASK(22, 21) /* hsw+ */ 2309 #define TRANSCONF_INTERLACE_PF_PD_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 0) 2310 #define TRANSCONF_INTERLACE_PF_ID_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 1) 2311 #define TRANSCONF_INTERLACE_IF_ID_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 3) 2312 #define TRANSCONF_INTERLACE_IF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */ 2313 #define TRANSCONF_INTERLACE_PF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */ 2314 #define TRANSCONF_REFRESH_RATE_ALT_ILK REG_BIT(20) 2315 #define TRANSCONF_MSA_TIMING_DELAY_MASK REG_GENMASK(19, 18) /* ilk/snb/ivb */ 2316 #define TRANSCONF_MSA_TIMING_DELAY(x) REG_FIELD_PREP(TRANSCONF_MSA_TIMING_DELAY_MASK, (x)) 2317 #define TRANSCONF_CXSR_DOWNCLOCK REG_BIT(16) 2318 #define TRANSCONF_WGC_ENABLE REG_BIT(15) /* vlv/chv only */ 2319 #define TRANSCONF_REFRESH_RATE_ALT_VLV REG_BIT(14) 2320 #define TRANSCONF_COLOR_RANGE_SELECT REG_BIT(13) 2321 #define TRANSCONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */ 2322 #define TRANSCONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */ 2323 #define TRANSCONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */ 2324 #define TRANSCONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */ 2325 #define TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11) /* hsw only */ 2326 #define TRANSCONF_BPC_MASK REG_GENMASK(7, 5) /* ctg-ivb */ 2327 #define TRANSCONF_BPC_8 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 0) 2328 #define TRANSCONF_BPC_10 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 1) 2329 #define TRANSCONF_BPC_6 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 2) 2330 #define TRANSCONF_BPC_12 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 3) 2331 #define TRANSCONF_DITHER_EN REG_BIT(4) 2332 #define TRANSCONF_DITHER_TYPE_MASK REG_GENMASK(3, 2) 2333 #define TRANSCONF_DITHER_TYPE_SP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 0) 2334 #define TRANSCONF_DITHER_TYPE_ST1 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 1) 2335 #define TRANSCONF_DITHER_TYPE_ST2 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 2) 2336 #define TRANSCONF_DITHER_TYPE_TEMP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 3) 2337 #define TRANSCONF_PIXEL_COUNT_SCALING_MASK REG_GENMASK(1, 0) 2338 #define TRANSCONF_PIXEL_COUNT_SCALING_X4 1 2339 2340 #define _PIPEASTAT 0x70024 2341 #define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31) 2342 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30) 2343 #define PIPE_CRC_ERROR_ENABLE (1UL << 29) 2344 #define PIPE_CRC_DONE_ENABLE (1UL << 28) 2345 #define PERF_COUNTER2_INTERRUPT_EN (1UL << 27) 2346 #define PIPE_GMBUS_EVENT_ENABLE (1UL << 27) 2347 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26) 2348 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26) 2349 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25) 2350 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24) 2351 #define PIPE_DPST_EVENT_ENABLE (1UL << 23) 2352 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22) 2353 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22) 2354 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21) 2355 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20) 2356 #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL << 19) 2357 #define PERF_COUNTER_INTERRUPT_EN (1UL << 19) 2358 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */ 2359 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) /* 965 or later */ 2360 #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL << 17) 2361 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17) 2362 #define PIPEA_HBLANK_INT_EN_VLV (1UL << 16) 2363 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16) 2364 #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL << 15) 2365 #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL << 14) 2366 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13) 2367 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12) 2368 #define PERF_COUNTER2_INTERRUPT_STATUS (1UL << 11) 2369 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11) 2370 #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL << 10) 2371 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10) 2372 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9) 2373 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8) 2374 #define PIPE_DPST_EVENT_STATUS (1UL << 7) 2375 #define PIPE_A_PSR_STATUS_VLV (1UL << 6) 2376 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6) 2377 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5) 2378 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4) 2379 #define PIPE_B_PSR_STATUS_VLV (1UL << 3) 2380 #define PERF_COUNTER_INTERRUPT_STATUS (1UL << 3) 2381 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */ 2382 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) /* 965 or later */ 2383 #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL << 1) 2384 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1) 2385 #define PIPE_HBLANK_INT_STATUS (1UL << 0) 2386 #define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0) 2387 2388 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 2389 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff 2390 2391 #define TRANSCONF(trans) _MMIO_PIPE2((trans), _TRANSACONF) 2392 #define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL) 2393 #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH) 2394 #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL) 2395 #define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT) 2396 2397 #define _PIPEAGCMAX 0x70010 2398 #define _PIPEBGCMAX 0x71010 2399 #define PIPEGCMAX(pipe, i) _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4) /* u1.16 */ 2400 2401 #define _PIPE_ARB_CTL_A 0x70028 /* icl+ */ 2402 #define PIPE_ARB_CTL(pipe) _MMIO_PIPE2(pipe, _PIPE_ARB_CTL_A) 2403 #define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13) 2404 2405 #define _PIPE_MISC_A 0x70030 2406 #define _PIPE_MISC_B 0x71030 2407 #define PIPE_MISC_YUV420_ENABLE REG_BIT(27) /* glk+ */ 2408 #define PIPE_MISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */ 2409 #define PIPE_MISC_HDR_MODE_PRECISION REG_BIT(23) /* icl+ */ 2410 #define PIPE_MISC_PSR_MASK_PRIMARY_FLIP REG_BIT(23) /* bdw */ 2411 #define PIPE_MISC_PSR_MASK_SPRITE_ENABLE REG_BIT(22) /* bdw */ 2412 #define PIPE_MISC_PSR_MASK_PIPE_REG_WRITE REG_BIT(21) /* skl+ */ 2413 #define PIPE_MISC_PSR_MASK_CURSOR_MOVE REG_BIT(21) /* bdw */ 2414 #define PIPE_MISC_PSR_MASK_VBLANK_VSYNC_INT REG_BIT(20) 2415 #define PIPE_MISC_OUTPUT_COLORSPACE_YUV REG_BIT(11) 2416 #define PIPE_MISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */ 2417 /* 2418 * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with 2419 * valid values of: 6, 8, 10 BPC. 2420 * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of: 2421 * 6, 8, 10, 12 BPC. 2422 */ 2423 #define PIPE_MISC_BPC_MASK REG_GENMASK(7, 5) 2424 #define PIPE_MISC_BPC_8 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 0) 2425 #define PIPE_MISC_BPC_10 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 1) 2426 #define PIPE_MISC_BPC_6 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 2) 2427 #define PIPE_MISC_BPC_12_ADLP REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 4) /* adlp+ */ 2428 #define PIPE_MISC_DITHER_ENABLE REG_BIT(4) 2429 #define PIPE_MISC_DITHER_TYPE_MASK REG_GENMASK(3, 2) 2430 #define PIPE_MISC_DITHER_TYPE_SP REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 0) 2431 #define PIPE_MISC_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 1) 2432 #define PIPE_MISC_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 2) 2433 #define PIPE_MISC_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 3) 2434 #define PIPE_MISC(pipe) _MMIO_PIPE(pipe, _PIPE_MISC_A, _PIPE_MISC_B) 2435 2436 #define _PIPE_MISC2_A 0x7002C 2437 #define _PIPE_MISC2_B 0x7102C 2438 #define PIPE_MISC2_BUBBLE_COUNTER_MASK REG_GENMASK(31, 24) 2439 #define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80) 2440 #define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20) 2441 #define PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK REG_GENMASK(2, 0) /* tgl+ */ 2442 #define PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id) REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id)) 2443 #define PIPE_MISC2(pipe) _MMIO_PIPE(pipe, _PIPE_MISC2_A, _PIPE_MISC2_B) 2444 2445 #define _ICL_PIPE_A_STATUS 0x70058 2446 #define ICL_PIPESTATUS(pipe) _MMIO_PIPE2(pipe, _ICL_PIPE_A_STATUS) 2447 #define PIPE_STATUS_UNDERRUN REG_BIT(31) 2448 #define PIPE_STATUS_SOFT_UNDERRUN_XELPD REG_BIT(28) 2449 #define PIPE_STATUS_HARD_UNDERRUN_XELPD REG_BIT(27) 2450 #define PIPE_STATUS_PORT_UNDERRUN_XELPD REG_BIT(26) 2451 2452 #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028) 2453 #define PIPEB_LINE_COMPARE_INT_EN REG_BIT(29) 2454 #define PIPEB_HLINE_INT_EN REG_BIT(28) 2455 #define PIPEB_VBLANK_INT_EN REG_BIT(27) 2456 #define SPRITED_FLIP_DONE_INT_EN REG_BIT(26) 2457 #define SPRITEC_FLIP_DONE_INT_EN REG_BIT(25) 2458 #define PLANEB_FLIP_DONE_INT_EN REG_BIT(24) 2459 #define PIPE_PSR_INT_EN REG_BIT(22) 2460 #define PIPEA_LINE_COMPARE_INT_EN REG_BIT(21) 2461 #define PIPEA_HLINE_INT_EN REG_BIT(20) 2462 #define PIPEA_VBLANK_INT_EN REG_BIT(19) 2463 #define SPRITEB_FLIP_DONE_INT_EN REG_BIT(18) 2464 #define SPRITEA_FLIP_DONE_INT_EN REG_BIT(17) 2465 #define PLANEA_FLIPDONE_INT_EN REG_BIT(16) 2466 #define PIPEC_LINE_COMPARE_INT_EN REG_BIT(13) 2467 #define PIPEC_HLINE_INT_EN REG_BIT(12) 2468 #define PIPEC_VBLANK_INT_EN REG_BIT(11) 2469 #define SPRITEF_FLIPDONE_INT_EN REG_BIT(10) 2470 #define SPRITEE_FLIPDONE_INT_EN REG_BIT(9) 2471 #define PLANEC_FLIPDONE_INT_EN REG_BIT(8) 2472 2473 #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ 2474 #define DPINVGTT_EN_MASK_CHV REG_GENMASK(27, 16) 2475 #define DPINVGTT_EN_MASK_VLV REG_GENMASK(23, 16) 2476 #define SPRITEF_INVALID_GTT_INT_EN REG_BIT(27) 2477 #define SPRITEE_INVALID_GTT_INT_EN REG_BIT(26) 2478 #define PLANEC_INVALID_GTT_INT_EN REG_BIT(25) 2479 #define CURSORC_INVALID_GTT_INT_EN REG_BIT(24) 2480 #define CURSORB_INVALID_GTT_INT_EN REG_BIT(23) 2481 #define CURSORA_INVALID_GTT_INT_EN REG_BIT(22) 2482 #define SPRITED_INVALID_GTT_INT_EN REG_BIT(21) 2483 #define SPRITEC_INVALID_GTT_INT_EN REG_BIT(20) 2484 #define PLANEB_INVALID_GTT_INT_EN REG_BIT(19) 2485 #define SPRITEB_INVALID_GTT_INT_EN REG_BIT(18) 2486 #define SPRITEA_INVALID_GTT_INT_EN REG_BIT(17) 2487 #define PLANEA_INVALID_GTT_INT_EN REG_BIT(16) 2488 #define DPINVGTT_STATUS_MASK_CHV REG_GENMASK(11, 0) 2489 #define DPINVGTT_STATUS_MASK_VLV REG_GENMASK(7, 0) 2490 #define SPRITEF_INVALID_GTT_STATUS REG_BIT(11) 2491 #define SPRITEE_INVALID_GTT_STATUS REG_BIT(10) 2492 #define PLANEC_INVALID_GTT_STATUS REG_BIT(9) 2493 #define CURSORC_INVALID_GTT_STATUS REG_BIT(8) 2494 #define CURSORB_INVALID_GTT_STATUS REG_BIT(7) 2495 #define CURSORA_INVALID_GTT_STATUS REG_BIT(6) 2496 #define SPRITED_INVALID_GTT_STATUS REG_BIT(5) 2497 #define SPRITEC_INVALID_GTT_STATUS REG_BIT(4) 2498 #define PLANEB_INVALID_GTT_STATUS REG_BIT(3) 2499 #define SPRITEB_INVALID_GTT_STATUS REG_BIT(2) 2500 #define SPRITEA_INVALID_GTT_STATUS REG_BIT(1) 2501 #define PLANEA_INVALID_GTT_STATUS REG_BIT(0) 2502 2503 #define DSPARB _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030) 2504 #define DSPARB_CSTART_MASK (0x7f << 7) 2505 #define DSPARB_CSTART_SHIFT 7 2506 #define DSPARB_BSTART_MASK (0x7f) 2507 #define DSPARB_BSTART_SHIFT 0 2508 #define DSPARB_BEND_SHIFT 9 /* on 855 */ 2509 #define DSPARB_AEND_SHIFT 0 2510 #define DSPARB_SPRITEA_SHIFT_VLV 0 2511 #define DSPARB_SPRITEA_MASK_VLV (0xff << 0) 2512 #define DSPARB_SPRITEB_SHIFT_VLV 8 2513 #define DSPARB_SPRITEB_MASK_VLV (0xff << 8) 2514 #define DSPARB_SPRITEC_SHIFT_VLV 16 2515 #define DSPARB_SPRITEC_MASK_VLV (0xff << 16) 2516 #define DSPARB_SPRITED_SHIFT_VLV 24 2517 #define DSPARB_SPRITED_MASK_VLV (0xff << 24) 2518 #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */ 2519 #define DSPARB_SPRITEA_HI_SHIFT_VLV 0 2520 #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0) 2521 #define DSPARB_SPRITEB_HI_SHIFT_VLV 4 2522 #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4) 2523 #define DSPARB_SPRITEC_HI_SHIFT_VLV 8 2524 #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8) 2525 #define DSPARB_SPRITED_HI_SHIFT_VLV 12 2526 #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12) 2527 #define DSPARB_SPRITEE_HI_SHIFT_VLV 16 2528 #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16) 2529 #define DSPARB_SPRITEF_HI_SHIFT_VLV 20 2530 #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20) 2531 #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */ 2532 #define DSPARB_SPRITEE_SHIFT_VLV 0 2533 #define DSPARB_SPRITEE_MASK_VLV (0xff << 0) 2534 #define DSPARB_SPRITEF_SHIFT_VLV 8 2535 #define DSPARB_SPRITEF_MASK_VLV (0xff << 8) 2536 2537 /* pnv/gen4/g4x/vlv/chv */ 2538 #define DSPFW1 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034) 2539 #define DSPFW_SR_SHIFT 23 2540 #define DSPFW_SR_MASK (0x1ff << 23) 2541 #define DSPFW_CURSORB_SHIFT 16 2542 #define DSPFW_CURSORB_MASK (0x3f << 16) 2543 #define DSPFW_PLANEB_SHIFT 8 2544 #define DSPFW_PLANEB_MASK (0x7f << 8) 2545 #define DSPFW_PLANEB_MASK_VLV (0xff << 8) /* vlv/chv */ 2546 #define DSPFW_PLANEA_SHIFT 0 2547 #define DSPFW_PLANEA_MASK (0x7f << 0) 2548 #define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */ 2549 #define DSPFW2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038) 2550 #define DSPFW_FBC_SR_EN (1 << 31) /* g4x */ 2551 #define DSPFW_FBC_SR_SHIFT 28 2552 #define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */ 2553 #define DSPFW_FBC_HPLL_SR_SHIFT 24 2554 #define DSPFW_FBC_HPLL_SR_MASK (0xf << 24) /* g4x */ 2555 #define DSPFW_SPRITEB_SHIFT (16) 2556 #define DSPFW_SPRITEB_MASK (0x7f << 16) /* g4x */ 2557 #define DSPFW_SPRITEB_MASK_VLV (0xff << 16) /* vlv/chv */ 2558 #define DSPFW_CURSORA_SHIFT 8 2559 #define DSPFW_CURSORA_MASK (0x3f << 8) 2560 #define DSPFW_PLANEC_OLD_SHIFT 0 2561 #define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */ 2562 #define DSPFW_SPRITEA_SHIFT 0 2563 #define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */ 2564 #define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */ 2565 #define DSPFW3 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c) 2566 #define DSPFW_HPLL_SR_EN (1 << 31) 2567 #define PINEVIEW_SELF_REFRESH_EN (1 << 30) 2568 #define DSPFW_CURSOR_SR_SHIFT 24 2569 #define DSPFW_CURSOR_SR_MASK (0x3f << 24) 2570 #define DSPFW_HPLL_CURSOR_SHIFT 16 2571 #define DSPFW_HPLL_CURSOR_MASK (0x3f << 16) 2572 #define DSPFW_HPLL_SR_SHIFT 0 2573 #define DSPFW_HPLL_SR_MASK (0x1ff << 0) 2574 2575 /* vlv/chv */ 2576 #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070) 2577 #define DSPFW_SPRITEB_WM1_SHIFT 16 2578 #define DSPFW_SPRITEB_WM1_MASK (0xff << 16) 2579 #define DSPFW_CURSORA_WM1_SHIFT 8 2580 #define DSPFW_CURSORA_WM1_MASK (0x3f << 8) 2581 #define DSPFW_SPRITEA_WM1_SHIFT 0 2582 #define DSPFW_SPRITEA_WM1_MASK (0xff << 0) 2583 #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074) 2584 #define DSPFW_PLANEB_WM1_SHIFT 24 2585 #define DSPFW_PLANEB_WM1_MASK (0xff << 24) 2586 #define DSPFW_PLANEA_WM1_SHIFT 16 2587 #define DSPFW_PLANEA_WM1_MASK (0xff << 16) 2588 #define DSPFW_CURSORB_WM1_SHIFT 8 2589 #define DSPFW_CURSORB_WM1_MASK (0x3f << 8) 2590 #define DSPFW_CURSOR_SR_WM1_SHIFT 0 2591 #define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0) 2592 #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078) 2593 #define DSPFW_SR_WM1_SHIFT 0 2594 #define DSPFW_SR_WM1_MASK (0x1ff << 0) 2595 #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c) 2596 #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */ 2597 #define DSPFW_SPRITED_WM1_SHIFT 24 2598 #define DSPFW_SPRITED_WM1_MASK (0xff << 24) 2599 #define DSPFW_SPRITED_SHIFT 16 2600 #define DSPFW_SPRITED_MASK_VLV (0xff << 16) 2601 #define DSPFW_SPRITEC_WM1_SHIFT 8 2602 #define DSPFW_SPRITEC_WM1_MASK (0xff << 8) 2603 #define DSPFW_SPRITEC_SHIFT 0 2604 #define DSPFW_SPRITEC_MASK_VLV (0xff << 0) 2605 #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8) 2606 #define DSPFW_SPRITEF_WM1_SHIFT 24 2607 #define DSPFW_SPRITEF_WM1_MASK (0xff << 24) 2608 #define DSPFW_SPRITEF_SHIFT 16 2609 #define DSPFW_SPRITEF_MASK_VLV (0xff << 16) 2610 #define DSPFW_SPRITEE_WM1_SHIFT 8 2611 #define DSPFW_SPRITEE_WM1_MASK (0xff << 8) 2612 #define DSPFW_SPRITEE_SHIFT 0 2613 #define DSPFW_SPRITEE_MASK_VLV (0xff << 0) 2614 #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */ 2615 #define DSPFW_PLANEC_WM1_SHIFT 24 2616 #define DSPFW_PLANEC_WM1_MASK (0xff << 24) 2617 #define DSPFW_PLANEC_SHIFT 16 2618 #define DSPFW_PLANEC_MASK_VLV (0xff << 16) 2619 #define DSPFW_CURSORC_WM1_SHIFT 8 2620 #define DSPFW_CURSORC_WM1_MASK (0x3f << 16) 2621 #define DSPFW_CURSORC_SHIFT 0 2622 #define DSPFW_CURSORC_MASK (0x3f << 0) 2623 2624 /* vlv/chv high order bits */ 2625 #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064) 2626 #define DSPFW_SR_HI_SHIFT 24 2627 #define DSPFW_SR_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */ 2628 #define DSPFW_SPRITEF_HI_SHIFT 23 2629 #define DSPFW_SPRITEF_HI_MASK (1 << 23) 2630 #define DSPFW_SPRITEE_HI_SHIFT 22 2631 #define DSPFW_SPRITEE_HI_MASK (1 << 22) 2632 #define DSPFW_PLANEC_HI_SHIFT 21 2633 #define DSPFW_PLANEC_HI_MASK (1 << 21) 2634 #define DSPFW_SPRITED_HI_SHIFT 20 2635 #define DSPFW_SPRITED_HI_MASK (1 << 20) 2636 #define DSPFW_SPRITEC_HI_SHIFT 16 2637 #define DSPFW_SPRITEC_HI_MASK (1 << 16) 2638 #define DSPFW_PLANEB_HI_SHIFT 12 2639 #define DSPFW_PLANEB_HI_MASK (1 << 12) 2640 #define DSPFW_SPRITEB_HI_SHIFT 8 2641 #define DSPFW_SPRITEB_HI_MASK (1 << 8) 2642 #define DSPFW_SPRITEA_HI_SHIFT 4 2643 #define DSPFW_SPRITEA_HI_MASK (1 << 4) 2644 #define DSPFW_PLANEA_HI_SHIFT 0 2645 #define DSPFW_PLANEA_HI_MASK (1 << 0) 2646 #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068) 2647 #define DSPFW_SR_WM1_HI_SHIFT 24 2648 #define DSPFW_SR_WM1_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */ 2649 #define DSPFW_SPRITEF_WM1_HI_SHIFT 23 2650 #define DSPFW_SPRITEF_WM1_HI_MASK (1 << 23) 2651 #define DSPFW_SPRITEE_WM1_HI_SHIFT 22 2652 #define DSPFW_SPRITEE_WM1_HI_MASK (1 << 22) 2653 #define DSPFW_PLANEC_WM1_HI_SHIFT 21 2654 #define DSPFW_PLANEC_WM1_HI_MASK (1 << 21) 2655 #define DSPFW_SPRITED_WM1_HI_SHIFT 20 2656 #define DSPFW_SPRITED_WM1_HI_MASK (1 << 20) 2657 #define DSPFW_SPRITEC_WM1_HI_SHIFT 16 2658 #define DSPFW_SPRITEC_WM1_HI_MASK (1 << 16) 2659 #define DSPFW_PLANEB_WM1_HI_SHIFT 12 2660 #define DSPFW_PLANEB_WM1_HI_MASK (1 << 12) 2661 #define DSPFW_SPRITEB_WM1_HI_SHIFT 8 2662 #define DSPFW_SPRITEB_WM1_HI_MASK (1 << 8) 2663 #define DSPFW_SPRITEA_WM1_HI_SHIFT 4 2664 #define DSPFW_SPRITEA_WM1_HI_MASK (1 << 4) 2665 #define DSPFW_PLANEA_WM1_HI_SHIFT 0 2666 #define DSPFW_PLANEA_WM1_HI_MASK (1 << 0) 2667 2668 /* drain latency register values*/ 2669 #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe)) 2670 #define DDL_CURSOR_SHIFT 24 2671 #define DDL_SPRITE_SHIFT(sprite) (8 + 8 * (sprite)) 2672 #define DDL_PLANE_SHIFT 0 2673 #define DDL_PRECISION_HIGH (1 << 7) 2674 #define DDL_PRECISION_LOW (0 << 7) 2675 #define DRAIN_LATENCY_MASK 0x7f 2676 2677 #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400) 2678 #define CBR_PND_DEADLINE_DISABLE (1 << 31) 2679 #define CBR_PWM_CLOCK_MUX_SELECT (1 << 30) 2680 2681 #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450) 2682 #define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */ 2683 2684 /* FIFO watermark sizes etc */ 2685 #define G4X_FIFO_LINE_SIZE 64 2686 #define I915_FIFO_LINE_SIZE 64 2687 #define I830_FIFO_LINE_SIZE 32 2688 2689 #define VALLEYVIEW_FIFO_SIZE 255 2690 #define G4X_FIFO_SIZE 127 2691 #define I965_FIFO_SIZE 512 2692 #define I945_FIFO_SIZE 127 2693 #define I915_FIFO_SIZE 95 2694 #define I855GM_FIFO_SIZE 127 /* In cachelines */ 2695 #define I830_FIFO_SIZE 95 2696 2697 #define VALLEYVIEW_MAX_WM 0xff 2698 #define G4X_MAX_WM 0x3f 2699 #define I915_MAX_WM 0x3f 2700 2701 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ 2702 #define PINEVIEW_FIFO_LINE_SIZE 64 2703 #define PINEVIEW_MAX_WM 0x1ff 2704 #define PINEVIEW_DFT_WM 0x3f 2705 #define PINEVIEW_DFT_HPLLOFF_WM 0 2706 #define PINEVIEW_GUARD_WM 10 2707 #define PINEVIEW_CURSOR_FIFO 64 2708 #define PINEVIEW_CURSOR_MAX_WM 0x3f 2709 #define PINEVIEW_CURSOR_DFT_WM 0 2710 #define PINEVIEW_CURSOR_GUARD_WM 5 2711 2712 #define VALLEYVIEW_CURSOR_MAX_WM 64 2713 #define I965_CURSOR_FIFO 64 2714 #define I965_CURSOR_MAX_WM 32 2715 #define I965_CURSOR_DFT_WM 8 2716 2717 /* define the Watermark register on Ironlake */ 2718 #define _WM0_PIPEA_ILK 0x45100 2719 #define _WM0_PIPEB_ILK 0x45104 2720 #define _WM0_PIPEC_IVB 0x45200 2721 #define WM0_PIPE_ILK(pipe) _MMIO_PIPE3((pipe), _WM0_PIPEA_ILK, \ 2722 _WM0_PIPEB_ILK, _WM0_PIPEC_IVB) 2723 #define WM0_PIPE_PRIMARY_MASK REG_GENMASK(31, 16) 2724 #define WM0_PIPE_SPRITE_MASK REG_GENMASK(15, 8) 2725 #define WM0_PIPE_CURSOR_MASK REG_GENMASK(7, 0) 2726 #define WM0_PIPE_PRIMARY(x) REG_FIELD_PREP(WM0_PIPE_PRIMARY_MASK, (x)) 2727 #define WM0_PIPE_SPRITE(x) REG_FIELD_PREP(WM0_PIPE_SPRITE_MASK, (x)) 2728 #define WM0_PIPE_CURSOR(x) REG_FIELD_PREP(WM0_PIPE_CURSOR_MASK, (x)) 2729 #define WM1_LP_ILK _MMIO(0x45108) 2730 #define WM2_LP_ILK _MMIO(0x4510c) 2731 #define WM3_LP_ILK _MMIO(0x45110) 2732 #define WM_LP_ENABLE REG_BIT(31) 2733 #define WM_LP_LATENCY_MASK REG_GENMASK(30, 24) 2734 #define WM_LP_FBC_MASK_BDW REG_GENMASK(23, 19) 2735 #define WM_LP_FBC_MASK_ILK REG_GENMASK(23, 20) 2736 #define WM_LP_PRIMARY_MASK REG_GENMASK(18, 8) 2737 #define WM_LP_CURSOR_MASK REG_GENMASK(7, 0) 2738 #define WM_LP_LATENCY(x) REG_FIELD_PREP(WM_LP_LATENCY_MASK, (x)) 2739 #define WM_LP_FBC_BDW(x) REG_FIELD_PREP(WM_LP_FBC_MASK_BDW, (x)) 2740 #define WM_LP_FBC_ILK(x) REG_FIELD_PREP(WM_LP_FBC_MASK_ILK, (x)) 2741 #define WM_LP_PRIMARY(x) REG_FIELD_PREP(WM_LP_PRIMARY_MASK, (x)) 2742 #define WM_LP_CURSOR(x) REG_FIELD_PREP(WM_LP_CURSOR_MASK, (x)) 2743 #define WM1S_LP_ILK _MMIO(0x45120) 2744 #define WM2S_LP_IVB _MMIO(0x45124) 2745 #define WM3S_LP_IVB _MMIO(0x45128) 2746 #define WM_LP_SPRITE_ENABLE REG_BIT(31) /* ilk/snb WM1S only */ 2747 #define WM_LP_SPRITE_MASK REG_GENMASK(10, 0) 2748 #define WM_LP_SPRITE(x) REG_FIELD_PREP(WM_LP_SPRITE_MASK, (x)) 2749 2750 /* 2751 * The two pipe frame counter registers are not synchronized, so 2752 * reading a stable value is somewhat tricky. The following code 2753 * should work: 2754 * 2755 * do { 2756 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 2757 * PIPE_FRAME_HIGH_SHIFT; 2758 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 2759 * PIPE_FRAME_LOW_SHIFT); 2760 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 2761 * PIPE_FRAME_HIGH_SHIFT); 2762 * } while (high1 != high2); 2763 * frame = (high1 << 8) | low1; 2764 */ 2765 #define _PIPEAFRAMEHIGH 0x70040 2766 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 2767 #define PIPE_FRAME_HIGH_SHIFT 0 2768 #define _PIPEAFRAMEPIXEL 0x70044 2769 #define PIPE_FRAME_LOW_MASK 0xff000000 2770 #define PIPE_FRAME_LOW_SHIFT 24 2771 #define PIPE_PIXEL_MASK 0x00ffffff 2772 #define PIPE_PIXEL_SHIFT 0 2773 /* GM45+ just has to be different */ 2774 #define _PIPEA_FRMCOUNT_G4X 0x70040 2775 #define _PIPEA_FLIPCOUNT_G4X 0x70044 2776 #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X) 2777 #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X) 2778 2779 /* Cursor A & B regs */ 2780 #define _CURACNTR 0x70080 2781 /* Old style CUR*CNTR flags (desktop 8xx) */ 2782 #define CURSOR_ENABLE REG_BIT(31) 2783 #define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30) 2784 #define CURSOR_STRIDE_MASK REG_GENMASK(29, 28) 2785 #define CURSOR_STRIDE(stride) REG_FIELD_PREP(CURSOR_STRIDE_MASK, ffs(stride) - 9) /* 256,512,1k,2k */ 2786 #define CURSOR_FORMAT_MASK REG_GENMASK(26, 24) 2787 #define CURSOR_FORMAT_2C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 0) 2788 #define CURSOR_FORMAT_3C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 1) 2789 #define CURSOR_FORMAT_4C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 2) 2790 #define CURSOR_FORMAT_ARGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 4) 2791 #define CURSOR_FORMAT_XRGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 5) 2792 /* New style CUR*CNTR flags */ 2793 #define MCURSOR_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ 2794 #define MCURSOR_ARB_SLOTS(x) REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */ 2795 #define MCURSOR_PIPE_SEL_MASK REG_GENMASK(29, 28) 2796 #define MCURSOR_PIPE_SEL(pipe) REG_FIELD_PREP(MCURSOR_PIPE_SEL_MASK, (pipe)) 2797 #define MCURSOR_PIPE_GAMMA_ENABLE REG_BIT(26) 2798 #define MCURSOR_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ 2799 #define MCURSOR_ROTATE_180 REG_BIT(15) 2800 #define MCURSOR_TRICKLE_FEED_DISABLE REG_BIT(14) 2801 #define MCURSOR_MODE_MASK 0x27 2802 #define MCURSOR_MODE_DISABLE 0x00 2803 #define MCURSOR_MODE_128_32B_AX 0x02 2804 #define MCURSOR_MODE_256_32B_AX 0x03 2805 #define MCURSOR_MODE_64_2B 0x04 2806 #define MCURSOR_MODE_64_32B_AX 0x07 2807 #define MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX) 2808 #define MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX) 2809 #define MCURSOR_MODE_64_ARGB_AX (0x20 | MCURSOR_MODE_64_32B_AX) 2810 #define _CURABASE 0x70084 2811 #define _CURAPOS 0x70088 2812 #define _CURAPOS_ERLY_TPT 0x7008c 2813 #define CURSOR_POS_Y_SIGN REG_BIT(31) 2814 #define CURSOR_POS_Y_MASK REG_GENMASK(30, 16) 2815 #define CURSOR_POS_Y(y) REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y)) 2816 #define CURSOR_POS_X_SIGN REG_BIT(15) 2817 #define CURSOR_POS_X_MASK REG_GENMASK(14, 0) 2818 #define CURSOR_POS_X(x) REG_FIELD_PREP(CURSOR_POS_X_MASK, (x)) 2819 #define _CURASIZE 0x700a0 /* 845/865 */ 2820 #define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12) 2821 #define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h)) 2822 #define CURSOR_WIDTH_MASK REG_GENMASK(9, 0) 2823 #define CURSOR_WIDTH(w) REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w)) 2824 #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */ 2825 #define CUR_FBC_EN REG_BIT(31) 2826 #define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0) 2827 #define CUR_FBC_HEIGHT(h) REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h)) 2828 #define _CUR_CHICKEN_A 0x700a4 /* mtl+ */ 2829 #define _CURASURFLIVE 0x700ac /* g4x+ */ 2830 #define _CURBCNTR 0x700c0 2831 #define _CURBBASE 0x700c4 2832 #define _CURBPOS 0x700c8 2833 2834 #define _CURBCNTR_IVB 0x71080 2835 #define _CURBBASE_IVB 0x71084 2836 #define _CURBPOS_IVB 0x71088 2837 2838 #define CURCNTR(pipe) _MMIO_CURSOR2(pipe, _CURACNTR) 2839 #define CURBASE(pipe) _MMIO_CURSOR2(pipe, _CURABASE) 2840 #define CURPOS(pipe) _MMIO_CURSOR2(pipe, _CURAPOS) 2841 #define CURPOS_ERLY_TPT(pipe) _MMIO_CURSOR2(pipe, _CURAPOS_ERLY_TPT) 2842 #define CURSIZE(pipe) _MMIO_CURSOR2(pipe, _CURASIZE) 2843 #define CUR_FBC_CTL(pipe) _MMIO_CURSOR2(pipe, _CUR_FBC_CTL_A) 2844 #define CUR_CHICKEN(pipe) _MMIO_CURSOR2(pipe, _CUR_CHICKEN_A) 2845 #define CURSURFLIVE(pipe) _MMIO_CURSOR2(pipe, _CURASURFLIVE) 2846 2847 /* Display A control */ 2848 #define _DSPAADDR_VLV 0x7017C /* vlv/chv */ 2849 #define _DSPACNTR 0x70180 2850 #define DISP_ENABLE REG_BIT(31) 2851 #define DISP_PIPE_GAMMA_ENABLE REG_BIT(30) 2852 #define DISP_FORMAT_MASK REG_GENMASK(29, 26) 2853 #define DISP_FORMAT_8BPP REG_FIELD_PREP(DISP_FORMAT_MASK, 2) 2854 #define DISP_FORMAT_BGRA555 REG_FIELD_PREP(DISP_FORMAT_MASK, 3) 2855 #define DISP_FORMAT_BGRX555 REG_FIELD_PREP(DISP_FORMAT_MASK, 4) 2856 #define DISP_FORMAT_BGRX565 REG_FIELD_PREP(DISP_FORMAT_MASK, 5) 2857 #define DISP_FORMAT_BGRX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 6) 2858 #define DISP_FORMAT_BGRA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 7) 2859 #define DISP_FORMAT_RGBX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 8) 2860 #define DISP_FORMAT_RGBA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 9) 2861 #define DISP_FORMAT_BGRX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 10) 2862 #define DISP_FORMAT_BGRA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 11) 2863 #define DISP_FORMAT_RGBX161616 REG_FIELD_PREP(DISP_FORMAT_MASK, 12) 2864 #define DISP_FORMAT_RGBX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 14) 2865 #define DISP_FORMAT_RGBA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 15) 2866 #define DISP_STEREO_ENABLE REG_BIT(25) 2867 #define DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ 2868 #define DISP_PIPE_SEL_MASK REG_GENMASK(25, 24) 2869 #define DISP_PIPE_SEL(pipe) REG_FIELD_PREP(DISP_PIPE_SEL_MASK, (pipe)) 2870 #define DISP_SRC_KEY_ENABLE REG_BIT(22) 2871 #define DISP_LINE_DOUBLE REG_BIT(20) 2872 #define DISP_STEREO_POLARITY_SECOND REG_BIT(18) 2873 #define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */ 2874 #define DISP_ROTATE_180 REG_BIT(15) 2875 #define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */ 2876 #define DISP_TILED REG_BIT(10) 2877 #define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */ 2878 #define DISP_MIRROR REG_BIT(8) /* CHV pipe B */ 2879 #define _DSPAADDR 0x70184 2880 #define _DSPASTRIDE 0x70188 2881 #define _DSPAPOS 0x7018C /* reserved */ 2882 #define DISP_POS_Y_MASK REG_GENMASK(31, 16) 2883 #define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y)) 2884 #define DISP_POS_X_MASK REG_GENMASK(15, 0) 2885 #define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x)) 2886 #define _DSPASIZE 0x70190 2887 #define DISP_HEIGHT_MASK REG_GENMASK(31, 16) 2888 #define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h)) 2889 #define DISP_WIDTH_MASK REG_GENMASK(15, 0) 2890 #define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w)) 2891 #define _DSPASURF 0x7019C /* 965+ only */ 2892 #define DISP_ADDR_MASK REG_GENMASK(31, 12) 2893 #define _DSPATILEOFF 0x701A4 /* 965+ only */ 2894 #define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16) 2895 #define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y)) 2896 #define DISP_OFFSET_X_MASK REG_GENMASK(15, 0) 2897 #define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x)) 2898 #define _DSPAOFFSET 0x701A4 /* HSW */ 2899 #define _DSPASURFLIVE 0x701AC 2900 #define _DSPAGAMC 0x701E0 2901 2902 #define DSPADDR_VLV(plane) _MMIO_PIPE2(plane, _DSPAADDR_VLV) 2903 #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR) 2904 #define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR) 2905 #define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE) 2906 #define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS) 2907 #define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE) 2908 #define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF) 2909 #define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF) 2910 #define DSPLINOFF(plane) DSPADDR(plane) 2911 #define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET) 2912 #define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE) 2913 #define DSPGAMC(plane, i) _MMIO_PIPE2(plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ 2914 2915 /* CHV pipe B blender and primary plane */ 2916 #define _CHV_BLEND_A 0x60a00 2917 #define CHV_BLEND_MASK REG_GENMASK(31, 30) 2918 #define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0) 2919 #define CHV_BLEND_ANDROID REG_FIELD_PREP(CHV_BLEND_MASK, 1) 2920 #define CHV_BLEND_MPO REG_FIELD_PREP(CHV_BLEND_MASK, 2) 2921 #define _CHV_CANVAS_A 0x60a04 2922 #define CHV_CANVAS_RED_MASK REG_GENMASK(29, 20) 2923 #define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10) 2924 #define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0) 2925 #define _PRIMPOS_A 0x60a08 2926 #define PRIM_POS_Y_MASK REG_GENMASK(31, 16) 2927 #define PRIM_POS_Y(y) REG_FIELD_PREP(PRIM_POS_Y_MASK, (y)) 2928 #define PRIM_POS_X_MASK REG_GENMASK(15, 0) 2929 #define PRIM_POS_X(x) REG_FIELD_PREP(PRIM_POS_X_MASK, (x)) 2930 #define _PRIMSIZE_A 0x60a0c 2931 #define PRIM_HEIGHT_MASK REG_GENMASK(31, 16) 2932 #define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h)) 2933 #define PRIM_WIDTH_MASK REG_GENMASK(15, 0) 2934 #define PRIM_WIDTH(w) REG_FIELD_PREP(PRIM_WIDTH_MASK, (w)) 2935 #define _PRIMCNSTALPHA_A 0x60a10 2936 #define PRIM_CONST_ALPHA_ENABLE REG_BIT(31) 2937 #define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0) 2938 #define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha)) 2939 2940 #define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A) 2941 #define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A) 2942 #define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A) 2943 #define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A) 2944 #define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A) 2945 2946 /* Display/Sprite base address macros */ 2947 #define DISP_BASEADDR_MASK (0xfffff000) 2948 #define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK) 2949 #define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK) 2950 2951 /* 2952 * VBIOS flags 2953 * gen2: 2954 * [00:06] alm,mgm 2955 * [10:16] all 2956 * [30:32] alm,mgm 2957 * gen3+: 2958 * [00:0f] all 2959 * [10:1f] all 2960 * [30:32] all 2961 */ 2962 #define SWF0(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4) 2963 #define SWF1(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4) 2964 #define SWF3(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4) 2965 #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) 2966 2967 /* Pipe B */ 2968 #define _PIPEBDSL (DISPLAY_MMIO_BASE(dev_priv) + 0x71000) 2969 #define _TRANSBCONF (DISPLAY_MMIO_BASE(dev_priv) + 0x71008) 2970 #define _PIPEBSTAT (DISPLAY_MMIO_BASE(dev_priv) + 0x71024) 2971 #define _PIPEBFRAMEHIGH 0x71040 2972 #define _PIPEBFRAMEPIXEL 0x71044 2973 #define _PIPEB_FRMCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71040) 2974 #define _PIPEB_FLIPCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71044) 2975 2976 2977 /* Display B control */ 2978 #define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180) 2979 #define DISP_ALPHA_TRANS_ENABLE REG_BIT(15) 2980 #define DISP_SPRITE_ABOVE_OVERLAY REG_BIT(0) 2981 #define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184) 2982 #define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188) 2983 #define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C) 2984 #define _DSPBSIZE (DISPLAY_MMIO_BASE(dev_priv) + 0x71190) 2985 #define _DSPBSURF (DISPLAY_MMIO_BASE(dev_priv) + 0x7119C) 2986 #define _DSPBTILEOFF (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) 2987 #define _DSPBOFFSET (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) 2988 #define _DSPBSURFLIVE (DISPLAY_MMIO_BASE(dev_priv) + 0x711AC) 2989 2990 /* ICL DSI 0 and 1 */ 2991 #define _PIPEDSI0CONF 0x7b008 2992 #define _PIPEDSI1CONF 0x7b808 2993 2994 /* Sprite A control */ 2995 #define _DVSACNTR 0x72180 2996 #define DVS_ENABLE REG_BIT(31) 2997 #define DVS_PIPE_GAMMA_ENABLE REG_BIT(30) 2998 #define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27) 2999 #define DVS_FORMAT_MASK REG_GENMASK(26, 25) 3000 #define DVS_FORMAT_YUV422 REG_FIELD_PREP(DVS_FORMAT_MASK, 0) 3001 #define DVS_FORMAT_RGBX101010 REG_FIELD_PREP(DVS_FORMAT_MASK, 1) 3002 #define DVS_FORMAT_RGBX888 REG_FIELD_PREP(DVS_FORMAT_MASK, 2) 3003 #define DVS_FORMAT_RGBX161616 REG_FIELD_PREP(DVS_FORMAT_MASK, 3) 3004 #define DVS_PIPE_CSC_ENABLE REG_BIT(24) 3005 #define DVS_SOURCE_KEY REG_BIT(22) 3006 #define DVS_RGB_ORDER_XBGR REG_BIT(20) 3007 #define DVS_YUV_FORMAT_BT709 REG_BIT(18) 3008 #define DVS_YUV_ORDER_MASK REG_GENMASK(17, 16) 3009 #define DVS_YUV_ORDER_YUYV REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 0) 3010 #define DVS_YUV_ORDER_UYVY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 1) 3011 #define DVS_YUV_ORDER_YVYU REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 2) 3012 #define DVS_YUV_ORDER_VYUY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 3) 3013 #define DVS_ROTATE_180 REG_BIT(15) 3014 #define DVS_TRICKLE_FEED_DISABLE REG_BIT(14) 3015 #define DVS_TILED REG_BIT(10) 3016 #define DVS_DEST_KEY REG_BIT(2) 3017 #define _DVSALINOFF 0x72184 3018 #define _DVSASTRIDE 0x72188 3019 #define _DVSAPOS 0x7218c 3020 #define DVS_POS_Y_MASK REG_GENMASK(31, 16) 3021 #define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, (y)) 3022 #define DVS_POS_X_MASK REG_GENMASK(15, 0) 3023 #define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, (x)) 3024 #define _DVSASIZE 0x72190 3025 #define DVS_HEIGHT_MASK REG_GENMASK(31, 16) 3026 #define DVS_HEIGHT(h) REG_FIELD_PREP(DVS_HEIGHT_MASK, (h)) 3027 #define DVS_WIDTH_MASK REG_GENMASK(15, 0) 3028 #define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, (w)) 3029 #define _DVSAKEYVAL 0x72194 3030 #define _DVSAKEYMSK 0x72198 3031 #define _DVSASURF 0x7219c 3032 #define DVS_ADDR_MASK REG_GENMASK(31, 12) 3033 #define _DVSAKEYMAXVAL 0x721a0 3034 #define _DVSATILEOFF 0x721a4 3035 #define DVS_OFFSET_Y_MASK REG_GENMASK(31, 16) 3036 #define DVS_OFFSET_Y(y) REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y)) 3037 #define DVS_OFFSET_X_MASK REG_GENMASK(15, 0) 3038 #define DVS_OFFSET_X(x) REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x)) 3039 #define _DVSASURFLIVE 0x721ac 3040 #define _DVSAGAMC_G4X 0x721e0 /* g4x */ 3041 #define _DVSASCALE 0x72204 3042 #define DVS_SCALE_ENABLE REG_BIT(31) 3043 #define DVS_FILTER_MASK REG_GENMASK(30, 29) 3044 #define DVS_FILTER_MEDIUM REG_FIELD_PREP(DVS_FILTER_MASK, 0) 3045 #define DVS_FILTER_ENHANCING REG_FIELD_PREP(DVS_FILTER_MASK, 1) 3046 #define DVS_FILTER_SOFTENING REG_FIELD_PREP(DVS_FILTER_MASK, 2) 3047 #define DVS_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */ 3048 #define DVS_VERTICAL_OFFSET_ENABLE REG_BIT(27) 3049 #define DVS_SRC_WIDTH_MASK REG_GENMASK(26, 16) 3050 #define DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w)) 3051 #define DVS_SRC_HEIGHT_MASK REG_GENMASK(10, 0) 3052 #define DVS_SRC_HEIGHT(h) REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h)) 3053 #define _DVSAGAMC_ILK 0x72300 /* ilk/snb */ 3054 #define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */ 3055 3056 #define _DVSBCNTR 0x73180 3057 #define _DVSBLINOFF 0x73184 3058 #define _DVSBSTRIDE 0x73188 3059 #define _DVSBPOS 0x7318c 3060 #define _DVSBSIZE 0x73190 3061 #define _DVSBKEYVAL 0x73194 3062 #define _DVSBKEYMSK 0x73198 3063 #define _DVSBSURF 0x7319c 3064 #define _DVSBKEYMAXVAL 0x731a0 3065 #define _DVSBTILEOFF 0x731a4 3066 #define _DVSBSURFLIVE 0x731ac 3067 #define _DVSBGAMC_G4X 0x731e0 /* g4x */ 3068 #define _DVSBSCALE 0x73204 3069 #define _DVSBGAMC_ILK 0x73300 /* ilk/snb */ 3070 #define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */ 3071 3072 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR) 3073 #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) 3074 #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) 3075 #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS) 3076 #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF) 3077 #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) 3078 #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE) 3079 #define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE) 3080 #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) 3081 #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) 3082 #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) 3083 #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) 3084 #define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */ 3085 #define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */ 3086 #define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */ 3087 3088 #define _SPRA_CTL 0x70280 3089 #define SPRITE_ENABLE REG_BIT(31) 3090 #define SPRITE_PIPE_GAMMA_ENABLE REG_BIT(30) 3091 #define SPRITE_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) 3092 #define SPRITE_FORMAT_MASK REG_GENMASK(27, 25) 3093 #define SPRITE_FORMAT_YUV422 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 0) 3094 #define SPRITE_FORMAT_RGBX101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 1) 3095 #define SPRITE_FORMAT_RGBX888 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 2) 3096 #define SPRITE_FORMAT_RGBX161616 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 3) 3097 #define SPRITE_FORMAT_YUV444 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 4) 3098 #define SPRITE_FORMAT_XR_BGR101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 5) /* Extended range */ 3099 #define SPRITE_PIPE_CSC_ENABLE REG_BIT(24) 3100 #define SPRITE_SOURCE_KEY REG_BIT(22) 3101 #define SPRITE_RGB_ORDER_RGBX REG_BIT(20) /* only for 888 and 161616 */ 3102 #define SPRITE_YUV_TO_RGB_CSC_DISABLE REG_BIT(19) 3103 #define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) /* 0 is BT601 */ 3104 #define SPRITE_YUV_ORDER_MASK REG_GENMASK(17, 16) 3105 #define SPRITE_YUV_ORDER_YUYV REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 0) 3106 #define SPRITE_YUV_ORDER_UYVY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 1) 3107 #define SPRITE_YUV_ORDER_YVYU REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 2) 3108 #define SPRITE_YUV_ORDER_VYUY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 3) 3109 #define SPRITE_ROTATE_180 REG_BIT(15) 3110 #define SPRITE_TRICKLE_FEED_DISABLE REG_BIT(14) 3111 #define SPRITE_PLANE_GAMMA_DISABLE REG_BIT(13) 3112 #define SPRITE_TILED REG_BIT(10) 3113 #define SPRITE_DEST_KEY REG_BIT(2) 3114 #define _SPRA_LINOFF 0x70284 3115 #define _SPRA_STRIDE 0x70288 3116 #define _SPRA_POS 0x7028c 3117 #define SPRITE_POS_Y_MASK REG_GENMASK(31, 16) 3118 #define SPRITE_POS_Y(y) REG_FIELD_PREP(SPRITE_POS_Y_MASK, (y)) 3119 #define SPRITE_POS_X_MASK REG_GENMASK(15, 0) 3120 #define SPRITE_POS_X(x) REG_FIELD_PREP(SPRITE_POS_X_MASK, (x)) 3121 #define _SPRA_SIZE 0x70290 3122 #define SPRITE_HEIGHT_MASK REG_GENMASK(31, 16) 3123 #define SPRITE_HEIGHT(h) REG_FIELD_PREP(SPRITE_HEIGHT_MASK, (h)) 3124 #define SPRITE_WIDTH_MASK REG_GENMASK(15, 0) 3125 #define SPRITE_WIDTH(w) REG_FIELD_PREP(SPRITE_WIDTH_MASK, (w)) 3126 #define _SPRA_KEYVAL 0x70294 3127 #define _SPRA_KEYMSK 0x70298 3128 #define _SPRA_SURF 0x7029c 3129 #define SPRITE_ADDR_MASK REG_GENMASK(31, 12) 3130 #define _SPRA_KEYMAX 0x702a0 3131 #define _SPRA_TILEOFF 0x702a4 3132 #define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16) 3133 #define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y)) 3134 #define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0) 3135 #define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x)) 3136 #define _SPRA_OFFSET 0x702a4 3137 #define _SPRA_SURFLIVE 0x702ac 3138 #define _SPRA_SCALE 0x70304 3139 #define SPRITE_SCALE_ENABLE REG_BIT(31) 3140 #define SPRITE_FILTER_MASK REG_GENMASK(30, 29) 3141 #define SPRITE_FILTER_MEDIUM REG_FIELD_PREP(SPRITE_FILTER_MASK, 0) 3142 #define SPRITE_FILTER_ENHANCING REG_FIELD_PREP(SPRITE_FILTER_MASK, 1) 3143 #define SPRITE_FILTER_SOFTENING REG_FIELD_PREP(SPRITE_FILTER_MASK, 2) 3144 #define SPRITE_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */ 3145 #define SPRITE_VERTICAL_OFFSET_ENABLE REG_BIT(27) 3146 #define SPRITE_SRC_WIDTH_MASK REG_GENMASK(26, 16) 3147 #define SPRITE_SRC_WIDTH(w) REG_FIELD_PREP(SPRITE_SRC_WIDTH_MASK, (w)) 3148 #define SPRITE_SRC_HEIGHT_MASK REG_GENMASK(10, 0) 3149 #define SPRITE_SRC_HEIGHT(h) REG_FIELD_PREP(SPRITE_SRC_HEIGHT_MASK, (h)) 3150 #define _SPRA_GAMC 0x70400 3151 #define _SPRA_GAMC16 0x70440 3152 #define _SPRA_GAMC17 0x7044c 3153 3154 #define _SPRB_CTL 0x71280 3155 #define _SPRB_LINOFF 0x71284 3156 #define _SPRB_STRIDE 0x71288 3157 #define _SPRB_POS 0x7128c 3158 #define _SPRB_SIZE 0x71290 3159 #define _SPRB_KEYVAL 0x71294 3160 #define _SPRB_KEYMSK 0x71298 3161 #define _SPRB_SURF 0x7129c 3162 #define _SPRB_KEYMAX 0x712a0 3163 #define _SPRB_TILEOFF 0x712a4 3164 #define _SPRB_OFFSET 0x712a4 3165 #define _SPRB_SURFLIVE 0x712ac 3166 #define _SPRB_SCALE 0x71304 3167 #define _SPRB_GAMC 0x71400 3168 #define _SPRB_GAMC16 0x71440 3169 #define _SPRB_GAMC17 0x7144c 3170 3171 #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL) 3172 #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) 3173 #define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) 3174 #define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS) 3175 #define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) 3176 #define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) 3177 #define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) 3178 #define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF) 3179 #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) 3180 #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) 3181 #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) 3182 #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) 3183 #define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */ 3184 #define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */ 3185 #define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */ 3186 #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) 3187 3188 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) 3189 #define SP_ENABLE REG_BIT(31) 3190 #define SP_PIPE_GAMMA_ENABLE REG_BIT(30) 3191 #define SP_FORMAT_MASK REG_GENMASK(29, 26) 3192 #define SP_FORMAT_YUV422 REG_FIELD_PREP(SP_FORMAT_MASK, 0) 3193 #define SP_FORMAT_8BPP REG_FIELD_PREP(SP_FORMAT_MASK, 2) 3194 #define SP_FORMAT_BGR565 REG_FIELD_PREP(SP_FORMAT_MASK, 5) 3195 #define SP_FORMAT_BGRX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 6) 3196 #define SP_FORMAT_BGRA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 7) 3197 #define SP_FORMAT_RGBX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 8) 3198 #define SP_FORMAT_RGBA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 9) 3199 #define SP_FORMAT_BGRX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 10) /* CHV pipe B */ 3200 #define SP_FORMAT_BGRA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 11) /* CHV pipe B */ 3201 #define SP_FORMAT_RGBX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 14) 3202 #define SP_FORMAT_RGBA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 15) 3203 #define SP_ALPHA_PREMULTIPLY REG_BIT(23) /* CHV pipe B */ 3204 #define SP_SOURCE_KEY REG_BIT(22) 3205 #define SP_YUV_FORMAT_BT709 REG_BIT(18) 3206 #define SP_YUV_ORDER_MASK REG_GENMASK(17, 16) 3207 #define SP_YUV_ORDER_YUYV REG_FIELD_PREP(SP_YUV_ORDER_MASK, 0) 3208 #define SP_YUV_ORDER_UYVY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 1) 3209 #define SP_YUV_ORDER_YVYU REG_FIELD_PREP(SP_YUV_ORDER_MASK, 2) 3210 #define SP_YUV_ORDER_VYUY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 3) 3211 #define SP_ROTATE_180 REG_BIT(15) 3212 #define SP_TILED REG_BIT(10) 3213 #define SP_MIRROR REG_BIT(8) /* CHV pipe B */ 3214 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) 3215 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) 3216 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c) 3217 #define SP_POS_Y_MASK REG_GENMASK(31, 16) 3218 #define SP_POS_Y(y) REG_FIELD_PREP(SP_POS_Y_MASK, (y)) 3219 #define SP_POS_X_MASK REG_GENMASK(15, 0) 3220 #define SP_POS_X(x) REG_FIELD_PREP(SP_POS_X_MASK, (x)) 3221 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190) 3222 #define SP_HEIGHT_MASK REG_GENMASK(31, 16) 3223 #define SP_HEIGHT(h) REG_FIELD_PREP(SP_HEIGHT_MASK, (h)) 3224 #define SP_WIDTH_MASK REG_GENMASK(15, 0) 3225 #define SP_WIDTH(w) REG_FIELD_PREP(SP_WIDTH_MASK, (w)) 3226 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194) 3227 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198) 3228 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c) 3229 #define SP_ADDR_MASK REG_GENMASK(31, 12) 3230 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0) 3231 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4) 3232 #define SP_OFFSET_Y_MASK REG_GENMASK(31, 16) 3233 #define SP_OFFSET_Y(y) REG_FIELD_PREP(SP_OFFSET_Y_MASK, (y)) 3234 #define SP_OFFSET_X_MASK REG_GENMASK(15, 0) 3235 #define SP_OFFSET_X(x) REG_FIELD_PREP(SP_OFFSET_X_MASK, (x)) 3236 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) 3237 #define SP_CONST_ALPHA_ENABLE REG_BIT(31) 3238 #define SP_CONST_ALPHA_MASK REG_GENMASK(7, 0) 3239 #define SP_CONST_ALPHA(alpha) REG_FIELD_PREP(SP_CONST_ALPHA_MASK, (alpha)) 3240 #define _SPASURFLIVE (VLV_DISPLAY_BASE + 0x721ac) 3241 #define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0) 3242 #define SP_CONTRAST_MASK REG_GENMASK(26, 18) 3243 #define SP_CONTRAST(x) REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /* u3.6 */ 3244 #define SP_BRIGHTNESS_MASK REG_GENMASK(7, 0) 3245 #define SP_BRIGHTNESS(x) REG_FIELD_PREP(SP_BRIGHTNESS_MASK, (x)) /* s8 */ 3246 #define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4) 3247 #define SP_SH_SIN_MASK REG_GENMASK(26, 16) 3248 #define SP_SH_SIN(x) REG_FIELD_PREP(SP_SH_SIN_MASK, (x)) /* s4.7 */ 3249 #define SP_SH_COS_MASK REG_GENMASK(9, 0) 3250 #define SP_SH_COS(x) REG_FIELD_PREP(SP_SH_COS_MASK, (x)) /* u3.7 */ 3251 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0) 3252 3253 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) 3254 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) 3255 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) 3256 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c) 3257 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) 3258 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294) 3259 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) 3260 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) 3261 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) 3262 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) 3263 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) 3264 #define _SPBSURFLIVE (VLV_DISPLAY_BASE + 0x722ac) 3265 #define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0) 3266 #define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4) 3267 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0) 3268 3269 #define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \ 3270 _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b)) 3271 #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \ 3272 _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b))) 3273 3274 #define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR) 3275 #define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF) 3276 #define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE) 3277 #define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS) 3278 #define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE) 3279 #define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL) 3280 #define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK) 3281 #define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF) 3282 #define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL) 3283 #define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF) 3284 #define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA) 3285 #define SPSURFLIVE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURFLIVE, _SPBSURFLIVE) 3286 #define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0) 3287 #define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1) 3288 #define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */ 3289 3290 /* 3291 * CHV pipe B sprite CSC 3292 * 3293 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff| 3294 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff| 3295 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff| 3296 */ 3297 #define _MMIO_CHV_SPCSC(plane_id, reg) \ 3298 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg)) 3299 3300 #define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900) 3301 #define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904) 3302 #define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908) 3303 #define SPCSC_OOFF_MASK REG_GENMASK(26, 16) 3304 #define SPCSC_OOFF(x) REG_FIELD_PREP(SPCSC_OOFF_MASK, (x) & 0x7ff) /* s11 */ 3305 #define SPCSC_IOFF_MASK REG_GENMASK(10, 0) 3306 #define SPCSC_IOFF(x) REG_FIELD_PREP(SPCSC_IOFF_MASK, (x) & 0x7ff) /* s11 */ 3307 3308 #define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c) 3309 #define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910) 3310 #define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914) 3311 #define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918) 3312 #define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c) 3313 #define SPCSC_C1_MASK REG_GENMASK(30, 16) 3314 #define SPCSC_C1(x) REG_FIELD_PREP(SPCSC_C1_MASK, (x) & 0x7fff) /* s3.12 */ 3315 #define SPCSC_C0_MASK REG_GENMASK(14, 0) 3316 #define SPCSC_C0(x) REG_FIELD_PREP(SPCSC_C0_MASK, (x) & 0x7fff) /* s3.12 */ 3317 3318 #define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920) 3319 #define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924) 3320 #define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928) 3321 #define SPCSC_IMAX_MASK REG_GENMASK(26, 16) 3322 #define SPCSC_IMAX(x) REG_FIELD_PREP(SPCSC_IMAX_MASK, (x) & 0x7ff) /* s11 */ 3323 #define SPCSC_IMIN_MASK REG_GENMASK(10, 0) 3324 #define SPCSC_IMIN(x) REG_FIELD_PREP(SPCSC_IMIN_MASK, (x) & 0x7ff) /* s11 */ 3325 3326 #define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c) 3327 #define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930) 3328 #define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934) 3329 #define SPCSC_OMAX_MASK REG_GENMASK(25, 16) 3330 #define SPCSC_OMAX(x) REG_FIELD_PREP(SPCSC_OMAX_MASK, (x)) /* u10 */ 3331 #define SPCSC_OMIN_MASK REG_GENMASK(9, 0) 3332 #define SPCSC_OMIN(x) REG_FIELD_PREP(SPCSC_OMIN_MASK, (x)) /* u10 */ 3333 3334 /* Skylake plane registers */ 3335 3336 #define _PLANE_CTL_1_A 0x70180 3337 #define _PLANE_CTL_2_A 0x70280 3338 #define _PLANE_CTL_3_A 0x70380 3339 #define PLANE_CTL_ENABLE REG_BIT(31) 3340 #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ 3341 #define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */ 3342 #define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */ 3343 #define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) 3344 /* 3345 * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition 3346 * expanded to include bit 23 as well. However, the shift-24 based values 3347 * correctly map to the same formats in ICL, as long as bit 23 is set to 0 3348 */ 3349 #define PLANE_CTL_FORMAT_MASK_SKL REG_GENMASK(27, 24) /* pre-icl */ 3350 #define PLANE_CTL_FORMAT_MASK_ICL REG_GENMASK(27, 23) /* icl+ */ 3351 #define PLANE_CTL_FORMAT_YUV422 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0) 3352 #define PLANE_CTL_FORMAT_NV12 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 1) 3353 #define PLANE_CTL_FORMAT_XRGB_2101010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 2) 3354 #define PLANE_CTL_FORMAT_P010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 3) 3355 #define PLANE_CTL_FORMAT_XRGB_8888 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 4) 3356 #define PLANE_CTL_FORMAT_P012 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 5) 3357 #define PLANE_CTL_FORMAT_XRGB_16161616F REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 6) 3358 #define PLANE_CTL_FORMAT_P016 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 7) 3359 #define PLANE_CTL_FORMAT_XYUV REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 8) 3360 #define PLANE_CTL_FORMAT_INDEXED REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 12) 3361 #define PLANE_CTL_FORMAT_RGB_565 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 14) 3362 #define PLANE_CTL_FORMAT_Y210 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 1) 3363 #define PLANE_CTL_FORMAT_Y212 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 3) 3364 #define PLANE_CTL_FORMAT_Y216 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 5) 3365 #define PLANE_CTL_FORMAT_Y410 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 7) 3366 #define PLANE_CTL_FORMAT_Y412 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 9) 3367 #define PLANE_CTL_FORMAT_Y416 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 11) 3368 #define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */ 3369 #define PLANE_CTL_KEY_ENABLE_MASK REG_GENMASK(22, 21) 3370 #define PLANE_CTL_KEY_ENABLE_SOURCE REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 1) 3371 #define PLANE_CTL_KEY_ENABLE_DESTINATION REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 2) 3372 #define PLANE_CTL_ORDER_RGBX REG_BIT(20) 3373 #define PLANE_CTL_YUV420_Y_PLANE REG_BIT(19) 3374 #define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) 3375 #define PLANE_CTL_YUV422_ORDER_MASK REG_GENMASK(17, 16) 3376 #define PLANE_CTL_YUV422_ORDER_YUYV REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0) 3377 #define PLANE_CTL_YUV422_ORDER_UYVY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 1) 3378 #define PLANE_CTL_YUV422_ORDER_YVYU REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 2) 3379 #define PLANE_CTL_YUV422_ORDER_VYUY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 3) 3380 #define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE REG_BIT(15) 3381 #define PLANE_CTL_TRICKLE_FEED_DISABLE REG_BIT(14) 3382 #define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */ 3383 #define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */ 3384 #define PLANE_CTL_TILED_MASK REG_GENMASK(12, 10) 3385 #define PLANE_CTL_TILED_LINEAR REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 0) 3386 #define PLANE_CTL_TILED_X REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 1) 3387 #define PLANE_CTL_TILED_Y REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 4) 3388 #define PLANE_CTL_TILED_YF REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5) 3389 #define PLANE_CTL_TILED_4 REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5) 3390 #define PLANE_CTL_ASYNC_FLIP REG_BIT(9) 3391 #define PLANE_CTL_FLIP_HORIZONTAL REG_BIT(8) 3392 #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */ 3393 #define PLANE_CTL_ALPHA_MASK REG_GENMASK(5, 4) /* Pre-GLK */ 3394 #define PLANE_CTL_ALPHA_DISABLE REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 0) 3395 #define PLANE_CTL_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 2) 3396 #define PLANE_CTL_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 3) 3397 #define PLANE_CTL_ROTATE_MASK REG_GENMASK(1, 0) 3398 #define PLANE_CTL_ROTATE_0 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 0) 3399 #define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1) 3400 #define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2) 3401 #define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3) 3402 #define _PLANE_STRIDE_1_A 0x70188 3403 #define _PLANE_STRIDE_2_A 0x70288 3404 #define _PLANE_STRIDE_3_A 0x70388 3405 #define PLANE_STRIDE__MASK REG_GENMASK(11, 0) 3406 #define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride)) 3407 #define _PLANE_POS_1_A 0x7018c 3408 #define _PLANE_POS_2_A 0x7028c 3409 #define _PLANE_POS_3_A 0x7038c 3410 #define PLANE_POS_Y_MASK REG_GENMASK(31, 16) 3411 #define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y)) 3412 #define PLANE_POS_X_MASK REG_GENMASK(15, 0) 3413 #define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x)) 3414 #define _PLANE_SIZE_1_A 0x70190 3415 #define _PLANE_SIZE_2_A 0x70290 3416 #define _PLANE_SIZE_3_A 0x70390 3417 #define PLANE_HEIGHT_MASK REG_GENMASK(31, 16) 3418 #define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h)) 3419 #define PLANE_WIDTH_MASK REG_GENMASK(15, 0) 3420 #define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w)) 3421 #define _PLANE_SURF_1_A 0x7019c 3422 #define _PLANE_SURF_2_A 0x7029c 3423 #define _PLANE_SURF_3_A 0x7039c 3424 #define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12) 3425 #define PLANE_SURF_DECRYPT REG_BIT(2) 3426 #define _PLANE_OFFSET_1_A 0x701a4 3427 #define _PLANE_OFFSET_2_A 0x702a4 3428 #define _PLANE_OFFSET_3_A 0x703a4 3429 #define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16) 3430 #define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y)) 3431 #define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0) 3432 #define PLANE_OFFSET_X(x) REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x)) 3433 #define _PLANE_KEYVAL_1_A 0x70194 3434 #define _PLANE_KEYVAL_2_A 0x70294 3435 #define _PLANE_KEYMSK_1_A 0x70198 3436 #define _PLANE_KEYMSK_2_A 0x70298 3437 #define PLANE_KEYMSK_ALPHA_ENABLE REG_BIT(31) 3438 #define _PLANE_KEYMAX_1_A 0x701a0 3439 #define _PLANE_KEYMAX_2_A 0x702a0 3440 #define PLANE_KEYMAX_ALPHA_MASK REG_GENMASK(31, 24) 3441 #define PLANE_KEYMAX_ALPHA(a) REG_FIELD_PREP(PLANE_KEYMAX_ALPHA_MASK, (a)) 3442 #define _PLANE_SURFLIVE_1_A 0x701ac 3443 #define _PLANE_SURFLIVE_2_A 0x702ac 3444 #define _PLANE_CC_VAL_1_A 0x701b4 3445 #define _PLANE_CC_VAL_2_A 0x702b4 3446 #define _PLANE_AUX_DIST_1_A 0x701c0 3447 #define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12) 3448 #define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0) 3449 #define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride)) 3450 #define _PLANE_AUX_DIST_2_A 0x702c0 3451 #define _PLANE_AUX_OFFSET_1_A 0x701c4 3452 #define _PLANE_AUX_OFFSET_2_A 0x702c4 3453 #define _PLANE_CUS_CTL_1_A 0x701c8 3454 #define _PLANE_CUS_CTL_2_A 0x702c8 3455 #define PLANE_CUS_ENABLE REG_BIT(31) 3456 #define PLANE_CUS_Y_PLANE_MASK REG_BIT(30) 3457 #define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) 3458 #define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) 3459 #define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) 3460 #define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) 3461 #define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19) 3462 #define PLANE_CUS_HPHASE_MASK REG_GENMASK(17, 16) 3463 #define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0) 3464 #define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1) 3465 #define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2) 3466 #define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15) 3467 #define PLANE_CUS_VPHASE_MASK REG_GENMASK(13, 12) 3468 #define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0) 3469 #define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1) 3470 #define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2) 3471 #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */ 3472 #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */ 3473 #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */ 3474 #define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */ 3475 #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) 3476 #define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */ 3477 #define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */ 3478 #define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */ 3479 #define PLANE_COLOR_CSC_MODE_MASK REG_GENMASK(19, 17) 3480 #define PLANE_COLOR_CSC_MODE_BYPASS REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0) 3481 #define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 1) 3482 #define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 2) 3483 #define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 3) 3484 #define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 4) 3485 #define PLANE_COLOR_PLANE_GAMMA_DISABLE REG_BIT(13) 3486 #define PLANE_COLOR_ALPHA_MASK REG_GENMASK(5, 4) 3487 #define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0) 3488 #define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2) 3489 #define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3) 3490 #define _PLANE_CHICKEN_1_A 0x7026C /* tgl+ */ 3491 #define _PLANE_CHICKEN_2_A 0x7036C /* tgl+ */ 3492 #define PLANE_CHICKEN_DISABLE_DPT REG_BIT(19) /* mtl+ */ 3493 #define _PLANE_BUF_CFG_1_A 0x7027c 3494 #define _PLANE_BUF_CFG_2_A 0x7037c 3495 /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */ 3496 #define PLANE_BUF_END_MASK REG_GENMASK(27, 16) 3497 #define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end)) 3498 #define PLANE_BUF_START_MASK REG_GENMASK(11, 0) 3499 #define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start)) 3500 #define _PLANE_NV12_BUF_CFG_1_A 0x70278 3501 #define _PLANE_NV12_BUF_CFG_2_A 0x70378 3502 3503 #define _PLANE_CC_VAL_1_B 0x711b4 3504 #define _PLANE_CC_VAL_2_B 0x712b4 3505 #define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4) 3506 #define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4) 3507 #define PLANE_CC_VAL(pipe, plane, dw) \ 3508 _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw))) 3509 3510 /* Input CSC Register Definitions */ 3511 #define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0 3512 #define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0 3513 3514 #define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0 3515 #define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0 3516 3517 #define _PLANE_INPUT_CSC_RY_GY_1(pipe) \ 3518 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \ 3519 _PLANE_INPUT_CSC_RY_GY_1_B) 3520 #define _PLANE_INPUT_CSC_RY_GY_2(pipe) \ 3521 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \ 3522 _PLANE_INPUT_CSC_RY_GY_2_B) 3523 3524 #define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \ 3525 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \ 3526 _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4) 3527 3528 #define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8 3529 #define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8 3530 3531 #define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8 3532 #define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8 3533 3534 #define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \ 3535 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \ 3536 _PLANE_INPUT_CSC_PREOFF_HI_1_B) 3537 #define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \ 3538 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \ 3539 _PLANE_INPUT_CSC_PREOFF_HI_2_B) 3540 #define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \ 3541 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \ 3542 _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4) 3543 3544 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204 3545 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304 3546 3547 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204 3548 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304 3549 3550 #define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \ 3551 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \ 3552 _PLANE_INPUT_CSC_POSTOFF_HI_1_B) 3553 #define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \ 3554 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \ 3555 _PLANE_INPUT_CSC_POSTOFF_HI_2_B) 3556 #define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \ 3557 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \ 3558 _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4) 3559 3560 #define _PLANE_CTL_1_B 0x71180 3561 #define _PLANE_CTL_2_B 0x71280 3562 #define _PLANE_CTL_3_B 0x71380 3563 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) 3564 #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) 3565 #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B) 3566 #define PLANE_CTL(pipe, plane) \ 3567 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) 3568 3569 #define _PLANE_STRIDE_1_B 0x71188 3570 #define _PLANE_STRIDE_2_B 0x71288 3571 #define _PLANE_STRIDE_3_B 0x71388 3572 #define _PLANE_STRIDE_1(pipe) \ 3573 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) 3574 #define _PLANE_STRIDE_2(pipe) \ 3575 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) 3576 #define _PLANE_STRIDE_3(pipe) \ 3577 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B) 3578 #define PLANE_STRIDE(pipe, plane) \ 3579 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) 3580 3581 #define _PLANE_POS_1_B 0x7118c 3582 #define _PLANE_POS_2_B 0x7128c 3583 #define _PLANE_POS_3_B 0x7138c 3584 #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) 3585 #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) 3586 #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B) 3587 #define PLANE_POS(pipe, plane) \ 3588 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) 3589 3590 #define _PLANE_SIZE_1_B 0x71190 3591 #define _PLANE_SIZE_2_B 0x71290 3592 #define _PLANE_SIZE_3_B 0x71390 3593 #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) 3594 #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) 3595 #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B) 3596 #define PLANE_SIZE(pipe, plane) \ 3597 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) 3598 3599 #define _PLANE_SURF_1_B 0x7119c 3600 #define _PLANE_SURF_2_B 0x7129c 3601 #define _PLANE_SURF_3_B 0x7139c 3602 #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B) 3603 #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B) 3604 #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) 3605 #define PLANE_SURF(pipe, plane) \ 3606 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) 3607 3608 #define _PLANE_OFFSET_1_B 0x711a4 3609 #define _PLANE_OFFSET_2_B 0x712a4 3610 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B) 3611 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B) 3612 #define PLANE_OFFSET(pipe, plane) \ 3613 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe)) 3614 3615 #define _PLANE_KEYVAL_1_B 0x71194 3616 #define _PLANE_KEYVAL_2_B 0x71294 3617 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B) 3618 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) 3619 #define PLANE_KEYVAL(pipe, plane) \ 3620 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe)) 3621 3622 #define _PLANE_KEYMSK_1_B 0x71198 3623 #define _PLANE_KEYMSK_2_B 0x71298 3624 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B) 3625 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B) 3626 #define PLANE_KEYMSK(pipe, plane) \ 3627 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe)) 3628 3629 #define _PLANE_KEYMAX_1_B 0x711a0 3630 #define _PLANE_KEYMAX_2_B 0x712a0 3631 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B) 3632 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B) 3633 #define PLANE_KEYMAX(pipe, plane) \ 3634 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe)) 3635 3636 #define _PLANE_SURFLIVE_1_B 0x711ac 3637 #define _PLANE_SURFLIVE_2_B 0x712ac 3638 #define _PLANE_SURFLIVE_1(pipe) _PIPE(pipe, _PLANE_SURFLIVE_1_A, _PLANE_SURFLIVE_1_B) 3639 #define _PLANE_SURFLIVE_2(pipe) _PIPE(pipe, _PLANE_SURFLIVE_2_A, _PLANE_SURFLIVE_2_B) 3640 #define PLANE_SURFLIVE(pipe, plane) \ 3641 _MMIO_PLANE(plane, _PLANE_SURFLIVE_1(pipe), _PLANE_SURFLIVE_2(pipe)) 3642 3643 #define _PLANE_CHICKEN_1_B 0x7126c 3644 #define _PLANE_CHICKEN_2_B 0x7136c 3645 #define _PLANE_CHICKEN_1(pipe) _PIPE(pipe, _PLANE_CHICKEN_1_A, _PLANE_CHICKEN_1_B) 3646 #define _PLANE_CHICKEN_2(pipe) _PIPE(pipe, _PLANE_CHICKEN_2_A, _PLANE_CHICKEN_2_B) 3647 #define PLANE_CHICKEN(pipe, plane) \ 3648 _MMIO_PLANE(plane, _PLANE_CHICKEN_1(pipe), _PLANE_CHICKEN_2(pipe)) 3649 3650 #define _PLANE_AUX_DIST_1_B 0x711c0 3651 #define _PLANE_AUX_DIST_2_B 0x712c0 3652 #define _PLANE_AUX_DIST_1(pipe) \ 3653 _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B) 3654 #define _PLANE_AUX_DIST_2(pipe) \ 3655 _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B) 3656 #define PLANE_AUX_DIST(pipe, plane) \ 3657 _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe)) 3658 3659 #define _PLANE_AUX_OFFSET_1_B 0x711c4 3660 #define _PLANE_AUX_OFFSET_2_B 0x712c4 3661 #define _PLANE_AUX_OFFSET_1(pipe) \ 3662 _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B) 3663 #define _PLANE_AUX_OFFSET_2(pipe) \ 3664 _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B) 3665 #define PLANE_AUX_OFFSET(pipe, plane) \ 3666 _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe)) 3667 3668 #define _PLANE_CUS_CTL_1_B 0x711c8 3669 #define _PLANE_CUS_CTL_2_B 0x712c8 3670 #define _PLANE_CUS_CTL_1(pipe) \ 3671 _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B) 3672 #define _PLANE_CUS_CTL_2(pipe) \ 3673 _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B) 3674 #define PLANE_CUS_CTL(pipe, plane) \ 3675 _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe)) 3676 3677 #define _PLANE_COLOR_CTL_1_B 0x711CC 3678 #define _PLANE_COLOR_CTL_2_B 0x712CC 3679 #define _PLANE_COLOR_CTL_3_B 0x713CC 3680 #define _PLANE_COLOR_CTL_1(pipe) \ 3681 _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B) 3682 #define _PLANE_COLOR_CTL_2(pipe) \ 3683 _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B) 3684 #define PLANE_COLOR_CTL(pipe, plane) \ 3685 _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe)) 3686 3687 /* VBIOS regs */ 3688 #define VGACNTRL _MMIO(0x71400) 3689 # define VGA_DISP_DISABLE (1 << 31) 3690 # define VGA_2X_MODE (1 << 30) 3691 # define VGA_PIPE_B_SELECT (1 << 29) 3692 3693 #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400) 3694 3695 /* Ironlake */ 3696 3697 #define CPU_VGACNTRL _MMIO(0x41000) 3698 3699 #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030) 3700 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 3701 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */ 3702 #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */ 3703 #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */ 3704 #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */ 3705 #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */ 3706 #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0) 3707 #define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0) 3708 #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0) 3709 #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0) 3710 3711 /* refresh rate hardware control */ 3712 #define RR_HW_CTL _MMIO(0x45300) 3713 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff 3714 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 3715 3716 #define PCH_3DCGDIS0 _MMIO(0x46020) 3717 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) 3718 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) 3719 3720 #define PCH_3DCGDIS1 _MMIO(0x46024) 3721 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) 3722 3723 #define _PIPEA_DATA_M1 0x60030 3724 #define _PIPEA_DATA_N1 0x60034 3725 #define _PIPEA_DATA_M2 0x60038 3726 #define _PIPEA_DATA_N2 0x6003c 3727 #define _PIPEA_LINK_M1 0x60040 3728 #define _PIPEA_LINK_N1 0x60044 3729 #define _PIPEA_LINK_M2 0x60048 3730 #define _PIPEA_LINK_N2 0x6004c 3731 3732 /* PIPEB timing regs are same start from 0x61000 */ 3733 3734 #define _PIPEB_DATA_M1 0x61030 3735 #define _PIPEB_DATA_N1 0x61034 3736 #define _PIPEB_DATA_M2 0x61038 3737 #define _PIPEB_DATA_N2 0x6103c 3738 #define _PIPEB_LINK_M1 0x61040 3739 #define _PIPEB_LINK_N1 0x61044 3740 #define _PIPEB_LINK_M2 0x61048 3741 #define _PIPEB_LINK_N2 0x6104c 3742 3743 #define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1) 3744 #define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1) 3745 #define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2) 3746 #define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2) 3747 #define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1) 3748 #define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1) 3749 #define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2) 3750 #define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2) 3751 3752 /* CPU panel fitter */ 3753 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ 3754 #define _PFA_CTL_1 0x68080 3755 #define _PFB_CTL_1 0x68880 3756 #define PF_ENABLE REG_BIT(31) 3757 #define PF_PIPE_SEL_MASK_IVB REG_GENMASK(30, 29) /* ivb/hsw */ 3758 #define PF_PIPE_SEL_IVB(pipe) REG_FIELD_PREP(PF_PIPE_SEL_MASK_IVB, (pipe)) 3759 #define PF_FILTER_MASK REG_GENMASK(24, 23) 3760 #define PF_FILTER_PROGRAMMED REG_FIELD_PREP(PF_FILTER_MASK, 0) 3761 #define PF_FILTER_MED_3x3 REG_FIELD_PREP(PF_FILTER_MASK, 1) 3762 #define PF_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 2) 3763 #define PF_FILTER_EDGE_SOFTEN REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 3) 3764 #define _PFA_WIN_SZ 0x68074 3765 #define _PFB_WIN_SZ 0x68874 3766 #define PF_WIN_XSIZE_MASK REG_GENMASK(31, 16) 3767 #define PF_WIN_XSIZE(w) REG_FIELD_PREP(PF_WIN_XSIZE_MASK, (w)) 3768 #define PF_WIN_YSIZE_MASK REG_GENMASK(15, 0) 3769 #define PF_WIN_YSIZE(h) REG_FIELD_PREP(PF_WIN_YSIZE_MASK, (h)) 3770 #define _PFA_WIN_POS 0x68070 3771 #define _PFB_WIN_POS 0x68870 3772 #define PF_WIN_XPOS_MASK REG_GENMASK(31, 16) 3773 #define PF_WIN_XPOS(x) REG_FIELD_PREP(PF_WIN_XPOS_MASK, (x)) 3774 #define PF_WIN_YPOS_MASK REG_GENMASK(15, 0) 3775 #define PF_WIN_YPOS(y) REG_FIELD_PREP(PF_WIN_YPOS_MASK, (y)) 3776 #define _PFA_VSCALE 0x68084 3777 #define _PFB_VSCALE 0x68884 3778 #define _PFA_HSCALE 0x68090 3779 #define _PFB_HSCALE 0x68890 3780 3781 #define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) 3782 #define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) 3783 #define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) 3784 #define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) 3785 #define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) 3786 3787 /* 3788 * Skylake scalers 3789 */ 3790 #define _PS_1A_CTRL 0x68180 3791 #define _PS_2A_CTRL 0x68280 3792 #define _PS_1B_CTRL 0x68980 3793 #define _PS_2B_CTRL 0x68A80 3794 #define _PS_1C_CTRL 0x69180 3795 #define PS_SCALER_EN REG_BIT(31) 3796 #define PS_SCALER_TYPE_MASK REG_BIT(30) /* icl+ */ 3797 #define PS_SCALER_TYPE_NON_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 0) 3798 #define PS_SCALER_TYPE_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 1) 3799 #define SKL_PS_SCALER_MODE_MASK REG_GENMASK(29, 28) /* skl/bxt */ 3800 #define SKL_PS_SCALER_MODE_DYN REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 0) 3801 #define SKL_PS_SCALER_MODE_HQ REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 1) 3802 #define SKL_PS_SCALER_MODE_NV12 REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 2) 3803 #define PS_SCALER_MODE_MASK REG_BIT(29) /* glk-tgl */ 3804 #define PS_SCALER_MODE_NORMAL REG_FIELD_PREP(PS_SCALER_MODE_MASK, 0) 3805 #define PS_SCALER_MODE_PLANAR REG_FIELD_PREP(PS_SCALER_MODE_MASK, 1) 3806 #define PS_ADAPTIVE_FILTERING_EN REG_BIT(28) /* icl+ */ 3807 #define PS_BINDING_MASK REG_GENMASK(27, 25) 3808 #define PS_BINDING_PIPE REG_FIELD_PREP(PS_BINDING_MASK, 0) 3809 #define PS_BINDING_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_MASK, (plane_id) + 1) 3810 #define PS_FILTER_MASK REG_GENMASK(24, 23) 3811 #define PS_FILTER_MEDIUM REG_FIELD_PREP(PS_FILTER_MASK, 0) 3812 #define PS_FILTER_PROGRAMMED REG_FIELD_PREP(PS_FILTER_MASK, 1) 3813 #define PS_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_FILTER_MASK, 2) 3814 #define PS_FILTER_BILINEAR REG_FIELD_PREP(PS_FILTER_MASK, 3) 3815 #define PS_ADAPTIVE_FILTER_MASK REG_BIT(22) /* icl+ */ 3816 #define PS_ADAPTIVE_FILTER_MEDIUM REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 0) 3817 #define PS_ADAPTIVE_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 1) 3818 #define PS_PIPE_SCALER_LOC_MASK REG_BIT(21) /* icl+ */ 3819 #define PS_PIPE_SCALER_LOC_AFTER_OUTPUT_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 0) /* non-linear */ 3820 #define PS_PIPE_SCALER_LOC_AFTER_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 1) /* linear */ 3821 #define PS_VERT3TAP REG_BIT(21) /* skl/bxt */ 3822 #define PS_VERT_INT_INVERT_FIELD REG_BIT(20) 3823 #define PS_PROG_SCALE_FACTOR REG_BIT(19) /* tgl+ */ 3824 #define PS_PWRUP_PROGRESS REG_BIT(17) 3825 #define PS_V_FILTER_BYPASS REG_BIT(8) 3826 #define PS_VADAPT_EN REG_BIT(7) /* skl/bxt */ 3827 #define PS_VADAPT_MODE_MASK REG_GENMASK(6, 5) /* skl/bxt */ 3828 #define PS_VADAPT_MODE_LEAST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 0) 3829 #define PS_VADAPT_MODE_MOD_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 1) 3830 #define PS_VADAPT_MODE_MOST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 3) 3831 #define PS_BINDING_Y_MASK REG_GENMASK(7, 5) /* icl-tgl */ 3832 #define PS_BINDING_Y_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_Y_MASK, (plane_id) + 1) 3833 #define PS_Y_VERT_FILTER_SELECT_MASK REG_BIT(4) /* glk+ */ 3834 #define PS_Y_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_VERT_FILTER_SELECT_MASK, (set)) 3835 #define PS_Y_HORZ_FILTER_SELECT_MASK REG_BIT(3) /* glk+ */ 3836 #define PS_Y_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_HORZ_FILTER_SELECT_MASK, (set)) 3837 #define PS_UV_VERT_FILTER_SELECT_MASK REG_BIT(2) /* glk+ */ 3838 #define PS_UV_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_VERT_FILTER_SELECT_MASK, (set)) 3839 #define PS_UV_HORZ_FILTER_SELECT_MASK REG_BIT(1) /* glk+ */ 3840 #define PS_UV_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_HORZ_FILTER_SELECT_MASK, (set)) 3841 3842 #define _PS_PWR_GATE_1A 0x68160 3843 #define _PS_PWR_GATE_2A 0x68260 3844 #define _PS_PWR_GATE_1B 0x68960 3845 #define _PS_PWR_GATE_2B 0x68A60 3846 #define _PS_PWR_GATE_1C 0x69160 3847 #define PS_PWR_GATE_DIS_OVERRIDE REG_BIT(31) 3848 #define PS_PWR_GATE_SETTLING_TIME_MASK REG_GENMASK(4, 3) 3849 #define PS_PWR_GATE_SETTLING_TIME_32 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 0) 3850 #define PS_PWR_GATE_SETTLING_TIME_64 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 1) 3851 #define PS_PWR_GATE_SETTLING_TIME_96 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 2) 3852 #define PS_PWR_GATE_SETTLING_TIME_128 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 3) 3853 #define PS_PWR_GATE_SLPEN_MASK REG_GENMASK(1, 0) 3854 #define PS_PWR_GATE_SLPEN_8 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 0) 3855 #define PS_PWR_GATE_SLPEN_16 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 1) 3856 #define PS_PWR_GATE_SLPEN_24 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 2) 3857 #define PS_PWR_GATE_SLPEN_32 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 3) 3858 3859 #define _PS_WIN_POS_1A 0x68170 3860 #define _PS_WIN_POS_2A 0x68270 3861 #define _PS_WIN_POS_1B 0x68970 3862 #define _PS_WIN_POS_2B 0x68A70 3863 #define _PS_WIN_POS_1C 0x69170 3864 #define PS_WIN_XPOS_MASK REG_GENMASK(31, 16) 3865 #define PS_WIN_XPOS(x) REG_FIELD_PREP(PS_WIN_XPOS_MASK, (x)) 3866 #define PS_WIN_YPOS_MASK REG_GENMASK(15, 0) 3867 #define PS_WIN_YPOS(y) REG_FIELD_PREP(PS_WIN_YPOS_MASK, (y)) 3868 3869 #define _PS_WIN_SZ_1A 0x68174 3870 #define _PS_WIN_SZ_2A 0x68274 3871 #define _PS_WIN_SZ_1B 0x68974 3872 #define _PS_WIN_SZ_2B 0x68A74 3873 #define _PS_WIN_SZ_1C 0x69174 3874 #define PS_WIN_XSIZE_MASK REG_GENMASK(31, 16) 3875 #define PS_WIN_XSIZE(w) REG_FIELD_PREP(PS_WIN_XSIZE_MASK, (w)) 3876 #define PS_WIN_YSIZE_MASK REG_GENMASK(15, 0) 3877 #define PS_WIN_YSIZE(h) REG_FIELD_PREP(PS_WIN_YSIZE_MASK, (h)) 3878 3879 #define _PS_VSCALE_1A 0x68184 3880 #define _PS_VSCALE_2A 0x68284 3881 #define _PS_VSCALE_1B 0x68984 3882 #define _PS_VSCALE_2B 0x68A84 3883 #define _PS_VSCALE_1C 0x69184 3884 3885 #define _PS_HSCALE_1A 0x68190 3886 #define _PS_HSCALE_2A 0x68290 3887 #define _PS_HSCALE_1B 0x68990 3888 #define _PS_HSCALE_2B 0x68A90 3889 #define _PS_HSCALE_1C 0x69190 3890 3891 #define _PS_VPHASE_1A 0x68188 3892 #define _PS_VPHASE_2A 0x68288 3893 #define _PS_VPHASE_1B 0x68988 3894 #define _PS_VPHASE_2B 0x68A88 3895 #define _PS_VPHASE_1C 0x69188 3896 #define PS_Y_PHASE_MASK REG_GENMASK(31, 16) 3897 #define PS_Y_PHASE(x) REG_FIELD_PREP(PS_Y_PHASE_MASK, (x)) 3898 #define PS_UV_RGB_PHASE_MASK REG_GENMASK(15, 0) 3899 #define PS_UV_RGB_PHASE(x) REG_FIELD_PREP(PS_UV_RGB_PHASE_MASK, (x)) 3900 #define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */ 3901 #define PS_PHASE_TRIP (1 << 0) 3902 3903 #define _PS_HPHASE_1A 0x68194 3904 #define _PS_HPHASE_2A 0x68294 3905 #define _PS_HPHASE_1B 0x68994 3906 #define _PS_HPHASE_2B 0x68A94 3907 #define _PS_HPHASE_1C 0x69194 3908 3909 #define _PS_ECC_STAT_1A 0x681D0 3910 #define _PS_ECC_STAT_2A 0x682D0 3911 #define _PS_ECC_STAT_1B 0x689D0 3912 #define _PS_ECC_STAT_2B 0x68AD0 3913 #define _PS_ECC_STAT_1C 0x691D0 3914 3915 #define _PS_COEF_SET0_INDEX_1A 0x68198 3916 #define _PS_COEF_SET0_INDEX_2A 0x68298 3917 #define _PS_COEF_SET0_INDEX_1B 0x68998 3918 #define _PS_COEF_SET0_INDEX_2B 0x68A98 3919 #define PS_COEF_INDEX_AUTO_INC REG_BIT(10) 3920 3921 #define _PS_COEF_SET0_DATA_1A 0x6819C 3922 #define _PS_COEF_SET0_DATA_2A 0x6829C 3923 #define _PS_COEF_SET0_DATA_1B 0x6899C 3924 #define _PS_COEF_SET0_DATA_2B 0x68A9C 3925 3926 #define _ID(id, a, b) _PICK_EVEN(id, a, b) 3927 #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \ 3928 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \ 3929 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL)) 3930 #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \ 3931 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \ 3932 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B)) 3933 #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \ 3934 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \ 3935 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B)) 3936 #define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \ 3937 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \ 3938 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B)) 3939 #define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \ 3940 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \ 3941 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B)) 3942 #define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \ 3943 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \ 3944 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B)) 3945 #define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \ 3946 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \ 3947 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B)) 3948 #define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \ 3949 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \ 3950 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B)) 3951 #define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \ 3952 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \ 3953 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)) 3954 #define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe, \ 3955 _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \ 3956 _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8) 3957 3958 #define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \ 3959 _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \ 3960 _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8) 3961 3962 /* Display Internal Timeout Register */ 3963 #define RM_TIMEOUT _MMIO(0x42060) 3964 #define MMIO_TIMEOUT_US(us) ((us) << 0) 3965 3966 /* interrupts */ 3967 #define DE_MASTER_IRQ_CONTROL (1 << 31) 3968 #define DE_SPRITEB_FLIP_DONE (1 << 29) 3969 #define DE_SPRITEA_FLIP_DONE (1 << 28) 3970 #define DE_PLANEB_FLIP_DONE (1 << 27) 3971 #define DE_PLANEA_FLIP_DONE (1 << 26) 3972 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane))) 3973 #define DE_PCU_EVENT (1 << 25) 3974 #define DE_GTT_FAULT (1 << 24) 3975 #define DE_POISON (1 << 23) 3976 #define DE_PERFORM_COUNTER (1 << 22) 3977 #define DE_PCH_EVENT (1 << 21) 3978 #define DE_AUX_CHANNEL_A (1 << 20) 3979 #define DE_DP_A_HOTPLUG (1 << 19) 3980 #define DE_GSE (1 << 18) 3981 #define DE_PIPEB_VBLANK (1 << 15) 3982 #define DE_PIPEB_EVEN_FIELD (1 << 14) 3983 #define DE_PIPEB_ODD_FIELD (1 << 13) 3984 #define DE_PIPEB_LINE_COMPARE (1 << 12) 3985 #define DE_PIPEB_VSYNC (1 << 11) 3986 #define DE_PIPEB_CRC_DONE (1 << 10) 3987 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) 3988 #define DE_PIPEA_VBLANK (1 << 7) 3989 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe))) 3990 #define DE_PIPEA_EVEN_FIELD (1 << 6) 3991 #define DE_PIPEA_ODD_FIELD (1 << 5) 3992 #define DE_PIPEA_LINE_COMPARE (1 << 4) 3993 #define DE_PIPEA_VSYNC (1 << 3) 3994 #define DE_PIPEA_CRC_DONE (1 << 2) 3995 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe))) 3996 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 3997 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe))) 3998 3999 /* More Ivybridge lolz */ 4000 #define DE_ERR_INT_IVB (1 << 30) 4001 #define DE_GSE_IVB (1 << 29) 4002 #define DE_PCH_EVENT_IVB (1 << 28) 4003 #define DE_DP_A_HOTPLUG_IVB (1 << 27) 4004 #define DE_AUX_CHANNEL_A_IVB (1 << 26) 4005 #define DE_EDP_PSR_INT_HSW (1 << 19) 4006 #define DE_SPRITEC_FLIP_DONE_IVB (1 << 14) 4007 #define DE_PLANEC_FLIP_DONE_IVB (1 << 13) 4008 #define DE_PIPEC_VBLANK_IVB (1 << 10) 4009 #define DE_SPRITEB_FLIP_DONE_IVB (1 << 9) 4010 #define DE_PLANEB_FLIP_DONE_IVB (1 << 8) 4011 #define DE_PIPEB_VBLANK_IVB (1 << 5) 4012 #define DE_SPRITEA_FLIP_DONE_IVB (1 << 4) 4013 #define DE_PLANEA_FLIP_DONE_IVB (1 << 3) 4014 #define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane))) 4015 #define DE_PIPEA_VBLANK_IVB (1 << 0) 4016 #define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5)) 4017 4018 #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */ 4019 #define MASTER_INTERRUPT_ENABLE (1 << 31) 4020 4021 #define DEISR _MMIO(0x44000) 4022 #define DEIMR _MMIO(0x44004) 4023 #define DEIIR _MMIO(0x44008) 4024 #define DEIER _MMIO(0x4400c) 4025 4026 #define GTISR _MMIO(0x44010) 4027 #define GTIMR _MMIO(0x44014) 4028 #define GTIIR _MMIO(0x44018) 4029 #define GTIER _MMIO(0x4401c) 4030 4031 #define GEN8_MASTER_IRQ _MMIO(0x44200) 4032 #define GEN8_MASTER_IRQ_CONTROL (1 << 31) 4033 #define GEN8_PCU_IRQ (1 << 30) 4034 #define GEN8_DE_PCH_IRQ (1 << 23) 4035 #define GEN8_DE_MISC_IRQ (1 << 22) 4036 #define GEN8_DE_PORT_IRQ (1 << 20) 4037 #define GEN8_DE_PIPE_C_IRQ (1 << 18) 4038 #define GEN8_DE_PIPE_B_IRQ (1 << 17) 4039 #define GEN8_DE_PIPE_A_IRQ (1 << 16) 4040 #define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe))) 4041 #define GEN8_GT_VECS_IRQ (1 << 6) 4042 #define GEN8_GT_GUC_IRQ (1 << 5) 4043 #define GEN8_GT_PM_IRQ (1 << 4) 4044 #define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */ 4045 #define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */ 4046 #define GEN8_GT_BCS_IRQ (1 << 1) 4047 #define GEN8_GT_RCS_IRQ (1 << 0) 4048 4049 #define XELPD_DISPLAY_ERR_FATAL_MASK _MMIO(0x4421c) 4050 4051 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which))) 4052 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which))) 4053 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which))) 4054 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which))) 4055 4056 #define GEN8_RCS_IRQ_SHIFT 0 4057 #define GEN8_BCS_IRQ_SHIFT 16 4058 #define GEN8_VCS0_IRQ_SHIFT 0 /* NB: VCS1 in bspec! */ 4059 #define GEN8_VCS1_IRQ_SHIFT 16 /* NB: VCS2 in bpsec! */ 4060 #define GEN8_VECS_IRQ_SHIFT 0 4061 #define GEN8_WD_IRQ_SHIFT 16 4062 4063 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe))) 4064 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe))) 4065 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe))) 4066 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe))) 4067 #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31) 4068 #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29) 4069 #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28) 4070 #define XELPD_PIPE_SOFT_UNDERRUN (1 << 22) 4071 #define XELPD_PIPE_HARD_UNDERRUN (1 << 21) 4072 #define GEN12_PIPE_VBLANK_UNMOD (1 << 19) 4073 #define GEN8_PIPE_CURSOR_FAULT (1 << 10) 4074 #define GEN8_PIPE_SPRITE_FAULT (1 << 9) 4075 #define GEN8_PIPE_PRIMARY_FAULT (1 << 8) 4076 #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5) 4077 #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4) 4078 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) 4079 #define GEN8_PIPE_VSYNC (1 << 1) 4080 #define GEN8_PIPE_VBLANK (1 << 0) 4081 #define GEN9_PIPE_CURSOR_FAULT (1 << 11) 4082 #define GEN11_PIPE_PLANE7_FAULT (1 << 22) 4083 #define GEN11_PIPE_PLANE6_FAULT (1 << 21) 4084 #define GEN11_PIPE_PLANE5_FAULT (1 << 20) 4085 #define GEN9_PIPE_PLANE4_FAULT (1 << 10) 4086 #define GEN9_PIPE_PLANE3_FAULT (1 << 9) 4087 #define GEN9_PIPE_PLANE2_FAULT (1 << 8) 4088 #define GEN9_PIPE_PLANE1_FAULT (1 << 7) 4089 #define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6) 4090 #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5) 4091 #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4) 4092 #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3) 4093 #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p))) 4094 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ 4095 (GEN8_PIPE_CURSOR_FAULT | \ 4096 GEN8_PIPE_SPRITE_FAULT | \ 4097 GEN8_PIPE_PRIMARY_FAULT) 4098 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \ 4099 (GEN9_PIPE_CURSOR_FAULT | \ 4100 GEN9_PIPE_PLANE4_FAULT | \ 4101 GEN9_PIPE_PLANE3_FAULT | \ 4102 GEN9_PIPE_PLANE2_FAULT | \ 4103 GEN9_PIPE_PLANE1_FAULT) 4104 #define GEN11_DE_PIPE_IRQ_FAULT_ERRORS \ 4105 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \ 4106 GEN11_PIPE_PLANE7_FAULT | \ 4107 GEN11_PIPE_PLANE6_FAULT | \ 4108 GEN11_PIPE_PLANE5_FAULT) 4109 #define RKL_DE_PIPE_IRQ_FAULT_ERRORS \ 4110 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \ 4111 GEN11_PIPE_PLANE5_FAULT) 4112 4113 #define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A) 4114 #define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1) 4115 4116 #define GEN8_DE_PORT_ISR _MMIO(0x44440) 4117 #define GEN8_DE_PORT_IMR _MMIO(0x44444) 4118 #define GEN8_DE_PORT_IIR _MMIO(0x44448) 4119 #define GEN8_DE_PORT_IER _MMIO(0x4444c) 4120 #define DSI1_NON_TE (1 << 31) 4121 #define DSI0_NON_TE (1 << 30) 4122 #define ICL_AUX_CHANNEL_E (1 << 29) 4123 #define ICL_AUX_CHANNEL_F (1 << 28) 4124 #define GEN9_AUX_CHANNEL_D (1 << 27) 4125 #define GEN9_AUX_CHANNEL_C (1 << 26) 4126 #define GEN9_AUX_CHANNEL_B (1 << 25) 4127 #define DSI1_TE (1 << 24) 4128 #define DSI0_TE (1 << 23) 4129 #define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin)) 4130 #define BXT_DE_PORT_HOTPLUG_MASK (GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \ 4131 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \ 4132 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)) 4133 #define BDW_DE_PORT_HOTPLUG_MASK GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) 4134 #define BXT_DE_PORT_GMBUS (1 << 1) 4135 #define GEN8_AUX_CHANNEL_A (1 << 0) 4136 #define TGL_DE_PORT_AUX_USBC6 REG_BIT(13) 4137 #define XELPD_DE_PORT_AUX_DDIE REG_BIT(13) 4138 #define TGL_DE_PORT_AUX_USBC5 REG_BIT(12) 4139 #define XELPD_DE_PORT_AUX_DDID REG_BIT(12) 4140 #define TGL_DE_PORT_AUX_USBC4 REG_BIT(11) 4141 #define TGL_DE_PORT_AUX_USBC3 REG_BIT(10) 4142 #define TGL_DE_PORT_AUX_USBC2 REG_BIT(9) 4143 #define TGL_DE_PORT_AUX_USBC1 REG_BIT(8) 4144 #define TGL_DE_PORT_AUX_DDIC REG_BIT(2) 4145 #define TGL_DE_PORT_AUX_DDIB REG_BIT(1) 4146 #define TGL_DE_PORT_AUX_DDIA REG_BIT(0) 4147 4148 #define GEN8_DE_MISC_ISR _MMIO(0x44460) 4149 #define GEN8_DE_MISC_IMR _MMIO(0x44464) 4150 #define GEN8_DE_MISC_IIR _MMIO(0x44468) 4151 #define GEN8_DE_MISC_IER _MMIO(0x4446c) 4152 #define XELPDP_PMDEMAND_RSPTOUT_ERR REG_BIT(27) 4153 #define GEN8_DE_MISC_GSE REG_BIT(27) 4154 #define GEN8_DE_EDP_PSR REG_BIT(19) 4155 #define XELPDP_PMDEMAND_RSP REG_BIT(3) 4156 4157 #define GEN8_PCU_ISR _MMIO(0x444e0) 4158 #define GEN8_PCU_IMR _MMIO(0x444e4) 4159 #define GEN8_PCU_IIR _MMIO(0x444e8) 4160 #define GEN8_PCU_IER _MMIO(0x444ec) 4161 4162 #define GEN11_GU_MISC_ISR _MMIO(0x444f0) 4163 #define GEN11_GU_MISC_IMR _MMIO(0x444f4) 4164 #define GEN11_GU_MISC_IIR _MMIO(0x444f8) 4165 #define GEN11_GU_MISC_IER _MMIO(0x444fc) 4166 #define GEN11_GU_MISC_GSE (1 << 27) 4167 4168 #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010) 4169 #define GEN11_MASTER_IRQ (1 << 31) 4170 #define GEN11_PCU_IRQ (1 << 30) 4171 #define GEN11_GU_MISC_IRQ (1 << 29) 4172 #define GEN11_DISPLAY_IRQ (1 << 16) 4173 #define GEN11_GT_DW_IRQ(x) (1 << (x)) 4174 #define GEN11_GT_DW1_IRQ (1 << 1) 4175 #define GEN11_GT_DW0_IRQ (1 << 0) 4176 4177 #define DG1_MSTR_TILE_INTR _MMIO(0x190008) 4178 #define DG1_MSTR_IRQ REG_BIT(31) 4179 #define DG1_MSTR_TILE(t) REG_BIT(t) 4180 4181 #define GEN11_DISPLAY_INT_CTL _MMIO(0x44200) 4182 #define GEN11_DISPLAY_IRQ_ENABLE (1 << 31) 4183 #define GEN11_AUDIO_CODEC_IRQ (1 << 24) 4184 #define GEN11_DE_PCH_IRQ (1 << 23) 4185 #define GEN11_DE_MISC_IRQ (1 << 22) 4186 #define GEN11_DE_HPD_IRQ (1 << 21) 4187 #define GEN11_DE_PORT_IRQ (1 << 20) 4188 #define GEN11_DE_PIPE_C (1 << 18) 4189 #define GEN11_DE_PIPE_B (1 << 17) 4190 #define GEN11_DE_PIPE_A (1 << 16) 4191 4192 #define GEN11_DE_HPD_ISR _MMIO(0x44470) 4193 #define GEN11_DE_HPD_IMR _MMIO(0x44474) 4194 #define GEN11_DE_HPD_IIR _MMIO(0x44478) 4195 #define GEN11_DE_HPD_IER _MMIO(0x4447c) 4196 #define GEN11_TC_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin)) 4197 #define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(HPD_PORT_TC6) | \ 4198 GEN11_TC_HOTPLUG(HPD_PORT_TC5) | \ 4199 GEN11_TC_HOTPLUG(HPD_PORT_TC4) | \ 4200 GEN11_TC_HOTPLUG(HPD_PORT_TC3) | \ 4201 GEN11_TC_HOTPLUG(HPD_PORT_TC2) | \ 4202 GEN11_TC_HOTPLUG(HPD_PORT_TC1)) 4203 #define GEN11_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin)) 4204 #define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(HPD_PORT_TC6) | \ 4205 GEN11_TBT_HOTPLUG(HPD_PORT_TC5) | \ 4206 GEN11_TBT_HOTPLUG(HPD_PORT_TC4) | \ 4207 GEN11_TBT_HOTPLUG(HPD_PORT_TC3) | \ 4208 GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \ 4209 GEN11_TBT_HOTPLUG(HPD_PORT_TC1)) 4210 4211 #define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030) 4212 #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038) 4213 #define GEN11_HOTPLUG_CTL_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4)) 4214 #define GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4)) 4215 #define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4)) 4216 #define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 << (_HPD_PIN_TC(hpd_pin) * 4)) 4217 4218 #define PICAINTERRUPT_ISR _MMIO(0x16FE50) 4219 #define PICAINTERRUPT_IMR _MMIO(0x16FE54) 4220 #define PICAINTERRUPT_IIR _MMIO(0x16FE58) 4221 #define PICAINTERRUPT_IER _MMIO(0x16FE5C) 4222 #define XELPDP_DP_ALT_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin)) 4223 #define XELPDP_DP_ALT_HOTPLUG_MASK REG_GENMASK(19, 16) 4224 #define XELPDP_AUX_TC(hpd_pin) REG_BIT(8 + _HPD_PIN_TC(hpd_pin)) 4225 #define XELPDP_AUX_TC_MASK REG_GENMASK(11, 8) 4226 #define XE2LPD_AUX_DDI(hpd_pin) REG_BIT(6 + _HPD_PIN_DDI(hpd_pin)) 4227 #define XE2LPD_AUX_DDI_MASK REG_GENMASK(7, 6) 4228 #define XELPDP_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin)) 4229 #define XELPDP_TBT_HOTPLUG_MASK REG_GENMASK(3, 0) 4230 4231 #define XELPDP_PORT_HOTPLUG_CTL(hpd_pin) _MMIO(0x16F270 + (_HPD_PIN_TC(hpd_pin) * 0x200)) 4232 #define XELPDP_TBT_HOTPLUG_ENABLE REG_BIT(6) 4233 #define XELPDP_TBT_HPD_LONG_DETECT REG_BIT(5) 4234 #define XELPDP_TBT_HPD_SHORT_DETECT REG_BIT(4) 4235 #define XELPDP_DP_ALT_HOTPLUG_ENABLE REG_BIT(2) 4236 #define XELPDP_DP_ALT_HPD_LONG_DETECT REG_BIT(1) 4237 #define XELPDP_DP_ALT_HPD_SHORT_DETECT REG_BIT(0) 4238 4239 #define XELPDP_INITIATE_PMDEMAND_REQUEST(dword) _MMIO(0x45230 + 4 * (dword)) 4240 #define XELPDP_PMDEMAND_QCLK_GV_BW_MASK REG_GENMASK(31, 16) 4241 #define XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK REG_GENMASK(14, 12) 4242 #define XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK REG_GENMASK(11, 8) 4243 #define XELPDP_PMDEMAND_PIPES_MASK REG_GENMASK(7, 6) 4244 #define XELPDP_PMDEMAND_DBUFS_MASK REG_GENMASK(5, 4) 4245 #define XELPDP_PMDEMAND_PHYS_MASK REG_GENMASK(2, 0) 4246 4247 #define XELPDP_PMDEMAND_REQ_ENABLE REG_BIT(31) 4248 #define XELPDP_PMDEMAND_CDCLK_FREQ_MASK REG_GENMASK(30, 20) 4249 #define XELPDP_PMDEMAND_DDICLK_FREQ_MASK REG_GENMASK(18, 8) 4250 #define XELPDP_PMDEMAND_SCALERS_MASK REG_GENMASK(6, 4) 4251 #define XELPDP_PMDEMAND_PLLS_MASK REG_GENMASK(2, 0) 4252 4253 #define GEN12_DCPR_STATUS_1 _MMIO(0x46440) 4254 #define XELPDP_PMDEMAND_INFLIGHT_STATUS REG_BIT(26) 4255 4256 #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004) 4257 /* Required on all Ironlake and Sandybridge according to the B-Spec. */ 4258 #define ILK_ELPIN_409_SELECT REG_BIT(25) 4259 #define ILK_DPARB_GATE REG_BIT(22) 4260 #define ILK_VSDPFD_FULL REG_BIT(21) 4261 4262 #define FUSE_STRAP _MMIO(0x42014) 4263 #define ILK_INTERNAL_GRAPHICS_DISABLE REG_BIT(31) 4264 #define ILK_INTERNAL_DISPLAY_DISABLE REG_BIT(30) 4265 #define ILK_DISPLAY_DEBUG_DISABLE REG_BIT(29) 4266 #define IVB_PIPE_C_DISABLE REG_BIT(28) 4267 #define ILK_HDCP_DISABLE REG_BIT(25) 4268 #define ILK_eDP_A_DISABLE REG_BIT(24) 4269 #define HSW_CDCLK_LIMIT REG_BIT(24) 4270 #define ILK_DESKTOP REG_BIT(23) 4271 #define HSW_CPU_SSC_ENABLE REG_BIT(21) 4272 4273 #define FUSE_STRAP3 _MMIO(0x42020) 4274 #define HSW_REF_CLK_SELECT REG_BIT(1) 4275 4276 #define ILK_DSPCLK_GATE_D _MMIO(0x42020) 4277 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE REG_BIT(28) 4278 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE REG_BIT(9) 4279 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE REG_BIT(8) 4280 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE REG_BIT(7) 4281 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE REG_BIT(5) 4282 4283 #define IVB_CHICKEN3 _MMIO(0x4200c) 4284 #define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE REG_BIT(5) 4285 #define CHICKEN3_DGMG_DONE_FIX_DISABLE REG_BIT(2) 4286 4287 #define CHICKEN_PAR1_1 _MMIO(0x42080) 4288 #define IGNORE_KVMR_PIPE_A REG_BIT(23) 4289 #define KBL_ARB_FILL_SPARE_22 REG_BIT(22) 4290 #define DIS_RAM_BYPASS_PSR2_MAN_TRACK REG_BIT(16) 4291 #define SKL_DE_COMPRESSED_HASH_MODE REG_BIT(15) 4292 #define HSW_MASK_VBL_TO_PIPE_IN_SRD REG_BIT(15) /* hsw/bdw */ 4293 #define FORCE_ARB_IDLE_PLANES REG_BIT(14) 4294 #define SKL_EDP_PSR_FIX_RDWRAP REG_BIT(3) 4295 #define IGNORE_PSR2_HW_TRACKING REG_BIT(1) 4296 4297 #define CHICKEN_PAR2_1 _MMIO(0x42090) 4298 #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT REG_BIT(14) 4299 4300 #define CHICKEN_MISC_2 _MMIO(0x42084) 4301 #define CHICKEN_MISC_DISABLE_DPT REG_BIT(30) /* adl,dg2 */ 4302 #define KBL_ARB_FILL_SPARE_14 REG_BIT(14) 4303 #define KBL_ARB_FILL_SPARE_13 REG_BIT(13) 4304 #define GLK_CL2_PWR_DOWN REG_BIT(12) 4305 #define GLK_CL1_PWR_DOWN REG_BIT(11) 4306 #define GLK_CL0_PWR_DOWN REG_BIT(10) 4307 4308 #define CHICKEN_MISC_3 _MMIO(0x42088) 4309 #define DP_MST_DPT_DPTP_ALIGN_WA(trans) REG_BIT(9 + (trans) - TRANSCODER_A) 4310 #define DP_MST_SHORT_HBLANK_WA(trans) REG_BIT(5 + (trans) - TRANSCODER_A) 4311 #define DP_MST_FEC_BS_JITTER_WA(trans) REG_BIT(0 + (trans) - TRANSCODER_A) 4312 4313 #define CHICKEN_MISC_4 _MMIO(0x4208c) 4314 #define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13) 4315 #define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0) 4316 #define CHICKEN_FBC_STRIDE(x) REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x)) 4317 4318 #define _CHICKEN_PIPESL_1_A 0x420b0 4319 #define _CHICKEN_PIPESL_1_B 0x420b4 4320 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) 4321 #define HSW_PRI_STRETCH_MAX_MASK REG_GENMASK(28, 27) 4322 #define HSW_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0) 4323 #define HSW_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1) 4324 #define HSW_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2) 4325 #define HSW_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3) 4326 #define HSW_SPR_STRETCH_MAX_MASK REG_GENMASK(26, 25) 4327 #define HSW_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0) 4328 #define HSW_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1) 4329 #define HSW_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2) 4330 #define HSW_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3) 4331 #define HSW_FBCQ_DIS REG_BIT(22) 4332 #define HSW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(15) /* hsw */ 4333 #define SKL_PSR_MASK_PLANE_FLIP REG_BIT(11) /* skl+ */ 4334 #define SKL_PLANE1_STRETCH_MAX_MASK REG_GENMASK(1, 0) 4335 #define SKL_PLANE1_STRETCH_MAX_X8 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0) 4336 #define SKL_PLANE1_STRETCH_MAX_X4 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1) 4337 #define SKL_PLANE1_STRETCH_MAX_X2 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2) 4338 #define SKL_PLANE1_STRETCH_MAX_X1 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3) 4339 #define BDW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(0) /* bdw */ 4340 4341 #define _CHICKEN_TRANS_A 0x420c0 4342 #define _CHICKEN_TRANS_B 0x420c4 4343 #define _CHICKEN_TRANS_C 0x420c8 4344 #define _CHICKEN_TRANS_EDP 0x420cc 4345 #define _CHICKEN_TRANS_D 0x420d8 4346 #define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \ 4347 [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \ 4348 [TRANSCODER_A] = _CHICKEN_TRANS_A, \ 4349 [TRANSCODER_B] = _CHICKEN_TRANS_B, \ 4350 [TRANSCODER_C] = _CHICKEN_TRANS_C, \ 4351 [TRANSCODER_D] = _CHICKEN_TRANS_D)) 4352 #define _MTL_CHICKEN_TRANS_A 0x604e0 4353 #define _MTL_CHICKEN_TRANS_B 0x614e0 4354 #define MTL_CHICKEN_TRANS(trans) _MMIO_TRANS((trans), \ 4355 _MTL_CHICKEN_TRANS_A, \ 4356 _MTL_CHICKEN_TRANS_B) 4357 #define PIPE_VBLANK_WITH_DELAY REG_BIT(31) /* tgl+ */ 4358 #define SKL_UNMASK_VBL_TO_PIPE_IN_SRD REG_BIT(30) /* skl+ */ 4359 #define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) 4360 #define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x) 4361 #define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */ 4362 #define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23) 4363 #define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19) 4364 #define ADLP_1_BASED_X_GRANULARITY REG_BIT(18) 4365 #define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18) 4366 #define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */ 4367 #define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */ 4368 #define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15) 4369 #define DP_FEC_BS_JITTER_WA REG_BIT(15) 4370 #define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12) 4371 #define DP_DSC_INSERT_SF_AT_EOL_WA REG_BIT(4) 4372 4373 #define DISP_ARB_CTL _MMIO(0x45000) 4374 #define DISP_FBC_MEMORY_WAKE REG_BIT(31) 4375 #define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13) 4376 #define DISP_FBC_WM_DIS REG_BIT(15) 4377 4378 #define DISP_ARB_CTL2 _MMIO(0x45004) 4379 #define DISP_DATA_PARTITION_5_6 REG_BIT(6) 4380 #define DISP_IPC_ENABLE REG_BIT(3) 4381 4382 #define GEN7_MSG_CTL _MMIO(0x45010) 4383 #define WAIT_FOR_PCH_RESET_ACK (1 << 1) 4384 #define WAIT_FOR_PCH_FLR_ACK (1 << 0) 4385 4386 #define _BW_BUDDY0_CTL 0x45130 4387 #define _BW_BUDDY1_CTL 0x45140 4388 #define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \ 4389 _BW_BUDDY0_CTL, \ 4390 _BW_BUDDY1_CTL)) 4391 #define BW_BUDDY_DISABLE REG_BIT(31) 4392 #define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16) 4393 #define BW_BUDDY_TLB_REQ_TIMER(x) REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x) 4394 4395 #define _BW_BUDDY0_PAGE_MASK 0x45134 4396 #define _BW_BUDDY1_PAGE_MASK 0x45144 4397 #define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \ 4398 _BW_BUDDY0_PAGE_MASK, \ 4399 _BW_BUDDY1_PAGE_MASK)) 4400 4401 #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) 4402 #define MTL_RESET_PICA_HANDSHAKE_EN REG_BIT(6) 4403 #define RESET_PCH_HANDSHAKE_ENABLE REG_BIT(4) 4404 4405 #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) 4406 #define LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31) 4407 #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30) 4408 #define LATENCY_REPORTING_REMOVED_PIPE_C REG_BIT(25) 4409 #define LATENCY_REPORTING_REMOVED_PIPE_B REG_BIT(24) 4410 #define LATENCY_REPORTING_REMOVED_PIPE_A REG_BIT(23) 4411 #define ICL_DELAY_PMRSP REG_BIT(22) 4412 #define DISABLE_FLR_SRC REG_BIT(15) 4413 #define MASK_WAKEMEM REG_BIT(13) 4414 #define DDI_CLOCK_REG_ACCESS REG_BIT(7) 4415 4416 #define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434) 4417 #define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27) 4418 #define DCPR_MASK_LPMODE REG_BIT(26) 4419 #define DCPR_SEND_RESP_IMM REG_BIT(25) 4420 #define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24) 4421 4422 #define XELPD_CHICKEN_DCPR_3 _MMIO(0x46438) 4423 #define DMD_RSP_TIMEOUT_DISABLE REG_BIT(19) 4424 4425 #define SKL_DFSM _MMIO(0x51000) 4426 #define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27) 4427 #define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25) 4428 #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23) 4429 #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23) 4430 #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23) 4431 #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23) 4432 #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23) 4433 #define ICL_DFSM_DMC_DISABLE (1 << 23) 4434 #define SKL_DFSM_PIPE_A_DISABLE (1 << 30) 4435 #define SKL_DFSM_PIPE_B_DISABLE (1 << 21) 4436 #define SKL_DFSM_PIPE_C_DISABLE (1 << 28) 4437 #define TGL_DFSM_PIPE_D_DISABLE (1 << 22) 4438 #define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7) 4439 4440 #define XE2LPD_DE_CAP _MMIO(0x41100) 4441 #define XE2LPD_DE_CAP_3DLUT_MASK REG_GENMASK(31, 30) 4442 #define XE2LPD_DE_CAP_DSC_MASK REG_GENMASK(29, 28) 4443 #define XE2LPD_DE_CAP_DSC_REMOVED 1 4444 #define XE2LPD_DE_CAP_SCALER_MASK REG_GENMASK(27, 26) 4445 #define XE2LPD_DE_CAP_SCALER_SINGLE 1 4446 4447 #define SKL_DSSM _MMIO(0x51004) 4448 #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29) 4449 #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29) 4450 #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29) 4451 #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29) 4452 4453 #define GMD_ID_DISPLAY _MMIO(0x510a0) 4454 #define GMD_ID_ARCH_MASK REG_GENMASK(31, 22) 4455 #define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14) 4456 #define GMD_ID_STEP REG_GENMASK(5, 0) 4457 4458 /*GEN11 chicken */ 4459 #define _PIPEA_CHICKEN 0x70038 4460 #define _PIPEB_CHICKEN 0x71038 4461 #define _PIPEC_CHICKEN 0x72038 4462 #define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\ 4463 _PIPEB_CHICKEN) 4464 #define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30) 4465 #define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30) 4466 #define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15) 4467 #define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12) 4468 #define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7) 4469 4470 /* PCH */ 4471 4472 #define PCH_DISPLAY_BASE 0xc0000u 4473 4474 /* south display engine interrupt: IBX */ 4475 #define SDE_AUDIO_POWER_D (1 << 27) 4476 #define SDE_AUDIO_POWER_C (1 << 26) 4477 #define SDE_AUDIO_POWER_B (1 << 25) 4478 #define SDE_AUDIO_POWER_SHIFT (25) 4479 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) 4480 #define SDE_GMBUS (1 << 24) 4481 #define SDE_AUDIO_HDCP_TRANSB (1 << 23) 4482 #define SDE_AUDIO_HDCP_TRANSA (1 << 22) 4483 #define SDE_AUDIO_HDCP_MASK (3 << 22) 4484 #define SDE_AUDIO_TRANSB (1 << 21) 4485 #define SDE_AUDIO_TRANSA (1 << 20) 4486 #define SDE_AUDIO_TRANS_MASK (3 << 20) 4487 #define SDE_POISON (1 << 19) 4488 /* 18 reserved */ 4489 #define SDE_FDI_RXB (1 << 17) 4490 #define SDE_FDI_RXA (1 << 16) 4491 #define SDE_FDI_MASK (3 << 16) 4492 #define SDE_AUXD (1 << 15) 4493 #define SDE_AUXC (1 << 14) 4494 #define SDE_AUXB (1 << 13) 4495 #define SDE_AUX_MASK (7 << 13) 4496 /* 12 reserved */ 4497 #define SDE_CRT_HOTPLUG (1 << 11) 4498 #define SDE_PORTD_HOTPLUG (1 << 10) 4499 #define SDE_PORTC_HOTPLUG (1 << 9) 4500 #define SDE_PORTB_HOTPLUG (1 << 8) 4501 #define SDE_SDVOB_HOTPLUG (1 << 6) 4502 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \ 4503 SDE_SDVOB_HOTPLUG | \ 4504 SDE_PORTB_HOTPLUG | \ 4505 SDE_PORTC_HOTPLUG | \ 4506 SDE_PORTD_HOTPLUG) 4507 #define SDE_TRANSB_CRC_DONE (1 << 5) 4508 #define SDE_TRANSB_CRC_ERR (1 << 4) 4509 #define SDE_TRANSB_FIFO_UNDER (1 << 3) 4510 #define SDE_TRANSA_CRC_DONE (1 << 2) 4511 #define SDE_TRANSA_CRC_ERR (1 << 1) 4512 #define SDE_TRANSA_FIFO_UNDER (1 << 0) 4513 #define SDE_TRANS_MASK (0x3f) 4514 4515 /* south display engine interrupt: CPT - CNP */ 4516 #define SDE_AUDIO_POWER_D_CPT (1 << 31) 4517 #define SDE_AUDIO_POWER_C_CPT (1 << 30) 4518 #define SDE_AUDIO_POWER_B_CPT (1 << 29) 4519 #define SDE_AUDIO_POWER_SHIFT_CPT 29 4520 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29) 4521 #define SDE_AUXD_CPT (1 << 27) 4522 #define SDE_AUXC_CPT (1 << 26) 4523 #define SDE_AUXB_CPT (1 << 25) 4524 #define SDE_AUX_MASK_CPT (7 << 25) 4525 #define SDE_PORTE_HOTPLUG_SPT (1 << 25) 4526 #define SDE_PORTA_HOTPLUG_SPT (1 << 24) 4527 #define SDE_PORTD_HOTPLUG_CPT (1 << 23) 4528 #define SDE_PORTC_HOTPLUG_CPT (1 << 22) 4529 #define SDE_PORTB_HOTPLUG_CPT (1 << 21) 4530 #define SDE_CRT_HOTPLUG_CPT (1 << 19) 4531 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18) 4532 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ 4533 SDE_SDVOB_HOTPLUG_CPT | \ 4534 SDE_PORTD_HOTPLUG_CPT | \ 4535 SDE_PORTC_HOTPLUG_CPT | \ 4536 SDE_PORTB_HOTPLUG_CPT) 4537 #define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \ 4538 SDE_PORTD_HOTPLUG_CPT | \ 4539 SDE_PORTC_HOTPLUG_CPT | \ 4540 SDE_PORTB_HOTPLUG_CPT | \ 4541 SDE_PORTA_HOTPLUG_SPT) 4542 #define SDE_GMBUS_CPT (1 << 17) 4543 #define SDE_ERROR_CPT (1 << 16) 4544 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) 4545 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) 4546 #define SDE_FDI_RXC_CPT (1 << 8) 4547 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) 4548 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) 4549 #define SDE_FDI_RXB_CPT (1 << 4) 4550 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) 4551 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) 4552 #define SDE_FDI_RXA_CPT (1 << 0) 4553 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \ 4554 SDE_AUDIO_CP_REQ_B_CPT | \ 4555 SDE_AUDIO_CP_REQ_A_CPT) 4556 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \ 4557 SDE_AUDIO_CP_CHG_B_CPT | \ 4558 SDE_AUDIO_CP_CHG_A_CPT) 4559 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \ 4560 SDE_FDI_RXB_CPT | \ 4561 SDE_FDI_RXA_CPT) 4562 4563 /* south display engine interrupt: ICP/TGP/MTP */ 4564 #define SDE_PICAINTERRUPT REG_BIT(31) 4565 #define SDE_GMBUS_ICP (1 << 23) 4566 #define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin)) 4567 #define SDE_TC_HOTPLUG_DG2(hpd_pin) REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */ 4568 #define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin)) 4569 #define SDE_DDI_HOTPLUG_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \ 4570 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \ 4571 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \ 4572 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A)) 4573 #define SDE_TC_HOTPLUG_MASK_ICP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \ 4574 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \ 4575 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \ 4576 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \ 4577 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \ 4578 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1)) 4579 4580 #define SDEISR _MMIO(0xc4000) 4581 #define SDEIMR _MMIO(0xc4004) 4582 #define SDEIIR _MMIO(0xc4008) 4583 #define SDEIER _MMIO(0xc400c) 4584 4585 #define SERR_INT _MMIO(0xc4040) 4586 #define SERR_INT_POISON (1 << 31) 4587 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) 4588 4589 /* digital port hotplug */ 4590 #define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */ 4591 #define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */ 4592 #define BXT_DDIA_HPD_INVERT (1 << 27) 4593 #define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */ 4594 #define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */ 4595 #define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */ 4596 #define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */ 4597 #define PORTD_HOTPLUG_ENABLE (1 << 20) 4598 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */ 4599 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */ 4600 #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */ 4601 #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */ 4602 #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */ 4603 #define PORTD_HOTPLUG_STATUS_MASK (3 << 16) 4604 #define PORTD_HOTPLUG_NO_DETECT (0 << 16) 4605 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) 4606 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16) 4607 #define PORTC_HOTPLUG_ENABLE (1 << 12) 4608 #define BXT_DDIC_HPD_INVERT (1 << 11) 4609 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */ 4610 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */ 4611 #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */ 4612 #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */ 4613 #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */ 4614 #define PORTC_HOTPLUG_STATUS_MASK (3 << 8) 4615 #define PORTC_HOTPLUG_NO_DETECT (0 << 8) 4616 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) 4617 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8) 4618 #define PORTB_HOTPLUG_ENABLE (1 << 4) 4619 #define BXT_DDIB_HPD_INVERT (1 << 3) 4620 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */ 4621 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */ 4622 #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */ 4623 #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */ 4624 #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */ 4625 #define PORTB_HOTPLUG_STATUS_MASK (3 << 0) 4626 #define PORTB_HOTPLUG_NO_DETECT (0 << 0) 4627 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) 4628 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0) 4629 #define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \ 4630 BXT_DDIB_HPD_INVERT | \ 4631 BXT_DDIC_HPD_INVERT) 4632 4633 #define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */ 4634 #define PORTE_HOTPLUG_ENABLE (1 << 4) 4635 #define PORTE_HOTPLUG_STATUS_MASK (3 << 0) 4636 #define PORTE_HOTPLUG_NO_DETECT (0 << 0) 4637 #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0) 4638 #define PORTE_HOTPLUG_LONG_DETECT (2 << 0) 4639 4640 /* This register is a reuse of PCH_PORT_HOTPLUG register. The 4641 * functionality covered in PCH_PORT_HOTPLUG is split into 4642 * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC. 4643 */ 4644 4645 #define SHOTPLUG_CTL_DDI _MMIO(0xc4030) 4646 #define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (_HPD_PIN_DDI(hpd_pin) * 4)) 4647 #define SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(hpd_pin) (0x4 << (_HPD_PIN_DDI(hpd_pin) * 4)) 4648 #define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4)) 4649 #define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin) (0x0 << (_HPD_PIN_DDI(hpd_pin) * 4)) 4650 #define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin) (0x1 << (_HPD_PIN_DDI(hpd_pin) * 4)) 4651 #define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin) (0x2 << (_HPD_PIN_DDI(hpd_pin) * 4)) 4652 #define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4)) 4653 4654 #define SHOTPLUG_CTL_TC _MMIO(0xc4034) 4655 #define ICP_TC_HPD_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4)) 4656 #define ICP_TC_HPD_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4)) 4657 #define ICP_TC_HPD_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4)) 4658 4659 #define SHPD_FILTER_CNT _MMIO(0xc4038) 4660 #define SHPD_FILTER_CNT_500_ADJ 0x001D9 4661 #define SHPD_FILTER_CNT_250 0x000F8 4662 4663 #define _PCH_DPLL_A 0xc6014 4664 #define _PCH_DPLL_B 0xc6018 4665 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) 4666 4667 #define _PCH_FPA0 0xc6040 4668 #define FP_CB_TUNE (0x3 << 22) 4669 #define _PCH_FPA1 0xc6044 4670 #define _PCH_FPB0 0xc6048 4671 #define _PCH_FPB1 0xc604c 4672 #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0) 4673 #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1) 4674 4675 #define PCH_DPLL_TEST _MMIO(0xc606c) 4676 4677 #define PCH_DREF_CONTROL _MMIO(0xC6200) 4678 #define DREF_CONTROL_MASK 0x7fc3 4679 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13) 4680 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13) 4681 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13) 4682 #define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13) 4683 #define DREF_SSC_SOURCE_DISABLE (0 << 11) 4684 #define DREF_SSC_SOURCE_ENABLE (2 << 11) 4685 #define DREF_SSC_SOURCE_MASK (3 << 11) 4686 #define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9) 4687 #define DREF_NONSPREAD_CK505_ENABLE (1 << 9) 4688 #define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9) 4689 #define DREF_NONSPREAD_SOURCE_MASK (3 << 9) 4690 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7) 4691 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7) 4692 #define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7) 4693 #define DREF_SSC4_DOWNSPREAD (0 << 6) 4694 #define DREF_SSC4_CENTERSPREAD (1 << 6) 4695 #define DREF_SSC1_DISABLE (0 << 1) 4696 #define DREF_SSC1_ENABLE (1 << 1) 4697 #define DREF_SSC4_DISABLE (0) 4698 #define DREF_SSC4_ENABLE (1) 4699 4700 #define PCH_RAWCLK_FREQ _MMIO(0xc6204) 4701 #define FDL_TP1_TIMER_SHIFT 12 4702 #define FDL_TP1_TIMER_MASK (3 << 12) 4703 #define FDL_TP2_TIMER_SHIFT 10 4704 #define FDL_TP2_TIMER_MASK (3 << 10) 4705 #define RAWCLK_FREQ_MASK 0x3ff 4706 #define CNP_RAWCLK_DIV_MASK (0x3ff << 16) 4707 #define CNP_RAWCLK_DIV(div) ((div) << 16) 4708 #define CNP_RAWCLK_FRAC_MASK (0xf << 26) 4709 #define CNP_RAWCLK_DEN(den) ((den) << 26) 4710 #define ICP_RAWCLK_NUM(num) ((num) << 11) 4711 4712 #define PCH_DPLL_TMR_CFG _MMIO(0xc6208) 4713 4714 #define PCH_SSC4_PARMS _MMIO(0xc6210) 4715 #define PCH_SSC4_AUX_PARMS _MMIO(0xc6214) 4716 4717 #define PCH_DPLL_SEL _MMIO(0xc7000) 4718 #define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4)) 4719 #define TRANS_DPLLA_SEL(pipe) 0 4720 #define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3)) 4721 4722 /* transcoder */ 4723 4724 #define _PCH_TRANS_HTOTAL_A 0xe0000 4725 #define TRANS_HTOTAL_SHIFT 16 4726 #define TRANS_HACTIVE_SHIFT 0 4727 #define _PCH_TRANS_HBLANK_A 0xe0004 4728 #define TRANS_HBLANK_END_SHIFT 16 4729 #define TRANS_HBLANK_START_SHIFT 0 4730 #define _PCH_TRANS_HSYNC_A 0xe0008 4731 #define TRANS_HSYNC_END_SHIFT 16 4732 #define TRANS_HSYNC_START_SHIFT 0 4733 #define _PCH_TRANS_VTOTAL_A 0xe000c 4734 #define TRANS_VTOTAL_SHIFT 16 4735 #define TRANS_VACTIVE_SHIFT 0 4736 #define _PCH_TRANS_VBLANK_A 0xe0010 4737 #define TRANS_VBLANK_END_SHIFT 16 4738 #define TRANS_VBLANK_START_SHIFT 0 4739 #define _PCH_TRANS_VSYNC_A 0xe0014 4740 #define TRANS_VSYNC_END_SHIFT 16 4741 #define TRANS_VSYNC_START_SHIFT 0 4742 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028 4743 4744 #define _PCH_TRANSA_DATA_M1 0xe0030 4745 #define _PCH_TRANSA_DATA_N1 0xe0034 4746 #define _PCH_TRANSA_DATA_M2 0xe0038 4747 #define _PCH_TRANSA_DATA_N2 0xe003c 4748 #define _PCH_TRANSA_LINK_M1 0xe0040 4749 #define _PCH_TRANSA_LINK_N1 0xe0044 4750 #define _PCH_TRANSA_LINK_M2 0xe0048 4751 #define _PCH_TRANSA_LINK_N2 0xe004c 4752 4753 /* Per-transcoder DIP controls (PCH) */ 4754 #define _VIDEO_DIP_CTL_A 0xe0200 4755 #define _VIDEO_DIP_DATA_A 0xe0208 4756 #define _VIDEO_DIP_GCP_A 0xe0210 4757 #define GCP_COLOR_INDICATION (1 << 2) 4758 #define GCP_DEFAULT_PHASE_ENABLE (1 << 1) 4759 #define GCP_AV_MUTE (1 << 0) 4760 4761 #define _VIDEO_DIP_CTL_B 0xe1200 4762 #define _VIDEO_DIP_DATA_B 0xe1208 4763 #define _VIDEO_DIP_GCP_B 0xe1210 4764 4765 #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) 4766 #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) 4767 #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) 4768 4769 /* Per-transcoder DIP controls (VLV) */ 4770 #define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200) 4771 #define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208) 4772 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210) 4773 4774 #define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170) 4775 #define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174) 4776 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178) 4777 4778 #define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0) 4779 #define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4) 4780 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8) 4781 4782 #define VLV_TVIDEO_DIP_CTL(pipe) \ 4783 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \ 4784 _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C) 4785 #define VLV_TVIDEO_DIP_DATA(pipe) \ 4786 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \ 4787 _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C) 4788 #define VLV_TVIDEO_DIP_GCP(pipe) \ 4789 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \ 4790 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C) 4791 4792 /* Haswell DIP controls */ 4793 4794 #define _HSW_VIDEO_DIP_CTL_A 0x60200 4795 #define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220 4796 #define _HSW_VIDEO_DIP_VS_DATA_A 0x60260 4797 #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 4798 #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 4799 #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320 4800 #define _ADL_VIDEO_DIP_AS_DATA_A 0x60484 4801 #define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440 4802 #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240 4803 #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280 4804 #define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 4805 #define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300 4806 #define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344 4807 #define _HSW_VIDEO_DIP_GCP_A 0x60210 4808 4809 #define _HSW_VIDEO_DIP_CTL_B 0x61200 4810 #define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220 4811 #define _HSW_VIDEO_DIP_VS_DATA_B 0x61260 4812 #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 4813 #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 4814 #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320 4815 #define _ADL_VIDEO_DIP_AS_DATA_B 0x61484 4816 #define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440 4817 #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240 4818 #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280 4819 #define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 4820 #define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300 4821 #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344 4822 #define _HSW_VIDEO_DIP_GCP_B 0x61210 4823 4824 /* Icelake PPS_DATA and _ECC DIP Registers. 4825 * These are available for transcoders B,C and eDP. 4826 * Adding the _A so as to reuse the _MMIO_TRANS2 4827 * definition, with which it offsets to the right location. 4828 */ 4829 4830 #define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350 4831 #define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350 4832 #define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4 4833 #define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4 4834 4835 #define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A) 4836 #define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A) 4837 #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4) 4838 #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4) 4839 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) 4840 #define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4) 4841 #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) 4842 #define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4) 4843 #define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4) 4844 #define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4) 4845 /*ADLP and later: */ 4846 #define ADL_TVIDEO_DIP_AS_SDP_DATA(trans, i) _MMIO_TRANS2(trans,\ 4847 _ADL_VIDEO_DIP_AS_DATA_A + (i) * 4) 4848 4849 #define _HSW_STEREO_3D_CTL_A 0x70020 4850 #define S3D_ENABLE (1 << 31) 4851 #define _HSW_STEREO_3D_CTL_B 0x71020 4852 4853 #define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A) 4854 4855 #define _PCH_TRANS_HTOTAL_B 0xe1000 4856 #define _PCH_TRANS_HBLANK_B 0xe1004 4857 #define _PCH_TRANS_HSYNC_B 0xe1008 4858 #define _PCH_TRANS_VTOTAL_B 0xe100c 4859 #define _PCH_TRANS_VBLANK_B 0xe1010 4860 #define _PCH_TRANS_VSYNC_B 0xe1014 4861 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 4862 4863 #define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B) 4864 #define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B) 4865 #define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B) 4866 #define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B) 4867 #define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B) 4868 #define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B) 4869 #define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B) 4870 4871 #define _PCH_TRANSB_DATA_M1 0xe1030 4872 #define _PCH_TRANSB_DATA_N1 0xe1034 4873 #define _PCH_TRANSB_DATA_M2 0xe1038 4874 #define _PCH_TRANSB_DATA_N2 0xe103c 4875 #define _PCH_TRANSB_LINK_M1 0xe1040 4876 #define _PCH_TRANSB_LINK_N1 0xe1044 4877 #define _PCH_TRANSB_LINK_M2 0xe1048 4878 #define _PCH_TRANSB_LINK_N2 0xe104c 4879 4880 #define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1) 4881 #define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1) 4882 #define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2) 4883 #define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2) 4884 #define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1) 4885 #define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1) 4886 #define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2) 4887 #define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2) 4888 4889 #define _PCH_TRANSACONF 0xf0008 4890 #define _PCH_TRANSBCONF 0xf1008 4891 #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF) 4892 #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */ 4893 #define TRANS_ENABLE REG_BIT(31) 4894 #define TRANS_STATE_ENABLE REG_BIT(30) 4895 #define TRANS_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* ibx */ 4896 #define TRANS_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */ 4897 #define TRANS_INTERLACE_MASK REG_GENMASK(23, 21) 4898 #define TRANS_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0) 4899 #define TRANS_INTERLACE_LEGACY_VSYNC_IBX REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */ 4900 #define TRANS_INTERLACE_INTERLACED REG_FIELD_PREP(TRANS_INTERLACE_MASK, 3) 4901 #define TRANS_BPC_MASK REG_GENMASK(7, 5) /* ibx */ 4902 #define TRANS_BPC_8 REG_FIELD_PREP(TRANS_BPC_MASK, 0) 4903 #define TRANS_BPC_10 REG_FIELD_PREP(TRANS_BPC_MASK, 1) 4904 #define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2) 4905 #define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, 3) 4906 4907 #define _TRANSA_CHICKEN1 0xf0060 4908 #define _TRANSB_CHICKEN1 0xf1060 4909 #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) 4910 #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE REG_BIT(10) 4911 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE REG_BIT(4) 4912 4913 #define _TRANSA_CHICKEN2 0xf0064 4914 #define _TRANSB_CHICKEN2 0xf1064 4915 #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) 4916 #define TRANS_CHICKEN2_TIMING_OVERRIDE REG_BIT(31) 4917 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED REG_BIT(29) 4918 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) 4919 #define TRANS_CHICKEN2_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */ 4920 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER REG_BIT(26) 4921 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH REG_BIT(25) 4922 4923 #define SOUTH_CHICKEN1 _MMIO(0xc2000) 4924 #define FDIA_PHASE_SYNC_SHIFT_OVR 19 4925 #define FDIA_PHASE_SYNC_SHIFT_EN 18 4926 #define INVERT_DDIE_HPD REG_BIT(28) 4927 #define INVERT_DDID_HPD_MTP REG_BIT(27) 4928 #define INVERT_TC4_HPD REG_BIT(26) 4929 #define INVERT_TC3_HPD REG_BIT(25) 4930 #define INVERT_TC2_HPD REG_BIT(24) 4931 #define INVERT_TC1_HPD REG_BIT(23) 4932 #define INVERT_DDID_HPD (1 << 18) 4933 #define INVERT_DDIC_HPD (1 << 17) 4934 #define INVERT_DDIB_HPD (1 << 16) 4935 #define INVERT_DDIA_HPD (1 << 15) 4936 #define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) 4937 #define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) 4938 #define FDI_BC_BIFURCATION_SELECT (1 << 12) 4939 #define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8) 4940 #define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8) 4941 #define SBCLK_RUN_REFCLK_DIS (1 << 7) 4942 #define ICP_SECOND_PPS_IO_SELECT REG_BIT(2) 4943 #define SPT_PWM_GRANULARITY (1 << 0) 4944 #define SOUTH_CHICKEN2 _MMIO(0xc2004) 4945 #define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13) 4946 #define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12) 4947 #define LPT_PWM_GRANULARITY (1 << 5) 4948 #define DPLS_EDP_PPS_FIX_DIS (1 << 0) 4949 4950 #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020) 4951 #define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31) 4952 #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30) 4953 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29) 4954 #define PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15) 4955 #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14) 4956 #define CNP_PWM_CGE_GATING_DISABLE (1 << 13) 4957 #define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12) 4958 4959 #define _PCH_DP_B 0xe4100 4960 #define PCH_DP_B _MMIO(_PCH_DP_B) 4961 #define _PCH_DPB_AUX_CH_CTL 0xe4110 4962 #define _PCH_DPB_AUX_CH_DATA1 0xe4114 4963 #define _PCH_DPB_AUX_CH_DATA2 0xe4118 4964 #define _PCH_DPB_AUX_CH_DATA3 0xe411c 4965 #define _PCH_DPB_AUX_CH_DATA4 0xe4120 4966 #define _PCH_DPB_AUX_CH_DATA5 0xe4124 4967 4968 #define _PCH_DP_C 0xe4200 4969 #define PCH_DP_C _MMIO(_PCH_DP_C) 4970 #define _PCH_DPC_AUX_CH_CTL 0xe4210 4971 #define _PCH_DPC_AUX_CH_DATA1 0xe4214 4972 #define _PCH_DPC_AUX_CH_DATA2 0xe4218 4973 #define _PCH_DPC_AUX_CH_DATA3 0xe421c 4974 #define _PCH_DPC_AUX_CH_DATA4 0xe4220 4975 #define _PCH_DPC_AUX_CH_DATA5 0xe4224 4976 4977 #define _PCH_DP_D 0xe4300 4978 #define PCH_DP_D _MMIO(_PCH_DP_D) 4979 #define _PCH_DPD_AUX_CH_CTL 0xe4310 4980 #define _PCH_DPD_AUX_CH_DATA1 0xe4314 4981 #define _PCH_DPD_AUX_CH_DATA2 0xe4318 4982 #define _PCH_DPD_AUX_CH_DATA3 0xe431c 4983 #define _PCH_DPD_AUX_CH_DATA4 0xe4320 4984 #define _PCH_DPD_AUX_CH_DATA5 0xe4324 4985 4986 #define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL) 4987 #define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ 4988 4989 /* CPT */ 4990 #define _TRANS_DP_CTL_A 0xe0300 4991 #define _TRANS_DP_CTL_B 0xe1300 4992 #define _TRANS_DP_CTL_C 0xe2300 4993 #define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B) 4994 #define TRANS_DP_OUTPUT_ENABLE REG_BIT(31) 4995 #define TRANS_DP_PORT_SEL_MASK REG_GENMASK(30, 29) 4996 #define TRANS_DP_PORT_SEL_NONE REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, 3) 4997 #define TRANS_DP_PORT_SEL(port) REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B) 4998 #define TRANS_DP_AUDIO_ONLY REG_BIT(26) 4999 #define TRANS_DP_ENH_FRAMING REG_BIT(18) 5000 #define TRANS_DP_BPC_MASK REG_GENMASK(10, 9) 5001 #define TRANS_DP_BPC_8 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0) 5002 #define TRANS_DP_BPC_10 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 1) 5003 #define TRANS_DP_BPC_6 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 2) 5004 #define TRANS_DP_BPC_12 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 3) 5005 #define TRANS_DP_VSYNC_ACTIVE_HIGH REG_BIT(4) 5006 #define TRANS_DP_HSYNC_ACTIVE_HIGH REG_BIT(3) 5007 5008 #define _TRANS_DP2_CTL_A 0x600a0 5009 #define _TRANS_DP2_CTL_B 0x610a0 5010 #define _TRANS_DP2_CTL_C 0x620a0 5011 #define _TRANS_DP2_CTL_D 0x630a0 5012 #define TRANS_DP2_CTL(trans) _MMIO_TRANS(trans, _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B) 5013 #define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31) 5014 #define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30) 5015 #define TRANS_DP2_DEBUG_ENABLE REG_BIT(23) 5016 5017 #define _TRANS_DP2_VFREQHIGH_A 0x600a4 5018 #define _TRANS_DP2_VFREQHIGH_B 0x610a4 5019 #define _TRANS_DP2_VFREQHIGH_C 0x620a4 5020 #define _TRANS_DP2_VFREQHIGH_D 0x630a4 5021 #define TRANS_DP2_VFREQHIGH(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQHIGH_A, _TRANS_DP2_VFREQHIGH_B) 5022 #define TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK REG_GENMASK(31, 8) 5023 #define TRANS_DP2_VFREQ_PIXEL_CLOCK(clk_hz) REG_FIELD_PREP(TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK, (clk_hz)) 5024 5025 #define _TRANS_DP2_VFREQLOW_A 0x600a8 5026 #define _TRANS_DP2_VFREQLOW_B 0x610a8 5027 #define _TRANS_DP2_VFREQLOW_C 0x620a8 5028 #define _TRANS_DP2_VFREQLOW_D 0x630a8 5029 #define TRANS_DP2_VFREQLOW(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQLOW_A, _TRANS_DP2_VFREQLOW_B) 5030 5031 /* SNB eDP training params */ 5032 /* SNB A-stepping */ 5033 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) 5034 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) 5035 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) 5036 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22) 5037 /* SNB B-stepping */ 5038 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22) 5039 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22) 5040 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22) 5041 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22) 5042 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22) 5043 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22) 5044 5045 /* IVB */ 5046 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22) 5047 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22) 5048 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22) 5049 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22) 5050 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22) 5051 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22) 5052 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22) 5053 5054 /* legacy values */ 5055 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22) 5056 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22) 5057 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22) 5058 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22) 5059 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22) 5060 5061 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22) 5062 5063 #define VLV_PMWGICZ _MMIO(0x1300a4) 5064 5065 #define HSW_EDRAM_CAP _MMIO(0x120010) 5066 #define EDRAM_ENABLED 0x1 5067 #define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf) 5068 #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7) 5069 #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3) 5070 5071 #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C) 5072 #define PIXEL_OVERLAP_CNT_MASK (3 << 30) 5073 #define PIXEL_OVERLAP_CNT_SHIFT 30 5074 5075 #define GEN6_PCODE_MAILBOX _MMIO(0x138124) 5076 #define GEN6_PCODE_READY (1 << 31) 5077 #define GEN6_PCODE_MB_PARAM2 REG_GENMASK(23, 16) 5078 #define GEN6_PCODE_MB_PARAM1 REG_GENMASK(15, 8) 5079 #define GEN6_PCODE_MB_COMMAND REG_GENMASK(7, 0) 5080 #define GEN6_PCODE_ERROR_MASK 0xFF 5081 #define GEN6_PCODE_SUCCESS 0x0 5082 #define GEN6_PCODE_ILLEGAL_CMD 0x1 5083 #define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2 5084 #define GEN6_PCODE_TIMEOUT 0x3 5085 #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF 5086 #define GEN7_PCODE_TIMEOUT 0x2 5087 #define GEN7_PCODE_ILLEGAL_DATA 0x3 5088 #define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4 5089 #define GEN11_PCODE_LOCKED 0x6 5090 #define GEN11_PCODE_REJECTED 0x11 5091 #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10 5092 #define GEN6_PCODE_WRITE_RC6VIDS 0x4 5093 #define GEN6_PCODE_READ_RC6VIDS 0x5 5094 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) 5095 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) 5096 #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18 5097 #define GEN9_PCODE_READ_MEM_LATENCY 0x6 5098 #define GEN9_MEM_LATENCY_LEVEL_3_7_MASK REG_GENMASK(31, 24) 5099 #define GEN9_MEM_LATENCY_LEVEL_2_6_MASK REG_GENMASK(23, 16) 5100 #define GEN9_MEM_LATENCY_LEVEL_1_5_MASK REG_GENMASK(15, 8) 5101 #define GEN9_MEM_LATENCY_LEVEL_0_4_MASK REG_GENMASK(7, 0) 5102 #define SKL_PCODE_LOAD_HDCP_KEYS 0x5 5103 #define SKL_PCODE_CDCLK_CONTROL 0x7 5104 #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3 5105 #define SKL_CDCLK_READY_FOR_CHANGE 0x1 5106 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 5107 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 5108 #define GEN6_READ_OC_PARAMS 0xc 5109 #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd 5110 #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8) 5111 #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8)) 5112 #define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO ((0) | (0x2 << 8)) 5113 #define DISPLAY_TO_PCODE_CDCLK_MAX 0x28D 5114 #define DISPLAY_TO_PCODE_VOLTAGE_MASK REG_GENMASK(1, 0) 5115 #define DISPLAY_TO_PCODE_VOLTAGE_MAX DISPLAY_TO_PCODE_VOLTAGE_MASK 5116 #define DISPLAY_TO_PCODE_CDCLK_VALID REG_BIT(27) 5117 #define DISPLAY_TO_PCODE_PIPE_COUNT_VALID REG_BIT(31) 5118 #define DISPLAY_TO_PCODE_CDCLK_MASK REG_GENMASK(25, 16) 5119 #define DISPLAY_TO_PCODE_PIPE_COUNT_MASK REG_GENMASK(30, 28) 5120 #define DISPLAY_TO_PCODE_CDCLK(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_CDCLK_MASK, (x)) 5121 #define DISPLAY_TO_PCODE_PIPE_COUNT(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_PIPE_COUNT_MASK, (x)) 5122 #define DISPLAY_TO_PCODE_VOLTAGE(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_VOLTAGE_MASK, (x)) 5123 #define DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes, voltage_level) \ 5124 ((DISPLAY_TO_PCODE_CDCLK(cdclk)) | \ 5125 (DISPLAY_TO_PCODE_PIPE_COUNT(num_pipes)) | \ 5126 (DISPLAY_TO_PCODE_VOLTAGE(voltage_level))) 5127 #define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe 5128 #define ICL_PCODE_REP_QGV_MASK REG_GENMASK(1, 0) 5129 #define ICL_PCODE_REP_QGV_SAFE REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0) 5130 #define ICL_PCODE_REP_QGV_POLL REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1) 5131 #define ICL_PCODE_REP_QGV_REJECTED REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2) 5132 #define ADLS_PCODE_REP_PSF_MASK REG_GENMASK(3, 2) 5133 #define ADLS_PCODE_REP_PSF_SAFE REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0) 5134 #define ADLS_PCODE_REP_PSF_POLL REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1) 5135 #define ADLS_PCODE_REP_PSF_REJECTED REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2) 5136 #define ICL_PCODE_REQ_QGV_PT_MASK REG_GENMASK(7, 0) 5137 #define ICL_PCODE_REQ_QGV_PT(x) REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x)) 5138 #define ADLS_PCODE_REQ_PSF_PT_MASK REG_GENMASK(10, 8) 5139 #define ADLS_PCODE_REQ_PSF_PT(x) REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x)) 5140 #define GEN6_PCODE_READ_D_COMP 0x10 5141 #define GEN6_PCODE_WRITE_D_COMP 0x11 5142 #define ICL_PCODE_EXIT_TCCOLD 0x12 5143 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17 5144 #define DISPLAY_IPS_CONTROL 0x19 5145 #define TGL_PCODE_TCCOLD 0x26 5146 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0) 5147 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0 5148 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0) 5149 /* See also IPS_CTL */ 5150 #define IPS_PCODE_CONTROL (1 << 30) 5151 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A 5152 #define GEN9_PCODE_SAGV_CONTROL 0x21 5153 #define GEN9_SAGV_DISABLE 0x0 5154 #define GEN9_SAGV_IS_DISABLED 0x1 5155 #define GEN9_SAGV_ENABLE 0x3 5156 #define DG1_PCODE_STATUS 0x7E 5157 #define DG1_UNCORE_GET_INIT_STATUS 0x0 5158 #define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1 5159 #define PCODE_POWER_SETUP 0x7C 5160 #define POWER_SETUP_SUBCOMMAND_READ_I1 0x4 5161 #define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5 5162 #define POWER_SETUP_I1_WATTS REG_BIT(31) 5163 #define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */ 5164 #define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0) 5165 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23 5166 #define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* pvc */ 5167 /* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */ 5168 #define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0 5169 #define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1 5170 /* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */ 5171 /* XEHP_PCODE_FREQUENCY_CONFIG param2 */ 5172 #define PCODE_MBOX_DOMAIN_NONE 0x0 5173 #define PCODE_MBOX_DOMAIN_MEDIAFF 0x3 5174 #define GEN6_PCODE_DATA _MMIO(0x138128) 5175 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 5176 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 5177 #define GEN6_PCODE_DATA1 _MMIO(0x13812C) 5178 5179 #define MTL_PCODE_STOLEN_ACCESS _MMIO(0x138914) 5180 #define STOLEN_ACCESS_ALLOWED 0x1 5181 5182 /* IVYBRIDGE DPF */ 5183 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */ 5184 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14) 5185 #define GEN7_PARITY_ERROR_VALID (1 << 13) 5186 #define GEN7_L3CDERRST1_BANK_MASK (3 << 11) 5187 #define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8) 5188 #define GEN7_PARITY_ERROR_ROW(reg) \ 5189 (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14) 5190 #define GEN7_PARITY_ERROR_BANK(reg) \ 5191 (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11) 5192 #define GEN7_PARITY_ERROR_SUBBANK(reg) \ 5193 (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) 5194 #define GEN7_L3CDERRST1_ENABLE (1 << 7) 5195 5196 /* These are the 4 32-bit write offset registers for each stream 5197 * output buffer. It determines the offset from the 5198 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. 5199 */ 5200 #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4) 5201 5202 /* 5203 * HSW - ICL power wells 5204 * 5205 * Platforms have up to 3 power well control register sets, each set 5206 * controlling up to 16 power wells via a request/status HW flag tuple: 5207 * - main (HSW_PWR_WELL_CTL[1-4]) 5208 * - AUX (ICL_PWR_WELL_CTL_AUX[1-4]) 5209 * - DDI (ICL_PWR_WELL_CTL_DDI[1-4]) 5210 * Each control register set consists of up to 4 registers used by different 5211 * sources that can request a power well to be enabled: 5212 * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1) 5213 * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2) 5214 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set) 5215 * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4) 5216 */ 5217 #define HSW_PWR_WELL_CTL1 _MMIO(0x45400) 5218 #define HSW_PWR_WELL_CTL2 _MMIO(0x45404) 5219 #define HSW_PWR_WELL_CTL3 _MMIO(0x45408) 5220 #define HSW_PWR_WELL_CTL4 _MMIO(0x4540C) 5221 #define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2)) 5222 #define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2)) 5223 5224 /* HSW/BDW power well */ 5225 #define HSW_PW_CTL_IDX_GLOBAL 15 5226 5227 /* SKL/BXT/GLK power wells */ 5228 #define SKL_PW_CTL_IDX_PW_2 15 5229 #define SKL_PW_CTL_IDX_PW_1 14 5230 #define GLK_PW_CTL_IDX_AUX_C 10 5231 #define GLK_PW_CTL_IDX_AUX_B 9 5232 #define GLK_PW_CTL_IDX_AUX_A 8 5233 #define SKL_PW_CTL_IDX_DDI_D 4 5234 #define SKL_PW_CTL_IDX_DDI_C 3 5235 #define SKL_PW_CTL_IDX_DDI_B 2 5236 #define SKL_PW_CTL_IDX_DDI_A_E 1 5237 #define GLK_PW_CTL_IDX_DDI_A 1 5238 #define SKL_PW_CTL_IDX_MISC_IO 0 5239 5240 /* ICL/TGL - power wells */ 5241 #define TGL_PW_CTL_IDX_PW_5 4 5242 #define ICL_PW_CTL_IDX_PW_4 3 5243 #define ICL_PW_CTL_IDX_PW_3 2 5244 #define ICL_PW_CTL_IDX_PW_2 1 5245 #define ICL_PW_CTL_IDX_PW_1 0 5246 5247 /* XE_LPD - power wells */ 5248 #define XELPD_PW_CTL_IDX_PW_D 8 5249 #define XELPD_PW_CTL_IDX_PW_C 7 5250 #define XELPD_PW_CTL_IDX_PW_B 6 5251 #define XELPD_PW_CTL_IDX_PW_A 5 5252 5253 #define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440) 5254 #define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444) 5255 #define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C) 5256 #define TGL_PW_CTL_IDX_AUX_TBT6 14 5257 #define TGL_PW_CTL_IDX_AUX_TBT5 13 5258 #define TGL_PW_CTL_IDX_AUX_TBT4 12 5259 #define ICL_PW_CTL_IDX_AUX_TBT4 11 5260 #define TGL_PW_CTL_IDX_AUX_TBT3 11 5261 #define ICL_PW_CTL_IDX_AUX_TBT3 10 5262 #define TGL_PW_CTL_IDX_AUX_TBT2 10 5263 #define ICL_PW_CTL_IDX_AUX_TBT2 9 5264 #define TGL_PW_CTL_IDX_AUX_TBT1 9 5265 #define ICL_PW_CTL_IDX_AUX_TBT1 8 5266 #define TGL_PW_CTL_IDX_AUX_TC6 8 5267 #define XELPD_PW_CTL_IDX_AUX_E 8 5268 #define TGL_PW_CTL_IDX_AUX_TC5 7 5269 #define XELPD_PW_CTL_IDX_AUX_D 7 5270 #define TGL_PW_CTL_IDX_AUX_TC4 6 5271 #define ICL_PW_CTL_IDX_AUX_F 5 5272 #define TGL_PW_CTL_IDX_AUX_TC3 5 5273 #define ICL_PW_CTL_IDX_AUX_E 4 5274 #define TGL_PW_CTL_IDX_AUX_TC2 4 5275 #define ICL_PW_CTL_IDX_AUX_D 3 5276 #define TGL_PW_CTL_IDX_AUX_TC1 3 5277 #define ICL_PW_CTL_IDX_AUX_C 2 5278 #define ICL_PW_CTL_IDX_AUX_B 1 5279 #define ICL_PW_CTL_IDX_AUX_A 0 5280 5281 #define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450) 5282 #define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454) 5283 #define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C) 5284 #define XELPD_PW_CTL_IDX_DDI_E 8 5285 #define TGL_PW_CTL_IDX_DDI_TC6 8 5286 #define XELPD_PW_CTL_IDX_DDI_D 7 5287 #define TGL_PW_CTL_IDX_DDI_TC5 7 5288 #define TGL_PW_CTL_IDX_DDI_TC4 6 5289 #define ICL_PW_CTL_IDX_DDI_F 5 5290 #define TGL_PW_CTL_IDX_DDI_TC3 5 5291 #define ICL_PW_CTL_IDX_DDI_E 4 5292 #define TGL_PW_CTL_IDX_DDI_TC2 4 5293 #define ICL_PW_CTL_IDX_DDI_D 3 5294 #define TGL_PW_CTL_IDX_DDI_TC1 3 5295 #define ICL_PW_CTL_IDX_DDI_C 2 5296 #define ICL_PW_CTL_IDX_DDI_B 1 5297 #define ICL_PW_CTL_IDX_DDI_A 0 5298 5299 /* HSW - power well misc debug registers */ 5300 #define HSW_PWR_WELL_CTL5 _MMIO(0x45410) 5301 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31) 5302 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20) 5303 #define HSW_PWR_WELL_FORCE_ON (1 << 19) 5304 #define HSW_PWR_WELL_CTL6 _MMIO(0x45414) 5305 5306 /* SKL Fuse Status */ 5307 enum skl_power_gate { 5308 SKL_PG0, 5309 SKL_PG1, 5310 SKL_PG2, 5311 ICL_PG3, 5312 ICL_PG4, 5313 }; 5314 5315 #define SKL_FUSE_STATUS _MMIO(0x42000) 5316 #define SKL_FUSE_DOWNLOAD_STATUS (1 << 31) 5317 /* 5318 * PG0 is HW controlled, so doesn't have a corresponding power well control knob 5319 * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2 5320 */ 5321 #define SKL_PW_CTL_IDX_TO_PG(pw_idx) \ 5322 ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1) 5323 /* 5324 * PG0 is HW controlled, so doesn't have a corresponding power well control knob 5325 * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4 5326 */ 5327 #define ICL_PW_CTL_IDX_TO_PG(pw_idx) \ 5328 ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1) 5329 #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg))) 5330 5331 /* Per-pipe DDI Function Control */ 5332 #define _TRANS_DDI_FUNC_CTL_A 0x60400 5333 #define _TRANS_DDI_FUNC_CTL_B 0x61400 5334 #define _TRANS_DDI_FUNC_CTL_C 0x62400 5335 #define _TRANS_DDI_FUNC_CTL_D 0x63400 5336 #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400 5337 #define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400 5338 #define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00 5339 #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A) 5340 5341 #define TRANS_DDI_FUNC_ENABLE (1 << 31) 5342 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ 5343 #define TRANS_DDI_PORT_SHIFT 28 5344 #define TGL_TRANS_DDI_PORT_SHIFT 27 5345 #define TRANS_DDI_PORT_MASK (7 << TRANS_DDI_PORT_SHIFT) 5346 #define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT) 5347 #define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT) 5348 #define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT) 5349 #define TRANS_DDI_MODE_SELECT_MASK (7 << 24) 5350 #define TRANS_DDI_MODE_SELECT_HDMI (0 << 24) 5351 #define TRANS_DDI_MODE_SELECT_DVI (1 << 24) 5352 #define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24) 5353 #define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24) 5354 #define TRANS_DDI_MODE_SELECT_FDI_OR_128B132B (4 << 24) 5355 #define TRANS_DDI_BPC_MASK (7 << 20) 5356 #define TRANS_DDI_BPC_8 (0 << 20) 5357 #define TRANS_DDI_BPC_10 (1 << 20) 5358 #define TRANS_DDI_BPC_6 (2 << 20) 5359 #define TRANS_DDI_BPC_12 (3 << 20) 5360 #define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18) 5361 #define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x) REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x)) 5362 #define TRANS_DDI_PVSYNC (1 << 17) 5363 #define TRANS_DDI_PHSYNC (1 << 16) 5364 #define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15) 5365 #define TRANS_DDI_EDP_INPUT_MASK (7 << 12) 5366 #define TRANS_DDI_EDP_INPUT_A_ON (0 << 12) 5367 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12) 5368 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12) 5369 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12) 5370 #define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12) 5371 #define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10) 5372 #define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \ 5373 REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans) 5374 #define TRANS_DDI_HDCP_SIGNALLING (1 << 9) 5375 #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8) 5376 #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7) 5377 #define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6) 5378 #define TRANS_DDI_HDCP_SELECT REG_BIT(5) 5379 #define TRANS_DDI_BFI_ENABLE (1 << 4) 5380 #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4) 5381 #define TRANS_DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1) 5382 #define TRANS_DDI_PORT_WIDTH(width) REG_FIELD_PREP(TRANS_DDI_PORT_WIDTH_MASK, (width) - 1) 5383 #define TRANS_DDI_HDMI_SCRAMBLING (1 << 0) 5384 #define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \ 5385 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \ 5386 | TRANS_DDI_HDMI_SCRAMBLING) 5387 5388 #define _TRANS_DDI_FUNC_CTL2_A 0x60404 5389 #define _TRANS_DDI_FUNC_CTL2_B 0x61404 5390 #define _TRANS_DDI_FUNC_CTL2_C 0x62404 5391 #define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404 5392 #define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404 5393 #define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04 5394 #define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL2_A) 5395 #define PORT_SYNC_MODE_ENABLE REG_BIT(4) 5396 #define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0) 5397 #define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x)) 5398 5399 #define TRANS_CMTG_CHICKEN _MMIO(0x6fa90) 5400 #define DISABLE_DPT_CLK_GATING REG_BIT(1) 5401 5402 /* DisplayPort Transport Control */ 5403 #define _DP_TP_CTL_A 0x64040 5404 #define _DP_TP_CTL_B 0x64140 5405 #define _TGL_DP_TP_CTL_A 0x60540 5406 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) 5407 #define TGL_DP_TP_CTL(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_CTL_A) 5408 #define DP_TP_CTL_ENABLE (1 << 31) 5409 #define DP_TP_CTL_FEC_ENABLE (1 << 30) 5410 #define DP_TP_CTL_MODE_SST (0 << 27) 5411 #define DP_TP_CTL_MODE_MST (1 << 27) 5412 #define DP_TP_CTL_FORCE_ACT (1 << 25) 5413 #define DP_TP_CTL_TRAIN_PAT4_SEL_MASK (3 << 19) 5414 #define DP_TP_CTL_TRAIN_PAT4_SEL_TP4A (0 << 19) 5415 #define DP_TP_CTL_TRAIN_PAT4_SEL_TP4B (1 << 19) 5416 #define DP_TP_CTL_TRAIN_PAT4_SEL_TP4C (2 << 19) 5417 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18) 5418 #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15) 5419 #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8) 5420 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8) 5421 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1 << 8) 5422 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4 << 8) 5423 #define DP_TP_CTL_LINK_TRAIN_PAT4 (5 << 8) 5424 #define DP_TP_CTL_LINK_TRAIN_IDLE (2 << 8) 5425 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3 << 8) 5426 #define DP_TP_CTL_SCRAMBLE_DISABLE (1 << 7) 5427 5428 /* DisplayPort Transport Status */ 5429 #define _DP_TP_STATUS_A 0x64044 5430 #define _DP_TP_STATUS_B 0x64144 5431 #define _TGL_DP_TP_STATUS_A 0x60544 5432 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B) 5433 #define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_STATUS_A) 5434 #define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28) 5435 #define DP_TP_STATUS_IDLE_DONE (1 << 25) 5436 #define DP_TP_STATUS_ACT_SENT (1 << 24) 5437 #define DP_TP_STATUS_MODE_STATUS_MST (1 << 23) 5438 #define DP_TP_STATUS_AUTOTRAIN_DONE (1 << 12) 5439 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8) 5440 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4) 5441 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0) 5442 5443 /* DDI Buffer Control */ 5444 #define _DDI_BUF_CTL_A 0x64000 5445 #define _DDI_BUF_CTL_B 0x64100 5446 /* Known as DDI_CTL_DE in MTL+ */ 5447 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B) 5448 #define DDI_BUF_CTL_ENABLE (1 << 31) 5449 #define XE2LPD_DDI_BUF_D2D_LINK_ENABLE REG_BIT(29) 5450 #define XE2LPD_DDI_BUF_D2D_LINK_STATE REG_BIT(28) 5451 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24) 5452 #define DDI_BUF_EMP_MASK (0xf << 24) 5453 #define DDI_BUF_PHY_LINK_RATE(r) ((r) << 20) 5454 #define DDI_BUF_PORT_DATA_MASK REG_GENMASK(19, 18) 5455 #define DDI_BUF_PORT_DATA_10BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 0) 5456 #define DDI_BUF_PORT_DATA_20BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 1) 5457 #define DDI_BUF_PORT_DATA_40BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 2) 5458 #define DDI_BUF_PORT_REVERSAL (1 << 16) 5459 #define DDI_BUF_IS_IDLE (1 << 7) 5460 #define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6) 5461 #define DDI_A_4_LANES (1 << 4) 5462 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) 5463 #define DDI_PORT_WIDTH_MASK (7 << 1) 5464 #define DDI_PORT_WIDTH_SHIFT 1 5465 #define DDI_INIT_DISPLAY_DETECTED (1 << 0) 5466 5467 /* DDI Buffer Translations */ 5468 #define _DDI_BUF_TRANS_A 0x64E00 5469 #define _DDI_BUF_TRANS_B 0x64E60 5470 #define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8) 5471 #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31) 5472 #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4) 5473 5474 /* DDI DP Compliance Control */ 5475 #define _DDI_DP_COMP_CTL_A 0x605F0 5476 #define _DDI_DP_COMP_CTL_B 0x615F0 5477 #define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B) 5478 #define DDI_DP_COMP_CTL_ENABLE (1 << 31) 5479 #define DDI_DP_COMP_CTL_D10_2 (0 << 28) 5480 #define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28) 5481 #define DDI_DP_COMP_CTL_PRBS7 (2 << 28) 5482 #define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28) 5483 #define DDI_DP_COMP_CTL_HBR2 (4 << 28) 5484 #define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28) 5485 #define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0) 5486 5487 /* DDI DP Compliance Pattern */ 5488 #define _DDI_DP_COMP_PAT_A 0x605F4 5489 #define _DDI_DP_COMP_PAT_B 0x615F4 5490 #define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4) 5491 5492 /* Sideband Interface (SBI) is programmed indirectly, via 5493 * SBI_ADDR, which contains the register offset; and SBI_DATA, 5494 * which contains the payload */ 5495 #define SBI_ADDR _MMIO(0xC6000) 5496 #define SBI_DATA _MMIO(0xC6004) 5497 #define SBI_CTL_STAT _MMIO(0xC6008) 5498 #define SBI_CTL_DEST_ICLK (0x0 << 16) 5499 #define SBI_CTL_DEST_MPHY (0x1 << 16) 5500 #define SBI_CTL_OP_IORD (0x2 << 8) 5501 #define SBI_CTL_OP_IOWR (0x3 << 8) 5502 #define SBI_CTL_OP_CRRD (0x6 << 8) 5503 #define SBI_CTL_OP_CRWR (0x7 << 8) 5504 #define SBI_RESPONSE_FAIL (0x1 << 1) 5505 #define SBI_RESPONSE_SUCCESS (0x0 << 1) 5506 #define SBI_BUSY (0x1 << 0) 5507 #define SBI_READY (0x0 << 0) 5508 5509 /* SBI offsets */ 5510 #define SBI_SSCDIVINTPHASE 0x0200 5511 #define SBI_SSCDIVINTPHASE6 0x0600 5512 #define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1 5513 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1) 5514 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1) 5515 #define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8 5516 #define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8) 5517 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8) 5518 #define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15) 5519 #define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0) 5520 #define SBI_SSCDITHPHASE 0x0204 5521 #define SBI_SSCCTL 0x020c 5522 #define SBI_SSCCTL6 0x060C 5523 #define SBI_SSCCTL_PATHALT (1 << 3) 5524 #define SBI_SSCCTL_DISABLE (1 << 0) 5525 #define SBI_SSCAUXDIV6 0x0610 5526 #define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4 5527 #define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4) 5528 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4) 5529 #define SBI_DBUFF0 0x2a00 5530 #define SBI_GEN0 0x1f00 5531 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0) 5532 5533 /* LPT PIXCLK_GATE */ 5534 #define PIXCLK_GATE _MMIO(0xC6020) 5535 #define PIXCLK_GATE_UNGATE (1 << 0) 5536 #define PIXCLK_GATE_GATE (0 << 0) 5537 5538 /* SPLL */ 5539 #define SPLL_CTL _MMIO(0x46020) 5540 #define SPLL_PLL_ENABLE (1 << 31) 5541 #define SPLL_REF_BCLK (0 << 28) 5542 #define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */ 5543 #define SPLL_REF_NON_SSC_HSW (2 << 28) 5544 #define SPLL_REF_PCH_SSC_BDW (2 << 28) 5545 #define SPLL_REF_LCPLL (3 << 28) 5546 #define SPLL_REF_MASK (3 << 28) 5547 #define SPLL_FREQ_810MHz (0 << 26) 5548 #define SPLL_FREQ_1350MHz (1 << 26) 5549 #define SPLL_FREQ_2700MHz (2 << 26) 5550 #define SPLL_FREQ_MASK (3 << 26) 5551 5552 /* WRPLL */ 5553 #define _WRPLL_CTL1 0x46040 5554 #define _WRPLL_CTL2 0x46060 5555 #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2) 5556 #define WRPLL_PLL_ENABLE (1 << 31) 5557 #define WRPLL_REF_BCLK (0 << 28) 5558 #define WRPLL_REF_PCH_SSC (1 << 28) 5559 #define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */ 5560 #define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */ 5561 #define WRPLL_REF_LCPLL (3 << 28) 5562 #define WRPLL_REF_MASK (3 << 28) 5563 /* WRPLL divider programming */ 5564 #define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0) 5565 #define WRPLL_DIVIDER_REF_MASK (0xff) 5566 #define WRPLL_DIVIDER_POST(x) ((x) << 8) 5567 #define WRPLL_DIVIDER_POST_MASK (0x3f << 8) 5568 #define WRPLL_DIVIDER_POST_SHIFT 8 5569 #define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16) 5570 #define WRPLL_DIVIDER_FB_SHIFT 16 5571 #define WRPLL_DIVIDER_FB_MASK (0xff << 16) 5572 5573 /* Port clock selection */ 5574 #define _PORT_CLK_SEL_A 0x46100 5575 #define _PORT_CLK_SEL_B 0x46104 5576 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B) 5577 #define PORT_CLK_SEL_MASK REG_GENMASK(31, 29) 5578 #define PORT_CLK_SEL_LCPLL_2700 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 0) 5579 #define PORT_CLK_SEL_LCPLL_1350 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 1) 5580 #define PORT_CLK_SEL_LCPLL_810 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 2) 5581 #define PORT_CLK_SEL_SPLL REG_FIELD_PREP(PORT_CLK_SEL_MASK, 3) 5582 #define PORT_CLK_SEL_WRPLL(pll) REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4 + (pll)) 5583 #define PORT_CLK_SEL_WRPLL1 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4) 5584 #define PORT_CLK_SEL_WRPLL2 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 5) 5585 #define PORT_CLK_SEL_NONE REG_FIELD_PREP(PORT_CLK_SEL_MASK, 7) 5586 5587 /* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */ 5588 #define DDI_CLK_SEL(port) PORT_CLK_SEL(port) 5589 #define DDI_CLK_SEL_MASK REG_GENMASK(31, 28) 5590 #define DDI_CLK_SEL_NONE REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x0) 5591 #define DDI_CLK_SEL_MG REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x8) 5592 #define DDI_CLK_SEL_TBT_162 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xC) 5593 #define DDI_CLK_SEL_TBT_270 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xD) 5594 #define DDI_CLK_SEL_TBT_540 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xE) 5595 #define DDI_CLK_SEL_TBT_810 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xF) 5596 5597 /* Transcoder clock selection */ 5598 #define _TRANS_CLK_SEL_A 0x46140 5599 #define _TRANS_CLK_SEL_B 0x46144 5600 #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B) 5601 /* For each transcoder, we need to select the corresponding port clock */ 5602 #define TRANS_CLK_SEL_DISABLED (0x0 << 29) 5603 #define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29) 5604 #define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28) 5605 #define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28) 5606 5607 5608 #define CDCLK_FREQ _MMIO(0x46200) 5609 5610 #define _TRANSA_MSA_MISC 0x60410 5611 #define _TRANSB_MSA_MISC 0x61410 5612 #define _TRANSC_MSA_MISC 0x62410 5613 #define _TRANS_EDP_MSA_MISC 0x6f410 5614 #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC) 5615 /* See DP_MSA_MISC_* for the bit definitions */ 5616 5617 #define _TRANS_A_SET_CONTEXT_LATENCY 0x6007C 5618 #define _TRANS_B_SET_CONTEXT_LATENCY 0x6107C 5619 #define _TRANS_C_SET_CONTEXT_LATENCY 0x6207C 5620 #define _TRANS_D_SET_CONTEXT_LATENCY 0x6307C 5621 #define TRANS_SET_CONTEXT_LATENCY(tran) _MMIO_TRANS2(tran, _TRANS_A_SET_CONTEXT_LATENCY) 5622 #define TRANS_SET_CONTEXT_LATENCY_MASK REG_GENMASK(15, 0) 5623 #define TRANS_SET_CONTEXT_LATENCY_VALUE(x) REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x)) 5624 5625 /* LCPLL Control */ 5626 #define LCPLL_CTL _MMIO(0x130040) 5627 #define LCPLL_PLL_DISABLE (1 << 31) 5628 #define LCPLL_PLL_LOCK (1 << 30) 5629 #define LCPLL_REF_NON_SSC (0 << 28) 5630 #define LCPLL_REF_BCLK (2 << 28) 5631 #define LCPLL_REF_PCH_SSC (3 << 28) 5632 #define LCPLL_REF_MASK (3 << 28) 5633 #define LCPLL_CLK_FREQ_MASK (3 << 26) 5634 #define LCPLL_CLK_FREQ_450 (0 << 26) 5635 #define LCPLL_CLK_FREQ_54O_BDW (1 << 26) 5636 #define LCPLL_CLK_FREQ_337_5_BDW (2 << 26) 5637 #define LCPLL_CLK_FREQ_675_BDW (3 << 26) 5638 #define LCPLL_CD_CLOCK_DISABLE (1 << 25) 5639 #define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24) 5640 #define LCPLL_CD2X_CLOCK_DISABLE (1 << 23) 5641 #define LCPLL_POWER_DOWN_ALLOW (1 << 22) 5642 #define LCPLL_CD_SOURCE_FCLK (1 << 21) 5643 #define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19) 5644 5645 /* 5646 * SKL Clocks 5647 */ 5648 5649 /* CDCLK_CTL */ 5650 #define CDCLK_CTL _MMIO(0x46000) 5651 #define CDCLK_FREQ_SEL_MASK REG_GENMASK(27, 26) 5652 #define CDCLK_FREQ_450_432 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 0) 5653 #define CDCLK_FREQ_540 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1) 5654 #define CDCLK_FREQ_337_308 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2) 5655 #define CDCLK_FREQ_675_617 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3) 5656 #define MDCLK_SOURCE_SEL_MASK REG_GENMASK(25, 25) 5657 #define MDCLK_SOURCE_SEL_CD2XCLK REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 0) 5658 #define MDCLK_SOURCE_SEL_CDCLK_PLL REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 1) 5659 #define BXT_CDCLK_CD2X_DIV_SEL_MASK REG_GENMASK(23, 22) 5660 #define BXT_CDCLK_CD2X_DIV_SEL_1 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0) 5661 #define BXT_CDCLK_CD2X_DIV_SEL_1_5 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1) 5662 #define BXT_CDCLK_CD2X_DIV_SEL_2 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 2) 5663 #define BXT_CDCLK_CD2X_DIV_SEL_4 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 3) 5664 #define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20) 5665 #define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19) 5666 #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3) 5667 #define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19) 5668 #define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19) 5669 #define TGL_CDCLK_CD2X_PIPE(pipe) BXT_CDCLK_CD2X_PIPE(pipe) 5670 #define TGL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE_NONE 5671 #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16) 5672 #define CDCLK_FREQ_DECIMAL_MASK (0x7ff) 5673 5674 /* CDCLK_SQUASH_CTL */ 5675 #define CDCLK_SQUASH_CTL _MMIO(0x46008) 5676 #define CDCLK_SQUASH_ENABLE REG_BIT(31) 5677 #define CDCLK_SQUASH_WINDOW_SIZE_MASK REG_GENMASK(27, 24) 5678 #define CDCLK_SQUASH_WINDOW_SIZE(x) REG_FIELD_PREP(CDCLK_SQUASH_WINDOW_SIZE_MASK, (x)) 5679 #define CDCLK_SQUASH_WAVEFORM_MASK REG_GENMASK(15, 0) 5680 #define CDCLK_SQUASH_WAVEFORM(x) REG_FIELD_PREP(CDCLK_SQUASH_WAVEFORM_MASK, (x)) 5681 5682 /* LCPLL_CTL */ 5683 #define LCPLL1_CTL _MMIO(0x46010) 5684 #define LCPLL2_CTL _MMIO(0x46014) 5685 #define LCPLL_PLL_ENABLE (1 << 31) 5686 5687 /* DPLL control1 */ 5688 #define DPLL_CTRL1 _MMIO(0x6C058) 5689 #define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5)) 5690 #define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4)) 5691 #define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1)) 5692 #define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1) 5693 #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1)) 5694 #define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6)) 5695 #define DPLL_CTRL1_LINK_RATE_2700 0 5696 #define DPLL_CTRL1_LINK_RATE_1350 1 5697 #define DPLL_CTRL1_LINK_RATE_810 2 5698 #define DPLL_CTRL1_LINK_RATE_1620 3 5699 #define DPLL_CTRL1_LINK_RATE_1080 4 5700 #define DPLL_CTRL1_LINK_RATE_2160 5 5701 5702 /* DPLL control2 */ 5703 #define DPLL_CTRL2 _MMIO(0x6C05C) 5704 #define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15)) 5705 #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1)) 5706 #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1) 5707 #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1)) 5708 #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3)) 5709 5710 /* DPLL Status */ 5711 #define DPLL_STATUS _MMIO(0x6C060) 5712 #define DPLL_LOCK(id) (1 << ((id) * 8)) 5713 5714 /* DPLL cfg */ 5715 #define _DPLL1_CFGCR1 0x6C040 5716 #define _DPLL2_CFGCR1 0x6C048 5717 #define _DPLL3_CFGCR1 0x6C050 5718 #define DPLL_CFGCR1_FREQ_ENABLE (1 << 31) 5719 #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9) 5720 #define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9) 5721 #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff) 5722 5723 #define _DPLL1_CFGCR2 0x6C044 5724 #define _DPLL2_CFGCR2 0x6C04C 5725 #define _DPLL3_CFGCR2 0x6C054 5726 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8) 5727 #define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8) 5728 #define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7) 5729 #define DPLL_CFGCR2_KDIV_MASK (3 << 5) 5730 #define DPLL_CFGCR2_KDIV(x) ((x) << 5) 5731 #define DPLL_CFGCR2_KDIV_5 (0 << 5) 5732 #define DPLL_CFGCR2_KDIV_2 (1 << 5) 5733 #define DPLL_CFGCR2_KDIV_3 (2 << 5) 5734 #define DPLL_CFGCR2_KDIV_1 (3 << 5) 5735 #define DPLL_CFGCR2_PDIV_MASK (7 << 2) 5736 #define DPLL_CFGCR2_PDIV(x) ((x) << 2) 5737 #define DPLL_CFGCR2_PDIV_1 (0 << 2) 5738 #define DPLL_CFGCR2_PDIV_2 (1 << 2) 5739 #define DPLL_CFGCR2_PDIV_3 (2 << 2) 5740 #define DPLL_CFGCR2_PDIV_7 (4 << 2) 5741 #define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2) 5742 #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3) 5743 5744 #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1) 5745 #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2) 5746 5747 /* ICL Clocks */ 5748 #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280) 5749 #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24, 4, 5)) 5750 #define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10) 5751 #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \ 5752 (tc_port) + 12 : \ 5753 (tc_port) - TC_PORT_4 + 21)) 5754 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2) 5755 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 5756 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 5757 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27) 5758 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \ 5759 (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 5760 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \ 5761 ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 5762 5763 /* 5764 * DG1 Clocks 5765 * First registers controls the first A and B, while the second register 5766 * controls the phy C and D. The bits on these registers are the 5767 * same, but refer to different phys 5768 */ 5769 #define _DG1_DPCLKA_CFGCR0 0x164280 5770 #define _DG1_DPCLKA1_CFGCR0 0x16C280 5771 #define _DG1_DPCLKA_PHY_IDX(phy) ((phy) % 2) 5772 #define _DG1_DPCLKA_PLL_IDX(pll) ((pll) % 2) 5773 #define DG1_DPCLKA_CFGCR0(phy) _MMIO_PHY((phy) / 2, \ 5774 _DG1_DPCLKA_CFGCR0, \ 5775 _DG1_DPCLKA1_CFGCR0) 5776 #define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT(_DG1_DPCLKA_PHY_IDX(phy) + 10) 5777 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) (_DG1_DPCLKA_PHY_IDX(phy) * 2) 5778 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (_DG1_DPCLKA_PLL_IDX(pll) << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 5779 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 5780 5781 /* ADLS Clocks */ 5782 #define _ADLS_DPCLKA_CFGCR0 0x164280 5783 #define _ADLS_DPCLKA_CFGCR1 0x1642BC 5784 #define ADLS_DPCLKA_CFGCR(phy) _MMIO_PHY((phy) / 3, \ 5785 _ADLS_DPCLKA_CFGCR0, \ 5786 _ADLS_DPCLKA_CFGCR1) 5787 #define ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy) (((phy) % 3) * 2) 5788 /* ADLS DPCLKA_CFGCR0 DDI mask */ 5789 #define ADLS_DPCLKA_DDII_SEL_MASK REG_GENMASK(5, 4) 5790 #define ADLS_DPCLKA_DDIB_SEL_MASK REG_GENMASK(3, 2) 5791 #define ADLS_DPCLKA_DDIA_SEL_MASK REG_GENMASK(1, 0) 5792 /* ADLS DPCLKA_CFGCR1 DDI mask */ 5793 #define ADLS_DPCLKA_DDIK_SEL_MASK REG_GENMASK(3, 2) 5794 #define ADLS_DPCLKA_DDIJ_SEL_MASK REG_GENMASK(1, 0) 5795 #define ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy) _PICK((phy), \ 5796 ADLS_DPCLKA_DDIA_SEL_MASK, \ 5797 ADLS_DPCLKA_DDIB_SEL_MASK, \ 5798 ADLS_DPCLKA_DDII_SEL_MASK, \ 5799 ADLS_DPCLKA_DDIJ_SEL_MASK, \ 5800 ADLS_DPCLKA_DDIK_SEL_MASK) 5801 5802 /* ICL PLL */ 5803 #define _DPLL0_ENABLE 0x46010 5804 #define _DPLL1_ENABLE 0x46014 5805 #define _ADLS_DPLL2_ENABLE 0x46018 5806 #define _ADLS_DPLL3_ENABLE 0x46030 5807 #define PLL_ENABLE REG_BIT(31) 5808 #define PLL_LOCK REG_BIT(30) 5809 #define PLL_POWER_ENABLE REG_BIT(27) 5810 #define PLL_POWER_STATE REG_BIT(26) 5811 #define ICL_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \ 5812 _DPLL0_ENABLE, _DPLL1_ENABLE, \ 5813 _ADLS_DPLL3_ENABLE, _ADLS_DPLL3_ENABLE)) 5814 5815 #define _DG2_PLL3_ENABLE 0x4601C 5816 5817 #define DG2_PLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \ 5818 _DPLL0_ENABLE, _DPLL1_ENABLE, \ 5819 _DG2_PLL3_ENABLE, _DG2_PLL3_ENABLE)) 5820 5821 #define TBT_PLL_ENABLE _MMIO(0x46020) 5822 5823 #define _MG_PLL1_ENABLE 0x46030 5824 #define _MG_PLL2_ENABLE 0x46034 5825 #define _MG_PLL3_ENABLE 0x46038 5826 #define _MG_PLL4_ENABLE 0x4603C 5827 /* Bits are the same as _DPLL0_ENABLE */ 5828 #define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \ 5829 _MG_PLL2_ENABLE) 5830 5831 /* DG1 PLL */ 5832 #define DG1_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ 5833 _DPLL0_ENABLE, _DPLL1_ENABLE, \ 5834 _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)) 5835 5836 /* ADL-P Type C PLL */ 5837 #define PORTTC1_PLL_ENABLE 0x46038 5838 #define PORTTC2_PLL_ENABLE 0x46040 5839 5840 #define ADLP_PORTTC_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), \ 5841 PORTTC1_PLL_ENABLE, \ 5842 PORTTC2_PLL_ENABLE) 5843 5844 #define _ICL_DPLL0_CFGCR0 0x164000 5845 #define _ICL_DPLL1_CFGCR0 0x164080 5846 #define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \ 5847 _ICL_DPLL1_CFGCR0) 5848 #define DPLL_CFGCR0_HDMI_MODE (1 << 30) 5849 #define DPLL_CFGCR0_SSC_ENABLE (1 << 29) 5850 #define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25) 5851 #define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25) 5852 #define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25) 5853 #define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25) 5854 #define DPLL_CFGCR0_LINK_RATE_810 (2 << 25) 5855 #define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25) 5856 #define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25) 5857 #define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25) 5858 #define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25) 5859 #define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25) 5860 #define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10) 5861 #define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10) 5862 #define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10) 5863 #define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff) 5864 5865 #define _ICL_DPLL0_CFGCR1 0x164004 5866 #define _ICL_DPLL1_CFGCR1 0x164084 5867 #define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \ 5868 _ICL_DPLL1_CFGCR1) 5869 #define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10) 5870 #define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10) 5871 #define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10) 5872 #define DPLL_CFGCR1_QDIV_MODE_SHIFT (9) 5873 #define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9) 5874 #define DPLL_CFGCR1_KDIV_MASK (7 << 6) 5875 #define DPLL_CFGCR1_KDIV_SHIFT (6) 5876 #define DPLL_CFGCR1_KDIV(x) ((x) << 6) 5877 #define DPLL_CFGCR1_KDIV_1 (1 << 6) 5878 #define DPLL_CFGCR1_KDIV_2 (2 << 6) 5879 #define DPLL_CFGCR1_KDIV_3 (4 << 6) 5880 #define DPLL_CFGCR1_PDIV_MASK (0xf << 2) 5881 #define DPLL_CFGCR1_PDIV_SHIFT (2) 5882 #define DPLL_CFGCR1_PDIV(x) ((x) << 2) 5883 #define DPLL_CFGCR1_PDIV_2 (1 << 2) 5884 #define DPLL_CFGCR1_PDIV_3 (2 << 2) 5885 #define DPLL_CFGCR1_PDIV_5 (4 << 2) 5886 #define DPLL_CFGCR1_PDIV_7 (8 << 2) 5887 #define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0) 5888 #define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0) 5889 #define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0) 5890 5891 #define _TGL_DPLL0_CFGCR0 0x164284 5892 #define _TGL_DPLL1_CFGCR0 0x16428C 5893 #define _TGL_TBTPLL_CFGCR0 0x16429C 5894 #define TGL_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ 5895 _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \ 5896 _TGL_TBTPLL_CFGCR0, _TGL_TBTPLL_CFGCR0)) 5897 #define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \ 5898 _TGL_DPLL1_CFGCR0) 5899 5900 #define _TGL_DPLL0_DIV0 0x164B00 5901 #define _TGL_DPLL1_DIV0 0x164C00 5902 #define TGL_DPLL0_DIV0(pll) _MMIO_PLL(pll, _TGL_DPLL0_DIV0, _TGL_DPLL1_DIV0) 5903 #define TGL_DPLL0_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25) 5904 #define TGL_DPLL0_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(TGL_DPLL0_DIV0_AFC_STARTUP_MASK, (val)) 5905 5906 #define _TGL_DPLL0_CFGCR1 0x164288 5907 #define _TGL_DPLL1_CFGCR1 0x164290 5908 #define _TGL_TBTPLL_CFGCR1 0x1642A0 5909 #define TGL_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ 5910 _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \ 5911 _TGL_TBTPLL_CFGCR1, _TGL_TBTPLL_CFGCR1)) 5912 #define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \ 5913 _TGL_DPLL1_CFGCR1) 5914 5915 #define _DG1_DPLL2_CFGCR0 0x16C284 5916 #define _DG1_DPLL3_CFGCR0 0x16C28C 5917 #define DG1_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ 5918 _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \ 5919 _DG1_DPLL2_CFGCR0, _DG1_DPLL3_CFGCR0)) 5920 5921 #define _DG1_DPLL2_CFGCR1 0x16C288 5922 #define _DG1_DPLL3_CFGCR1 0x16C290 5923 #define DG1_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ 5924 _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \ 5925 _DG1_DPLL2_CFGCR1, _DG1_DPLL3_CFGCR1)) 5926 5927 /* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */ 5928 #define _ADLS_DPLL4_CFGCR0 0x164294 5929 #define _ADLS_DPLL3_CFGCR0 0x1642C0 5930 #define ADLS_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ 5931 _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \ 5932 _ADLS_DPLL4_CFGCR0, _ADLS_DPLL3_CFGCR0)) 5933 5934 #define _ADLS_DPLL4_CFGCR1 0x164298 5935 #define _ADLS_DPLL3_CFGCR1 0x1642C4 5936 #define ADLS_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ 5937 _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \ 5938 _ADLS_DPLL4_CFGCR1, _ADLS_DPLL3_CFGCR1)) 5939 5940 /* BXT display engine PLL */ 5941 #define BXT_DE_PLL_CTL _MMIO(0x6d000) 5942 #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */ 5943 #define BXT_DE_PLL_RATIO_MASK 0xff 5944 5945 #define BXT_DE_PLL_ENABLE _MMIO(0x46070) 5946 #define BXT_DE_PLL_PLL_ENABLE (1 << 31) 5947 #define BXT_DE_PLL_LOCK (1 << 30) 5948 #define BXT_DE_PLL_FREQ_REQ (1 << 23) 5949 #define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22) 5950 #define ICL_CDCLK_PLL_RATIO(x) (x) 5951 #define ICL_CDCLK_PLL_RATIO_MASK 0xff 5952 5953 /* GEN9 DC */ 5954 #define DC_STATE_EN _MMIO(0x45504) 5955 #define DC_STATE_DISABLE 0 5956 #define DC_STATE_EN_DC3CO REG_BIT(30) 5957 #define DC_STATE_DC3CO_STATUS REG_BIT(29) 5958 #define HOLD_PHY_CLKREQ_PG1_LATCH REG_BIT(21) 5959 #define HOLD_PHY_PG1_LATCH REG_BIT(20) 5960 #define DC_STATE_EN_UPTO_DC5 (1 << 0) 5961 #define DC_STATE_EN_DC9 (1 << 3) 5962 #define DC_STATE_EN_UPTO_DC6 (2 << 0) 5963 #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3 5964 5965 #define DC_STATE_DEBUG _MMIO(0x45520) 5966 #define DC_STATE_DEBUG_MASK_CORES (1 << 0) 5967 #define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1) 5968 5969 #define D_COMP_BDW _MMIO(0x138144) 5970 5971 /* Pipe WM_LINETIME - watermark line time */ 5972 #define _WM_LINETIME_A 0x45270 5973 #define _WM_LINETIME_B 0x45274 5974 #define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B) 5975 #define HSW_LINETIME_MASK REG_GENMASK(8, 0) 5976 #define HSW_LINETIME(x) REG_FIELD_PREP(HSW_LINETIME_MASK, (x)) 5977 #define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16) 5978 #define HSW_IPS_LINETIME(x) REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x)) 5979 5980 /* SFUSE_STRAP */ 5981 #define SFUSE_STRAP _MMIO(0xc2014) 5982 #define SFUSE_STRAP_FUSE_LOCK (1 << 13) 5983 #define SFUSE_STRAP_RAW_FREQUENCY (1 << 8) 5984 #define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7) 5985 #define SFUSE_STRAP_CRT_DISABLED (1 << 6) 5986 #define SFUSE_STRAP_DDIF_DETECTED (1 << 3) 5987 #define SFUSE_STRAP_DDIB_DETECTED (1 << 2) 5988 #define SFUSE_STRAP_DDIC_DETECTED (1 << 1) 5989 #define SFUSE_STRAP_DDID_DETECTED (1 << 0) 5990 5991 #define WM_MISC _MMIO(0x45260) 5992 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0) 5993 5994 #define WM_DBG _MMIO(0x45280) 5995 #define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0) 5996 #define WM_DBG_DISALLOW_MAXFIFO (1 << 1) 5997 #define WM_DBG_DISALLOW_SPRITE (1 << 2) 5998 5999 #define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4) 6000 6001 /* Plane CSC Registers */ 6002 #define _PLANE_CSC_RY_GY_1_A 0x70210 6003 #define _PLANE_CSC_RY_GY_2_A 0x70310 6004 6005 #define _PLANE_CSC_RY_GY_1_B 0x71210 6006 #define _PLANE_CSC_RY_GY_2_B 0x71310 6007 6008 #define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \ 6009 _PLANE_CSC_RY_GY_1_B) 6010 #define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_2_A, \ 6011 _PLANE_CSC_RY_GY_2_B) 6012 #define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \ 6013 _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \ 6014 _PLANE_CSC_RY_GY_2(pipe) + (index) * 4) 6015 6016 #define _PLANE_CSC_PREOFF_HI_1_A 0x70228 6017 #define _PLANE_CSC_PREOFF_HI_2_A 0x70328 6018 6019 #define _PLANE_CSC_PREOFF_HI_1_B 0x71228 6020 #define _PLANE_CSC_PREOFF_HI_2_B 0x71328 6021 6022 #define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \ 6023 _PLANE_CSC_PREOFF_HI_1_B) 6024 #define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \ 6025 _PLANE_CSC_PREOFF_HI_2_B) 6026 #define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \ 6027 (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \ 6028 (index) * 4) 6029 6030 #define _PLANE_CSC_POSTOFF_HI_1_A 0x70234 6031 #define _PLANE_CSC_POSTOFF_HI_2_A 0x70334 6032 6033 #define _PLANE_CSC_POSTOFF_HI_1_B 0x71234 6034 #define _PLANE_CSC_POSTOFF_HI_2_B 0x71334 6035 6036 #define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \ 6037 _PLANE_CSC_POSTOFF_HI_1_B) 6038 #define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \ 6039 _PLANE_CSC_POSTOFF_HI_2_B) 6040 #define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \ 6041 (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \ 6042 (index) * 4) 6043 6044 /* Gen4+ Timestamp and Pipe Frame time stamp registers */ 6045 #define GEN4_TIMESTAMP _MMIO(0x2358) 6046 #define ILK_TIMESTAMP_HI _MMIO(0x70070) 6047 #define IVB_TIMESTAMP_CTR _MMIO(0x44070) 6048 6049 #define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074) 6050 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0 6051 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff 6052 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12 6053 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12) 6054 6055 /* g4x+, except vlv/chv! */ 6056 #define _PIPE_FRMTMSTMP_A 0x70048 6057 #define _PIPE_FRMTMSTMP_B 0x71048 6058 #define PIPE_FRMTMSTMP(pipe) \ 6059 _MMIO_PIPE(pipe, _PIPE_FRMTMSTMP_A, _PIPE_FRMTMSTMP_B) 6060 6061 /* g4x+, except vlv/chv! */ 6062 #define _PIPE_FLIPTMSTMP_A 0x7004C 6063 #define _PIPE_FLIPTMSTMP_B 0x7104C 6064 #define PIPE_FLIPTMSTMP(pipe) \ 6065 _MMIO_PIPE(pipe, _PIPE_FLIPTMSTMP_A, _PIPE_FLIPTMSTMP_B) 6066 6067 /* tgl+ */ 6068 #define _PIPE_FLIPDONETMSTMP_A 0x70054 6069 #define _PIPE_FLIPDONETMSTMP_B 0x71054 6070 #define PIPE_FLIPDONETIMSTMP(pipe) \ 6071 _MMIO_PIPE(pipe, _PIPE_FLIPDONETMSTMP_A, _PIPE_FLIPDONETMSTMP_B) 6072 6073 #define _VLV_PIPE_MSA_MISC_A 0x70048 6074 #define VLV_PIPE_MSA_MISC(pipe) \ 6075 _MMIO_PIPE2(pipe, _VLV_PIPE_MSA_MISC_A) 6076 #define VLV_MSA_MISC1_HW_ENABLE REG_BIT(31) 6077 #define VLV_MSA_MISC1_SW_S3D_MASK REG_GENMASK(2, 0) /* MSA MISC1 3:1 */ 6078 6079 #define GGC _MMIO(0x108040) 6080 #define GMS_MASK REG_GENMASK(15, 8) 6081 #define GGMS_MASK REG_GENMASK(7, 6) 6082 6083 #define GEN6_GSMBASE _MMIO(0x108100) 6084 #define GEN6_DSMBASE _MMIO(0x1080C0) 6085 #define GEN6_BDSM_MASK REG_GENMASK64(31, 20) 6086 #define GEN11_BDSM_MASK REG_GENMASK64(63, 20) 6087 6088 #define XEHP_CLOCK_GATE_DIS _MMIO(0x101014) 6089 #define SGSI_SIDECLK_DIS REG_BIT(17) 6090 #define SGGI_DIS REG_BIT(15) 6091 #define SGR_DIS REG_BIT(13) 6092 6093 #define _ICL_PHY_MISC_A 0x64C00 6094 #define _ICL_PHY_MISC_B 0x64C04 6095 #define _DG2_PHY_MISC_TC1 0x64C14 /* TC1="PHY E" but offset as if "PHY F" */ 6096 #define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, _ICL_PHY_MISC_B) 6097 #define DG2_PHY_MISC(port) ((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \ 6098 ICL_PHY_MISC(port)) 6099 #define ICL_PHY_MISC_MUX_DDID (1 << 28) 6100 #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23) 6101 #define DG2_PHY_DP_TX_ACK_MASK REG_GENMASK(23, 20) 6102 6103 #define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0) 6104 #define MODULAR_FIA_MASK (1 << 4) 6105 #define TC_LIVE_STATE_TBT(idx) (1 << ((idx) * 8 + 6)) 6106 #define TC_LIVE_STATE_TC(idx) (1 << ((idx) * 8 + 5)) 6107 #define DP_LANE_ASSIGNMENT_SHIFT(idx) ((idx) * 8) 6108 #define DP_LANE_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 8)) 6109 #define DP_LANE_ASSIGNMENT(idx, x) ((x) << ((idx) * 8)) 6110 6111 #define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890) 6112 #define DP_PHY_MODE_STATUS_COMPLETED(idx) (1 << (idx)) 6113 6114 #define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894) 6115 #define DP_PHY_MODE_STATUS_NOT_SAFE(idx) (1 << (idx)) 6116 6117 #define PORT_TX_DFLEXPA1(fia) _MMIO_FIA((fia), 0x00880) 6118 #define DP_PIN_ASSIGNMENT_SHIFT(idx) ((idx) * 4) 6119 #define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4)) 6120 #define DP_PIN_ASSIGNMENT(idx, x) ((x) << ((idx) * 4)) 6121 6122 #define _TCSS_DDI_STATUS_1 0x161500 6123 #define _TCSS_DDI_STATUS_2 0x161504 6124 #define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \ 6125 _TCSS_DDI_STATUS_1, \ 6126 _TCSS_DDI_STATUS_2)) 6127 #define TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK REG_GENMASK(28, 25) 6128 #define TCSS_DDI_STATUS_READY REG_BIT(2) 6129 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1) 6130 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0) 6131 6132 #define PRIMARY_SPI_TRIGGER _MMIO(0x102040) 6133 #define PRIMARY_SPI_ADDRESS _MMIO(0x102080) 6134 #define PRIMARY_SPI_REGIONID _MMIO(0x102084) 6135 #define SPI_STATIC_REGIONS _MMIO(0x102090) 6136 #define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0) 6137 #define OROM_OFFSET _MMIO(0x1020c0) 6138 #define OROM_OFFSET_MASK REG_GENMASK(20, 16) 6139 6140 #define CLKREQ_POLICY _MMIO(0x101038) 6141 #define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1) 6142 6143 #define CLKGATE_DIS_MISC _MMIO(0x46534) 6144 #define CLKGATE_DIS_MISC_DMASC_GATING_DIS REG_BIT(21) 6145 6146 #define _MTL_CLKGATE_DIS_TRANS_A 0x604E8 6147 #define _MTL_CLKGATE_DIS_TRANS_B 0x614E8 6148 #define MTL_CLKGATE_DIS_TRANS(trans) _MMIO_TRANS2(trans, _MTL_CLKGATE_DIS_TRANS_A) 6149 #define MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS REG_BIT(7) 6150 6151 #define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700) 6152 #define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8) 6153 #define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4) 6154 #define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0) 6155 6156 #define MTL_MEM_SS_INFO_QGV_POINT_OFFSET 0x45710 6157 #define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8) 6158 #define MTL_TRCD_MASK REG_GENMASK(31, 24) 6159 #define MTL_TRP_MASK REG_GENMASK(23, 16) 6160 #define MTL_DCLK_MASK REG_GENMASK(15, 0) 6161 6162 #define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8 + 4) 6163 #define MTL_TRAS_MASK REG_GENMASK(16, 8) 6164 #define MTL_TRDPRE_MASK REG_GENMASK(7, 0) 6165 6166 #define MTL_MEDIA_GSI_BASE 0x380000 6167 6168 #endif /* _I915_REG_H_ */ 6169