1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 2 * All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef _I915_REG_H_ 26 #define _I915_REG_H_ 27 28 #include "i915_reg_defs.h" 29 #include "display/intel_display_reg_defs.h" 30 31 /** 32 * DOC: The i915 register macro definition style guide 33 * 34 * Follow the style described here for new macros, and while changing existing 35 * macros. Do **not** mass change existing definitions just to update the style. 36 * 37 * File Layout 38 * ~~~~~~~~~~~ 39 * 40 * Keep helper macros near the top. For example, _PIPE() and friends. 41 * 42 * Prefix macros that generally should not be used outside of this file with 43 * underscore '_'. For example, _PIPE() and friends, single instances of 44 * registers that are defined solely for the use by function-like macros. 45 * 46 * Avoid using the underscore prefixed macros outside of this file. There are 47 * exceptions, but keep them to a minimum. 48 * 49 * There are two basic types of register definitions: Single registers and 50 * register groups. Register groups are registers which have two or more 51 * instances, for example one per pipe, port, transcoder, etc. Register groups 52 * should be defined using function-like macros. 53 * 54 * For single registers, define the register offset first, followed by register 55 * contents. 56 * 57 * For register groups, define the register instance offsets first, prefixed 58 * with underscore, followed by a function-like macro choosing the right 59 * instance based on the parameter, followed by register contents. 60 * 61 * Define the register contents (i.e. bit and bit field macros) from most 62 * significant to least significant bit. Indent the register content macros 63 * using two extra spaces between ``#define`` and the macro name. 64 * 65 * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents 66 * using ``REG_FIELD_PREP(mask, value)``. This will define the values already 67 * shifted in place, so they can be directly OR'd together. For convenience, 68 * function-like macros may be used to define bit fields, but do note that the 69 * macros may be needed to read as well as write the register contents. 70 * 71 * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name. 72 * 73 * Group the register and its contents together without blank lines, separate 74 * from other registers and their contents with one blank line. 75 * 76 * Indent macro values from macro names using TABs. Align values vertically. Use 77 * braces in macro values as needed to avoid unintended precedence after macro 78 * substitution. Use spaces in macro values according to kernel coding 79 * style. Use lower case in hexadecimal values. 80 * 81 * Naming 82 * ~~~~~~ 83 * 84 * Try to name registers according to the specs. If the register name changes in 85 * the specs from platform to another, stick to the original name. 86 * 87 * Try to re-use existing register macro definitions. Only add new macros for 88 * new register offsets, or when the register contents have changed enough to 89 * warrant a full redefinition. 90 * 91 * When a register macro changes for a new platform, prefix the new macro using 92 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The 93 * prefix signifies the start platform/generation using the register. 94 * 95 * When a bit (field) macro changes or gets added for a new platform, while 96 * retaining the existing register macro, add a platform acronym or generation 97 * suffix to the name. For example, ``_SKL`` or ``_GEN8``. 98 * 99 * Examples 100 * ~~~~~~~~ 101 * 102 * (Note that the values in the example are indented using spaces instead of 103 * TABs to avoid misalignment in generated documentation. Use TABs in the 104 * definitions.):: 105 * 106 * #define _FOO_A 0xf000 107 * #define _FOO_B 0xf001 108 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B) 109 * #define FOO_ENABLE REG_BIT(31) 110 * #define FOO_MODE_MASK REG_GENMASK(19, 16) 111 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0) 112 * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1) 113 * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2) 114 * 115 * #define BAR _MMIO(0xb000) 116 * #define GEN8_BAR _MMIO(0xb888) 117 */ 118 119 #define GU_CNTL_PROTECTED _MMIO(0x10100C) 120 #define DEPRESENT REG_BIT(9) 121 122 #define GU_CNTL _MMIO(0x101010) 123 #define LMEM_INIT REG_BIT(7) 124 #define DRIVERFLR REG_BIT(31) 125 #define GU_DEBUG _MMIO(0x101018) 126 #define DRIVERFLR_STATUS REG_BIT(31) 127 128 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0) 129 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20) 130 #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18) 131 #define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4) 132 #define GEN6_STOLEN_RESERVED_1M (0 << 4) 133 #define GEN6_STOLEN_RESERVED_512K (1 << 4) 134 #define GEN6_STOLEN_RESERVED_256K (2 << 4) 135 #define GEN6_STOLEN_RESERVED_128K (3 << 4) 136 #define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5) 137 #define GEN7_STOLEN_RESERVED_1M (0 << 5) 138 #define GEN7_STOLEN_RESERVED_256K (1 << 5) 139 #define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7) 140 #define GEN8_STOLEN_RESERVED_1M (0 << 7) 141 #define GEN8_STOLEN_RESERVED_2M (1 << 7) 142 #define GEN8_STOLEN_RESERVED_4M (2 << 7) 143 #define GEN8_STOLEN_RESERVED_8M (3 << 7) 144 #define GEN6_STOLEN_RESERVED_ENABLE (1 << 0) 145 #define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20) 146 147 #define _VGA_MSR_WRITE _MMIO(0x3c2) 148 149 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 150 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 151 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL) 152 153 /* 154 * Reset registers 155 */ 156 #define DEBUG_RESET_I830 _MMIO(0x6070) 157 #define DEBUG_RESET_FULL (1 << 7) 158 #define DEBUG_RESET_RENDER (1 << 8) 159 #define DEBUG_RESET_DISPLAY (1 << 9) 160 161 /* 162 * IOSF sideband 163 */ 164 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100) 165 #define IOSF_DEVFN_SHIFT 24 166 #define IOSF_OPCODE_SHIFT 16 167 #define IOSF_PORT_SHIFT 8 168 #define IOSF_BYTE_ENABLES_SHIFT 4 169 #define IOSF_BAR_SHIFT 1 170 #define IOSF_SB_BUSY (1 << 0) 171 #define IOSF_PORT_BUNIT 0x03 172 #define IOSF_PORT_PUNIT 0x04 173 #define IOSF_PORT_NC 0x11 174 #define IOSF_PORT_DPIO 0x12 175 #define IOSF_PORT_GPIO_NC 0x13 176 #define IOSF_PORT_CCK 0x14 177 #define IOSF_PORT_DPIO_2 0x1a 178 #define IOSF_PORT_FLISDSI 0x1b 179 #define IOSF_PORT_GPIO_SC 0x48 180 #define IOSF_PORT_GPIO_SUS 0xa8 181 #define IOSF_PORT_CCU 0xa9 182 #define CHV_IOSF_PORT_GPIO_N 0x13 183 #define CHV_IOSF_PORT_GPIO_SE 0x48 184 #define CHV_IOSF_PORT_GPIO_E 0xa8 185 #define CHV_IOSF_PORT_GPIO_SW 0xb2 186 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104) 187 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108) 188 189 /* DPIO registers */ 190 #define DPIO_DEVFN 0 191 192 #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110) 193 #define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */ 194 #define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */ 195 #define DPIO_SFR_BYPASS (1 << 1) 196 #define DPIO_CMNRST (1 << 0) 197 198 #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090) 199 #define MIPIO_RST_CTRL (1 << 2) 200 201 #define _BXT_PHY_CTL_DDI_A 0x64C00 202 #define _BXT_PHY_CTL_DDI_B 0x64C10 203 #define _BXT_PHY_CTL_DDI_C 0x64C20 204 #define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10) 205 #define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9) 206 #define BXT_PHY_LANE_ENABLED (1 << 8) 207 #define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \ 208 _BXT_PHY_CTL_DDI_B) 209 210 #define _PHY_CTL_FAMILY_DDI 0x64C90 211 #define _PHY_CTL_FAMILY_EDP 0x64C80 212 #define _PHY_CTL_FAMILY_DDI_C 0x64CA0 213 #define COMMON_RESET_DIS (1 << 31) 214 #define BXT_PHY_CTL_FAMILY(phy) \ 215 _MMIO(_PICK_EVEN_2RANGES(phy, 1, \ 216 _PHY_CTL_FAMILY_DDI, _PHY_CTL_FAMILY_DDI, \ 217 _PHY_CTL_FAMILY_EDP, _PHY_CTL_FAMILY_DDI_C)) 218 219 /* UAIMI scratch pad register 1 */ 220 #define UAIMI_SPR1 _MMIO(0x4F074) 221 /* SKL VccIO mask */ 222 #define SKL_VCCIO_MASK 0x1 223 /* SKL balance leg register */ 224 #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C) 225 /* I_boost values */ 226 #define BALANCE_LEG_SHIFT(port) (8 + 3 * (port)) 227 #define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port))) 228 /* Balance leg disable bits */ 229 #define BALANCE_LEG_DISABLE_SHIFT 23 230 #define BALANCE_LEG_DISABLE(port) (1 << (23 + (port))) 231 232 /* 233 * Fence registers 234 * [0-7] @ 0x2000 gen2,gen3 235 * [8-15] @ 0x3000 945,g33,pnv 236 * 237 * [0-15] @ 0x3000 gen4,gen5 238 * 239 * [0-15] @ 0x100000 gen6,vlv,chv 240 * [0-31] @ 0x100000 gen7+ 241 */ 242 #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4) 243 #define I830_FENCE_START_MASK 0x07f80000 244 #define I830_FENCE_TILING_Y_SHIFT 12 245 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 246 #define I830_FENCE_PITCH_SHIFT 4 247 #define I830_FENCE_REG_VALID (1 << 0) 248 #define I915_FENCE_MAX_PITCH_VAL 4 249 #define I830_FENCE_MAX_PITCH_VAL 6 250 #define I830_FENCE_MAX_SIZE_VAL (1 << 8) 251 252 #define I915_FENCE_START_MASK 0x0ff00000 253 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) 254 255 #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8) 256 #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4) 257 #define I965_FENCE_PITCH_SHIFT 2 258 #define I965_FENCE_TILING_Y_SHIFT 1 259 #define I965_FENCE_REG_VALID (1 << 0) 260 #define I965_FENCE_MAX_PITCH_VAL 0x0400 261 262 #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8) 263 #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4) 264 #define GEN6_FENCE_PITCH_SHIFT 32 265 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 266 267 268 /* control register for cpu gtt access */ 269 #define TILECTL _MMIO(0x101000) 270 #define TILECTL_SWZCTL (1 << 0) 271 #define TILECTL_TLBPF (1 << 1) 272 #define TILECTL_TLB_PREFETCH_DIS (1 << 2) 273 #define TILECTL_BACKSNOOP_DIS (1 << 3) 274 275 /* 276 * Instruction and interrupt control regs 277 */ 278 #define PGTBL_CTL _MMIO(0x02020) 279 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ 280 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ 281 #define PGTBL_ER _MMIO(0x02024) 282 #define PRB0_BASE (0x2030 - 0x30) 283 #define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */ 284 #define PRB2_BASE (0x2050 - 0x30) /* gen3 */ 285 #define SRB0_BASE (0x2100 - 0x30) /* gen2 */ 286 #define SRB1_BASE (0x2110 - 0x30) /* gen2 */ 287 #define SRB2_BASE (0x2120 - 0x30) /* 830 */ 288 #define SRB3_BASE (0x2130 - 0x30) /* 830 */ 289 #define RENDER_RING_BASE 0x02000 290 #define BSD_RING_BASE 0x04000 291 #define GEN6_BSD_RING_BASE 0x12000 292 #define GEN8_BSD2_RING_BASE 0x1c000 293 #define GEN11_BSD_RING_BASE 0x1c0000 294 #define GEN11_BSD2_RING_BASE 0x1c4000 295 #define GEN11_BSD3_RING_BASE 0x1d0000 296 #define GEN11_BSD4_RING_BASE 0x1d4000 297 #define XEHP_BSD5_RING_BASE 0x1e0000 298 #define XEHP_BSD6_RING_BASE 0x1e4000 299 #define XEHP_BSD7_RING_BASE 0x1f0000 300 #define XEHP_BSD8_RING_BASE 0x1f4000 301 #define VEBOX_RING_BASE 0x1a000 302 #define GEN11_VEBOX_RING_BASE 0x1c8000 303 #define GEN11_VEBOX2_RING_BASE 0x1d8000 304 #define XEHP_VEBOX3_RING_BASE 0x1e8000 305 #define XEHP_VEBOX4_RING_BASE 0x1f8000 306 #define MTL_GSC_RING_BASE 0x11a000 307 #define GEN12_COMPUTE0_RING_BASE 0x1a000 308 #define GEN12_COMPUTE1_RING_BASE 0x1c000 309 #define GEN12_COMPUTE2_RING_BASE 0x1e000 310 #define GEN12_COMPUTE3_RING_BASE 0x26000 311 #define BLT_RING_BASE 0x22000 312 #define XEHPC_BCS1_RING_BASE 0x3e0000 313 #define XEHPC_BCS2_RING_BASE 0x3e2000 314 #define XEHPC_BCS3_RING_BASE 0x3e4000 315 #define XEHPC_BCS4_RING_BASE 0x3e6000 316 #define XEHPC_BCS5_RING_BASE 0x3e8000 317 #define XEHPC_BCS6_RING_BASE 0x3ea000 318 #define XEHPC_BCS7_RING_BASE 0x3ec000 319 #define XEHPC_BCS8_RING_BASE 0x3ee000 320 #define DG1_GSC_HECI1_BASE 0x00258000 321 #define DG1_GSC_HECI2_BASE 0x00259000 322 #define DG2_GSC_HECI1_BASE 0x00373000 323 #define DG2_GSC_HECI2_BASE 0x00374000 324 #define MTL_GSC_HECI1_BASE 0x00116000 325 #define MTL_GSC_HECI2_BASE 0x00117000 326 327 #define HECI_H_CSR(base) _MMIO((base) + 0x4) 328 #define HECI_H_CSR_IE REG_BIT(0) 329 #define HECI_H_CSR_IS REG_BIT(1) 330 #define HECI_H_CSR_IG REG_BIT(2) 331 #define HECI_H_CSR_RDY REG_BIT(3) 332 #define HECI_H_CSR_RST REG_BIT(4) 333 334 #define HECI_H_GS1(base) _MMIO((base) + 0xc4c) 335 #define HECI_H_GS1_ER_PREP REG_BIT(0) 336 337 /* 338 * The FWSTS register values are FW defined and can be different between 339 * HECI1 and HECI2 340 */ 341 #define HECI_FWSTS1 0xc40 342 #define HECI1_FWSTS1_CURRENT_STATE REG_GENMASK(3, 0) 343 #define HECI1_FWSTS1_CURRENT_STATE_RESET 0 344 #define HECI1_FWSTS1_PROXY_STATE_NORMAL 5 345 #define HECI1_FWSTS1_INIT_COMPLETE REG_BIT(9) 346 #define HECI_FWSTS2 0xc48 347 #define HECI_FWSTS3 0xc60 348 #define HECI_FWSTS4 0xc64 349 #define HECI_FWSTS5 0xc68 350 #define HECI1_FWSTS5_HUC_AUTH_DONE (1 << 19) 351 #define HECI_FWSTS6 0xc6c 352 353 /* the FWSTS regs are 1-based, so we use -base for index 0 to get an invalid reg */ 354 #define HECI_FWSTS(base, x) _MMIO((base) + _PICK(x, -(base), \ 355 HECI_FWSTS1, \ 356 HECI_FWSTS2, \ 357 HECI_FWSTS3, \ 358 HECI_FWSTS4, \ 359 HECI_FWSTS5, \ 360 HECI_FWSTS6)) 361 362 #define HSW_GTT_CACHE_EN _MMIO(0x4024) 363 #define GTT_CACHE_EN_ALL 0xF0007FFF 364 #define GEN7_WR_WATERMARK _MMIO(0x4028) 365 #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C) 366 #define ARB_MODE _MMIO(0x4030) 367 #define ARB_MODE_SWIZZLE_SNB (1 << 4) 368 #define ARB_MODE_SWIZZLE_IVB (1 << 5) 369 #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034) 370 #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038) 371 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ 372 #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4) 373 #define GEN7_LRA_LIMITS_REG_NUM 13 374 #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070) 375 #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074) 376 377 #define GEN7_ERR_INT _MMIO(0x44040) 378 #define ERR_INT_POISON (1 << 31) 379 #define ERR_INT_MMIO_UNCLAIMED (1 << 13) 380 #define ERR_INT_PIPE_CRC_DONE_C (1 << 8) 381 #define ERR_INT_FIFO_UNDERRUN_C (1 << 6) 382 #define ERR_INT_PIPE_CRC_DONE_B (1 << 5) 383 #define ERR_INT_FIFO_UNDERRUN_B (1 << 3) 384 #define ERR_INT_PIPE_CRC_DONE_A (1 << 2) 385 #define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3)) 386 #define ERR_INT_FIFO_UNDERRUN_A (1 << 0) 387 #define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) 388 389 #define FPGA_DBG _MMIO(0x42300) 390 #define FPGA_DBG_RM_NOCLAIM REG_BIT(31) 391 392 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028) 393 #define CLAIM_ER_CLR REG_BIT(31) 394 #define CLAIM_ER_OVERFLOW REG_BIT(16) 395 #define CLAIM_ER_CTR_MASK REG_GENMASK(15, 0) 396 397 #define DERRMR _MMIO(0x44050) 398 /* Note that HBLANK events are reserved on bdw+ */ 399 #define DERRMR_PIPEA_SCANLINE (1 << 0) 400 #define DERRMR_PIPEA_PRI_FLIP_DONE (1 << 1) 401 #define DERRMR_PIPEA_SPR_FLIP_DONE (1 << 2) 402 #define DERRMR_PIPEA_VBLANK (1 << 3) 403 #define DERRMR_PIPEA_HBLANK (1 << 5) 404 #define DERRMR_PIPEB_SCANLINE (1 << 8) 405 #define DERRMR_PIPEB_PRI_FLIP_DONE (1 << 9) 406 #define DERRMR_PIPEB_SPR_FLIP_DONE (1 << 10) 407 #define DERRMR_PIPEB_VBLANK (1 << 11) 408 #define DERRMR_PIPEB_HBLANK (1 << 13) 409 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */ 410 #define DERRMR_PIPEC_SCANLINE (1 << 14) 411 #define DERRMR_PIPEC_PRI_FLIP_DONE (1 << 15) 412 #define DERRMR_PIPEC_SPR_FLIP_DONE (1 << 20) 413 #define DERRMR_PIPEC_VBLANK (1 << 21) 414 #define DERRMR_PIPEC_HBLANK (1 << 22) 415 416 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030) 417 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034) 418 #define SCPD0 _MMIO(0x209c) /* 915+ only */ 419 #define SCPD_FBC_IGNORE_3D (1 << 6) 420 #define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5) 421 #define GEN2_IER _MMIO(0x20a0) 422 #define GEN2_IIR _MMIO(0x20a4) 423 #define GEN2_IMR _MMIO(0x20a8) 424 #define GEN2_ISR _MMIO(0x20ac) 425 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060) 426 #define GINT_DIS (1 << 22) 427 #define GCFG_DIS (1 << 8) 428 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064) 429 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084) 430 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0) 431 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4) 432 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8) 433 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac) 434 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120) 435 #define VLV_PCBR_ADDR_SHIFT 12 436 437 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */ 438 #define EIR _MMIO(0x20b0) 439 #define EMR _MMIO(0x20b4) 440 #define ESR _MMIO(0x20b8) 441 #define GM45_ERROR_PAGE_TABLE (1 << 5) 442 #define GM45_ERROR_MEM_PRIV (1 << 4) 443 #define I915_ERROR_PAGE_TABLE (1 << 4) 444 #define GM45_ERROR_CP_PRIV (1 << 3) 445 #define I915_ERROR_MEMORY_REFRESH (1 << 1) 446 #define I915_ERROR_INSTRUCTION (1 << 0) 447 #define INSTPM _MMIO(0x20c0) 448 #define INSTPM_SELF_EN (1 << 12) /* 915GM only */ 449 #define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts 450 will not assert AGPBUSY# and will only 451 be delivered when out of C3. */ 452 #define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */ 453 #define INSTPM_TLB_INVALIDATE (1 << 9) 454 #define INSTPM_SYNC_FLUSH (1 << 5) 455 #define MEM_MODE _MMIO(0x20cc) 456 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */ 457 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */ 458 #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */ 459 #define FW_BLC _MMIO(0x20d8) 460 #define FW_BLC2 _MMIO(0x20dc) 461 #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */ 462 #define FW_BLC_SELF_EN_MASK (1 << 31) 463 #define FW_BLC_SELF_FIFO_MASK (1 << 16) /* 945 only */ 464 #define FW_BLC_SELF_EN (1 << 15) /* 945 only */ 465 #define MM_BURST_LENGTH 0x00700000 466 #define MM_FIFO_WATERMARK 0x0001F000 467 #define LM_BURST_LENGTH 0x00000700 468 #define LM_FIFO_WATERMARK 0x0000001F 469 #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */ 470 471 #define _MBUS_ABOX0_CTL 0x45038 472 #define _MBUS_ABOX1_CTL 0x45048 473 #define _MBUS_ABOX2_CTL 0x4504C 474 #define MBUS_ABOX_CTL(x) \ 475 _MMIO(_PICK_EVEN_2RANGES(x, 2, \ 476 _MBUS_ABOX0_CTL, _MBUS_ABOX1_CTL, \ 477 _MBUS_ABOX2_CTL, _MBUS_ABOX2_CTL)) 478 479 #define MBUS_ABOX_BW_CREDIT_MASK (3 << 20) 480 #define MBUS_ABOX_BW_CREDIT(x) ((x) << 20) 481 #define MBUS_ABOX_B_CREDIT_MASK (0xF << 16) 482 #define MBUS_ABOX_B_CREDIT(x) ((x) << 16) 483 #define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8) 484 #define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8) 485 #define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0) 486 #define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0) 487 488 /* Make render/texture TLB fetches lower priorty than associated data 489 * fetches. This is not turned on by default 490 */ 491 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) 492 493 /* Isoch request wait on GTT enable (Display A/B/C streams). 494 * Make isoch requests stall on the TLB update. May cause 495 * display underruns (test mode only) 496 */ 497 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) 498 499 /* Block grant count for isoch requests when block count is 500 * set to a finite value. 501 */ 502 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) 503 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ 504 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ 505 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ 506 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ 507 508 /* Enable render writes to complete in C2/C3/C4 power states. 509 * If this isn't enabled, render writes are prevented in low 510 * power states. That seems bad to me. 511 */ 512 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) 513 514 /* This acknowledges an async flip immediately instead 515 * of waiting for 2TLB fetches. 516 */ 517 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) 518 519 /* Enables non-sequential data reads through arbiter 520 */ 521 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) 522 523 /* Disable FSB snooping of cacheable write cycles from binner/render 524 * command stream 525 */ 526 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) 527 528 /* Arbiter time slice for non-isoch streams */ 529 #define MI_ARB_TIME_SLICE_MASK (7 << 5) 530 #define MI_ARB_TIME_SLICE_1 (0 << 5) 531 #define MI_ARB_TIME_SLICE_2 (1 << 5) 532 #define MI_ARB_TIME_SLICE_4 (2 << 5) 533 #define MI_ARB_TIME_SLICE_6 (3 << 5) 534 #define MI_ARB_TIME_SLICE_8 (4 << 5) 535 #define MI_ARB_TIME_SLICE_10 (5 << 5) 536 #define MI_ARB_TIME_SLICE_14 (6 << 5) 537 #define MI_ARB_TIME_SLICE_16 (7 << 5) 538 539 /* Low priority grace period page size */ 540 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ 541 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) 542 543 /* Disable display A/B trickle feed */ 544 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) 545 546 /* Set display plane priority */ 547 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ 548 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ 549 550 #define MI_STATE _MMIO(0x20e4) /* gen2 only */ 551 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */ 552 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */ 553 554 /* On modern GEN architectures interrupt control consists of two sets 555 * of registers. The first set pertains to the ring generating the 556 * interrupt. The second control is for the functional block generating the 557 * interrupt. These are PM, GT, DE, etc. 558 * 559 * Luckily *knocks on wood* all the ring interrupt bits match up with the 560 * GT interrupt bits, so we don't need to duplicate the defines. 561 * 562 * These defines should cover us well from SNB->HSW with minor exceptions 563 * it can also work on ILK. 564 */ 565 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) 566 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25) 567 #define GT_BLT_USER_INTERRUPT (1 << 22) 568 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15) 569 #define GT_BSD_USER_INTERRUPT (1 << 12) 570 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */ 571 #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) /* bdw+ */ 572 #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8) 573 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */ 574 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) 575 #define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3) 576 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2) 577 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1) 578 #define GT_RENDER_USER_INTERRUPT (1 << 0) 579 580 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */ 581 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */ 582 583 #define GT_PARITY_ERROR(dev_priv) \ 584 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \ 585 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0)) 586 587 /* These are all the "old" interrupts */ 588 #define ILK_BSD_USER_INTERRUPT (1 << 5) 589 590 #define I915_PM_INTERRUPT (1 << 31) 591 #define I915_ISP_INTERRUPT (1 << 22) 592 #define I915_LPE_PIPE_B_INTERRUPT (1 << 21) 593 #define I915_LPE_PIPE_A_INTERRUPT (1 << 20) 594 #define I915_MIPIC_INTERRUPT (1 << 19) 595 #define I915_MIPIA_INTERRUPT (1 << 18) 596 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18) 597 #define I915_DISPLAY_PORT_INTERRUPT (1 << 17) 598 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16) 599 #define I915_MASTER_ERROR_INTERRUPT (1 << 15) 600 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14) 601 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */ 602 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13) 603 #define I915_HWB_OOM_INTERRUPT (1 << 13) 604 #define I915_LPE_PIPE_C_INTERRUPT (1 << 12) 605 #define I915_SYNC_STATUS_INTERRUPT (1 << 12) 606 #define I915_MISC_INTERRUPT (1 << 11) 607 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11) 608 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10) 609 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10) 610 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9) 611 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9) 612 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8) 613 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8) 614 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7) 615 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6) 616 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5) 617 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4) 618 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3) 619 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2) 620 #define I915_DEBUG_INTERRUPT (1 << 2) 621 #define I915_WINVALID_INTERRUPT (1 << 1) 622 #define I915_USER_INTERRUPT (1 << 1) 623 #define I915_ASLE_INTERRUPT (1 << 0) 624 #define I915_BSD_USER_INTERRUPT (1 << 25) 625 626 #define GEN6_BSD_RNCID _MMIO(0x12198) 627 628 #define GEN7_FF_THREAD_MODE _MMIO(0x20a0) 629 #define GEN7_FF_SCHED_MASK 0x0077070 630 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19) 631 #define GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19) 632 #define GEN7_FF_TS_SCHED_HS1 (0x5 << 16) 633 #define GEN7_FF_TS_SCHED_HS0 (0x3 << 16) 634 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16) 635 #define GEN7_FF_TS_SCHED_HW (0x0 << 16) /* Default */ 636 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15) 637 #define GEN7_FF_VS_SCHED_HS1 (0x5 << 12) 638 #define GEN7_FF_VS_SCHED_HS0 (0x3 << 12) 639 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */ 640 #define GEN7_FF_VS_SCHED_HW (0x0 << 12) 641 #define GEN7_FF_DS_SCHED_HS1 (0x5 << 4) 642 #define GEN7_FF_DS_SCHED_HS0 (0x3 << 4) 643 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */ 644 #define GEN7_FF_DS_SCHED_HW (0x0 << 4) 645 646 #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000) 647 #define ILK_FBCQ_DIS REG_BIT(22) 648 #define ILK_PABSTRETCH_DIS REG_BIT(21) 649 #define ILK_SABSTRETCH_DIS REG_BIT(20) 650 #define IVB_PRI_STRETCH_MAX_MASK REG_GENMASK(21, 20) 651 #define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0) 652 #define IVB_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1) 653 #define IVB_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2) 654 #define IVB_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3) 655 #define IVB_SPR_STRETCH_MAX_MASK REG_GENMASK(19, 18) 656 #define IVB_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0) 657 #define IVB_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1) 658 #define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2) 659 #define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3) 660 661 #define IPS_CTL _MMIO(0x43408) 662 #define IPS_ENABLE REG_BIT(31) 663 #define IPS_FALSE_COLOR REG_BIT(4) 664 665 /* 666 * Clock control & power management 667 */ 668 #define _DPLL_A 0x6014 669 #define _DPLL_B 0x6018 670 #define _CHV_DPLL_C 0x6030 671 #define DPLL(dev_priv, pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \ 672 (pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) 673 674 #define VGA0 _MMIO(0x6000) 675 #define VGA1 _MMIO(0x6004) 676 #define VGA_PD _MMIO(0x6010) 677 #define VGA0_PD_P2_DIV_4 (1 << 7) 678 #define VGA0_PD_P1_DIV_2 (1 << 5) 679 #define VGA0_PD_P1_SHIFT 0 680 #define VGA0_PD_P1_MASK (0x1f << 0) 681 #define VGA1_PD_P2_DIV_4 (1 << 15) 682 #define VGA1_PD_P1_DIV_2 (1 << 13) 683 #define VGA1_PD_P1_SHIFT 8 684 #define VGA1_PD_P1_MASK (0x1f << 8) 685 #define DPLL_VCO_ENABLE (1 << 31) 686 #define DPLL_SDVO_HIGH_SPEED (1 << 30) 687 #define DPLL_DVO_2X_MODE (1 << 30) 688 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) 689 #define DPLL_SYNCLOCK_ENABLE (1 << 29) 690 #define DPLL_REF_CLK_ENABLE_VLV (1 << 29) 691 #define DPLL_VGA_MODE_DIS (1 << 28) 692 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 693 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 694 #define DPLL_MODE_MASK (3 << 26) 695 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 696 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 697 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 698 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 699 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 700 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 701 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ 702 #define DPLL_LOCK_VLV (1 << 15) 703 #define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14) 704 #define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13) 705 #define DPLL_SSC_REF_CLK_CHV (1 << 13) 706 #define DPLL_PORTC_READY_MASK (0xf << 4) 707 #define DPLL_PORTB_READY_MASK (0xf) 708 709 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 710 711 /* Additional CHV pll/phy registers */ 712 #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240) 713 #define DPLL_PORTD_READY_MASK (0xf) 714 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100) 715 #define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27)) 716 #define PHY_LDO_DELAY_0NS 0x0 717 #define PHY_LDO_DELAY_200NS 0x1 718 #define PHY_LDO_DELAY_600NS 0x2 719 #define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23)) 720 #define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11)) 721 #define PHY_CH_SU_PSR 0x1 722 #define PHY_CH_DEEP_PSR 0x7 723 #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2)) 724 #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy)) 725 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104) 726 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30)) 727 #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch)))) 728 #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline)))) 729 730 /* 731 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 732 * this field (only one bit may be set). 733 */ 734 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 735 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 736 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 737 /* i830, required in DVO non-gang */ 738 #define PLL_P2_DIVIDE_BY_4 (1 << 23) 739 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 740 #define PLL_REF_INPUT_DREFCLK (0 << 13) 741 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 742 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 743 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 744 #define PLL_REF_INPUT_MASK (3 << 13) 745 #define PLL_LOAD_PULSE_PHASE_SHIFT 9 746 /* Ironlake */ 747 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 748 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) 749 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9) 750 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 751 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff 752 753 /* 754 * Parallel to Serial Load Pulse phase selection. 755 * Selects the phase for the 10X DPLL clock for the PCIe 756 * digital display port. The range is 4 to 13; 10 or more 757 * is just a flip delay. The default is 6 758 */ 759 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 760 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 761 /* 762 * SDVO multiplier for 945G/GM. Not used on 965. 763 */ 764 #define SDVO_MULTIPLIER_MASK 0x000000ff 765 #define SDVO_MULTIPLIER_SHIFT_HIRES 4 766 #define SDVO_MULTIPLIER_SHIFT_VGA 0 767 768 #define _DPLL_A_MD 0x601c 769 #define _DPLL_B_MD 0x6020 770 #define _CHV_DPLL_C_MD 0x603c 771 #define DPLL_MD(dev_priv, pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \ 772 (pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) 773 774 /* 775 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 776 * 777 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 778 */ 779 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 780 #define DPLL_MD_UDI_DIVIDER_SHIFT 24 781 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 782 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 783 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 784 /* 785 * SDVO/UDI pixel multiplier. 786 * 787 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 788 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 789 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 790 * dummy bytes in the datastream at an increased clock rate, with both sides of 791 * the link knowing how many bytes are fill. 792 * 793 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 794 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 795 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 796 * through an SDVO command. 797 * 798 * This register field has values of multiplication factor minus 1, with 799 * a maximum multiplier of 5 for SDVO. 800 */ 801 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 802 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 803 /* 804 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 805 * This best be set to the default value (3) or the CRT won't work. No, 806 * I don't entirely understand what this does... 807 */ 808 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 809 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 810 811 #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024) 812 813 #define _FPA0 0x6040 814 #define _FPA1 0x6044 815 #define _FPB0 0x6048 816 #define _FPB1 0x604c 817 #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0) 818 #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1) 819 #define FP_N_DIV_MASK 0x003f0000 820 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 821 #define FP_N_DIV_SHIFT 16 822 #define FP_M1_DIV_MASK 0x00003f00 823 #define FP_M1_DIV_SHIFT 8 824 #define FP_M2_DIV_MASK 0x0000003f 825 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff 826 #define FP_M2_DIV_SHIFT 0 827 #define DPLL_TEST _MMIO(0x606c) 828 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 829 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 830 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 831 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 832 #define DPLLB_TEST_N_BYPASS (1 << 19) 833 #define DPLLB_TEST_M_BYPASS (1 << 18) 834 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 835 #define DPLLA_TEST_N_BYPASS (1 << 3) 836 #define DPLLA_TEST_M_BYPASS (1 << 2) 837 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 838 #define D_STATE _MMIO(0x6104) 839 #define DSTATE_GFX_RESET_I830 (1 << 6) 840 #define DSTATE_PLL_D3_OFF (1 << 3) 841 #define DSTATE_GFX_CLOCK_GATING (1 << 1) 842 #define DSTATE_DOT_CLOCK_GATING (1 << 0) 843 #define DSPCLK_GATE_D(__i915) _MMIO(DISPLAY_MMIO_BASE(__i915) + 0x6200) 844 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 845 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 846 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 847 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ 848 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ 849 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ 850 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ 851 # define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */ 852 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ 853 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ 854 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ 855 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ 856 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ 857 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ 858 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ 859 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ 860 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ 861 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ 862 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ 863 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ 864 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 865 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) 866 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) 867 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) 868 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ 869 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ 870 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ 871 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) 872 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) 873 /* 874 * This bit must be set on the 830 to prevent hangs when turning off the 875 * overlay scaler. 876 */ 877 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 878 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) 879 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) 880 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ 881 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ 882 883 #define RENCLK_GATE_D1 _MMIO(0x6204) 884 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ 885 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ 886 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) 887 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) 888 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) 889 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) 890 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) 891 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) 892 # define MAG_CLOCK_GATE_DISABLE (1 << 5) 893 /* This bit must be unset on 855,865 */ 894 # define MECI_CLOCK_GATE_DISABLE (1 << 4) 895 # define DCMP_CLOCK_GATE_DISABLE (1 << 3) 896 # define MEC_CLOCK_GATE_DISABLE (1 << 2) 897 # define MECO_CLOCK_GATE_DISABLE (1 << 1) 898 /* This bit must be set on 855,865. */ 899 # define SV_CLOCK_GATE_DISABLE (1 << 0) 900 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) 901 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) 902 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) 903 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) 904 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) 905 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) 906 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) 907 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) 908 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) 909 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) 910 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) 911 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) 912 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) 913 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) 914 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) 915 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) 916 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) 917 918 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) 919 /* This bit must always be set on 965G/965GM */ 920 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) 921 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) 922 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) 923 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) 924 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) 925 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) 926 /* This bit must always be set on 965G */ 927 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) 928 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) 929 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) 930 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) 931 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) 932 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) 933 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) 934 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) 935 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) 936 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) 937 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) 938 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) 939 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) 940 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) 941 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) 942 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) 943 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) 944 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) 945 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) 946 947 #define RENCLK_GATE_D2 _MMIO(0x6208) 948 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) 949 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) 950 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) 951 952 #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */ 953 #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4) 954 955 #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */ 956 #define DEUC _MMIO(0x6214) /* CRL only */ 957 958 #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500) 959 #define FW_CSPWRDWNEN (1 << 15) 960 961 #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504) 962 963 #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508) 964 #define CDCLK_FREQ_SHIFT 4 965 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT) 966 #define CZCLK_FREQ_MASK 0xf 967 968 #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C) 969 #define PFI_CREDIT_63 (9 << 28) /* chv only */ 970 #define PFI_CREDIT_31 (8 << 28) /* chv only */ 971 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */ 972 #define PFI_CREDIT_RESEND (1 << 27) 973 #define VGA_FAST_MODE_DISABLE (1 << 14) 974 975 #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510) 976 977 #define PEG_BAND_GAP_DATA _MMIO(0x14d68) 978 979 #define BXT_RP_STATE_CAP _MMIO(0x138170) 980 #define GEN9_RP_STATE_LIMITS _MMIO(0x138148) 981 982 #define MTL_RP_STATE_CAP _MMIO(0x138000) 983 #define MTL_MEDIAP_STATE_CAP _MMIO(0x138020) 984 #define MTL_RP0_CAP_MASK REG_GENMASK(8, 0) 985 #define MTL_RPN_CAP_MASK REG_GENMASK(24, 16) 986 987 #define MTL_GT_RPE_FREQUENCY _MMIO(0x13800c) 988 #define MTL_MPE_FREQUENCY _MMIO(0x13802c) 989 #define MTL_RPE_MASK REG_GENMASK(8, 0) 990 991 #define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8) 992 #define GT0_PERF_LIMIT_REASONS_MASK 0xde3 993 #define PROCHOT_MASK REG_BIT(0) 994 #define THERMAL_LIMIT_MASK REG_BIT(1) 995 #define RATL_MASK REG_BIT(5) 996 #define VR_THERMALERT_MASK REG_BIT(6) 997 #define VR_TDC_MASK REG_BIT(7) 998 #define POWER_LIMIT_4_MASK REG_BIT(8) 999 #define POWER_LIMIT_1_MASK REG_BIT(10) 1000 #define POWER_LIMIT_2_MASK REG_BIT(11) 1001 #define GT0_PERF_LIMIT_REASONS_LOG_MASK REG_GENMASK(31, 16) 1002 #define MTL_MEDIA_PERF_LIMIT_REASONS _MMIO(0x138030) 1003 1004 #define CHV_CLK_CTL1 _MMIO(0x101100) 1005 #define VLV_CLK_CTL2 _MMIO(0x101104) 1006 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28 1007 1008 /* 1009 * Overlay regs 1010 */ 1011 1012 #define OVADD _MMIO(0x30000) 1013 #define DOVSTA _MMIO(0x30008) 1014 #define OC_BUF (0x3 << 20) 1015 #define OGAMC5 _MMIO(0x30010) 1016 #define OGAMC4 _MMIO(0x30014) 1017 #define OGAMC3 _MMIO(0x30018) 1018 #define OGAMC2 _MMIO(0x3001c) 1019 #define OGAMC1 _MMIO(0x30020) 1020 #define OGAMC0 _MMIO(0x30024) 1021 1022 /* 1023 * GEN9 clock gating regs 1024 */ 1025 #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530) 1026 #define DARBF_GATING_DIS REG_BIT(27) 1027 #define MTL_PIPEDMC_GATING_DIS_A REG_BIT(15) 1028 #define MTL_PIPEDMC_GATING_DIS_B REG_BIT(14) 1029 #define PWM2_GATING_DIS REG_BIT(14) 1030 #define PWM1_GATING_DIS REG_BIT(13) 1031 1032 #define GEN9_CLKGATE_DIS_3 _MMIO(0x46538) 1033 #define TGL_VRH_GATING_DIS REG_BIT(31) 1034 #define DPT_GATING_DIS REG_BIT(22) 1035 1036 #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C) 1037 #define BXT_GMBUS_GATING_DIS (1 << 14) 1038 1039 #define GEN9_CLKGATE_DIS_5 _MMIO(0x46540) 1040 #define DPCE_GATING_DIS REG_BIT(17) 1041 1042 #define _CLKGATE_DIS_PSL_A 0x46520 1043 #define _CLKGATE_DIS_PSL_B 0x46524 1044 #define _CLKGATE_DIS_PSL_C 0x46528 1045 #define DUPS1_GATING_DIS (1 << 15) 1046 #define DUPS2_GATING_DIS (1 << 19) 1047 #define DUPS3_GATING_DIS (1 << 23) 1048 #define CURSOR_GATING_DIS REG_BIT(28) 1049 #define DPF_GATING_DIS (1 << 10) 1050 #define DPF_RAM_GATING_DIS (1 << 9) 1051 #define DPFR_GATING_DIS (1 << 8) 1052 1053 #define CLKGATE_DIS_PSL(pipe) \ 1054 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B) 1055 1056 #define _CLKGATE_DIS_PSL_EXT_A 0x4654C 1057 #define _CLKGATE_DIS_PSL_EXT_B 0x46550 1058 #define PIPEDMC_GATING_DIS REG_BIT(12) 1059 1060 #define CLKGATE_DIS_PSL_EXT(pipe) \ 1061 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_EXT_A, _CLKGATE_DIS_PSL_EXT_B) 1062 1063 /* DDI Buffer Control */ 1064 #define _DDI_CLK_VALFREQ_A 0x64030 1065 #define _DDI_CLK_VALFREQ_B 0x64130 1066 #define DDI_CLK_VALFREQ(port) _MMIO_PORT(port, _DDI_CLK_VALFREQ_A, _DDI_CLK_VALFREQ_B) 1067 1068 /* 1069 * Display engine regs 1070 */ 1071 1072 /* Pipe/transcoder A timing regs */ 1073 #define _TRANS_HTOTAL_A 0x60000 1074 #define HTOTAL_MASK REG_GENMASK(31, 16) 1075 #define HTOTAL(htotal) REG_FIELD_PREP(HTOTAL_MASK, (htotal)) 1076 #define HACTIVE_MASK REG_GENMASK(15, 0) 1077 #define HACTIVE(hdisplay) REG_FIELD_PREP(HACTIVE_MASK, (hdisplay)) 1078 #define _TRANS_HBLANK_A 0x60004 1079 #define HBLANK_END_MASK REG_GENMASK(31, 16) 1080 #define HBLANK_END(hblank_end) REG_FIELD_PREP(HBLANK_END_MASK, (hblank_end)) 1081 #define HBLANK_START_MASK REG_GENMASK(15, 0) 1082 #define HBLANK_START(hblank_start) REG_FIELD_PREP(HBLANK_START_MASK, (hblank_start)) 1083 #define _TRANS_HSYNC_A 0x60008 1084 #define HSYNC_END_MASK REG_GENMASK(31, 16) 1085 #define HSYNC_END(hsync_end) REG_FIELD_PREP(HSYNC_END_MASK, (hsync_end)) 1086 #define HSYNC_START_MASK REG_GENMASK(15, 0) 1087 #define HSYNC_START(hsync_start) REG_FIELD_PREP(HSYNC_START_MASK, (hsync_start)) 1088 #define _TRANS_VTOTAL_A 0x6000c 1089 #define VTOTAL_MASK REG_GENMASK(31, 16) 1090 #define VTOTAL(vtotal) REG_FIELD_PREP(VTOTAL_MASK, (vtotal)) 1091 #define VACTIVE_MASK REG_GENMASK(15, 0) 1092 #define VACTIVE(vdisplay) REG_FIELD_PREP(VACTIVE_MASK, (vdisplay)) 1093 #define _TRANS_VBLANK_A 0x60010 1094 #define VBLANK_END_MASK REG_GENMASK(31, 16) 1095 #define VBLANK_END(vblank_end) REG_FIELD_PREP(VBLANK_END_MASK, (vblank_end)) 1096 #define VBLANK_START_MASK REG_GENMASK(15, 0) 1097 #define VBLANK_START(vblank_start) REG_FIELD_PREP(VBLANK_START_MASK, (vblank_start)) 1098 #define _TRANS_VSYNC_A 0x60014 1099 #define VSYNC_END_MASK REG_GENMASK(31, 16) 1100 #define VSYNC_END(vsync_end) REG_FIELD_PREP(VSYNC_END_MASK, (vsync_end)) 1101 #define VSYNC_START_MASK REG_GENMASK(15, 0) 1102 #define VSYNC_START(vsync_start) REG_FIELD_PREP(VSYNC_START_MASK, (vsync_start)) 1103 #define _TRANS_EXITLINE_A 0x60018 1104 #define _PIPEASRC 0x6001c 1105 #define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16) 1106 #define PIPESRC_WIDTH(w) REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w)) 1107 #define PIPESRC_HEIGHT_MASK REG_GENMASK(15, 0) 1108 #define PIPESRC_HEIGHT(h) REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h)) 1109 #define _BCLRPAT_A 0x60020 1110 #define _TRANS_VSYNCSHIFT_A 0x60028 1111 #define _TRANS_MULT_A 0x6002c 1112 1113 /* Pipe/transcoder B timing regs */ 1114 #define _TRANS_HTOTAL_B 0x61000 1115 #define _TRANS_HBLANK_B 0x61004 1116 #define _TRANS_HSYNC_B 0x61008 1117 #define _TRANS_VTOTAL_B 0x6100c 1118 #define _TRANS_VBLANK_B 0x61010 1119 #define _TRANS_VSYNC_B 0x61014 1120 #define _PIPEBSRC 0x6101c 1121 #define _BCLRPAT_B 0x61020 1122 #define _TRANS_VSYNCSHIFT_B 0x61028 1123 #define _TRANS_MULT_B 0x6102c 1124 1125 /* DSI 0 timing regs */ 1126 #define _TRANS_HTOTAL_DSI0 0x6b000 1127 #define _TRANS_HSYNC_DSI0 0x6b008 1128 #define _TRANS_VTOTAL_DSI0 0x6b00c 1129 #define _TRANS_VSYNC_DSI0 0x6b014 1130 #define _TRANS_VSYNCSHIFT_DSI0 0x6b028 1131 1132 /* DSI 1 timing regs */ 1133 #define _TRANS_HTOTAL_DSI1 0x6b800 1134 #define _TRANS_HSYNC_DSI1 0x6b808 1135 #define _TRANS_VTOTAL_DSI1 0x6b80c 1136 #define _TRANS_VSYNC_DSI1 0x6b814 1137 #define _TRANS_VSYNCSHIFT_DSI1 0x6b828 1138 1139 #define TRANS_HTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HTOTAL_A) 1140 #define TRANS_HBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A) 1141 #define TRANS_HSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A) 1142 #define TRANS_VTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A) 1143 #define TRANS_VBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A) 1144 #define TRANS_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A) 1145 #define BCLRPAT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A) 1146 #define TRANS_VSYNCSHIFT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A) 1147 #define PIPESRC(dev_priv, pipe) _MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC) 1148 #define TRANS_MULT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A) 1149 1150 /* VGA port control */ 1151 #define ADPA _MMIO(0x61100) 1152 #define PCH_ADPA _MMIO(0xe1100) 1153 #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100) 1154 1155 #define ADPA_DAC_ENABLE (1 << 31) 1156 #define ADPA_DAC_DISABLE 0 1157 #define ADPA_PIPE_SEL_SHIFT 30 1158 #define ADPA_PIPE_SEL_MASK (1 << 30) 1159 #define ADPA_PIPE_SEL(pipe) ((pipe) << 30) 1160 #define ADPA_PIPE_SEL_SHIFT_CPT 29 1161 #define ADPA_PIPE_SEL_MASK_CPT (3 << 29) 1162 #define ADPA_PIPE_SEL_CPT(pipe) ((pipe) << 29) 1163 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ 1164 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0 << 24) 1165 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3 << 24) 1166 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24) 1167 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2 << 24) 1168 #define ADPA_CRT_HOTPLUG_ENABLE (1 << 23) 1169 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0 << 22) 1170 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1 << 22) 1171 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0 << 21) 1172 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1 << 21) 1173 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0 << 20) 1174 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1 << 20) 1175 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0 << 18) 1176 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1 << 18) 1177 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2 << 18) 1178 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3 << 18) 1179 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0 << 17) 1180 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1 << 17) 1181 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16) 1182 #define ADPA_USE_VGA_HVPOLARITY (1 << 15) 1183 #define ADPA_SETS_HVPOLARITY 0 1184 #define ADPA_VSYNC_CNTL_DISABLE (1 << 10) 1185 #define ADPA_VSYNC_CNTL_ENABLE 0 1186 #define ADPA_HSYNC_CNTL_DISABLE (1 << 11) 1187 #define ADPA_HSYNC_CNTL_ENABLE 0 1188 #define ADPA_VSYNC_ACTIVE_HIGH (1 << 4) 1189 #define ADPA_VSYNC_ACTIVE_LOW 0 1190 #define ADPA_HSYNC_ACTIVE_HIGH (1 << 3) 1191 #define ADPA_HSYNC_ACTIVE_LOW 0 1192 #define ADPA_DPMS_MASK (~(3 << 10)) 1193 #define ADPA_DPMS_ON (0 << 10) 1194 #define ADPA_DPMS_SUSPEND (1 << 10) 1195 #define ADPA_DPMS_STANDBY (2 << 10) 1196 #define ADPA_DPMS_OFF (3 << 10) 1197 1198 1199 /* Hotplug control (945+ only) */ 1200 #define PORT_HOTPLUG_EN(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110) 1201 #define PORTB_HOTPLUG_INT_EN (1 << 29) 1202 #define PORTC_HOTPLUG_INT_EN (1 << 28) 1203 #define PORTD_HOTPLUG_INT_EN (1 << 27) 1204 #define SDVOB_HOTPLUG_INT_EN (1 << 26) 1205 #define SDVOC_HOTPLUG_INT_EN (1 << 25) 1206 #define TV_HOTPLUG_INT_EN (1 << 18) 1207 #define CRT_HOTPLUG_INT_EN (1 << 9) 1208 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \ 1209 PORTC_HOTPLUG_INT_EN | \ 1210 PORTD_HOTPLUG_INT_EN | \ 1211 SDVOC_HOTPLUG_INT_EN | \ 1212 SDVOB_HOTPLUG_INT_EN | \ 1213 CRT_HOTPLUG_INT_EN) 1214 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 1215 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 1216 /* must use period 64 on GM45 according to docs */ 1217 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 1218 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 1219 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 1220 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 1221 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 1222 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 1223 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 1224 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 1225 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 1226 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 1227 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 1228 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 1229 1230 #define PORT_HOTPLUG_STAT(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114) 1231 /* HDMI/DP bits are g4x+ */ 1232 #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27) 1233 #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) 1234 #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29) 1235 #define PORTD_HOTPLUG_INT_STATUS (3 << 21) 1236 #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21) 1237 #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21) 1238 #define PORTC_HOTPLUG_INT_STATUS (3 << 19) 1239 #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19) 1240 #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19) 1241 #define PORTB_HOTPLUG_INT_STATUS (3 << 17) 1242 #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17) 1243 #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17) 1244 /* CRT/TV common between gen3+ */ 1245 #define CRT_HOTPLUG_INT_STATUS (1 << 11) 1246 #define TV_HOTPLUG_INT_STATUS (1 << 10) 1247 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 1248 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 1249 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 1250 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 1251 #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6) 1252 #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5) 1253 #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4) 1254 #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4) 1255 1256 /* SDVO is different across gen3/4 */ 1257 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) 1258 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) 1259 /* 1260 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, 1261 * since reality corrobates that they're the same as on gen3. But keep these 1262 * bits here (and the comment!) to help any other lost wanderers back onto the 1263 * right tracks. 1264 */ 1265 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) 1266 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) 1267 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) 1268 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) 1269 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \ 1270 SDVOB_HOTPLUG_INT_STATUS_G4X | \ 1271 SDVOC_HOTPLUG_INT_STATUS_G4X | \ 1272 PORTB_HOTPLUG_INT_STATUS | \ 1273 PORTC_HOTPLUG_INT_STATUS | \ 1274 PORTD_HOTPLUG_INT_STATUS) 1275 1276 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \ 1277 SDVOB_HOTPLUG_INT_STATUS_I915 | \ 1278 SDVOC_HOTPLUG_INT_STATUS_I915 | \ 1279 PORTB_HOTPLUG_INT_STATUS | \ 1280 PORTC_HOTPLUG_INT_STATUS | \ 1281 PORTD_HOTPLUG_INT_STATUS) 1282 1283 /* SDVO and HDMI port control. 1284 * The same register may be used for SDVO or HDMI */ 1285 #define _GEN3_SDVOB 0x61140 1286 #define _GEN3_SDVOC 0x61160 1287 #define GEN3_SDVOB _MMIO(_GEN3_SDVOB) 1288 #define GEN3_SDVOC _MMIO(_GEN3_SDVOC) 1289 #define GEN4_HDMIB GEN3_SDVOB 1290 #define GEN4_HDMIC GEN3_SDVOC 1291 #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140) 1292 #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160) 1293 #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C) 1294 #define PCH_SDVOB _MMIO(0xe1140) 1295 #define PCH_HDMIB PCH_SDVOB 1296 #define PCH_HDMIC _MMIO(0xe1150) 1297 #define PCH_HDMID _MMIO(0xe1160) 1298 1299 #define PORT_DFT_I9XX _MMIO(0x61150) 1300 #define DC_BALANCE_RESET (1 << 25) 1301 #define PORT_DFT2_G4X(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154) 1302 #define DC_BALANCE_RESET_VLV (1 << 31) 1303 #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0)) 1304 #define PIPE_C_SCRAMBLE_RESET REG_BIT(14) /* chv */ 1305 #define PIPE_B_SCRAMBLE_RESET REG_BIT(1) 1306 #define PIPE_A_SCRAMBLE_RESET REG_BIT(0) 1307 1308 /* Gen 3 SDVO bits: */ 1309 #define SDVO_ENABLE (1 << 31) 1310 #define SDVO_PIPE_SEL_SHIFT 30 1311 #define SDVO_PIPE_SEL_MASK (1 << 30) 1312 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30) 1313 #define SDVO_STALL_SELECT (1 << 29) 1314 #define SDVO_INTERRUPT_ENABLE (1 << 26) 1315 /* 1316 * 915G/GM SDVO pixel multiplier. 1317 * Programmed value is multiplier - 1, up to 5x. 1318 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 1319 */ 1320 #define SDVO_PORT_MULTIPLY_MASK (7 << 23) 1321 #define SDVO_PORT_MULTIPLY_SHIFT 23 1322 #define SDVO_PHASE_SELECT_MASK (15 << 19) 1323 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 1324 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 1325 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */ 1326 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */ 1327 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */ 1328 #define SDVO_DETECTED (1 << 2) 1329 /* Bits to be preserved when writing */ 1330 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \ 1331 SDVO_INTERRUPT_ENABLE) 1332 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE) 1333 1334 /* Gen 4 SDVO/HDMI bits: */ 1335 #define SDVO_COLOR_FORMAT_8bpc (0 << 26) 1336 #define SDVO_COLOR_FORMAT_MASK (7 << 26) 1337 #define SDVO_ENCODING_SDVO (0 << 10) 1338 #define SDVO_ENCODING_HDMI (2 << 10) 1339 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */ 1340 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */ 1341 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */ 1342 #define HDMI_AUDIO_ENABLE (1 << 6) /* HDMI only */ 1343 /* VSYNC/HSYNC bits new with 965, default is to be set */ 1344 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) 1345 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) 1346 1347 /* Gen 5 (IBX) SDVO/HDMI bits: */ 1348 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */ 1349 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */ 1350 1351 /* Gen 6 (CPT) SDVO/HDMI bits: */ 1352 #define SDVO_PIPE_SEL_SHIFT_CPT 29 1353 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29) 1354 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29) 1355 1356 /* CHV SDVO/HDMI bits: */ 1357 #define SDVO_PIPE_SEL_SHIFT_CHV 24 1358 #define SDVO_PIPE_SEL_MASK_CHV (3 << 24) 1359 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24) 1360 1361 /* Video Data Island Packet control */ 1362 #define VIDEO_DIP_DATA _MMIO(0x61178) 1363 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC 1364 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte 1365 * of the infoframe structure specified by CEA-861. */ 1366 #define VIDEO_DIP_DATA_SIZE 32 1367 #define VIDEO_DIP_ASYNC_DATA_SIZE 36 1368 #define VIDEO_DIP_GMP_DATA_SIZE 36 1369 #define VIDEO_DIP_VSC_DATA_SIZE 36 1370 #define VIDEO_DIP_PPS_DATA_SIZE 132 1371 #define VIDEO_DIP_CTL _MMIO(0x61170) 1372 /* Pre HSW: */ 1373 #define VIDEO_DIP_ENABLE (1 << 31) 1374 #define VIDEO_DIP_PORT(port) ((port) << 29) 1375 #define VIDEO_DIP_PORT_MASK (3 << 29) 1376 #define VIDEO_DIP_ENABLE_GCP (1 << 25) /* ilk+ */ 1377 #define VIDEO_DIP_ENABLE_AVI (1 << 21) 1378 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) 1379 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) /* ilk+ */ 1380 #define VIDEO_DIP_ENABLE_SPD (8 << 21) 1381 #define VIDEO_DIP_SELECT_AVI (0 << 19) 1382 #define VIDEO_DIP_SELECT_VENDOR (1 << 19) 1383 #define VIDEO_DIP_SELECT_GAMUT (2 << 19) 1384 #define VIDEO_DIP_SELECT_SPD (3 << 19) 1385 #define VIDEO_DIP_SELECT_MASK (3 << 19) 1386 #define VIDEO_DIP_FREQ_ONCE (0 << 16) 1387 #define VIDEO_DIP_FREQ_VSYNC (1 << 16) 1388 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) 1389 #define VIDEO_DIP_FREQ_MASK (3 << 16) 1390 /* HSW and later: */ 1391 #define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28) 1392 #define PSR_VSC_BIT_7_SET (1 << 27) 1393 #define VSC_SELECT_MASK (0x3 << 25) 1394 #define VSC_SELECT_SHIFT 25 1395 #define VSC_DIP_HW_HEA_DATA (0 << 25) 1396 #define VSC_DIP_HW_HEA_SW_DATA (1 << 25) 1397 #define VSC_DIP_HW_DATA_SW_HEA (2 << 25) 1398 #define VSC_DIP_SW_HEA_DATA (3 << 25) 1399 #define VDIP_ENABLE_PPS (1 << 24) 1400 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) 1401 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) 1402 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) 1403 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) 1404 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) 1405 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) 1406 /* ADL and later: */ 1407 #define VIDEO_DIP_ENABLE_AS_ADL REG_BIT(23) 1408 1409 /* Panel fitting */ 1410 #define PFIT_CONTROL(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230) 1411 #define PFIT_ENABLE REG_BIT(31) 1412 #define PFIT_PIPE_MASK REG_GENMASK(30, 29) /* 965+ */ 1413 #define PFIT_PIPE(pipe) REG_FIELD_PREP(PFIT_PIPE_MASK, (pipe)) 1414 #define PFIT_SCALING_MASK REG_GENMASK(28, 26) /* 965+ */ 1415 #define PFIT_SCALING_AUTO REG_FIELD_PREP(PFIT_SCALING_MASK, 0) 1416 #define PFIT_SCALING_PROGRAMMED REG_FIELD_PREP(PFIT_SCALING_MASK, 1) 1417 #define PFIT_SCALING_PILLAR REG_FIELD_PREP(PFIT_SCALING_MASK, 2) 1418 #define PFIT_SCALING_LETTER REG_FIELD_PREP(PFIT_SCALING_MASK, 3) 1419 #define PFIT_FILTER_MASK REG_GENMASK(25, 24) /* 965+ */ 1420 #define PFIT_FILTER_FUZZY REG_FIELD_PREP(PFIT_FILTER_MASK, 0) 1421 #define PFIT_FILTER_CRISP REG_FIELD_PREP(PFIT_FILTER_MASK, 1) 1422 #define PFIT_FILTER_MEDIAN REG_FIELD_PREP(PFIT_FILTER_MASK, 2) 1423 #define PFIT_VERT_INTERP_MASK REG_GENMASK(11, 10) /* pre-965 */ 1424 #define PFIT_VERT_INTERP_BILINEAR REG_FIELD_PREP(PFIT_VERT_INTERP_MASK, 1) 1425 #define PFIT_VERT_AUTO_SCALE REG_BIT(9) /* pre-965 */ 1426 #define PFIT_HORIZ_INTERP_MASK REG_GENMASK(7, 6) /* pre-965 */ 1427 #define PFIT_HORIZ_INTERP_BILINEAR REG_FIELD_PREP(PFIT_HORIZ_INTERP_MASK, 1) 1428 #define PFIT_HORIZ_AUTO_SCALE REG_BIT(5) /* pre-965 */ 1429 #define PFIT_PANEL_8TO6_DITHER_ENABLE REG_BIT(3) /* pre-965 */ 1430 1431 #define PFIT_PGM_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234) 1432 #define PFIT_VERT_SCALE_MASK REG_GENMASK(31, 20) /* pre-965 */ 1433 #define PFIT_VERT_SCALE(x) REG_FIELD_PREP(PFIT_VERT_SCALE_MASK, (x)) 1434 #define PFIT_HORIZ_SCALE_MASK REG_GENMASK(15, 4) /* pre-965 */ 1435 #define PFIT_HORIZ_SCALE(x) REG_FIELD_PREP(PFIT_HORIZ_SCALE_MASK, (x)) 1436 #define PFIT_VERT_SCALE_MASK_965 REG_GENMASK(28, 16) /* 965+ */ 1437 #define PFIT_HORIZ_SCALE_MASK_965 REG_GENMASK(12, 0) /* 965+ */ 1438 1439 #define PFIT_AUTO_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238) 1440 1441 #define PCH_GTC_CTL _MMIO(0xe7000) 1442 #define PCH_GTC_ENABLE (1 << 31) 1443 1444 /* Display Port */ 1445 #define DP_A _MMIO(0x64000) /* eDP */ 1446 #define DP_B _MMIO(0x64100) 1447 #define DP_C _MMIO(0x64200) 1448 #define DP_D _MMIO(0x64300) 1449 1450 #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100) 1451 #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200) 1452 #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300) 1453 1454 #define DP_PORT_EN (1 << 31) 1455 #define DP_PIPE_SEL_SHIFT 30 1456 #define DP_PIPE_SEL_MASK (1 << 30) 1457 #define DP_PIPE_SEL(pipe) ((pipe) << 30) 1458 #define DP_PIPE_SEL_SHIFT_IVB 29 1459 #define DP_PIPE_SEL_MASK_IVB (3 << 29) 1460 #define DP_PIPE_SEL_IVB(pipe) ((pipe) << 29) 1461 #define DP_PIPE_SEL_SHIFT_CHV 16 1462 #define DP_PIPE_SEL_MASK_CHV (3 << 16) 1463 #define DP_PIPE_SEL_CHV(pipe) ((pipe) << 16) 1464 1465 /* Link training mode - select a suitable mode for each stage */ 1466 #define DP_LINK_TRAIN_PAT_1 (0 << 28) 1467 #define DP_LINK_TRAIN_PAT_2 (1 << 28) 1468 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) 1469 #define DP_LINK_TRAIN_OFF (3 << 28) 1470 #define DP_LINK_TRAIN_MASK (3 << 28) 1471 #define DP_LINK_TRAIN_SHIFT 28 1472 1473 /* CPT Link training mode */ 1474 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) 1475 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) 1476 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) 1477 #define DP_LINK_TRAIN_OFF_CPT (3 << 8) 1478 #define DP_LINK_TRAIN_MASK_CPT (7 << 8) 1479 #define DP_LINK_TRAIN_SHIFT_CPT 8 1480 1481 /* Signal voltages. These are mostly controlled by the other end */ 1482 #define DP_VOLTAGE_0_4 (0 << 25) 1483 #define DP_VOLTAGE_0_6 (1 << 25) 1484 #define DP_VOLTAGE_0_8 (2 << 25) 1485 #define DP_VOLTAGE_1_2 (3 << 25) 1486 #define DP_VOLTAGE_MASK (7 << 25) 1487 #define DP_VOLTAGE_SHIFT 25 1488 1489 /* Signal pre-emphasis levels, like voltages, the other end tells us what 1490 * they want 1491 */ 1492 #define DP_PRE_EMPHASIS_0 (0 << 22) 1493 #define DP_PRE_EMPHASIS_3_5 (1 << 22) 1494 #define DP_PRE_EMPHASIS_6 (2 << 22) 1495 #define DP_PRE_EMPHASIS_9_5 (3 << 22) 1496 #define DP_PRE_EMPHASIS_MASK (7 << 22) 1497 #define DP_PRE_EMPHASIS_SHIFT 22 1498 1499 /* How many wires to use. I guess 3 was too hard */ 1500 #define DP_PORT_WIDTH(width) (((width) - 1) << 19) 1501 #define DP_PORT_WIDTH_MASK (7 << 19) 1502 #define DP_PORT_WIDTH_SHIFT 19 1503 1504 /* Mystic DPCD version 1.1 special mode */ 1505 #define DP_ENHANCED_FRAMING (1 << 18) 1506 1507 /* eDP */ 1508 #define DP_PLL_FREQ_270MHZ (0 << 16) 1509 #define DP_PLL_FREQ_162MHZ (1 << 16) 1510 #define DP_PLL_FREQ_MASK (3 << 16) 1511 1512 /* locked once port is enabled */ 1513 #define DP_PORT_REVERSAL (1 << 15) 1514 1515 /* eDP */ 1516 #define DP_PLL_ENABLE (1 << 14) 1517 1518 /* sends the clock on lane 15 of the PEG for debug */ 1519 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 1520 1521 #define DP_SCRAMBLING_DISABLE (1 << 12) 1522 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) 1523 1524 /* limit RGB values to avoid confusing TVs */ 1525 #define DP_COLOR_RANGE_16_235 (1 << 8) 1526 1527 /* Turn on the audio link */ 1528 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) 1529 1530 /* vs and hs sync polarity */ 1531 #define DP_SYNC_VS_HIGH (1 << 4) 1532 #define DP_SYNC_HS_HIGH (1 << 3) 1533 1534 /* A fantasy */ 1535 #define DP_DETECTED (1 << 2) 1536 1537 /* 1538 * Computing GMCH M and N values for the Display Port link 1539 * 1540 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes 1541 * 1542 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) 1543 * 1544 * The GMCH value is used internally 1545 * 1546 * bytes_per_pixel is the number of bytes coming out of the plane, 1547 * which is after the LUTs, so we want the bytes for our color format. 1548 * For our current usage, this is always 3, one byte for R, G and B. 1549 */ 1550 #define _PIPEA_DATA_M_G4X 0x70050 1551 #define _PIPEB_DATA_M_G4X 0x71050 1552 1553 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 1554 #define TU_SIZE_MASK REG_GENMASK(30, 25) 1555 #define TU_SIZE(x) REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */ 1556 1557 #define DATA_LINK_M_N_MASK REG_GENMASK(23, 0) 1558 #define DATA_LINK_N_MAX (0x800000) 1559 1560 #define _PIPEA_DATA_N_G4X 0x70054 1561 #define _PIPEB_DATA_N_G4X 0x71054 1562 1563 /* 1564 * Computing Link M and N values for the Display Port link 1565 * 1566 * Link M / N = pixel_clock / ls_clk 1567 * 1568 * (the DP spec calls pixel_clock the 'strm_clk') 1569 * 1570 * The Link value is transmitted in the Main Stream 1571 * Attributes and VB-ID. 1572 */ 1573 1574 #define _PIPEA_LINK_M_G4X 0x70060 1575 #define _PIPEB_LINK_M_G4X 0x71060 1576 #define _PIPEA_LINK_N_G4X 0x70064 1577 #define _PIPEB_LINK_N_G4X 0x71064 1578 1579 #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X) 1580 #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X) 1581 #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X) 1582 #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X) 1583 1584 /* Pipe A */ 1585 #define _PIPEADSL 0x70000 1586 #define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */ 1587 #define PIPEDSL_LINE_MASK REG_GENMASK(19, 0) 1588 #define _TRANSACONF 0x70008 1589 #define TRANSCONF_ENABLE REG_BIT(31) 1590 #define TRANSCONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */ 1591 #define TRANSCONF_STATE_ENABLE REG_BIT(30) /* i965+ */ 1592 #define TRANSCONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv & pipe A only */ 1593 #define TRANSCONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */ 1594 #define TRANSCONF_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANSCONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */ 1595 #define TRANSCONF_PIPE_LOCKED REG_BIT(25) 1596 #define TRANSCONF_FORCE_BORDER REG_BIT(25) 1597 #define TRANSCONF_GAMMA_MODE_MASK_I9XX REG_BIT(24) /* gmch */ 1598 #define TRANSCONF_GAMMA_MODE_MASK_ILK REG_GENMASK(25, 24) /* ilk-ivb */ 1599 #define TRANSCONF_GAMMA_MODE_8BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 0) 1600 #define TRANSCONF_GAMMA_MODE_10BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 1) 1601 #define TRANSCONF_GAMMA_MODE_12BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */ 1602 #define TRANSCONF_GAMMA_MODE_SPLIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */ 1603 #define TRANSCONF_GAMMA_MODE(x) REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */ 1604 #define TRANSCONF_INTERLACE_MASK REG_GENMASK(23, 21) /* gen3+ */ 1605 #define TRANSCONF_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 0) 1606 #define TRANSCONF_INTERLACE_W_SYNC_SHIFT_PANEL REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 4) /* gen4 only */ 1607 #define TRANSCONF_INTERLACE_W_SYNC_SHIFT REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 5) /* gen4 only */ 1608 #define TRANSCONF_INTERLACE_W_FIELD_INDICATION REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 6) 1609 #define TRANSCONF_INTERLACE_FIELD_0_ONLY REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 7) /* gen3 only */ 1610 /* 1611 * ilk+: PF/D=progressive fetch/display, IF/D=interlaced fetch/display, 1612 * DBL=power saving pixel doubling, PF-ID* requires panel fitter 1613 */ 1614 #define TRANSCONF_INTERLACE_MASK_ILK REG_GENMASK(23, 21) /* ilk+ */ 1615 #define TRANSCONF_INTERLACE_MASK_HSW REG_GENMASK(22, 21) /* hsw+ */ 1616 #define TRANSCONF_INTERLACE_PF_PD_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 0) 1617 #define TRANSCONF_INTERLACE_PF_ID_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 1) 1618 #define TRANSCONF_INTERLACE_IF_ID_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 3) 1619 #define TRANSCONF_INTERLACE_IF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */ 1620 #define TRANSCONF_INTERLACE_PF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */ 1621 #define TRANSCONF_REFRESH_RATE_ALT_ILK REG_BIT(20) 1622 #define TRANSCONF_MSA_TIMING_DELAY_MASK REG_GENMASK(19, 18) /* ilk/snb/ivb */ 1623 #define TRANSCONF_MSA_TIMING_DELAY(x) REG_FIELD_PREP(TRANSCONF_MSA_TIMING_DELAY_MASK, (x)) 1624 #define TRANSCONF_CXSR_DOWNCLOCK REG_BIT(16) 1625 #define TRANSCONF_WGC_ENABLE REG_BIT(15) /* vlv/chv only */ 1626 #define TRANSCONF_REFRESH_RATE_ALT_VLV REG_BIT(14) 1627 #define TRANSCONF_COLOR_RANGE_SELECT REG_BIT(13) 1628 #define TRANSCONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */ 1629 #define TRANSCONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */ 1630 #define TRANSCONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */ 1631 #define TRANSCONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */ 1632 #define TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11) /* hsw only */ 1633 #define TRANSCONF_BPC_MASK REG_GENMASK(7, 5) /* ctg-ivb */ 1634 #define TRANSCONF_BPC_8 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 0) 1635 #define TRANSCONF_BPC_10 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 1) 1636 #define TRANSCONF_BPC_6 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 2) 1637 #define TRANSCONF_BPC_12 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 3) 1638 #define TRANSCONF_DITHER_EN REG_BIT(4) 1639 #define TRANSCONF_DITHER_TYPE_MASK REG_GENMASK(3, 2) 1640 #define TRANSCONF_DITHER_TYPE_SP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 0) 1641 #define TRANSCONF_DITHER_TYPE_ST1 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 1) 1642 #define TRANSCONF_DITHER_TYPE_ST2 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 2) 1643 #define TRANSCONF_DITHER_TYPE_TEMP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 3) 1644 #define TRANSCONF_PIXEL_COUNT_SCALING_MASK REG_GENMASK(1, 0) 1645 #define TRANSCONF_PIXEL_COUNT_SCALING_X4 1 1646 1647 #define _PIPEASTAT 0x70024 1648 #define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31) 1649 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30) 1650 #define PIPE_CRC_ERROR_ENABLE (1UL << 29) 1651 #define PIPE_CRC_DONE_ENABLE (1UL << 28) 1652 #define PERF_COUNTER2_INTERRUPT_EN (1UL << 27) 1653 #define PIPE_GMBUS_EVENT_ENABLE (1UL << 27) 1654 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26) 1655 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26) 1656 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25) 1657 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24) 1658 #define PIPE_DPST_EVENT_ENABLE (1UL << 23) 1659 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22) 1660 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22) 1661 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21) 1662 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20) 1663 #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL << 19) 1664 #define PERF_COUNTER_INTERRUPT_EN (1UL << 19) 1665 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */ 1666 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) /* 965 or later */ 1667 #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL << 17) 1668 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17) 1669 #define PIPEA_HBLANK_INT_EN_VLV (1UL << 16) 1670 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16) 1671 #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL << 15) 1672 #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL << 14) 1673 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13) 1674 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12) 1675 #define PERF_COUNTER2_INTERRUPT_STATUS (1UL << 11) 1676 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11) 1677 #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL << 10) 1678 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10) 1679 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9) 1680 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8) 1681 #define PIPE_DPST_EVENT_STATUS (1UL << 7) 1682 #define PIPE_A_PSR_STATUS_VLV (1UL << 6) 1683 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6) 1684 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5) 1685 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4) 1686 #define PIPE_B_PSR_STATUS_VLV (1UL << 3) 1687 #define PERF_COUNTER_INTERRUPT_STATUS (1UL << 3) 1688 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */ 1689 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) /* 965 or later */ 1690 #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL << 1) 1691 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1) 1692 #define PIPE_HBLANK_INT_STATUS (1UL << 0) 1693 #define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0) 1694 1695 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 1696 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff 1697 1698 #define TRANSCONF(dev_priv, trans) _MMIO_PIPE2(dev_priv, (trans), _TRANSACONF) 1699 #define PIPEDSL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEADSL) 1700 #define PIPEFRAME(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEHIGH) 1701 #define PIPEFRAMEPIXEL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL) 1702 #define PIPESTAT(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT) 1703 1704 #define _PIPE_ARB_CTL_A 0x70028 /* icl+ */ 1705 #define PIPE_ARB_CTL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPE_ARB_CTL_A) 1706 #define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13) 1707 1708 #define _PIPE_MISC_A 0x70030 1709 #define _PIPE_MISC_B 0x71030 1710 #define PIPE_MISC_YUV420_ENABLE REG_BIT(27) /* glk+ */ 1711 #define PIPE_MISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */ 1712 #define PIPE_MISC_HDR_MODE_PRECISION REG_BIT(23) /* icl+ */ 1713 #define PIPE_MISC_PSR_MASK_PRIMARY_FLIP REG_BIT(23) /* bdw */ 1714 #define PIPE_MISC_PSR_MASK_SPRITE_ENABLE REG_BIT(22) /* bdw */ 1715 #define PIPE_MISC_PSR_MASK_PIPE_REG_WRITE REG_BIT(21) /* skl+ */ 1716 #define PIPE_MISC_PSR_MASK_CURSOR_MOVE REG_BIT(21) /* bdw */ 1717 #define PIPE_MISC_PSR_MASK_VBLANK_VSYNC_INT REG_BIT(20) 1718 #define PIPE_MISC_OUTPUT_COLORSPACE_YUV REG_BIT(11) 1719 #define PIPE_MISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */ 1720 /* 1721 * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with 1722 * valid values of: 6, 8, 10 BPC. 1723 * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of: 1724 * 6, 8, 10, 12 BPC. 1725 */ 1726 #define PIPE_MISC_BPC_MASK REG_GENMASK(7, 5) 1727 #define PIPE_MISC_BPC_8 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 0) 1728 #define PIPE_MISC_BPC_10 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 1) 1729 #define PIPE_MISC_BPC_6 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 2) 1730 #define PIPE_MISC_BPC_12_ADLP REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 4) /* adlp+ */ 1731 #define PIPE_MISC_DITHER_ENABLE REG_BIT(4) 1732 #define PIPE_MISC_DITHER_TYPE_MASK REG_GENMASK(3, 2) 1733 #define PIPE_MISC_DITHER_TYPE_SP REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 0) 1734 #define PIPE_MISC_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 1) 1735 #define PIPE_MISC_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 2) 1736 #define PIPE_MISC_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 3) 1737 #define PIPE_MISC(pipe) _MMIO_PIPE(pipe, _PIPE_MISC_A, _PIPE_MISC_B) 1738 1739 #define _PIPE_MISC2_A 0x7002C 1740 #define _PIPE_MISC2_B 0x7102C 1741 #define PIPE_MISC2_BUBBLE_COUNTER_MASK REG_GENMASK(31, 24) 1742 #define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80) 1743 #define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20) 1744 #define PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK REG_GENMASK(2, 0) /* tgl+ */ 1745 #define PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id) REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id)) 1746 #define PIPE_MISC2(pipe) _MMIO_PIPE(pipe, _PIPE_MISC2_A, _PIPE_MISC2_B) 1747 1748 #define _ICL_PIPE_A_STATUS 0x70058 1749 #define ICL_PIPESTATUS(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _ICL_PIPE_A_STATUS) 1750 #define PIPE_STATUS_UNDERRUN REG_BIT(31) 1751 #define PIPE_STATUS_SOFT_UNDERRUN_XELPD REG_BIT(28) 1752 #define PIPE_STATUS_HARD_UNDERRUN_XELPD REG_BIT(27) 1753 #define PIPE_STATUS_PORT_UNDERRUN_XELPD REG_BIT(26) 1754 1755 #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028) 1756 #define PIPEB_LINE_COMPARE_INT_EN REG_BIT(29) 1757 #define PIPEB_HLINE_INT_EN REG_BIT(28) 1758 #define PIPEB_VBLANK_INT_EN REG_BIT(27) 1759 #define SPRITED_FLIP_DONE_INT_EN REG_BIT(26) 1760 #define SPRITEC_FLIP_DONE_INT_EN REG_BIT(25) 1761 #define PLANEB_FLIP_DONE_INT_EN REG_BIT(24) 1762 #define PIPE_PSR_INT_EN REG_BIT(22) 1763 #define PIPEA_LINE_COMPARE_INT_EN REG_BIT(21) 1764 #define PIPEA_HLINE_INT_EN REG_BIT(20) 1765 #define PIPEA_VBLANK_INT_EN REG_BIT(19) 1766 #define SPRITEB_FLIP_DONE_INT_EN REG_BIT(18) 1767 #define SPRITEA_FLIP_DONE_INT_EN REG_BIT(17) 1768 #define PLANEA_FLIPDONE_INT_EN REG_BIT(16) 1769 #define PIPEC_LINE_COMPARE_INT_EN REG_BIT(13) 1770 #define PIPEC_HLINE_INT_EN REG_BIT(12) 1771 #define PIPEC_VBLANK_INT_EN REG_BIT(11) 1772 #define SPRITEF_FLIPDONE_INT_EN REG_BIT(10) 1773 #define SPRITEE_FLIPDONE_INT_EN REG_BIT(9) 1774 #define PLANEC_FLIPDONE_INT_EN REG_BIT(8) 1775 1776 #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ 1777 #define DPINVGTT_EN_MASK_CHV REG_GENMASK(27, 16) 1778 #define DPINVGTT_EN_MASK_VLV REG_GENMASK(23, 16) 1779 #define SPRITEF_INVALID_GTT_INT_EN REG_BIT(27) 1780 #define SPRITEE_INVALID_GTT_INT_EN REG_BIT(26) 1781 #define PLANEC_INVALID_GTT_INT_EN REG_BIT(25) 1782 #define CURSORC_INVALID_GTT_INT_EN REG_BIT(24) 1783 #define CURSORB_INVALID_GTT_INT_EN REG_BIT(23) 1784 #define CURSORA_INVALID_GTT_INT_EN REG_BIT(22) 1785 #define SPRITED_INVALID_GTT_INT_EN REG_BIT(21) 1786 #define SPRITEC_INVALID_GTT_INT_EN REG_BIT(20) 1787 #define PLANEB_INVALID_GTT_INT_EN REG_BIT(19) 1788 #define SPRITEB_INVALID_GTT_INT_EN REG_BIT(18) 1789 #define SPRITEA_INVALID_GTT_INT_EN REG_BIT(17) 1790 #define PLANEA_INVALID_GTT_INT_EN REG_BIT(16) 1791 #define DPINVGTT_STATUS_MASK_CHV REG_GENMASK(11, 0) 1792 #define DPINVGTT_STATUS_MASK_VLV REG_GENMASK(7, 0) 1793 #define SPRITEF_INVALID_GTT_STATUS REG_BIT(11) 1794 #define SPRITEE_INVALID_GTT_STATUS REG_BIT(10) 1795 #define PLANEC_INVALID_GTT_STATUS REG_BIT(9) 1796 #define CURSORC_INVALID_GTT_STATUS REG_BIT(8) 1797 #define CURSORB_INVALID_GTT_STATUS REG_BIT(7) 1798 #define CURSORA_INVALID_GTT_STATUS REG_BIT(6) 1799 #define SPRITED_INVALID_GTT_STATUS REG_BIT(5) 1800 #define SPRITEC_INVALID_GTT_STATUS REG_BIT(4) 1801 #define PLANEB_INVALID_GTT_STATUS REG_BIT(3) 1802 #define SPRITEB_INVALID_GTT_STATUS REG_BIT(2) 1803 #define SPRITEA_INVALID_GTT_STATUS REG_BIT(1) 1804 #define PLANEA_INVALID_GTT_STATUS REG_BIT(0) 1805 1806 #define DSPARB(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030) 1807 #define DSPARB_CSTART_MASK (0x7f << 7) 1808 #define DSPARB_CSTART_SHIFT 7 1809 #define DSPARB_BSTART_MASK (0x7f) 1810 #define DSPARB_BSTART_SHIFT 0 1811 #define DSPARB_BEND_SHIFT 9 /* on 855 */ 1812 #define DSPARB_AEND_SHIFT 0 1813 #define DSPARB_SPRITEA_SHIFT_VLV 0 1814 #define DSPARB_SPRITEA_MASK_VLV (0xff << 0) 1815 #define DSPARB_SPRITEB_SHIFT_VLV 8 1816 #define DSPARB_SPRITEB_MASK_VLV (0xff << 8) 1817 #define DSPARB_SPRITEC_SHIFT_VLV 16 1818 #define DSPARB_SPRITEC_MASK_VLV (0xff << 16) 1819 #define DSPARB_SPRITED_SHIFT_VLV 24 1820 #define DSPARB_SPRITED_MASK_VLV (0xff << 24) 1821 #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */ 1822 #define DSPARB_SPRITEA_HI_SHIFT_VLV 0 1823 #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0) 1824 #define DSPARB_SPRITEB_HI_SHIFT_VLV 4 1825 #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4) 1826 #define DSPARB_SPRITEC_HI_SHIFT_VLV 8 1827 #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8) 1828 #define DSPARB_SPRITED_HI_SHIFT_VLV 12 1829 #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12) 1830 #define DSPARB_SPRITEE_HI_SHIFT_VLV 16 1831 #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16) 1832 #define DSPARB_SPRITEF_HI_SHIFT_VLV 20 1833 #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20) 1834 #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */ 1835 #define DSPARB_SPRITEE_SHIFT_VLV 0 1836 #define DSPARB_SPRITEE_MASK_VLV (0xff << 0) 1837 #define DSPARB_SPRITEF_SHIFT_VLV 8 1838 #define DSPARB_SPRITEF_MASK_VLV (0xff << 8) 1839 1840 /* pnv/gen4/g4x/vlv/chv */ 1841 #define DSPFW1(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034) 1842 #define DSPFW_SR_SHIFT 23 1843 #define DSPFW_SR_MASK (0x1ff << 23) 1844 #define DSPFW_CURSORB_SHIFT 16 1845 #define DSPFW_CURSORB_MASK (0x3f << 16) 1846 #define DSPFW_PLANEB_SHIFT 8 1847 #define DSPFW_PLANEB_MASK (0x7f << 8) 1848 #define DSPFW_PLANEB_MASK_VLV (0xff << 8) /* vlv/chv */ 1849 #define DSPFW_PLANEA_SHIFT 0 1850 #define DSPFW_PLANEA_MASK (0x7f << 0) 1851 #define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */ 1852 #define DSPFW2(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038) 1853 #define DSPFW_FBC_SR_EN (1 << 31) /* g4x */ 1854 #define DSPFW_FBC_SR_SHIFT 28 1855 #define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */ 1856 #define DSPFW_FBC_HPLL_SR_SHIFT 24 1857 #define DSPFW_FBC_HPLL_SR_MASK (0xf << 24) /* g4x */ 1858 #define DSPFW_SPRITEB_SHIFT (16) 1859 #define DSPFW_SPRITEB_MASK (0x7f << 16) /* g4x */ 1860 #define DSPFW_SPRITEB_MASK_VLV (0xff << 16) /* vlv/chv */ 1861 #define DSPFW_CURSORA_SHIFT 8 1862 #define DSPFW_CURSORA_MASK (0x3f << 8) 1863 #define DSPFW_PLANEC_OLD_SHIFT 0 1864 #define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */ 1865 #define DSPFW_SPRITEA_SHIFT 0 1866 #define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */ 1867 #define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */ 1868 #define DSPFW3(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c) 1869 #define DSPFW_HPLL_SR_EN (1 << 31) 1870 #define PINEVIEW_SELF_REFRESH_EN (1 << 30) 1871 #define DSPFW_CURSOR_SR_SHIFT 24 1872 #define DSPFW_CURSOR_SR_MASK (0x3f << 24) 1873 #define DSPFW_HPLL_CURSOR_SHIFT 16 1874 #define DSPFW_HPLL_CURSOR_MASK (0x3f << 16) 1875 #define DSPFW_HPLL_SR_SHIFT 0 1876 #define DSPFW_HPLL_SR_MASK (0x1ff << 0) 1877 1878 /* vlv/chv */ 1879 #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070) 1880 #define DSPFW_SPRITEB_WM1_SHIFT 16 1881 #define DSPFW_SPRITEB_WM1_MASK (0xff << 16) 1882 #define DSPFW_CURSORA_WM1_SHIFT 8 1883 #define DSPFW_CURSORA_WM1_MASK (0x3f << 8) 1884 #define DSPFW_SPRITEA_WM1_SHIFT 0 1885 #define DSPFW_SPRITEA_WM1_MASK (0xff << 0) 1886 #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074) 1887 #define DSPFW_PLANEB_WM1_SHIFT 24 1888 #define DSPFW_PLANEB_WM1_MASK (0xff << 24) 1889 #define DSPFW_PLANEA_WM1_SHIFT 16 1890 #define DSPFW_PLANEA_WM1_MASK (0xff << 16) 1891 #define DSPFW_CURSORB_WM1_SHIFT 8 1892 #define DSPFW_CURSORB_WM1_MASK (0x3f << 8) 1893 #define DSPFW_CURSOR_SR_WM1_SHIFT 0 1894 #define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0) 1895 #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078) 1896 #define DSPFW_SR_WM1_SHIFT 0 1897 #define DSPFW_SR_WM1_MASK (0x1ff << 0) 1898 #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c) 1899 #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */ 1900 #define DSPFW_SPRITED_WM1_SHIFT 24 1901 #define DSPFW_SPRITED_WM1_MASK (0xff << 24) 1902 #define DSPFW_SPRITED_SHIFT 16 1903 #define DSPFW_SPRITED_MASK_VLV (0xff << 16) 1904 #define DSPFW_SPRITEC_WM1_SHIFT 8 1905 #define DSPFW_SPRITEC_WM1_MASK (0xff << 8) 1906 #define DSPFW_SPRITEC_SHIFT 0 1907 #define DSPFW_SPRITEC_MASK_VLV (0xff << 0) 1908 #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8) 1909 #define DSPFW_SPRITEF_WM1_SHIFT 24 1910 #define DSPFW_SPRITEF_WM1_MASK (0xff << 24) 1911 #define DSPFW_SPRITEF_SHIFT 16 1912 #define DSPFW_SPRITEF_MASK_VLV (0xff << 16) 1913 #define DSPFW_SPRITEE_WM1_SHIFT 8 1914 #define DSPFW_SPRITEE_WM1_MASK (0xff << 8) 1915 #define DSPFW_SPRITEE_SHIFT 0 1916 #define DSPFW_SPRITEE_MASK_VLV (0xff << 0) 1917 #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */ 1918 #define DSPFW_PLANEC_WM1_SHIFT 24 1919 #define DSPFW_PLANEC_WM1_MASK (0xff << 24) 1920 #define DSPFW_PLANEC_SHIFT 16 1921 #define DSPFW_PLANEC_MASK_VLV (0xff << 16) 1922 #define DSPFW_CURSORC_WM1_SHIFT 8 1923 #define DSPFW_CURSORC_WM1_MASK (0x3f << 16) 1924 #define DSPFW_CURSORC_SHIFT 0 1925 #define DSPFW_CURSORC_MASK (0x3f << 0) 1926 1927 /* vlv/chv high order bits */ 1928 #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064) 1929 #define DSPFW_SR_HI_SHIFT 24 1930 #define DSPFW_SR_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */ 1931 #define DSPFW_SPRITEF_HI_SHIFT 23 1932 #define DSPFW_SPRITEF_HI_MASK (1 << 23) 1933 #define DSPFW_SPRITEE_HI_SHIFT 22 1934 #define DSPFW_SPRITEE_HI_MASK (1 << 22) 1935 #define DSPFW_PLANEC_HI_SHIFT 21 1936 #define DSPFW_PLANEC_HI_MASK (1 << 21) 1937 #define DSPFW_SPRITED_HI_SHIFT 20 1938 #define DSPFW_SPRITED_HI_MASK (1 << 20) 1939 #define DSPFW_SPRITEC_HI_SHIFT 16 1940 #define DSPFW_SPRITEC_HI_MASK (1 << 16) 1941 #define DSPFW_PLANEB_HI_SHIFT 12 1942 #define DSPFW_PLANEB_HI_MASK (1 << 12) 1943 #define DSPFW_SPRITEB_HI_SHIFT 8 1944 #define DSPFW_SPRITEB_HI_MASK (1 << 8) 1945 #define DSPFW_SPRITEA_HI_SHIFT 4 1946 #define DSPFW_SPRITEA_HI_MASK (1 << 4) 1947 #define DSPFW_PLANEA_HI_SHIFT 0 1948 #define DSPFW_PLANEA_HI_MASK (1 << 0) 1949 #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068) 1950 #define DSPFW_SR_WM1_HI_SHIFT 24 1951 #define DSPFW_SR_WM1_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */ 1952 #define DSPFW_SPRITEF_WM1_HI_SHIFT 23 1953 #define DSPFW_SPRITEF_WM1_HI_MASK (1 << 23) 1954 #define DSPFW_SPRITEE_WM1_HI_SHIFT 22 1955 #define DSPFW_SPRITEE_WM1_HI_MASK (1 << 22) 1956 #define DSPFW_PLANEC_WM1_HI_SHIFT 21 1957 #define DSPFW_PLANEC_WM1_HI_MASK (1 << 21) 1958 #define DSPFW_SPRITED_WM1_HI_SHIFT 20 1959 #define DSPFW_SPRITED_WM1_HI_MASK (1 << 20) 1960 #define DSPFW_SPRITEC_WM1_HI_SHIFT 16 1961 #define DSPFW_SPRITEC_WM1_HI_MASK (1 << 16) 1962 #define DSPFW_PLANEB_WM1_HI_SHIFT 12 1963 #define DSPFW_PLANEB_WM1_HI_MASK (1 << 12) 1964 #define DSPFW_SPRITEB_WM1_HI_SHIFT 8 1965 #define DSPFW_SPRITEB_WM1_HI_MASK (1 << 8) 1966 #define DSPFW_SPRITEA_WM1_HI_SHIFT 4 1967 #define DSPFW_SPRITEA_WM1_HI_MASK (1 << 4) 1968 #define DSPFW_PLANEA_WM1_HI_SHIFT 0 1969 #define DSPFW_PLANEA_WM1_HI_MASK (1 << 0) 1970 1971 /* drain latency register values*/ 1972 #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe)) 1973 #define DDL_CURSOR_SHIFT 24 1974 #define DDL_SPRITE_SHIFT(sprite) (8 + 8 * (sprite)) 1975 #define DDL_PLANE_SHIFT 0 1976 #define DDL_PRECISION_HIGH (1 << 7) 1977 #define DDL_PRECISION_LOW (0 << 7) 1978 #define DRAIN_LATENCY_MASK 0x7f 1979 1980 #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400) 1981 #define CBR_PND_DEADLINE_DISABLE (1 << 31) 1982 #define CBR_PWM_CLOCK_MUX_SELECT (1 << 30) 1983 1984 #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450) 1985 #define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */ 1986 1987 /* FIFO watermark sizes etc */ 1988 #define G4X_FIFO_LINE_SIZE 64 1989 #define I915_FIFO_LINE_SIZE 64 1990 #define I830_FIFO_LINE_SIZE 32 1991 1992 #define VALLEYVIEW_FIFO_SIZE 255 1993 #define G4X_FIFO_SIZE 127 1994 #define I965_FIFO_SIZE 512 1995 #define I945_FIFO_SIZE 127 1996 #define I915_FIFO_SIZE 95 1997 #define I855GM_FIFO_SIZE 127 /* In cachelines */ 1998 #define I830_FIFO_SIZE 95 1999 2000 #define VALLEYVIEW_MAX_WM 0xff 2001 #define G4X_MAX_WM 0x3f 2002 #define I915_MAX_WM 0x3f 2003 2004 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ 2005 #define PINEVIEW_FIFO_LINE_SIZE 64 2006 #define PINEVIEW_MAX_WM 0x1ff 2007 #define PINEVIEW_DFT_WM 0x3f 2008 #define PINEVIEW_DFT_HPLLOFF_WM 0 2009 #define PINEVIEW_GUARD_WM 10 2010 #define PINEVIEW_CURSOR_FIFO 64 2011 #define PINEVIEW_CURSOR_MAX_WM 0x3f 2012 #define PINEVIEW_CURSOR_DFT_WM 0 2013 #define PINEVIEW_CURSOR_GUARD_WM 5 2014 2015 #define VALLEYVIEW_CURSOR_MAX_WM 64 2016 #define I965_CURSOR_FIFO 64 2017 #define I965_CURSOR_MAX_WM 32 2018 #define I965_CURSOR_DFT_WM 8 2019 2020 /* define the Watermark register on Ironlake */ 2021 #define _WM0_PIPEA_ILK 0x45100 2022 #define _WM0_PIPEB_ILK 0x45104 2023 #define _WM0_PIPEC_IVB 0x45200 2024 #define WM0_PIPE_ILK(pipe) _MMIO_BASE_PIPE3(0, (pipe), _WM0_PIPEA_ILK, \ 2025 _WM0_PIPEB_ILK, _WM0_PIPEC_IVB) 2026 #define WM0_PIPE_PRIMARY_MASK REG_GENMASK(31, 16) 2027 #define WM0_PIPE_SPRITE_MASK REG_GENMASK(15, 8) 2028 #define WM0_PIPE_CURSOR_MASK REG_GENMASK(7, 0) 2029 #define WM0_PIPE_PRIMARY(x) REG_FIELD_PREP(WM0_PIPE_PRIMARY_MASK, (x)) 2030 #define WM0_PIPE_SPRITE(x) REG_FIELD_PREP(WM0_PIPE_SPRITE_MASK, (x)) 2031 #define WM0_PIPE_CURSOR(x) REG_FIELD_PREP(WM0_PIPE_CURSOR_MASK, (x)) 2032 #define WM1_LP_ILK _MMIO(0x45108) 2033 #define WM2_LP_ILK _MMIO(0x4510c) 2034 #define WM3_LP_ILK _MMIO(0x45110) 2035 #define WM_LP_ENABLE REG_BIT(31) 2036 #define WM_LP_LATENCY_MASK REG_GENMASK(30, 24) 2037 #define WM_LP_FBC_MASK_BDW REG_GENMASK(23, 19) 2038 #define WM_LP_FBC_MASK_ILK REG_GENMASK(23, 20) 2039 #define WM_LP_PRIMARY_MASK REG_GENMASK(18, 8) 2040 #define WM_LP_CURSOR_MASK REG_GENMASK(7, 0) 2041 #define WM_LP_LATENCY(x) REG_FIELD_PREP(WM_LP_LATENCY_MASK, (x)) 2042 #define WM_LP_FBC_BDW(x) REG_FIELD_PREP(WM_LP_FBC_MASK_BDW, (x)) 2043 #define WM_LP_FBC_ILK(x) REG_FIELD_PREP(WM_LP_FBC_MASK_ILK, (x)) 2044 #define WM_LP_PRIMARY(x) REG_FIELD_PREP(WM_LP_PRIMARY_MASK, (x)) 2045 #define WM_LP_CURSOR(x) REG_FIELD_PREP(WM_LP_CURSOR_MASK, (x)) 2046 #define WM1S_LP_ILK _MMIO(0x45120) 2047 #define WM2S_LP_IVB _MMIO(0x45124) 2048 #define WM3S_LP_IVB _MMIO(0x45128) 2049 #define WM_LP_SPRITE_ENABLE REG_BIT(31) /* ilk/snb WM1S only */ 2050 #define WM_LP_SPRITE_MASK REG_GENMASK(10, 0) 2051 #define WM_LP_SPRITE(x) REG_FIELD_PREP(WM_LP_SPRITE_MASK, (x)) 2052 2053 /* 2054 * The two pipe frame counter registers are not synchronized, so 2055 * reading a stable value is somewhat tricky. The following code 2056 * should work: 2057 * 2058 * do { 2059 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 2060 * PIPE_FRAME_HIGH_SHIFT; 2061 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 2062 * PIPE_FRAME_LOW_SHIFT); 2063 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 2064 * PIPE_FRAME_HIGH_SHIFT); 2065 * } while (high1 != high2); 2066 * frame = (high1 << 8) | low1; 2067 */ 2068 #define _PIPEAFRAMEHIGH 0x70040 2069 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 2070 #define PIPE_FRAME_HIGH_SHIFT 0 2071 #define _PIPEAFRAMEPIXEL 0x70044 2072 #define PIPE_FRAME_LOW_MASK 0xff000000 2073 #define PIPE_FRAME_LOW_SHIFT 24 2074 #define PIPE_PIXEL_MASK 0x00ffffff 2075 #define PIPE_PIXEL_SHIFT 0 2076 /* GM45+ just has to be different */ 2077 #define _PIPEA_FRMCOUNT_G4X 0x70040 2078 #define _PIPEA_FLIPCOUNT_G4X 0x70044 2079 #define PIPE_FRMCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FRMCOUNT_G4X) 2080 #define PIPE_FLIPCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FLIPCOUNT_G4X) 2081 2082 /* CHV pipe B blender */ 2083 #define _CHV_BLEND_A 0x60a00 2084 #define CHV_BLEND_MASK REG_GENMASK(31, 30) 2085 #define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0) 2086 #define CHV_BLEND_ANDROID REG_FIELD_PREP(CHV_BLEND_MASK, 1) 2087 #define CHV_BLEND_MPO REG_FIELD_PREP(CHV_BLEND_MASK, 2) 2088 #define _CHV_CANVAS_A 0x60a04 2089 #define CHV_CANVAS_RED_MASK REG_GENMASK(29, 20) 2090 #define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10) 2091 #define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0) 2092 2093 #define CHV_BLEND(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_BLEND_A) 2094 #define CHV_CANVAS(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_CANVAS_A) 2095 2096 /* Display/Sprite base address macros */ 2097 #define DISP_BASEADDR_MASK (0xfffff000) 2098 #define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK) 2099 #define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK) 2100 2101 /* 2102 * VBIOS flags 2103 * gen2: 2104 * [00:06] alm,mgm 2105 * [10:16] all 2106 * [30:32] alm,mgm 2107 * gen3+: 2108 * [00:0f] all 2109 * [10:1f] all 2110 * [30:32] all 2111 */ 2112 #define SWF0(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4) 2113 #define SWF1(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4) 2114 #define SWF3(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4) 2115 #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) 2116 2117 /* ICL DSI 0 and 1 */ 2118 #define _PIPEDSI0CONF 0x7b008 2119 #define _PIPEDSI1CONF 0x7b808 2120 2121 2122 /* VBIOS regs */ 2123 #define VGACNTRL _MMIO(0x71400) 2124 # define VGA_DISP_DISABLE (1 << 31) 2125 # define VGA_2X_MODE (1 << 30) 2126 # define VGA_PIPE_B_SELECT (1 << 29) 2127 2128 #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400) 2129 2130 /* Ironlake */ 2131 2132 #define CPU_VGACNTRL _MMIO(0x41000) 2133 2134 #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030) 2135 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 2136 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */ 2137 #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */ 2138 #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */ 2139 #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */ 2140 #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */ 2141 #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0) 2142 #define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0) 2143 #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0) 2144 #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0) 2145 2146 /* refresh rate hardware control */ 2147 #define RR_HW_CTL _MMIO(0x45300) 2148 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff 2149 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 2150 2151 #define PCH_3DCGDIS0 _MMIO(0x46020) 2152 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) 2153 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) 2154 2155 #define PCH_3DCGDIS1 _MMIO(0x46024) 2156 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) 2157 2158 #define _PIPEA_DATA_M1 0x60030 2159 #define _PIPEA_DATA_N1 0x60034 2160 #define _PIPEA_DATA_M2 0x60038 2161 #define _PIPEA_DATA_N2 0x6003c 2162 #define _PIPEA_LINK_M1 0x60040 2163 #define _PIPEA_LINK_N1 0x60044 2164 #define _PIPEA_LINK_M2 0x60048 2165 #define _PIPEA_LINK_N2 0x6004c 2166 2167 /* PIPEB timing regs are same start from 0x61000 */ 2168 2169 #define _PIPEB_DATA_M1 0x61030 2170 #define _PIPEB_DATA_N1 0x61034 2171 #define _PIPEB_DATA_M2 0x61038 2172 #define _PIPEB_DATA_N2 0x6103c 2173 #define _PIPEB_LINK_M1 0x61040 2174 #define _PIPEB_LINK_N1 0x61044 2175 #define _PIPEB_LINK_M2 0x61048 2176 #define _PIPEB_LINK_N2 0x6104c 2177 2178 #define PIPE_DATA_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M1) 2179 #define PIPE_DATA_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1) 2180 #define PIPE_DATA_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2) 2181 #define PIPE_DATA_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2) 2182 #define PIPE_LINK_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1) 2183 #define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1) 2184 #define PIPE_LINK_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2) 2185 #define PIPE_LINK_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2) 2186 2187 /* CPU panel fitter */ 2188 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ 2189 #define _PFA_CTL_1 0x68080 2190 #define _PFB_CTL_1 0x68880 2191 #define PF_ENABLE REG_BIT(31) 2192 #define PF_PIPE_SEL_MASK_IVB REG_GENMASK(30, 29) /* ivb/hsw */ 2193 #define PF_PIPE_SEL_IVB(pipe) REG_FIELD_PREP(PF_PIPE_SEL_MASK_IVB, (pipe)) 2194 #define PF_FILTER_MASK REG_GENMASK(24, 23) 2195 #define PF_FILTER_PROGRAMMED REG_FIELD_PREP(PF_FILTER_MASK, 0) 2196 #define PF_FILTER_MED_3x3 REG_FIELD_PREP(PF_FILTER_MASK, 1) 2197 #define PF_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 2) 2198 #define PF_FILTER_EDGE_SOFTEN REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 3) 2199 #define _PFA_WIN_SZ 0x68074 2200 #define _PFB_WIN_SZ 0x68874 2201 #define PF_WIN_XSIZE_MASK REG_GENMASK(31, 16) 2202 #define PF_WIN_XSIZE(w) REG_FIELD_PREP(PF_WIN_XSIZE_MASK, (w)) 2203 #define PF_WIN_YSIZE_MASK REG_GENMASK(15, 0) 2204 #define PF_WIN_YSIZE(h) REG_FIELD_PREP(PF_WIN_YSIZE_MASK, (h)) 2205 #define _PFA_WIN_POS 0x68070 2206 #define _PFB_WIN_POS 0x68870 2207 #define PF_WIN_XPOS_MASK REG_GENMASK(31, 16) 2208 #define PF_WIN_XPOS(x) REG_FIELD_PREP(PF_WIN_XPOS_MASK, (x)) 2209 #define PF_WIN_YPOS_MASK REG_GENMASK(15, 0) 2210 #define PF_WIN_YPOS(y) REG_FIELD_PREP(PF_WIN_YPOS_MASK, (y)) 2211 #define _PFA_VSCALE 0x68084 2212 #define _PFB_VSCALE 0x68884 2213 #define _PFA_HSCALE 0x68090 2214 #define _PFB_HSCALE 0x68890 2215 2216 #define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) 2217 #define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) 2218 #define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) 2219 #define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) 2220 #define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) 2221 2222 /* 2223 * Skylake scalers 2224 */ 2225 #define _PS_1A_CTRL 0x68180 2226 #define _PS_2A_CTRL 0x68280 2227 #define _PS_1B_CTRL 0x68980 2228 #define _PS_2B_CTRL 0x68A80 2229 #define _PS_1C_CTRL 0x69180 2230 #define PS_SCALER_EN REG_BIT(31) 2231 #define PS_SCALER_TYPE_MASK REG_BIT(30) /* icl+ */ 2232 #define PS_SCALER_TYPE_NON_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 0) 2233 #define PS_SCALER_TYPE_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 1) 2234 #define SKL_PS_SCALER_MODE_MASK REG_GENMASK(29, 28) /* skl/bxt */ 2235 #define SKL_PS_SCALER_MODE_DYN REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 0) 2236 #define SKL_PS_SCALER_MODE_HQ REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 1) 2237 #define SKL_PS_SCALER_MODE_NV12 REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 2) 2238 #define PS_SCALER_MODE_MASK REG_BIT(29) /* glk-tgl */ 2239 #define PS_SCALER_MODE_NORMAL REG_FIELD_PREP(PS_SCALER_MODE_MASK, 0) 2240 #define PS_SCALER_MODE_PLANAR REG_FIELD_PREP(PS_SCALER_MODE_MASK, 1) 2241 #define PS_ADAPTIVE_FILTERING_EN REG_BIT(28) /* icl+ */ 2242 #define PS_BINDING_MASK REG_GENMASK(27, 25) 2243 #define PS_BINDING_PIPE REG_FIELD_PREP(PS_BINDING_MASK, 0) 2244 #define PS_BINDING_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_MASK, (plane_id) + 1) 2245 #define PS_FILTER_MASK REG_GENMASK(24, 23) 2246 #define PS_FILTER_MEDIUM REG_FIELD_PREP(PS_FILTER_MASK, 0) 2247 #define PS_FILTER_PROGRAMMED REG_FIELD_PREP(PS_FILTER_MASK, 1) 2248 #define PS_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_FILTER_MASK, 2) 2249 #define PS_FILTER_BILINEAR REG_FIELD_PREP(PS_FILTER_MASK, 3) 2250 #define PS_ADAPTIVE_FILTER_MASK REG_BIT(22) /* icl+ */ 2251 #define PS_ADAPTIVE_FILTER_MEDIUM REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 0) 2252 #define PS_ADAPTIVE_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 1) 2253 #define PS_PIPE_SCALER_LOC_MASK REG_BIT(21) /* icl+ */ 2254 #define PS_PIPE_SCALER_LOC_AFTER_OUTPUT_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 0) /* non-linear */ 2255 #define PS_PIPE_SCALER_LOC_AFTER_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 1) /* linear */ 2256 #define PS_VERT3TAP REG_BIT(21) /* skl/bxt */ 2257 #define PS_VERT_INT_INVERT_FIELD REG_BIT(20) 2258 #define PS_PROG_SCALE_FACTOR REG_BIT(19) /* tgl+ */ 2259 #define PS_PWRUP_PROGRESS REG_BIT(17) 2260 #define PS_V_FILTER_BYPASS REG_BIT(8) 2261 #define PS_VADAPT_EN REG_BIT(7) /* skl/bxt */ 2262 #define PS_VADAPT_MODE_MASK REG_GENMASK(6, 5) /* skl/bxt */ 2263 #define PS_VADAPT_MODE_LEAST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 0) 2264 #define PS_VADAPT_MODE_MOD_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 1) 2265 #define PS_VADAPT_MODE_MOST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 3) 2266 #define PS_BINDING_Y_MASK REG_GENMASK(7, 5) /* icl-tgl */ 2267 #define PS_BINDING_Y_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_Y_MASK, (plane_id) + 1) 2268 #define PS_Y_VERT_FILTER_SELECT_MASK REG_BIT(4) /* glk+ */ 2269 #define PS_Y_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_VERT_FILTER_SELECT_MASK, (set)) 2270 #define PS_Y_HORZ_FILTER_SELECT_MASK REG_BIT(3) /* glk+ */ 2271 #define PS_Y_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_HORZ_FILTER_SELECT_MASK, (set)) 2272 #define PS_UV_VERT_FILTER_SELECT_MASK REG_BIT(2) /* glk+ */ 2273 #define PS_UV_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_VERT_FILTER_SELECT_MASK, (set)) 2274 #define PS_UV_HORZ_FILTER_SELECT_MASK REG_BIT(1) /* glk+ */ 2275 #define PS_UV_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_HORZ_FILTER_SELECT_MASK, (set)) 2276 2277 #define _PS_PWR_GATE_1A 0x68160 2278 #define _PS_PWR_GATE_2A 0x68260 2279 #define _PS_PWR_GATE_1B 0x68960 2280 #define _PS_PWR_GATE_2B 0x68A60 2281 #define _PS_PWR_GATE_1C 0x69160 2282 #define PS_PWR_GATE_DIS_OVERRIDE REG_BIT(31) 2283 #define PS_PWR_GATE_SETTLING_TIME_MASK REG_GENMASK(4, 3) 2284 #define PS_PWR_GATE_SETTLING_TIME_32 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 0) 2285 #define PS_PWR_GATE_SETTLING_TIME_64 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 1) 2286 #define PS_PWR_GATE_SETTLING_TIME_96 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 2) 2287 #define PS_PWR_GATE_SETTLING_TIME_128 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 3) 2288 #define PS_PWR_GATE_SLPEN_MASK REG_GENMASK(1, 0) 2289 #define PS_PWR_GATE_SLPEN_8 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 0) 2290 #define PS_PWR_GATE_SLPEN_16 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 1) 2291 #define PS_PWR_GATE_SLPEN_24 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 2) 2292 #define PS_PWR_GATE_SLPEN_32 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 3) 2293 2294 #define _PS_WIN_POS_1A 0x68170 2295 #define _PS_WIN_POS_2A 0x68270 2296 #define _PS_WIN_POS_1B 0x68970 2297 #define _PS_WIN_POS_2B 0x68A70 2298 #define _PS_WIN_POS_1C 0x69170 2299 #define PS_WIN_XPOS_MASK REG_GENMASK(31, 16) 2300 #define PS_WIN_XPOS(x) REG_FIELD_PREP(PS_WIN_XPOS_MASK, (x)) 2301 #define PS_WIN_YPOS_MASK REG_GENMASK(15, 0) 2302 #define PS_WIN_YPOS(y) REG_FIELD_PREP(PS_WIN_YPOS_MASK, (y)) 2303 2304 #define _PS_WIN_SZ_1A 0x68174 2305 #define _PS_WIN_SZ_2A 0x68274 2306 #define _PS_WIN_SZ_1B 0x68974 2307 #define _PS_WIN_SZ_2B 0x68A74 2308 #define _PS_WIN_SZ_1C 0x69174 2309 #define PS_WIN_XSIZE_MASK REG_GENMASK(31, 16) 2310 #define PS_WIN_XSIZE(w) REG_FIELD_PREP(PS_WIN_XSIZE_MASK, (w)) 2311 #define PS_WIN_YSIZE_MASK REG_GENMASK(15, 0) 2312 #define PS_WIN_YSIZE(h) REG_FIELD_PREP(PS_WIN_YSIZE_MASK, (h)) 2313 2314 #define _PS_VSCALE_1A 0x68184 2315 #define _PS_VSCALE_2A 0x68284 2316 #define _PS_VSCALE_1B 0x68984 2317 #define _PS_VSCALE_2B 0x68A84 2318 #define _PS_VSCALE_1C 0x69184 2319 2320 #define _PS_HSCALE_1A 0x68190 2321 #define _PS_HSCALE_2A 0x68290 2322 #define _PS_HSCALE_1B 0x68990 2323 #define _PS_HSCALE_2B 0x68A90 2324 #define _PS_HSCALE_1C 0x69190 2325 2326 #define _PS_VPHASE_1A 0x68188 2327 #define _PS_VPHASE_2A 0x68288 2328 #define _PS_VPHASE_1B 0x68988 2329 #define _PS_VPHASE_2B 0x68A88 2330 #define _PS_VPHASE_1C 0x69188 2331 #define PS_Y_PHASE_MASK REG_GENMASK(31, 16) 2332 #define PS_Y_PHASE(x) REG_FIELD_PREP(PS_Y_PHASE_MASK, (x)) 2333 #define PS_UV_RGB_PHASE_MASK REG_GENMASK(15, 0) 2334 #define PS_UV_RGB_PHASE(x) REG_FIELD_PREP(PS_UV_RGB_PHASE_MASK, (x)) 2335 #define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */ 2336 #define PS_PHASE_TRIP (1 << 0) 2337 2338 #define _PS_HPHASE_1A 0x68194 2339 #define _PS_HPHASE_2A 0x68294 2340 #define _PS_HPHASE_1B 0x68994 2341 #define _PS_HPHASE_2B 0x68A94 2342 #define _PS_HPHASE_1C 0x69194 2343 2344 #define _PS_ECC_STAT_1A 0x681D0 2345 #define _PS_ECC_STAT_2A 0x682D0 2346 #define _PS_ECC_STAT_1B 0x689D0 2347 #define _PS_ECC_STAT_2B 0x68AD0 2348 #define _PS_ECC_STAT_1C 0x691D0 2349 2350 #define _PS_COEF_SET0_INDEX_1A 0x68198 2351 #define _PS_COEF_SET0_INDEX_2A 0x68298 2352 #define _PS_COEF_SET0_INDEX_1B 0x68998 2353 #define _PS_COEF_SET0_INDEX_2B 0x68A98 2354 #define PS_COEF_INDEX_AUTO_INC REG_BIT(10) 2355 2356 #define _PS_COEF_SET0_DATA_1A 0x6819C 2357 #define _PS_COEF_SET0_DATA_2A 0x6829C 2358 #define _PS_COEF_SET0_DATA_1B 0x6899C 2359 #define _PS_COEF_SET0_DATA_2B 0x68A9C 2360 2361 #define _ID(id, a, b) _PICK_EVEN(id, a, b) 2362 #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \ 2363 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \ 2364 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL)) 2365 #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \ 2366 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \ 2367 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B)) 2368 #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \ 2369 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \ 2370 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B)) 2371 #define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \ 2372 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \ 2373 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B)) 2374 #define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \ 2375 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \ 2376 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B)) 2377 #define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \ 2378 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \ 2379 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B)) 2380 #define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \ 2381 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \ 2382 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B)) 2383 #define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \ 2384 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \ 2385 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B)) 2386 #define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \ 2387 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \ 2388 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)) 2389 #define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe, \ 2390 _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \ 2391 _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8) 2392 2393 #define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \ 2394 _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \ 2395 _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8) 2396 2397 /* Display Internal Timeout Register */ 2398 #define RM_TIMEOUT _MMIO(0x42060) 2399 #define MMIO_TIMEOUT_US(us) ((us) << 0) 2400 2401 /* interrupts */ 2402 #define DE_MASTER_IRQ_CONTROL (1 << 31) 2403 #define DE_SPRITEB_FLIP_DONE (1 << 29) 2404 #define DE_SPRITEA_FLIP_DONE (1 << 28) 2405 #define DE_PLANEB_FLIP_DONE (1 << 27) 2406 #define DE_PLANEA_FLIP_DONE (1 << 26) 2407 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane))) 2408 #define DE_PCU_EVENT (1 << 25) 2409 #define DE_GTT_FAULT (1 << 24) 2410 #define DE_POISON (1 << 23) 2411 #define DE_PERFORM_COUNTER (1 << 22) 2412 #define DE_PCH_EVENT (1 << 21) 2413 #define DE_AUX_CHANNEL_A (1 << 20) 2414 #define DE_DP_A_HOTPLUG (1 << 19) 2415 #define DE_GSE (1 << 18) 2416 #define DE_PIPEB_VBLANK (1 << 15) 2417 #define DE_PIPEB_EVEN_FIELD (1 << 14) 2418 #define DE_PIPEB_ODD_FIELD (1 << 13) 2419 #define DE_PIPEB_LINE_COMPARE (1 << 12) 2420 #define DE_PIPEB_VSYNC (1 << 11) 2421 #define DE_PIPEB_CRC_DONE (1 << 10) 2422 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) 2423 #define DE_PIPEA_VBLANK (1 << 7) 2424 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe))) 2425 #define DE_PIPEA_EVEN_FIELD (1 << 6) 2426 #define DE_PIPEA_ODD_FIELD (1 << 5) 2427 #define DE_PIPEA_LINE_COMPARE (1 << 4) 2428 #define DE_PIPEA_VSYNC (1 << 3) 2429 #define DE_PIPEA_CRC_DONE (1 << 2) 2430 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe))) 2431 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 2432 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe))) 2433 2434 /* More Ivybridge lolz */ 2435 #define DE_ERR_INT_IVB (1 << 30) 2436 #define DE_GSE_IVB (1 << 29) 2437 #define DE_PCH_EVENT_IVB (1 << 28) 2438 #define DE_DP_A_HOTPLUG_IVB (1 << 27) 2439 #define DE_AUX_CHANNEL_A_IVB (1 << 26) 2440 #define DE_EDP_PSR_INT_HSW (1 << 19) 2441 #define DE_SPRITEC_FLIP_DONE_IVB (1 << 14) 2442 #define DE_PLANEC_FLIP_DONE_IVB (1 << 13) 2443 #define DE_PIPEC_VBLANK_IVB (1 << 10) 2444 #define DE_SPRITEB_FLIP_DONE_IVB (1 << 9) 2445 #define DE_PLANEB_FLIP_DONE_IVB (1 << 8) 2446 #define DE_PIPEB_VBLANK_IVB (1 << 5) 2447 #define DE_SPRITEA_FLIP_DONE_IVB (1 << 4) 2448 #define DE_PLANEA_FLIP_DONE_IVB (1 << 3) 2449 #define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane))) 2450 #define DE_PIPEA_VBLANK_IVB (1 << 0) 2451 #define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5)) 2452 2453 #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */ 2454 #define MASTER_INTERRUPT_ENABLE (1 << 31) 2455 2456 #define DEISR _MMIO(0x44000) 2457 #define DEIMR _MMIO(0x44004) 2458 #define DEIIR _MMIO(0x44008) 2459 #define DEIER _MMIO(0x4400c) 2460 2461 #define GTISR _MMIO(0x44010) 2462 #define GTIMR _MMIO(0x44014) 2463 #define GTIIR _MMIO(0x44018) 2464 #define GTIER _MMIO(0x4401c) 2465 2466 #define GEN8_MASTER_IRQ _MMIO(0x44200) 2467 #define GEN8_MASTER_IRQ_CONTROL (1 << 31) 2468 #define GEN8_PCU_IRQ (1 << 30) 2469 #define GEN8_DE_PCH_IRQ (1 << 23) 2470 #define GEN8_DE_MISC_IRQ (1 << 22) 2471 #define GEN8_DE_PORT_IRQ (1 << 20) 2472 #define GEN8_DE_PIPE_C_IRQ (1 << 18) 2473 #define GEN8_DE_PIPE_B_IRQ (1 << 17) 2474 #define GEN8_DE_PIPE_A_IRQ (1 << 16) 2475 #define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe))) 2476 #define GEN8_GT_VECS_IRQ (1 << 6) 2477 #define GEN8_GT_GUC_IRQ (1 << 5) 2478 #define GEN8_GT_PM_IRQ (1 << 4) 2479 #define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */ 2480 #define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */ 2481 #define GEN8_GT_BCS_IRQ (1 << 1) 2482 #define GEN8_GT_RCS_IRQ (1 << 0) 2483 2484 #define XELPD_DISPLAY_ERR_FATAL_MASK _MMIO(0x4421c) 2485 2486 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which))) 2487 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which))) 2488 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which))) 2489 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which))) 2490 2491 #define GEN8_RCS_IRQ_SHIFT 0 2492 #define GEN8_BCS_IRQ_SHIFT 16 2493 #define GEN8_VCS0_IRQ_SHIFT 0 /* NB: VCS1 in bspec! */ 2494 #define GEN8_VCS1_IRQ_SHIFT 16 /* NB: VCS2 in bpsec! */ 2495 #define GEN8_VECS_IRQ_SHIFT 0 2496 #define GEN8_WD_IRQ_SHIFT 16 2497 2498 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe))) 2499 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe))) 2500 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe))) 2501 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe))) 2502 #define GEN8_PIPE_FIFO_UNDERRUN REG_BIT(31) 2503 #define GEN8_PIPE_CDCLK_CRC_ERROR REG_BIT(29) 2504 #define GEN8_PIPE_CDCLK_CRC_DONE REG_BIT(28) 2505 #define GEN12_PIPEDMC_INTERRUPT REG_BIT(26) /* tgl+ */ 2506 #define GEN12_PIPEDMC_FAULT REG_BIT(25) /* tgl+ */ 2507 #define MTL_PIPEDMC_ATS_FAULT REG_BIT(24) /* mtl+ */ 2508 #define XELPD_PIPE_SOFT_UNDERRUN REG_BIT(22) /* adl/dg2+ */ 2509 #define GEN11_PIPE_PLANE7_FAULT REG_BIT(22) /* icl/tgl */ 2510 #define XELPD_PIPE_HARD_UNDERRUN REG_BIT(21) /* adl/dg2+ */ 2511 #define GEN11_PIPE_PLANE6_FAULT REG_BIT(21) /* icl/tgl */ 2512 #define GEN11_PIPE_PLANE5_FAULT REG_BIT(20) /* icl+ */ 2513 #define GEN12_PIPE_VBLANK_UNMOD REG_BIT(19) /* tgl+ */ 2514 #define MTL_PLANE_ATS_FAULT REG_BIT(18) /* mtl+ */ 2515 #define GEN11_PIPE_PLANE7_FLIP_DONE REG_BIT(18) /* icl/tgl */ 2516 #define GEN11_PIPE_PLANE6_FLIP_DONE REG_BIT(17) /* icl/tgl */ 2517 #define GEN11_PIPE_PLANE5_FLIP_DONE REG_BIT(16) /* icl+ */ 2518 #define GEN9_PIPE_CURSOR_FAULT REG_BIT(11) /* skl+ */ 2519 #define GEN9_PIPE_PLANE4_FAULT REG_BIT(10) /* skl+ */ 2520 #define GEN8_PIPE_CURSOR_FAULT REG_BIT(10) /* bdw */ 2521 #define GEN9_PIPE_PLANE3_FAULT REG_BIT(9) /* skl+ */ 2522 #define GEN8_PIPE_SPRITE_FAULT REG_BIT(9) /* bdw */ 2523 #define GEN9_PIPE_PLANE2_FAULT REG_BIT(8) /* skl+ */ 2524 #define GEN8_PIPE_PRIMARY_FAULT REG_BIT(8) /* bdw */ 2525 #define GEN9_PIPE_PLANE1_FAULT REG_BIT(7) /* skl+ */ 2526 #define GEN9_PIPE_PLANE4_FLIP_DONE REG_BIT(6) /* skl+ */ 2527 #define GEN9_PIPE_PLANE3_FLIP_DONE REG_BIT(5) /* skl+ */ 2528 #define GEN8_PIPE_SPRITE_FLIP_DONE REG_BIT(5) /* bdw */ 2529 #define GEN9_PIPE_PLANE2_FLIP_DONE REG_BIT(4) /* skl+ */ 2530 #define GEN8_PIPE_PRIMARY_FLIP_DONE REG_BIT(4) /* bdw */ 2531 #define GEN9_PIPE_PLANE1_FLIP_DONE REG_BIT(3) /* skl+ */ 2532 #define GEN9_PIPE_PLANE_FLIP_DONE(plane_id) \ 2533 REG_BIT(((plane_id) >= PLANE_5 ? 16 - PLANE_5 : 3 - PLANE_1) + (plane_id)) /* skl+ */ 2534 #define GEN8_PIPE_SCAN_LINE_EVENT REG_BIT(2) 2535 #define GEN8_PIPE_VSYNC REG_BIT(1) 2536 #define GEN8_PIPE_VBLANK REG_BIT(0) 2537 2538 #define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A) 2539 #define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1) 2540 2541 #define GEN8_DE_PORT_ISR _MMIO(0x44440) 2542 #define GEN8_DE_PORT_IMR _MMIO(0x44444) 2543 #define GEN8_DE_PORT_IIR _MMIO(0x44448) 2544 #define GEN8_DE_PORT_IER _MMIO(0x4444c) 2545 #define DSI1_NON_TE (1 << 31) 2546 #define DSI0_NON_TE (1 << 30) 2547 #define ICL_AUX_CHANNEL_E (1 << 29) 2548 #define ICL_AUX_CHANNEL_F (1 << 28) 2549 #define GEN9_AUX_CHANNEL_D (1 << 27) 2550 #define GEN9_AUX_CHANNEL_C (1 << 26) 2551 #define GEN9_AUX_CHANNEL_B (1 << 25) 2552 #define DSI1_TE (1 << 24) 2553 #define DSI0_TE (1 << 23) 2554 #define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin)) 2555 #define BXT_DE_PORT_HOTPLUG_MASK (GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \ 2556 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \ 2557 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)) 2558 #define BDW_DE_PORT_HOTPLUG_MASK GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) 2559 #define BXT_DE_PORT_GMBUS (1 << 1) 2560 #define GEN8_AUX_CHANNEL_A (1 << 0) 2561 #define TGL_DE_PORT_AUX_USBC6 REG_BIT(13) 2562 #define XELPD_DE_PORT_AUX_DDIE REG_BIT(13) 2563 #define TGL_DE_PORT_AUX_USBC5 REG_BIT(12) 2564 #define XELPD_DE_PORT_AUX_DDID REG_BIT(12) 2565 #define TGL_DE_PORT_AUX_USBC4 REG_BIT(11) 2566 #define TGL_DE_PORT_AUX_USBC3 REG_BIT(10) 2567 #define TGL_DE_PORT_AUX_USBC2 REG_BIT(9) 2568 #define TGL_DE_PORT_AUX_USBC1 REG_BIT(8) 2569 #define TGL_DE_PORT_AUX_DDIC REG_BIT(2) 2570 #define TGL_DE_PORT_AUX_DDIB REG_BIT(1) 2571 #define TGL_DE_PORT_AUX_DDIA REG_BIT(0) 2572 2573 #define GEN8_DE_MISC_ISR _MMIO(0x44460) 2574 #define GEN8_DE_MISC_IMR _MMIO(0x44464) 2575 #define GEN8_DE_MISC_IIR _MMIO(0x44468) 2576 #define GEN8_DE_MISC_IER _MMIO(0x4446c) 2577 #define XELPDP_PMDEMAND_RSPTOUT_ERR REG_BIT(27) 2578 #define GEN8_DE_MISC_GSE REG_BIT(27) 2579 #define GEN8_DE_EDP_PSR REG_BIT(19) 2580 #define XELPDP_PMDEMAND_RSP REG_BIT(3) 2581 2582 #define GEN8_PCU_ISR _MMIO(0x444e0) 2583 #define GEN8_PCU_IMR _MMIO(0x444e4) 2584 #define GEN8_PCU_IIR _MMIO(0x444e8) 2585 #define GEN8_PCU_IER _MMIO(0x444ec) 2586 2587 #define GEN11_GU_MISC_ISR _MMIO(0x444f0) 2588 #define GEN11_GU_MISC_IMR _MMIO(0x444f4) 2589 #define GEN11_GU_MISC_IIR _MMIO(0x444f8) 2590 #define GEN11_GU_MISC_IER _MMIO(0x444fc) 2591 #define GEN11_GU_MISC_GSE (1 << 27) 2592 2593 #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010) 2594 #define GEN11_MASTER_IRQ (1 << 31) 2595 #define GEN11_PCU_IRQ (1 << 30) 2596 #define GEN11_GU_MISC_IRQ (1 << 29) 2597 #define GEN11_DISPLAY_IRQ (1 << 16) 2598 #define GEN11_GT_DW_IRQ(x) (1 << (x)) 2599 #define GEN11_GT_DW1_IRQ (1 << 1) 2600 #define GEN11_GT_DW0_IRQ (1 << 0) 2601 2602 #define DG1_MSTR_TILE_INTR _MMIO(0x190008) 2603 #define DG1_MSTR_IRQ REG_BIT(31) 2604 #define DG1_MSTR_TILE(t) REG_BIT(t) 2605 2606 #define GEN11_DISPLAY_INT_CTL _MMIO(0x44200) 2607 #define GEN11_DISPLAY_IRQ_ENABLE (1 << 31) 2608 #define GEN11_AUDIO_CODEC_IRQ (1 << 24) 2609 #define GEN11_DE_PCH_IRQ (1 << 23) 2610 #define GEN11_DE_MISC_IRQ (1 << 22) 2611 #define GEN11_DE_HPD_IRQ (1 << 21) 2612 #define GEN11_DE_PORT_IRQ (1 << 20) 2613 #define GEN11_DE_PIPE_C (1 << 18) 2614 #define GEN11_DE_PIPE_B (1 << 17) 2615 #define GEN11_DE_PIPE_A (1 << 16) 2616 2617 #define GEN11_DE_HPD_ISR _MMIO(0x44470) 2618 #define GEN11_DE_HPD_IMR _MMIO(0x44474) 2619 #define GEN11_DE_HPD_IIR _MMIO(0x44478) 2620 #define GEN11_DE_HPD_IER _MMIO(0x4447c) 2621 #define GEN11_TC_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin)) 2622 #define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(HPD_PORT_TC6) | \ 2623 GEN11_TC_HOTPLUG(HPD_PORT_TC5) | \ 2624 GEN11_TC_HOTPLUG(HPD_PORT_TC4) | \ 2625 GEN11_TC_HOTPLUG(HPD_PORT_TC3) | \ 2626 GEN11_TC_HOTPLUG(HPD_PORT_TC2) | \ 2627 GEN11_TC_HOTPLUG(HPD_PORT_TC1)) 2628 #define GEN11_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin)) 2629 #define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(HPD_PORT_TC6) | \ 2630 GEN11_TBT_HOTPLUG(HPD_PORT_TC5) | \ 2631 GEN11_TBT_HOTPLUG(HPD_PORT_TC4) | \ 2632 GEN11_TBT_HOTPLUG(HPD_PORT_TC3) | \ 2633 GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \ 2634 GEN11_TBT_HOTPLUG(HPD_PORT_TC1)) 2635 2636 #define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030) 2637 #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038) 2638 #define GEN11_HOTPLUG_CTL_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4)) 2639 #define GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4)) 2640 #define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4)) 2641 #define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 << (_HPD_PIN_TC(hpd_pin) * 4)) 2642 2643 #define PICAINTERRUPT_ISR _MMIO(0x16FE50) 2644 #define PICAINTERRUPT_IMR _MMIO(0x16FE54) 2645 #define PICAINTERRUPT_IIR _MMIO(0x16FE58) 2646 #define PICAINTERRUPT_IER _MMIO(0x16FE5C) 2647 #define XELPDP_DP_ALT_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin)) 2648 #define XELPDP_DP_ALT_HOTPLUG_MASK REG_GENMASK(19, 16) 2649 #define XELPDP_AUX_TC(hpd_pin) REG_BIT(8 + _HPD_PIN_TC(hpd_pin)) 2650 #define XELPDP_AUX_TC_MASK REG_GENMASK(11, 8) 2651 #define XE2LPD_AUX_DDI(hpd_pin) REG_BIT(6 + _HPD_PIN_DDI(hpd_pin)) 2652 #define XE2LPD_AUX_DDI_MASK REG_GENMASK(7, 6) 2653 #define XELPDP_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin)) 2654 #define XELPDP_TBT_HOTPLUG_MASK REG_GENMASK(3, 0) 2655 2656 #define XELPDP_PORT_HOTPLUG_CTL(hpd_pin) _MMIO(0x16F270 + (_HPD_PIN_TC(hpd_pin) * 0x200)) 2657 #define XELPDP_TBT_HOTPLUG_ENABLE REG_BIT(6) 2658 #define XELPDP_TBT_HPD_LONG_DETECT REG_BIT(5) 2659 #define XELPDP_TBT_HPD_SHORT_DETECT REG_BIT(4) 2660 #define XELPDP_DP_ALT_HOTPLUG_ENABLE REG_BIT(2) 2661 #define XELPDP_DP_ALT_HPD_LONG_DETECT REG_BIT(1) 2662 #define XELPDP_DP_ALT_HPD_SHORT_DETECT REG_BIT(0) 2663 2664 #define XELPDP_INITIATE_PMDEMAND_REQUEST(dword) _MMIO(0x45230 + 4 * (dword)) 2665 #define XELPDP_PMDEMAND_QCLK_GV_BW_MASK REG_GENMASK(31, 16) 2666 #define XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK REG_GENMASK(14, 12) 2667 #define XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK REG_GENMASK(11, 8) 2668 #define XELPDP_PMDEMAND_PIPES_MASK REG_GENMASK(7, 6) 2669 #define XELPDP_PMDEMAND_DBUFS_MASK REG_GENMASK(5, 4) 2670 #define XELPDP_PMDEMAND_PHYS_MASK REG_GENMASK(2, 0) 2671 2672 #define XELPDP_PMDEMAND_REQ_ENABLE REG_BIT(31) 2673 #define XELPDP_PMDEMAND_CDCLK_FREQ_MASK REG_GENMASK(30, 20) 2674 #define XELPDP_PMDEMAND_DDICLK_FREQ_MASK REG_GENMASK(18, 8) 2675 #define XELPDP_PMDEMAND_SCALERS_MASK REG_GENMASK(6, 4) 2676 #define XELPDP_PMDEMAND_PLLS_MASK REG_GENMASK(2, 0) 2677 2678 #define GEN12_DCPR_STATUS_1 _MMIO(0x46440) 2679 #define XELPDP_PMDEMAND_INFLIGHT_STATUS REG_BIT(26) 2680 2681 #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004) 2682 /* Required on all Ironlake and Sandybridge according to the B-Spec. */ 2683 #define ILK_ELPIN_409_SELECT REG_BIT(25) 2684 #define ILK_DPARB_GATE REG_BIT(22) 2685 #define ILK_VSDPFD_FULL REG_BIT(21) 2686 2687 #define FUSE_STRAP _MMIO(0x42014) 2688 #define ILK_INTERNAL_GRAPHICS_DISABLE REG_BIT(31) 2689 #define ILK_INTERNAL_DISPLAY_DISABLE REG_BIT(30) 2690 #define ILK_DISPLAY_DEBUG_DISABLE REG_BIT(29) 2691 #define IVB_PIPE_C_DISABLE REG_BIT(28) 2692 #define ILK_HDCP_DISABLE REG_BIT(25) 2693 #define ILK_eDP_A_DISABLE REG_BIT(24) 2694 #define HSW_CDCLK_LIMIT REG_BIT(24) 2695 #define ILK_DESKTOP REG_BIT(23) 2696 #define HSW_CPU_SSC_ENABLE REG_BIT(21) 2697 2698 #define FUSE_STRAP3 _MMIO(0x42020) 2699 #define HSW_REF_CLK_SELECT REG_BIT(1) 2700 2701 #define ILK_DSPCLK_GATE_D _MMIO(0x42020) 2702 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE REG_BIT(28) 2703 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE REG_BIT(9) 2704 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE REG_BIT(8) 2705 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE REG_BIT(7) 2706 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE REG_BIT(5) 2707 2708 #define IVB_CHICKEN3 _MMIO(0x4200c) 2709 #define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE REG_BIT(5) 2710 #define CHICKEN3_DGMG_DONE_FIX_DISABLE REG_BIT(2) 2711 2712 #define CHICKEN_PAR1_1 _MMIO(0x42080) 2713 #define IGNORE_KVMR_PIPE_A REG_BIT(23) 2714 #define KBL_ARB_FILL_SPARE_22 REG_BIT(22) 2715 #define DIS_RAM_BYPASS_PSR2_MAN_TRACK REG_BIT(16) 2716 #define SKL_DE_COMPRESSED_HASH_MODE REG_BIT(15) 2717 #define HSW_MASK_VBL_TO_PIPE_IN_SRD REG_BIT(15) /* hsw/bdw */ 2718 #define FORCE_ARB_IDLE_PLANES REG_BIT(14) 2719 #define SKL_EDP_PSR_FIX_RDWRAP REG_BIT(3) 2720 #define IGNORE_PSR2_HW_TRACKING REG_BIT(1) 2721 2722 #define CHICKEN_PAR2_1 _MMIO(0x42090) 2723 #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT REG_BIT(14) 2724 2725 #define CHICKEN_MISC_2 _MMIO(0x42084) 2726 #define CHICKEN_MISC_DISABLE_DPT REG_BIT(30) /* adl,dg2 */ 2727 #define BMG_DARB_HALF_BLK_END_BURST REG_BIT(27) 2728 #define KBL_ARB_FILL_SPARE_14 REG_BIT(14) 2729 #define KBL_ARB_FILL_SPARE_13 REG_BIT(13) 2730 #define GLK_CL2_PWR_DOWN REG_BIT(12) 2731 #define GLK_CL1_PWR_DOWN REG_BIT(11) 2732 #define GLK_CL0_PWR_DOWN REG_BIT(10) 2733 2734 #define CHICKEN_MISC_3 _MMIO(0x42088) 2735 #define DP_MST_DPT_DPTP_ALIGN_WA(trans) REG_BIT(9 + (trans) - TRANSCODER_A) 2736 #define DP_MST_SHORT_HBLANK_WA(trans) REG_BIT(5 + (trans) - TRANSCODER_A) 2737 #define DP_MST_FEC_BS_JITTER_WA(trans) REG_BIT(0 + (trans) - TRANSCODER_A) 2738 2739 #define CHICKEN_MISC_4 _MMIO(0x4208c) 2740 #define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13) 2741 #define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0) 2742 #define CHICKEN_FBC_STRIDE(x) REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x)) 2743 2744 #define _CHICKEN_PIPESL_1_A 0x420b0 2745 #define _CHICKEN_PIPESL_1_B 0x420b4 2746 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) 2747 #define HSW_PRI_STRETCH_MAX_MASK REG_GENMASK(28, 27) 2748 #define HSW_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0) 2749 #define HSW_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1) 2750 #define HSW_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2) 2751 #define HSW_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3) 2752 #define HSW_SPR_STRETCH_MAX_MASK REG_GENMASK(26, 25) 2753 #define HSW_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0) 2754 #define HSW_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1) 2755 #define HSW_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2) 2756 #define HSW_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3) 2757 #define HSW_FBCQ_DIS REG_BIT(22) 2758 #define HSW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(15) /* hsw */ 2759 #define SKL_PSR_MASK_PLANE_FLIP REG_BIT(11) /* skl+ */ 2760 #define SKL_PLANE1_STRETCH_MAX_MASK REG_GENMASK(1, 0) 2761 #define SKL_PLANE1_STRETCH_MAX_X8 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0) 2762 #define SKL_PLANE1_STRETCH_MAX_X4 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1) 2763 #define SKL_PLANE1_STRETCH_MAX_X2 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2) 2764 #define SKL_PLANE1_STRETCH_MAX_X1 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3) 2765 #define BDW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(0) /* bdw */ 2766 2767 #define _CHICKEN_TRANS_A 0x420c0 2768 #define _CHICKEN_TRANS_B 0x420c4 2769 #define _CHICKEN_TRANS_C 0x420c8 2770 #define _CHICKEN_TRANS_EDP 0x420cc 2771 #define _CHICKEN_TRANS_D 0x420d8 2772 #define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \ 2773 [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \ 2774 [TRANSCODER_A] = _CHICKEN_TRANS_A, \ 2775 [TRANSCODER_B] = _CHICKEN_TRANS_B, \ 2776 [TRANSCODER_C] = _CHICKEN_TRANS_C, \ 2777 [TRANSCODER_D] = _CHICKEN_TRANS_D)) 2778 #define _MTL_CHICKEN_TRANS_A 0x604e0 2779 #define _MTL_CHICKEN_TRANS_B 0x614e0 2780 #define MTL_CHICKEN_TRANS(trans) _MMIO_TRANS((trans), \ 2781 _MTL_CHICKEN_TRANS_A, \ 2782 _MTL_CHICKEN_TRANS_B) 2783 #define PIPE_VBLANK_WITH_DELAY REG_BIT(31) /* tgl+ */ 2784 #define SKL_UNMASK_VBL_TO_PIPE_IN_SRD REG_BIT(30) /* skl+ */ 2785 #define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) 2786 #define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x) 2787 #define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */ 2788 #define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23) 2789 #define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19) 2790 #define ADLP_1_BASED_X_GRANULARITY REG_BIT(18) 2791 #define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18) 2792 #define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */ 2793 #define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */ 2794 #define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15) 2795 #define DP_FEC_BS_JITTER_WA REG_BIT(15) 2796 #define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12) 2797 #define DP_DSC_INSERT_SF_AT_EOL_WA REG_BIT(4) 2798 #define HDCP_LINE_REKEY_DISABLE REG_BIT(0) 2799 2800 #define DISP_ARB_CTL _MMIO(0x45000) 2801 #define DISP_FBC_MEMORY_WAKE REG_BIT(31) 2802 #define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13) 2803 #define DISP_FBC_WM_DIS REG_BIT(15) 2804 2805 #define DISP_ARB_CTL2 _MMIO(0x45004) 2806 #define DISP_DATA_PARTITION_5_6 REG_BIT(6) 2807 #define DISP_IPC_ENABLE REG_BIT(3) 2808 2809 #define GEN7_MSG_CTL _MMIO(0x45010) 2810 #define WAIT_FOR_PCH_RESET_ACK (1 << 1) 2811 #define WAIT_FOR_PCH_FLR_ACK (1 << 0) 2812 2813 #define _BW_BUDDY0_CTL 0x45130 2814 #define _BW_BUDDY1_CTL 0x45140 2815 #define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \ 2816 _BW_BUDDY0_CTL, \ 2817 _BW_BUDDY1_CTL)) 2818 #define BW_BUDDY_DISABLE REG_BIT(31) 2819 #define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16) 2820 #define BW_BUDDY_TLB_REQ_TIMER(x) REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x) 2821 2822 #define _BW_BUDDY0_PAGE_MASK 0x45134 2823 #define _BW_BUDDY1_PAGE_MASK 0x45144 2824 #define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \ 2825 _BW_BUDDY0_PAGE_MASK, \ 2826 _BW_BUDDY1_PAGE_MASK)) 2827 2828 #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) 2829 #define MTL_RESET_PICA_HANDSHAKE_EN REG_BIT(6) 2830 #define RESET_PCH_HANDSHAKE_ENABLE REG_BIT(4) 2831 2832 #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) 2833 #define LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31) 2834 #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30) 2835 #define LATENCY_REPORTING_REMOVED_PIPE_C REG_BIT(25) 2836 #define LATENCY_REPORTING_REMOVED_PIPE_B REG_BIT(24) 2837 #define LATENCY_REPORTING_REMOVED_PIPE_A REG_BIT(23) 2838 #define ICL_DELAY_PMRSP REG_BIT(22) 2839 #define DISABLE_FLR_SRC REG_BIT(15) 2840 #define MASK_WAKEMEM REG_BIT(13) 2841 #define DDI_CLOCK_REG_ACCESS REG_BIT(7) 2842 2843 #define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434) 2844 #define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27) 2845 #define DCPR_MASK_LPMODE REG_BIT(26) 2846 #define DCPR_SEND_RESP_IMM REG_BIT(25) 2847 #define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24) 2848 2849 #define XELPD_CHICKEN_DCPR_3 _MMIO(0x46438) 2850 #define DMD_RSP_TIMEOUT_DISABLE REG_BIT(19) 2851 2852 #define SKL_DFSM _MMIO(0x51000) 2853 #define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27) 2854 #define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25) 2855 #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23) 2856 #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23) 2857 #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23) 2858 #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23) 2859 #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23) 2860 #define ICL_DFSM_DMC_DISABLE (1 << 23) 2861 #define SKL_DFSM_PIPE_A_DISABLE (1 << 30) 2862 #define SKL_DFSM_PIPE_B_DISABLE (1 << 21) 2863 #define SKL_DFSM_PIPE_C_DISABLE (1 << 28) 2864 #define TGL_DFSM_PIPE_D_DISABLE (1 << 22) 2865 #define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7) 2866 2867 #define XE2LPD_DE_CAP _MMIO(0x41100) 2868 #define XE2LPD_DE_CAP_3DLUT_MASK REG_GENMASK(31, 30) 2869 #define XE2LPD_DE_CAP_DSC_MASK REG_GENMASK(29, 28) 2870 #define XE2LPD_DE_CAP_DSC_REMOVED 1 2871 #define XE2LPD_DE_CAP_SCALER_MASK REG_GENMASK(27, 26) 2872 #define XE2LPD_DE_CAP_SCALER_SINGLE 1 2873 2874 #define SKL_DSSM _MMIO(0x51004) 2875 #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29) 2876 #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29) 2877 #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29) 2878 #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29) 2879 2880 #define GMD_ID_DISPLAY _MMIO(0x510a0) 2881 #define GMD_ID_ARCH_MASK REG_GENMASK(31, 22) 2882 #define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14) 2883 #define GMD_ID_STEP REG_GENMASK(5, 0) 2884 2885 /*GEN11 chicken */ 2886 #define _PIPEA_CHICKEN 0x70038 2887 #define _PIPEB_CHICKEN 0x71038 2888 #define _PIPEC_CHICKEN 0x72038 2889 #define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\ 2890 _PIPEB_CHICKEN) 2891 #define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30) 2892 #define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30) 2893 #define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15) 2894 #define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12) 2895 #define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7) 2896 2897 /* PCH */ 2898 2899 #define PCH_DISPLAY_BASE 0xc0000u 2900 2901 /* south display engine interrupt: IBX */ 2902 #define SDE_AUDIO_POWER_D (1 << 27) 2903 #define SDE_AUDIO_POWER_C (1 << 26) 2904 #define SDE_AUDIO_POWER_B (1 << 25) 2905 #define SDE_AUDIO_POWER_SHIFT (25) 2906 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) 2907 #define SDE_GMBUS (1 << 24) 2908 #define SDE_AUDIO_HDCP_TRANSB (1 << 23) 2909 #define SDE_AUDIO_HDCP_TRANSA (1 << 22) 2910 #define SDE_AUDIO_HDCP_MASK (3 << 22) 2911 #define SDE_AUDIO_TRANSB (1 << 21) 2912 #define SDE_AUDIO_TRANSA (1 << 20) 2913 #define SDE_AUDIO_TRANS_MASK (3 << 20) 2914 #define SDE_POISON (1 << 19) 2915 /* 18 reserved */ 2916 #define SDE_FDI_RXB (1 << 17) 2917 #define SDE_FDI_RXA (1 << 16) 2918 #define SDE_FDI_MASK (3 << 16) 2919 #define SDE_AUXD (1 << 15) 2920 #define SDE_AUXC (1 << 14) 2921 #define SDE_AUXB (1 << 13) 2922 #define SDE_AUX_MASK (7 << 13) 2923 /* 12 reserved */ 2924 #define SDE_CRT_HOTPLUG (1 << 11) 2925 #define SDE_PORTD_HOTPLUG (1 << 10) 2926 #define SDE_PORTC_HOTPLUG (1 << 9) 2927 #define SDE_PORTB_HOTPLUG (1 << 8) 2928 #define SDE_SDVOB_HOTPLUG (1 << 6) 2929 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \ 2930 SDE_SDVOB_HOTPLUG | \ 2931 SDE_PORTB_HOTPLUG | \ 2932 SDE_PORTC_HOTPLUG | \ 2933 SDE_PORTD_HOTPLUG) 2934 #define SDE_TRANSB_CRC_DONE (1 << 5) 2935 #define SDE_TRANSB_CRC_ERR (1 << 4) 2936 #define SDE_TRANSB_FIFO_UNDER (1 << 3) 2937 #define SDE_TRANSA_CRC_DONE (1 << 2) 2938 #define SDE_TRANSA_CRC_ERR (1 << 1) 2939 #define SDE_TRANSA_FIFO_UNDER (1 << 0) 2940 #define SDE_TRANS_MASK (0x3f) 2941 2942 /* south display engine interrupt: CPT - CNP */ 2943 #define SDE_AUDIO_POWER_D_CPT (1 << 31) 2944 #define SDE_AUDIO_POWER_C_CPT (1 << 30) 2945 #define SDE_AUDIO_POWER_B_CPT (1 << 29) 2946 #define SDE_AUDIO_POWER_SHIFT_CPT 29 2947 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29) 2948 #define SDE_AUXD_CPT (1 << 27) 2949 #define SDE_AUXC_CPT (1 << 26) 2950 #define SDE_AUXB_CPT (1 << 25) 2951 #define SDE_AUX_MASK_CPT (7 << 25) 2952 #define SDE_PORTE_HOTPLUG_SPT (1 << 25) 2953 #define SDE_PORTA_HOTPLUG_SPT (1 << 24) 2954 #define SDE_PORTD_HOTPLUG_CPT (1 << 23) 2955 #define SDE_PORTC_HOTPLUG_CPT (1 << 22) 2956 #define SDE_PORTB_HOTPLUG_CPT (1 << 21) 2957 #define SDE_CRT_HOTPLUG_CPT (1 << 19) 2958 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18) 2959 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ 2960 SDE_SDVOB_HOTPLUG_CPT | \ 2961 SDE_PORTD_HOTPLUG_CPT | \ 2962 SDE_PORTC_HOTPLUG_CPT | \ 2963 SDE_PORTB_HOTPLUG_CPT) 2964 #define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \ 2965 SDE_PORTD_HOTPLUG_CPT | \ 2966 SDE_PORTC_HOTPLUG_CPT | \ 2967 SDE_PORTB_HOTPLUG_CPT | \ 2968 SDE_PORTA_HOTPLUG_SPT) 2969 #define SDE_GMBUS_CPT (1 << 17) 2970 #define SDE_ERROR_CPT (1 << 16) 2971 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) 2972 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) 2973 #define SDE_FDI_RXC_CPT (1 << 8) 2974 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) 2975 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) 2976 #define SDE_FDI_RXB_CPT (1 << 4) 2977 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) 2978 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) 2979 #define SDE_FDI_RXA_CPT (1 << 0) 2980 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \ 2981 SDE_AUDIO_CP_REQ_B_CPT | \ 2982 SDE_AUDIO_CP_REQ_A_CPT) 2983 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \ 2984 SDE_AUDIO_CP_CHG_B_CPT | \ 2985 SDE_AUDIO_CP_CHG_A_CPT) 2986 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \ 2987 SDE_FDI_RXB_CPT | \ 2988 SDE_FDI_RXA_CPT) 2989 2990 /* south display engine interrupt: ICP/TGP/MTP */ 2991 #define SDE_PICAINTERRUPT REG_BIT(31) 2992 #define SDE_GMBUS_ICP (1 << 23) 2993 #define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin)) 2994 #define SDE_TC_HOTPLUG_DG2(hpd_pin) REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */ 2995 #define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin)) 2996 #define SDE_DDI_HOTPLUG_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \ 2997 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \ 2998 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \ 2999 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A)) 3000 #define SDE_TC_HOTPLUG_MASK_ICP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \ 3001 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \ 3002 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \ 3003 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \ 3004 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \ 3005 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1)) 3006 3007 #define SDEISR _MMIO(0xc4000) 3008 #define SDEIMR _MMIO(0xc4004) 3009 #define SDEIIR _MMIO(0xc4008) 3010 #define SDEIER _MMIO(0xc400c) 3011 3012 #define SERR_INT _MMIO(0xc4040) 3013 #define SERR_INT_POISON (1 << 31) 3014 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) 3015 3016 /* digital port hotplug */ 3017 #define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */ 3018 #define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */ 3019 #define BXT_DDIA_HPD_INVERT (1 << 27) 3020 #define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */ 3021 #define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */ 3022 #define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */ 3023 #define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */ 3024 #define PORTD_HOTPLUG_ENABLE (1 << 20) 3025 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */ 3026 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */ 3027 #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */ 3028 #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */ 3029 #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */ 3030 #define PORTD_HOTPLUG_STATUS_MASK (3 << 16) 3031 #define PORTD_HOTPLUG_NO_DETECT (0 << 16) 3032 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) 3033 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16) 3034 #define PORTC_HOTPLUG_ENABLE (1 << 12) 3035 #define BXT_DDIC_HPD_INVERT (1 << 11) 3036 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */ 3037 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */ 3038 #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */ 3039 #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */ 3040 #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */ 3041 #define PORTC_HOTPLUG_STATUS_MASK (3 << 8) 3042 #define PORTC_HOTPLUG_NO_DETECT (0 << 8) 3043 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) 3044 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8) 3045 #define PORTB_HOTPLUG_ENABLE (1 << 4) 3046 #define BXT_DDIB_HPD_INVERT (1 << 3) 3047 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */ 3048 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */ 3049 #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */ 3050 #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */ 3051 #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */ 3052 #define PORTB_HOTPLUG_STATUS_MASK (3 << 0) 3053 #define PORTB_HOTPLUG_NO_DETECT (0 << 0) 3054 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) 3055 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0) 3056 #define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \ 3057 BXT_DDIB_HPD_INVERT | \ 3058 BXT_DDIC_HPD_INVERT) 3059 3060 #define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */ 3061 #define PORTE_HOTPLUG_ENABLE (1 << 4) 3062 #define PORTE_HOTPLUG_STATUS_MASK (3 << 0) 3063 #define PORTE_HOTPLUG_NO_DETECT (0 << 0) 3064 #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0) 3065 #define PORTE_HOTPLUG_LONG_DETECT (2 << 0) 3066 3067 /* This register is a reuse of PCH_PORT_HOTPLUG register. The 3068 * functionality covered in PCH_PORT_HOTPLUG is split into 3069 * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC. 3070 */ 3071 3072 #define SHOTPLUG_CTL_DDI _MMIO(0xc4030) 3073 #define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (_HPD_PIN_DDI(hpd_pin) * 4)) 3074 #define SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(hpd_pin) (0x4 << (_HPD_PIN_DDI(hpd_pin) * 4)) 3075 #define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4)) 3076 #define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin) (0x0 << (_HPD_PIN_DDI(hpd_pin) * 4)) 3077 #define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin) (0x1 << (_HPD_PIN_DDI(hpd_pin) * 4)) 3078 #define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin) (0x2 << (_HPD_PIN_DDI(hpd_pin) * 4)) 3079 #define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4)) 3080 3081 #define SHOTPLUG_CTL_TC _MMIO(0xc4034) 3082 #define ICP_TC_HPD_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4)) 3083 #define ICP_TC_HPD_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4)) 3084 #define ICP_TC_HPD_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4)) 3085 3086 #define SHPD_FILTER_CNT _MMIO(0xc4038) 3087 #define SHPD_FILTER_CNT_500_ADJ 0x001D9 3088 #define SHPD_FILTER_CNT_250 0x000F8 3089 3090 #define _PCH_DPLL_A 0xc6014 3091 #define _PCH_DPLL_B 0xc6018 3092 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) 3093 3094 #define _PCH_FPA0 0xc6040 3095 #define FP_CB_TUNE (0x3 << 22) 3096 #define _PCH_FPA1 0xc6044 3097 #define _PCH_FPB0 0xc6048 3098 #define _PCH_FPB1 0xc604c 3099 #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0) 3100 #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1) 3101 3102 #define PCH_DPLL_TEST _MMIO(0xc606c) 3103 3104 #define PCH_DREF_CONTROL _MMIO(0xC6200) 3105 #define DREF_CONTROL_MASK 0x7fc3 3106 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13) 3107 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13) 3108 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13) 3109 #define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13) 3110 #define DREF_SSC_SOURCE_DISABLE (0 << 11) 3111 #define DREF_SSC_SOURCE_ENABLE (2 << 11) 3112 #define DREF_SSC_SOURCE_MASK (3 << 11) 3113 #define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9) 3114 #define DREF_NONSPREAD_CK505_ENABLE (1 << 9) 3115 #define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9) 3116 #define DREF_NONSPREAD_SOURCE_MASK (3 << 9) 3117 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7) 3118 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7) 3119 #define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7) 3120 #define DREF_SSC4_DOWNSPREAD (0 << 6) 3121 #define DREF_SSC4_CENTERSPREAD (1 << 6) 3122 #define DREF_SSC1_DISABLE (0 << 1) 3123 #define DREF_SSC1_ENABLE (1 << 1) 3124 #define DREF_SSC4_DISABLE (0) 3125 #define DREF_SSC4_ENABLE (1) 3126 3127 #define PCH_RAWCLK_FREQ _MMIO(0xc6204) 3128 #define FDL_TP1_TIMER_SHIFT 12 3129 #define FDL_TP1_TIMER_MASK (3 << 12) 3130 #define FDL_TP2_TIMER_SHIFT 10 3131 #define FDL_TP2_TIMER_MASK (3 << 10) 3132 #define RAWCLK_FREQ_MASK 0x3ff 3133 #define CNP_RAWCLK_DIV_MASK (0x3ff << 16) 3134 #define CNP_RAWCLK_DIV(div) ((div) << 16) 3135 #define CNP_RAWCLK_FRAC_MASK (0xf << 26) 3136 #define CNP_RAWCLK_DEN(den) ((den) << 26) 3137 #define ICP_RAWCLK_NUM(num) ((num) << 11) 3138 3139 #define PCH_DPLL_TMR_CFG _MMIO(0xc6208) 3140 3141 #define PCH_SSC4_PARMS _MMIO(0xc6210) 3142 #define PCH_SSC4_AUX_PARMS _MMIO(0xc6214) 3143 3144 #define PCH_DPLL_SEL _MMIO(0xc7000) 3145 #define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4)) 3146 #define TRANS_DPLLA_SEL(pipe) 0 3147 #define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3)) 3148 3149 /* transcoder */ 3150 3151 #define _PCH_TRANS_HTOTAL_A 0xe0000 3152 #define TRANS_HTOTAL_SHIFT 16 3153 #define TRANS_HACTIVE_SHIFT 0 3154 #define _PCH_TRANS_HBLANK_A 0xe0004 3155 #define TRANS_HBLANK_END_SHIFT 16 3156 #define TRANS_HBLANK_START_SHIFT 0 3157 #define _PCH_TRANS_HSYNC_A 0xe0008 3158 #define TRANS_HSYNC_END_SHIFT 16 3159 #define TRANS_HSYNC_START_SHIFT 0 3160 #define _PCH_TRANS_VTOTAL_A 0xe000c 3161 #define TRANS_VTOTAL_SHIFT 16 3162 #define TRANS_VACTIVE_SHIFT 0 3163 #define _PCH_TRANS_VBLANK_A 0xe0010 3164 #define TRANS_VBLANK_END_SHIFT 16 3165 #define TRANS_VBLANK_START_SHIFT 0 3166 #define _PCH_TRANS_VSYNC_A 0xe0014 3167 #define TRANS_VSYNC_END_SHIFT 16 3168 #define TRANS_VSYNC_START_SHIFT 0 3169 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028 3170 3171 #define _PCH_TRANSA_DATA_M1 0xe0030 3172 #define _PCH_TRANSA_DATA_N1 0xe0034 3173 #define _PCH_TRANSA_DATA_M2 0xe0038 3174 #define _PCH_TRANSA_DATA_N2 0xe003c 3175 #define _PCH_TRANSA_LINK_M1 0xe0040 3176 #define _PCH_TRANSA_LINK_N1 0xe0044 3177 #define _PCH_TRANSA_LINK_M2 0xe0048 3178 #define _PCH_TRANSA_LINK_N2 0xe004c 3179 3180 /* Per-transcoder DIP controls (PCH) */ 3181 #define _VIDEO_DIP_CTL_A 0xe0200 3182 #define _VIDEO_DIP_DATA_A 0xe0208 3183 #define _VIDEO_DIP_GCP_A 0xe0210 3184 #define GCP_COLOR_INDICATION (1 << 2) 3185 #define GCP_DEFAULT_PHASE_ENABLE (1 << 1) 3186 #define GCP_AV_MUTE (1 << 0) 3187 3188 #define _VIDEO_DIP_CTL_B 0xe1200 3189 #define _VIDEO_DIP_DATA_B 0xe1208 3190 #define _VIDEO_DIP_GCP_B 0xe1210 3191 3192 #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) 3193 #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) 3194 #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) 3195 3196 /* Per-transcoder DIP controls (VLV) */ 3197 #define _VLV_VIDEO_DIP_CTL_A 0x60200 3198 #define _VLV_VIDEO_DIP_CTL_B 0x61170 3199 #define _CHV_VIDEO_DIP_CTL_C 0x611f0 3200 #define VLV_TVIDEO_DIP_CTL(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \ 3201 _VLV_VIDEO_DIP_CTL_A, \ 3202 _VLV_VIDEO_DIP_CTL_B, \ 3203 _CHV_VIDEO_DIP_CTL_C) 3204 3205 #define _VLV_VIDEO_DIP_DATA_A 0x60208 3206 #define _VLV_VIDEO_DIP_DATA_B 0x61174 3207 #define _CHV_VIDEO_DIP_DATA_C 0x611f4 3208 #define VLV_TVIDEO_DIP_DATA(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \ 3209 _VLV_VIDEO_DIP_DATA_A, \ 3210 _VLV_VIDEO_DIP_DATA_B, \ 3211 _CHV_VIDEO_DIP_DATA_C) 3212 3213 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A 0x60210 3214 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B 0x61178 3215 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C 0x611f8 3216 #define VLV_TVIDEO_DIP_GCP(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \ 3217 _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \ 3218 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, \ 3219 _CHV_VIDEO_DIP_GDCP_PAYLOAD_C) 3220 3221 /* Haswell DIP controls */ 3222 3223 #define _HSW_VIDEO_DIP_CTL_A 0x60200 3224 #define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220 3225 #define _HSW_VIDEO_DIP_VS_DATA_A 0x60260 3226 #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 3227 #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 3228 #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320 3229 #define _ADL_VIDEO_DIP_AS_DATA_A 0x60484 3230 #define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440 3231 #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240 3232 #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280 3233 #define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 3234 #define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300 3235 #define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344 3236 #define _HSW_VIDEO_DIP_GCP_A 0x60210 3237 3238 #define _HSW_VIDEO_DIP_CTL_B 0x61200 3239 #define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220 3240 #define _HSW_VIDEO_DIP_VS_DATA_B 0x61260 3241 #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 3242 #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 3243 #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320 3244 #define _ADL_VIDEO_DIP_AS_DATA_B 0x61484 3245 #define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440 3246 #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240 3247 #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280 3248 #define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 3249 #define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300 3250 #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344 3251 #define _HSW_VIDEO_DIP_GCP_B 0x61210 3252 3253 /* Icelake PPS_DATA and _ECC DIP Registers. 3254 * These are available for transcoders B,C and eDP. 3255 * Adding the _A so as to reuse the _MMIO_TRANS2 3256 * definition, with which it offsets to the right location. 3257 */ 3258 3259 #define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350 3260 #define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350 3261 #define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4 3262 #define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4 3263 3264 #define HSW_TVIDEO_DIP_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_CTL_A) 3265 #define HSW_TVIDEO_DIP_GCP(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GCP_A) 3266 #define HSW_TVIDEO_DIP_AVI_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4) 3267 #define HSW_TVIDEO_DIP_VS_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4) 3268 #define HSW_TVIDEO_DIP_SPD_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) 3269 #define HSW_TVIDEO_DIP_GMP_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4) 3270 #define HSW_TVIDEO_DIP_VSC_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) 3271 #define GLK_TVIDEO_DIP_DRM_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4) 3272 #define ICL_VIDEO_DIP_PPS_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4) 3273 #define ICL_VIDEO_DIP_PPS_ECC(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4) 3274 /*ADLP and later: */ 3275 #define ADL_TVIDEO_DIP_AS_SDP_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans,\ 3276 _ADL_VIDEO_DIP_AS_DATA_A + (i) * 4) 3277 3278 #define _HSW_STEREO_3D_CTL_A 0x70020 3279 #define S3D_ENABLE (1 << 31) 3280 #define _HSW_STEREO_3D_CTL_B 0x71020 3281 3282 #define HSW_STEREO_3D_CTL(dev_priv, trans) _MMIO_PIPE2(dev_priv, trans, _HSW_STEREO_3D_CTL_A) 3283 3284 #define _PCH_TRANS_HTOTAL_B 0xe1000 3285 #define _PCH_TRANS_HBLANK_B 0xe1004 3286 #define _PCH_TRANS_HSYNC_B 0xe1008 3287 #define _PCH_TRANS_VTOTAL_B 0xe100c 3288 #define _PCH_TRANS_VBLANK_B 0xe1010 3289 #define _PCH_TRANS_VSYNC_B 0xe1014 3290 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 3291 3292 #define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B) 3293 #define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B) 3294 #define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B) 3295 #define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B) 3296 #define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B) 3297 #define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B) 3298 #define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B) 3299 3300 #define _PCH_TRANSB_DATA_M1 0xe1030 3301 #define _PCH_TRANSB_DATA_N1 0xe1034 3302 #define _PCH_TRANSB_DATA_M2 0xe1038 3303 #define _PCH_TRANSB_DATA_N2 0xe103c 3304 #define _PCH_TRANSB_LINK_M1 0xe1040 3305 #define _PCH_TRANSB_LINK_N1 0xe1044 3306 #define _PCH_TRANSB_LINK_M2 0xe1048 3307 #define _PCH_TRANSB_LINK_N2 0xe104c 3308 3309 #define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1) 3310 #define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1) 3311 #define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2) 3312 #define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2) 3313 #define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1) 3314 #define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1) 3315 #define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2) 3316 #define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2) 3317 3318 #define _PCH_TRANSACONF 0xf0008 3319 #define _PCH_TRANSBCONF 0xf1008 3320 #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF) 3321 #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */ 3322 #define TRANS_ENABLE REG_BIT(31) 3323 #define TRANS_STATE_ENABLE REG_BIT(30) 3324 #define TRANS_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* ibx */ 3325 #define TRANS_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */ 3326 #define TRANS_INTERLACE_MASK REG_GENMASK(23, 21) 3327 #define TRANS_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0) 3328 #define TRANS_INTERLACE_LEGACY_VSYNC_IBX REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */ 3329 #define TRANS_INTERLACE_INTERLACED REG_FIELD_PREP(TRANS_INTERLACE_MASK, 3) 3330 #define TRANS_BPC_MASK REG_GENMASK(7, 5) /* ibx */ 3331 #define TRANS_BPC_8 REG_FIELD_PREP(TRANS_BPC_MASK, 0) 3332 #define TRANS_BPC_10 REG_FIELD_PREP(TRANS_BPC_MASK, 1) 3333 #define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2) 3334 #define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, 3) 3335 3336 #define _TRANSA_CHICKEN1 0xf0060 3337 #define _TRANSB_CHICKEN1 0xf1060 3338 #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) 3339 #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE REG_BIT(10) 3340 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE REG_BIT(4) 3341 3342 #define _TRANSA_CHICKEN2 0xf0064 3343 #define _TRANSB_CHICKEN2 0xf1064 3344 #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) 3345 #define TRANS_CHICKEN2_TIMING_OVERRIDE REG_BIT(31) 3346 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED REG_BIT(29) 3347 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) 3348 #define TRANS_CHICKEN2_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */ 3349 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER REG_BIT(26) 3350 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH REG_BIT(25) 3351 3352 #define SOUTH_CHICKEN1 _MMIO(0xc2000) 3353 #define FDIA_PHASE_SYNC_SHIFT_OVR 19 3354 #define FDIA_PHASE_SYNC_SHIFT_EN 18 3355 #define INVERT_DDIE_HPD REG_BIT(28) 3356 #define INVERT_DDID_HPD_MTP REG_BIT(27) 3357 #define INVERT_TC4_HPD REG_BIT(26) 3358 #define INVERT_TC3_HPD REG_BIT(25) 3359 #define INVERT_TC2_HPD REG_BIT(24) 3360 #define INVERT_TC1_HPD REG_BIT(23) 3361 #define INVERT_DDID_HPD (1 << 18) 3362 #define INVERT_DDIC_HPD (1 << 17) 3363 #define INVERT_DDIB_HPD (1 << 16) 3364 #define INVERT_DDIA_HPD (1 << 15) 3365 #define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) 3366 #define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) 3367 #define FDI_BC_BIFURCATION_SELECT (1 << 12) 3368 #define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8) 3369 #define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8) 3370 #define SBCLK_RUN_REFCLK_DIS (1 << 7) 3371 #define ICP_SECOND_PPS_IO_SELECT REG_BIT(2) 3372 #define SPT_PWM_GRANULARITY (1 << 0) 3373 #define SOUTH_CHICKEN2 _MMIO(0xc2004) 3374 #define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13) 3375 #define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12) 3376 #define LPT_PWM_GRANULARITY (1 << 5) 3377 #define DPLS_EDP_PPS_FIX_DIS (1 << 0) 3378 3379 #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020) 3380 #define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31) 3381 #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30) 3382 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29) 3383 #define PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15) 3384 #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14) 3385 #define CNP_PWM_CGE_GATING_DISABLE (1 << 13) 3386 #define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12) 3387 3388 #define PCH_DP_B _MMIO(0xe4100) 3389 #define PCH_DP_C _MMIO(0xe4200) 3390 #define PCH_DP_D _MMIO(0xe4300) 3391 3392 /* CPT */ 3393 #define _TRANS_DP_CTL_A 0xe0300 3394 #define _TRANS_DP_CTL_B 0xe1300 3395 #define _TRANS_DP_CTL_C 0xe2300 3396 #define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B) 3397 #define TRANS_DP_OUTPUT_ENABLE REG_BIT(31) 3398 #define TRANS_DP_PORT_SEL_MASK REG_GENMASK(30, 29) 3399 #define TRANS_DP_PORT_SEL_NONE REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, 3) 3400 #define TRANS_DP_PORT_SEL(port) REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B) 3401 #define TRANS_DP_AUDIO_ONLY REG_BIT(26) 3402 #define TRANS_DP_ENH_FRAMING REG_BIT(18) 3403 #define TRANS_DP_BPC_MASK REG_GENMASK(10, 9) 3404 #define TRANS_DP_BPC_8 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0) 3405 #define TRANS_DP_BPC_10 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 1) 3406 #define TRANS_DP_BPC_6 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 2) 3407 #define TRANS_DP_BPC_12 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 3) 3408 #define TRANS_DP_VSYNC_ACTIVE_HIGH REG_BIT(4) 3409 #define TRANS_DP_HSYNC_ACTIVE_HIGH REG_BIT(3) 3410 3411 #define _TRANS_DP2_CTL_A 0x600a0 3412 #define _TRANS_DP2_CTL_B 0x610a0 3413 #define _TRANS_DP2_CTL_C 0x620a0 3414 #define _TRANS_DP2_CTL_D 0x630a0 3415 #define TRANS_DP2_CTL(trans) _MMIO_TRANS(trans, _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B) 3416 #define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31) 3417 #define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30) 3418 #define TRANS_DP2_DEBUG_ENABLE REG_BIT(23) 3419 3420 #define _TRANS_DP2_VFREQHIGH_A 0x600a4 3421 #define _TRANS_DP2_VFREQHIGH_B 0x610a4 3422 #define _TRANS_DP2_VFREQHIGH_C 0x620a4 3423 #define _TRANS_DP2_VFREQHIGH_D 0x630a4 3424 #define TRANS_DP2_VFREQHIGH(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQHIGH_A, _TRANS_DP2_VFREQHIGH_B) 3425 #define TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK REG_GENMASK(31, 8) 3426 #define TRANS_DP2_VFREQ_PIXEL_CLOCK(clk_hz) REG_FIELD_PREP(TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK, (clk_hz)) 3427 3428 #define _TRANS_DP2_VFREQLOW_A 0x600a8 3429 #define _TRANS_DP2_VFREQLOW_B 0x610a8 3430 #define _TRANS_DP2_VFREQLOW_C 0x620a8 3431 #define _TRANS_DP2_VFREQLOW_D 0x630a8 3432 #define TRANS_DP2_VFREQLOW(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQLOW_A, _TRANS_DP2_VFREQLOW_B) 3433 3434 /* SNB eDP training params */ 3435 /* SNB A-stepping */ 3436 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) 3437 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) 3438 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) 3439 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22) 3440 /* SNB B-stepping */ 3441 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22) 3442 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22) 3443 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22) 3444 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22) 3445 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22) 3446 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22) 3447 3448 /* IVB */ 3449 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22) 3450 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22) 3451 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22) 3452 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22) 3453 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22) 3454 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22) 3455 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22) 3456 3457 /* legacy values */ 3458 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22) 3459 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22) 3460 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22) 3461 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22) 3462 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22) 3463 3464 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22) 3465 3466 #define VLV_PMWGICZ _MMIO(0x1300a4) 3467 3468 #define HSW_EDRAM_CAP _MMIO(0x120010) 3469 #define EDRAM_ENABLED 0x1 3470 #define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf) 3471 #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7) 3472 #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3) 3473 3474 #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C) 3475 #define PIXEL_OVERLAP_CNT_MASK (3 << 30) 3476 #define PIXEL_OVERLAP_CNT_SHIFT 30 3477 3478 #define GEN6_PCODE_MAILBOX _MMIO(0x138124) 3479 #define GEN6_PCODE_READY (1 << 31) 3480 #define GEN6_PCODE_MB_PARAM2 REG_GENMASK(23, 16) 3481 #define GEN6_PCODE_MB_PARAM1 REG_GENMASK(15, 8) 3482 #define GEN6_PCODE_MB_COMMAND REG_GENMASK(7, 0) 3483 #define GEN6_PCODE_ERROR_MASK 0xFF 3484 #define GEN6_PCODE_SUCCESS 0x0 3485 #define GEN6_PCODE_ILLEGAL_CMD 0x1 3486 #define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2 3487 #define GEN6_PCODE_TIMEOUT 0x3 3488 #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF 3489 #define GEN7_PCODE_TIMEOUT 0x2 3490 #define GEN7_PCODE_ILLEGAL_DATA 0x3 3491 #define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4 3492 #define GEN11_PCODE_LOCKED 0x6 3493 #define GEN11_PCODE_REJECTED 0x11 3494 #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10 3495 #define GEN6_PCODE_WRITE_RC6VIDS 0x4 3496 #define GEN6_PCODE_READ_RC6VIDS 0x5 3497 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) 3498 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) 3499 #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18 3500 #define GEN9_PCODE_READ_MEM_LATENCY 0x6 3501 #define GEN9_MEM_LATENCY_LEVEL_3_7_MASK REG_GENMASK(31, 24) 3502 #define GEN9_MEM_LATENCY_LEVEL_2_6_MASK REG_GENMASK(23, 16) 3503 #define GEN9_MEM_LATENCY_LEVEL_1_5_MASK REG_GENMASK(15, 8) 3504 #define GEN9_MEM_LATENCY_LEVEL_0_4_MASK REG_GENMASK(7, 0) 3505 #define SKL_PCODE_LOAD_HDCP_KEYS 0x5 3506 #define SKL_PCODE_CDCLK_CONTROL 0x7 3507 #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3 3508 #define SKL_CDCLK_READY_FOR_CHANGE 0x1 3509 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 3510 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 3511 #define GEN6_READ_OC_PARAMS 0xc 3512 #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd 3513 #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8) 3514 #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8)) 3515 #define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO ((0) | (0x2 << 8)) 3516 #define DISPLAY_TO_PCODE_CDCLK_MAX 0x28D 3517 #define DISPLAY_TO_PCODE_VOLTAGE_MASK REG_GENMASK(1, 0) 3518 #define DISPLAY_TO_PCODE_VOLTAGE_MAX DISPLAY_TO_PCODE_VOLTAGE_MASK 3519 #define DISPLAY_TO_PCODE_CDCLK_VALID REG_BIT(27) 3520 #define DISPLAY_TO_PCODE_PIPE_COUNT_VALID REG_BIT(31) 3521 #define DISPLAY_TO_PCODE_CDCLK_MASK REG_GENMASK(25, 16) 3522 #define DISPLAY_TO_PCODE_PIPE_COUNT_MASK REG_GENMASK(30, 28) 3523 #define DISPLAY_TO_PCODE_CDCLK(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_CDCLK_MASK, (x)) 3524 #define DISPLAY_TO_PCODE_PIPE_COUNT(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_PIPE_COUNT_MASK, (x)) 3525 #define DISPLAY_TO_PCODE_VOLTAGE(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_VOLTAGE_MASK, (x)) 3526 #define DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes, voltage_level) \ 3527 ((DISPLAY_TO_PCODE_CDCLK(cdclk)) | \ 3528 (DISPLAY_TO_PCODE_PIPE_COUNT(num_pipes)) | \ 3529 (DISPLAY_TO_PCODE_VOLTAGE(voltage_level))) 3530 #define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe 3531 #define ICL_PCODE_REP_QGV_MASK REG_GENMASK(1, 0) 3532 #define ICL_PCODE_REP_QGV_SAFE REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0) 3533 #define ICL_PCODE_REP_QGV_POLL REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1) 3534 #define ICL_PCODE_REP_QGV_REJECTED REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2) 3535 #define ADLS_PCODE_REP_PSF_MASK REG_GENMASK(3, 2) 3536 #define ADLS_PCODE_REP_PSF_SAFE REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0) 3537 #define ADLS_PCODE_REP_PSF_POLL REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1) 3538 #define ADLS_PCODE_REP_PSF_REJECTED REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2) 3539 #define ICL_PCODE_REQ_QGV_PT_MASK REG_GENMASK(7, 0) 3540 #define ICL_PCODE_REQ_QGV_PT(x) REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x)) 3541 #define ADLS_PCODE_REQ_PSF_PT_MASK REG_GENMASK(10, 8) 3542 #define ADLS_PCODE_REQ_PSF_PT(x) REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x)) 3543 #define GEN6_PCODE_READ_D_COMP 0x10 3544 #define GEN6_PCODE_WRITE_D_COMP 0x11 3545 #define ICL_PCODE_EXIT_TCCOLD 0x12 3546 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17 3547 #define DISPLAY_IPS_CONTROL 0x19 3548 #define TGL_PCODE_TCCOLD 0x26 3549 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0) 3550 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0 3551 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0) 3552 /* See also IPS_CTL */ 3553 #define IPS_PCODE_CONTROL (1 << 30) 3554 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A 3555 #define GEN9_PCODE_SAGV_CONTROL 0x21 3556 #define GEN9_SAGV_DISABLE 0x0 3557 #define GEN9_SAGV_IS_DISABLED 0x1 3558 #define GEN9_SAGV_ENABLE 0x3 3559 #define DG1_PCODE_STATUS 0x7E 3560 #define DG1_UNCORE_GET_INIT_STATUS 0x0 3561 #define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1 3562 #define PCODE_POWER_SETUP 0x7C 3563 #define POWER_SETUP_SUBCOMMAND_READ_I1 0x4 3564 #define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5 3565 #define POWER_SETUP_I1_WATTS REG_BIT(31) 3566 #define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */ 3567 #define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0) 3568 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23 3569 #define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* pvc */ 3570 /* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */ 3571 #define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0 3572 #define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1 3573 /* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */ 3574 /* XEHP_PCODE_FREQUENCY_CONFIG param2 */ 3575 #define PCODE_MBOX_DOMAIN_NONE 0x0 3576 #define PCODE_MBOX_DOMAIN_MEDIAFF 0x3 3577 #define GEN6_PCODE_DATA _MMIO(0x138128) 3578 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 3579 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 3580 #define GEN6_PCODE_DATA1 _MMIO(0x13812C) 3581 3582 #define MTL_PCODE_STOLEN_ACCESS _MMIO(0x138914) 3583 #define STOLEN_ACCESS_ALLOWED 0x1 3584 3585 /* IVYBRIDGE DPF */ 3586 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */ 3587 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14) 3588 #define GEN7_PARITY_ERROR_VALID (1 << 13) 3589 #define GEN7_L3CDERRST1_BANK_MASK (3 << 11) 3590 #define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8) 3591 #define GEN7_PARITY_ERROR_ROW(reg) \ 3592 (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14) 3593 #define GEN7_PARITY_ERROR_BANK(reg) \ 3594 (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11) 3595 #define GEN7_PARITY_ERROR_SUBBANK(reg) \ 3596 (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) 3597 #define GEN7_L3CDERRST1_ENABLE (1 << 7) 3598 3599 /* These are the 4 32-bit write offset registers for each stream 3600 * output buffer. It determines the offset from the 3601 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. 3602 */ 3603 #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4) 3604 3605 /* 3606 * HSW - ICL power wells 3607 * 3608 * Platforms have up to 3 power well control register sets, each set 3609 * controlling up to 16 power wells via a request/status HW flag tuple: 3610 * - main (HSW_PWR_WELL_CTL[1-4]) 3611 * - AUX (ICL_PWR_WELL_CTL_AUX[1-4]) 3612 * - DDI (ICL_PWR_WELL_CTL_DDI[1-4]) 3613 * Each control register set consists of up to 4 registers used by different 3614 * sources that can request a power well to be enabled: 3615 * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1) 3616 * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2) 3617 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set) 3618 * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4) 3619 */ 3620 #define HSW_PWR_WELL_CTL1 _MMIO(0x45400) 3621 #define HSW_PWR_WELL_CTL2 _MMIO(0x45404) 3622 #define HSW_PWR_WELL_CTL3 _MMIO(0x45408) 3623 #define HSW_PWR_WELL_CTL4 _MMIO(0x4540C) 3624 #define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2)) 3625 #define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2)) 3626 3627 /* HSW/BDW power well */ 3628 #define HSW_PW_CTL_IDX_GLOBAL 15 3629 3630 /* SKL/BXT/GLK power wells */ 3631 #define SKL_PW_CTL_IDX_PW_2 15 3632 #define SKL_PW_CTL_IDX_PW_1 14 3633 #define GLK_PW_CTL_IDX_AUX_C 10 3634 #define GLK_PW_CTL_IDX_AUX_B 9 3635 #define GLK_PW_CTL_IDX_AUX_A 8 3636 #define SKL_PW_CTL_IDX_DDI_D 4 3637 #define SKL_PW_CTL_IDX_DDI_C 3 3638 #define SKL_PW_CTL_IDX_DDI_B 2 3639 #define SKL_PW_CTL_IDX_DDI_A_E 1 3640 #define GLK_PW_CTL_IDX_DDI_A 1 3641 #define SKL_PW_CTL_IDX_MISC_IO 0 3642 3643 /* ICL/TGL - power wells */ 3644 #define TGL_PW_CTL_IDX_PW_5 4 3645 #define ICL_PW_CTL_IDX_PW_4 3 3646 #define ICL_PW_CTL_IDX_PW_3 2 3647 #define ICL_PW_CTL_IDX_PW_2 1 3648 #define ICL_PW_CTL_IDX_PW_1 0 3649 3650 /* XE_LPD - power wells */ 3651 #define XELPD_PW_CTL_IDX_PW_D 8 3652 #define XELPD_PW_CTL_IDX_PW_C 7 3653 #define XELPD_PW_CTL_IDX_PW_B 6 3654 #define XELPD_PW_CTL_IDX_PW_A 5 3655 3656 #define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440) 3657 #define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444) 3658 #define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C) 3659 #define TGL_PW_CTL_IDX_AUX_TBT6 14 3660 #define TGL_PW_CTL_IDX_AUX_TBT5 13 3661 #define TGL_PW_CTL_IDX_AUX_TBT4 12 3662 #define ICL_PW_CTL_IDX_AUX_TBT4 11 3663 #define TGL_PW_CTL_IDX_AUX_TBT3 11 3664 #define ICL_PW_CTL_IDX_AUX_TBT3 10 3665 #define TGL_PW_CTL_IDX_AUX_TBT2 10 3666 #define ICL_PW_CTL_IDX_AUX_TBT2 9 3667 #define TGL_PW_CTL_IDX_AUX_TBT1 9 3668 #define ICL_PW_CTL_IDX_AUX_TBT1 8 3669 #define TGL_PW_CTL_IDX_AUX_TC6 8 3670 #define XELPD_PW_CTL_IDX_AUX_E 8 3671 #define TGL_PW_CTL_IDX_AUX_TC5 7 3672 #define XELPD_PW_CTL_IDX_AUX_D 7 3673 #define TGL_PW_CTL_IDX_AUX_TC4 6 3674 #define ICL_PW_CTL_IDX_AUX_F 5 3675 #define TGL_PW_CTL_IDX_AUX_TC3 5 3676 #define ICL_PW_CTL_IDX_AUX_E 4 3677 #define TGL_PW_CTL_IDX_AUX_TC2 4 3678 #define ICL_PW_CTL_IDX_AUX_D 3 3679 #define TGL_PW_CTL_IDX_AUX_TC1 3 3680 #define ICL_PW_CTL_IDX_AUX_C 2 3681 #define ICL_PW_CTL_IDX_AUX_B 1 3682 #define ICL_PW_CTL_IDX_AUX_A 0 3683 3684 #define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450) 3685 #define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454) 3686 #define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C) 3687 #define XELPD_PW_CTL_IDX_DDI_E 8 3688 #define TGL_PW_CTL_IDX_DDI_TC6 8 3689 #define XELPD_PW_CTL_IDX_DDI_D 7 3690 #define TGL_PW_CTL_IDX_DDI_TC5 7 3691 #define TGL_PW_CTL_IDX_DDI_TC4 6 3692 #define ICL_PW_CTL_IDX_DDI_F 5 3693 #define TGL_PW_CTL_IDX_DDI_TC3 5 3694 #define ICL_PW_CTL_IDX_DDI_E 4 3695 #define TGL_PW_CTL_IDX_DDI_TC2 4 3696 #define ICL_PW_CTL_IDX_DDI_D 3 3697 #define TGL_PW_CTL_IDX_DDI_TC1 3 3698 #define ICL_PW_CTL_IDX_DDI_C 2 3699 #define ICL_PW_CTL_IDX_DDI_B 1 3700 #define ICL_PW_CTL_IDX_DDI_A 0 3701 3702 /* HSW - power well misc debug registers */ 3703 #define HSW_PWR_WELL_CTL5 _MMIO(0x45410) 3704 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31) 3705 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20) 3706 #define HSW_PWR_WELL_FORCE_ON (1 << 19) 3707 #define HSW_PWR_WELL_CTL6 _MMIO(0x45414) 3708 3709 /* SKL Fuse Status */ 3710 enum skl_power_gate { 3711 SKL_PG0, 3712 SKL_PG1, 3713 SKL_PG2, 3714 ICL_PG3, 3715 ICL_PG4, 3716 }; 3717 3718 #define SKL_FUSE_STATUS _MMIO(0x42000) 3719 #define SKL_FUSE_DOWNLOAD_STATUS (1 << 31) 3720 /* 3721 * PG0 is HW controlled, so doesn't have a corresponding power well control knob 3722 * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2 3723 */ 3724 #define SKL_PW_CTL_IDX_TO_PG(pw_idx) \ 3725 ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1) 3726 /* 3727 * PG0 is HW controlled, so doesn't have a corresponding power well control knob 3728 * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4 3729 */ 3730 #define ICL_PW_CTL_IDX_TO_PG(pw_idx) \ 3731 ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1) 3732 #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg))) 3733 3734 /* Per-pipe DDI Function Control */ 3735 #define _TRANS_DDI_FUNC_CTL_A 0x60400 3736 #define _TRANS_DDI_FUNC_CTL_B 0x61400 3737 #define _TRANS_DDI_FUNC_CTL_C 0x62400 3738 #define _TRANS_DDI_FUNC_CTL_D 0x63400 3739 #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400 3740 #define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400 3741 #define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00 3742 #define TRANS_DDI_FUNC_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL_A) 3743 3744 #define TRANS_DDI_FUNC_ENABLE (1 << 31) 3745 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ 3746 #define TRANS_DDI_PORT_SHIFT 28 3747 #define TGL_TRANS_DDI_PORT_SHIFT 27 3748 #define TRANS_DDI_PORT_MASK (7 << TRANS_DDI_PORT_SHIFT) 3749 #define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT) 3750 #define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT) 3751 #define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT) 3752 #define TRANS_DDI_MODE_SELECT_MASK (7 << 24) 3753 #define TRANS_DDI_MODE_SELECT_HDMI (0 << 24) 3754 #define TRANS_DDI_MODE_SELECT_DVI (1 << 24) 3755 #define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24) 3756 #define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24) 3757 #define TRANS_DDI_MODE_SELECT_FDI_OR_128B132B (4 << 24) 3758 #define TRANS_DDI_BPC_MASK (7 << 20) 3759 #define TRANS_DDI_BPC_8 (0 << 20) 3760 #define TRANS_DDI_BPC_10 (1 << 20) 3761 #define TRANS_DDI_BPC_6 (2 << 20) 3762 #define TRANS_DDI_BPC_12 (3 << 20) 3763 #define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18) 3764 #define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x) REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x)) 3765 #define TRANS_DDI_PVSYNC (1 << 17) 3766 #define TRANS_DDI_PHSYNC (1 << 16) 3767 #define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15) 3768 #define TRANS_DDI_EDP_INPUT_MASK (7 << 12) 3769 #define TRANS_DDI_EDP_INPUT_A_ON (0 << 12) 3770 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12) 3771 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12) 3772 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12) 3773 #define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12) 3774 #define TRANS_DDI_HDCP_LINE_REKEY_DISABLE REG_BIT(12) 3775 #define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10) 3776 #define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \ 3777 REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans) 3778 #define TRANS_DDI_HDCP_SIGNALLING (1 << 9) 3779 #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8) 3780 #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7) 3781 #define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6) 3782 #define TRANS_DDI_HDCP_SELECT REG_BIT(5) 3783 #define TRANS_DDI_BFI_ENABLE (1 << 4) 3784 #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4) 3785 #define TRANS_DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1) 3786 #define TRANS_DDI_PORT_WIDTH(width) REG_FIELD_PREP(TRANS_DDI_PORT_WIDTH_MASK, (width) - 1) 3787 #define TRANS_DDI_HDMI_SCRAMBLING (1 << 0) 3788 #define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \ 3789 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \ 3790 | TRANS_DDI_HDMI_SCRAMBLING) 3791 3792 #define _TRANS_DDI_FUNC_CTL2_A 0x60404 3793 #define _TRANS_DDI_FUNC_CTL2_B 0x61404 3794 #define _TRANS_DDI_FUNC_CTL2_C 0x62404 3795 #define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404 3796 #define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404 3797 #define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04 3798 #define TRANS_DDI_FUNC_CTL2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL2_A) 3799 #define PORT_SYNC_MODE_ENABLE REG_BIT(4) 3800 #define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0) 3801 #define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x)) 3802 3803 #define TRANS_CMTG_CHICKEN _MMIO(0x6fa90) 3804 #define DISABLE_DPT_CLK_GATING REG_BIT(1) 3805 3806 /* DisplayPort Transport Control */ 3807 #define _DP_TP_CTL_A 0x64040 3808 #define _DP_TP_CTL_B 0x64140 3809 #define _TGL_DP_TP_CTL_A 0x60540 3810 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) 3811 #define TGL_DP_TP_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_CTL_A) 3812 #define DP_TP_CTL_ENABLE (1 << 31) 3813 #define DP_TP_CTL_FEC_ENABLE (1 << 30) 3814 #define DP_TP_CTL_MODE_SST (0 << 27) 3815 #define DP_TP_CTL_MODE_MST (1 << 27) 3816 #define DP_TP_CTL_FORCE_ACT (1 << 25) 3817 #define DP_TP_CTL_TRAIN_PAT4_SEL_MASK (3 << 19) 3818 #define DP_TP_CTL_TRAIN_PAT4_SEL_TP4A (0 << 19) 3819 #define DP_TP_CTL_TRAIN_PAT4_SEL_TP4B (1 << 19) 3820 #define DP_TP_CTL_TRAIN_PAT4_SEL_TP4C (2 << 19) 3821 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18) 3822 #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15) 3823 #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8) 3824 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8) 3825 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1 << 8) 3826 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4 << 8) 3827 #define DP_TP_CTL_LINK_TRAIN_PAT4 (5 << 8) 3828 #define DP_TP_CTL_LINK_TRAIN_IDLE (2 << 8) 3829 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3 << 8) 3830 #define DP_TP_CTL_SCRAMBLE_DISABLE (1 << 7) 3831 3832 /* DisplayPort Transport Status */ 3833 #define _DP_TP_STATUS_A 0x64044 3834 #define _DP_TP_STATUS_B 0x64144 3835 #define _TGL_DP_TP_STATUS_A 0x60544 3836 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B) 3837 #define TGL_DP_TP_STATUS(dev_priv, tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_STATUS_A) 3838 #define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28) 3839 #define DP_TP_STATUS_IDLE_DONE (1 << 25) 3840 #define DP_TP_STATUS_ACT_SENT (1 << 24) 3841 #define DP_TP_STATUS_MODE_STATUS_MST (1 << 23) 3842 #define DP_TP_STATUS_AUTOTRAIN_DONE (1 << 12) 3843 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8) 3844 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4) 3845 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0) 3846 3847 /* DDI Buffer Control */ 3848 #define _DDI_BUF_CTL_A 0x64000 3849 #define _DDI_BUF_CTL_B 0x64100 3850 /* Known as DDI_CTL_DE in MTL+ */ 3851 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B) 3852 #define DDI_BUF_CTL_ENABLE (1 << 31) 3853 #define XE2LPD_DDI_BUF_D2D_LINK_ENABLE REG_BIT(29) 3854 #define XE2LPD_DDI_BUF_D2D_LINK_STATE REG_BIT(28) 3855 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24) 3856 #define DDI_BUF_EMP_MASK (0xf << 24) 3857 #define DDI_BUF_PHY_LINK_RATE(r) ((r) << 20) 3858 #define DDI_BUF_PORT_DATA_MASK REG_GENMASK(19, 18) 3859 #define DDI_BUF_PORT_DATA_10BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 0) 3860 #define DDI_BUF_PORT_DATA_20BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 1) 3861 #define DDI_BUF_PORT_DATA_40BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 2) 3862 #define DDI_BUF_PORT_REVERSAL (1 << 16) 3863 #define DDI_BUF_IS_IDLE (1 << 7) 3864 #define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6) 3865 #define DDI_A_4_LANES (1 << 4) 3866 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) 3867 #define DDI_PORT_WIDTH_MASK (7 << 1) 3868 #define DDI_PORT_WIDTH_SHIFT 1 3869 #define DDI_INIT_DISPLAY_DETECTED (1 << 0) 3870 3871 /* DDI Buffer Translations */ 3872 #define _DDI_BUF_TRANS_A 0x64E00 3873 #define _DDI_BUF_TRANS_B 0x64E60 3874 #define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8) 3875 #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31) 3876 #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4) 3877 3878 /* DDI DP Compliance Control */ 3879 #define _DDI_DP_COMP_CTL_A 0x605F0 3880 #define _DDI_DP_COMP_CTL_B 0x615F0 3881 #define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B) 3882 #define DDI_DP_COMP_CTL_ENABLE (1 << 31) 3883 #define DDI_DP_COMP_CTL_D10_2 (0 << 28) 3884 #define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28) 3885 #define DDI_DP_COMP_CTL_PRBS7 (2 << 28) 3886 #define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28) 3887 #define DDI_DP_COMP_CTL_HBR2 (4 << 28) 3888 #define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28) 3889 #define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0) 3890 3891 /* DDI DP Compliance Pattern */ 3892 #define _DDI_DP_COMP_PAT_A 0x605F4 3893 #define _DDI_DP_COMP_PAT_B 0x615F4 3894 #define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4) 3895 3896 /* Sideband Interface (SBI) is programmed indirectly, via 3897 * SBI_ADDR, which contains the register offset; and SBI_DATA, 3898 * which contains the payload */ 3899 #define SBI_ADDR _MMIO(0xC6000) 3900 #define SBI_DATA _MMIO(0xC6004) 3901 #define SBI_CTL_STAT _MMIO(0xC6008) 3902 #define SBI_CTL_DEST_ICLK (0x0 << 16) 3903 #define SBI_CTL_DEST_MPHY (0x1 << 16) 3904 #define SBI_CTL_OP_IORD (0x2 << 8) 3905 #define SBI_CTL_OP_IOWR (0x3 << 8) 3906 #define SBI_CTL_OP_CRRD (0x6 << 8) 3907 #define SBI_CTL_OP_CRWR (0x7 << 8) 3908 #define SBI_RESPONSE_FAIL (0x1 << 1) 3909 #define SBI_RESPONSE_SUCCESS (0x0 << 1) 3910 #define SBI_BUSY (0x1 << 0) 3911 #define SBI_READY (0x0 << 0) 3912 3913 /* SBI offsets */ 3914 #define SBI_SSCDIVINTPHASE 0x0200 3915 #define SBI_SSCDIVINTPHASE6 0x0600 3916 #define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1 3917 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1) 3918 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1) 3919 #define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8 3920 #define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8) 3921 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8) 3922 #define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15) 3923 #define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0) 3924 #define SBI_SSCDITHPHASE 0x0204 3925 #define SBI_SSCCTL 0x020c 3926 #define SBI_SSCCTL6 0x060C 3927 #define SBI_SSCCTL_PATHALT (1 << 3) 3928 #define SBI_SSCCTL_DISABLE (1 << 0) 3929 #define SBI_SSCAUXDIV6 0x0610 3930 #define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4 3931 #define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4) 3932 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4) 3933 #define SBI_DBUFF0 0x2a00 3934 #define SBI_GEN0 0x1f00 3935 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0) 3936 3937 /* LPT PIXCLK_GATE */ 3938 #define PIXCLK_GATE _MMIO(0xC6020) 3939 #define PIXCLK_GATE_UNGATE (1 << 0) 3940 #define PIXCLK_GATE_GATE (0 << 0) 3941 3942 /* SPLL */ 3943 #define SPLL_CTL _MMIO(0x46020) 3944 #define SPLL_PLL_ENABLE (1 << 31) 3945 #define SPLL_REF_BCLK (0 << 28) 3946 #define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */ 3947 #define SPLL_REF_NON_SSC_HSW (2 << 28) 3948 #define SPLL_REF_PCH_SSC_BDW (2 << 28) 3949 #define SPLL_REF_LCPLL (3 << 28) 3950 #define SPLL_REF_MASK (3 << 28) 3951 #define SPLL_FREQ_810MHz (0 << 26) 3952 #define SPLL_FREQ_1350MHz (1 << 26) 3953 #define SPLL_FREQ_2700MHz (2 << 26) 3954 #define SPLL_FREQ_MASK (3 << 26) 3955 3956 /* WRPLL */ 3957 #define _WRPLL_CTL1 0x46040 3958 #define _WRPLL_CTL2 0x46060 3959 #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2) 3960 #define WRPLL_PLL_ENABLE (1 << 31) 3961 #define WRPLL_REF_BCLK (0 << 28) 3962 #define WRPLL_REF_PCH_SSC (1 << 28) 3963 #define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */ 3964 #define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */ 3965 #define WRPLL_REF_LCPLL (3 << 28) 3966 #define WRPLL_REF_MASK (3 << 28) 3967 /* WRPLL divider programming */ 3968 #define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0) 3969 #define WRPLL_DIVIDER_REF_MASK (0xff) 3970 #define WRPLL_DIVIDER_POST(x) ((x) << 8) 3971 #define WRPLL_DIVIDER_POST_MASK (0x3f << 8) 3972 #define WRPLL_DIVIDER_POST_SHIFT 8 3973 #define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16) 3974 #define WRPLL_DIVIDER_FB_SHIFT 16 3975 #define WRPLL_DIVIDER_FB_MASK (0xff << 16) 3976 3977 /* Port clock selection */ 3978 #define _PORT_CLK_SEL_A 0x46100 3979 #define _PORT_CLK_SEL_B 0x46104 3980 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B) 3981 #define PORT_CLK_SEL_MASK REG_GENMASK(31, 29) 3982 #define PORT_CLK_SEL_LCPLL_2700 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 0) 3983 #define PORT_CLK_SEL_LCPLL_1350 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 1) 3984 #define PORT_CLK_SEL_LCPLL_810 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 2) 3985 #define PORT_CLK_SEL_SPLL REG_FIELD_PREP(PORT_CLK_SEL_MASK, 3) 3986 #define PORT_CLK_SEL_WRPLL(pll) REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4 + (pll)) 3987 #define PORT_CLK_SEL_WRPLL1 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4) 3988 #define PORT_CLK_SEL_WRPLL2 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 5) 3989 #define PORT_CLK_SEL_NONE REG_FIELD_PREP(PORT_CLK_SEL_MASK, 7) 3990 3991 /* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */ 3992 #define DDI_CLK_SEL(port) PORT_CLK_SEL(port) 3993 #define DDI_CLK_SEL_MASK REG_GENMASK(31, 28) 3994 #define DDI_CLK_SEL_NONE REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x0) 3995 #define DDI_CLK_SEL_MG REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x8) 3996 #define DDI_CLK_SEL_TBT_162 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xC) 3997 #define DDI_CLK_SEL_TBT_270 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xD) 3998 #define DDI_CLK_SEL_TBT_540 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xE) 3999 #define DDI_CLK_SEL_TBT_810 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xF) 4000 4001 /* Transcoder clock selection */ 4002 #define _TRANS_CLK_SEL_A 0x46140 4003 #define _TRANS_CLK_SEL_B 0x46144 4004 #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B) 4005 /* For each transcoder, we need to select the corresponding port clock */ 4006 #define TRANS_CLK_SEL_DISABLED (0x0 << 29) 4007 #define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29) 4008 #define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28) 4009 #define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28) 4010 4011 4012 #define CDCLK_FREQ _MMIO(0x46200) 4013 4014 #define _TRANSA_MSA_MISC 0x60410 4015 #define _TRANSB_MSA_MISC 0x61410 4016 #define _TRANSC_MSA_MISC 0x62410 4017 #define _TRANS_EDP_MSA_MISC 0x6f410 4018 #define TRANS_MSA_MISC(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANSA_MSA_MISC) 4019 /* See DP_MSA_MISC_* for the bit definitions */ 4020 4021 #define _TRANS_A_SET_CONTEXT_LATENCY 0x6007C 4022 #define _TRANS_B_SET_CONTEXT_LATENCY 0x6107C 4023 #define _TRANS_C_SET_CONTEXT_LATENCY 0x6207C 4024 #define _TRANS_D_SET_CONTEXT_LATENCY 0x6307C 4025 #define TRANS_SET_CONTEXT_LATENCY(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_A_SET_CONTEXT_LATENCY) 4026 #define TRANS_SET_CONTEXT_LATENCY_MASK REG_GENMASK(15, 0) 4027 #define TRANS_SET_CONTEXT_LATENCY_VALUE(x) REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x)) 4028 4029 /* LCPLL Control */ 4030 #define LCPLL_CTL _MMIO(0x130040) 4031 #define LCPLL_PLL_DISABLE (1 << 31) 4032 #define LCPLL_PLL_LOCK (1 << 30) 4033 #define LCPLL_REF_NON_SSC (0 << 28) 4034 #define LCPLL_REF_BCLK (2 << 28) 4035 #define LCPLL_REF_PCH_SSC (3 << 28) 4036 #define LCPLL_REF_MASK (3 << 28) 4037 #define LCPLL_CLK_FREQ_MASK (3 << 26) 4038 #define LCPLL_CLK_FREQ_450 (0 << 26) 4039 #define LCPLL_CLK_FREQ_54O_BDW (1 << 26) 4040 #define LCPLL_CLK_FREQ_337_5_BDW (2 << 26) 4041 #define LCPLL_CLK_FREQ_675_BDW (3 << 26) 4042 #define LCPLL_CD_CLOCK_DISABLE (1 << 25) 4043 #define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24) 4044 #define LCPLL_CD2X_CLOCK_DISABLE (1 << 23) 4045 #define LCPLL_POWER_DOWN_ALLOW (1 << 22) 4046 #define LCPLL_CD_SOURCE_FCLK (1 << 21) 4047 #define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19) 4048 4049 /* 4050 * SKL Clocks 4051 */ 4052 4053 /* CDCLK_CTL */ 4054 #define CDCLK_CTL _MMIO(0x46000) 4055 #define CDCLK_FREQ_SEL_MASK REG_GENMASK(27, 26) 4056 #define CDCLK_FREQ_450_432 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 0) 4057 #define CDCLK_FREQ_540 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1) 4058 #define CDCLK_FREQ_337_308 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2) 4059 #define CDCLK_FREQ_675_617 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3) 4060 #define MDCLK_SOURCE_SEL_MASK REG_GENMASK(25, 25) 4061 #define MDCLK_SOURCE_SEL_CD2XCLK REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 0) 4062 #define MDCLK_SOURCE_SEL_CDCLK_PLL REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 1) 4063 #define BXT_CDCLK_CD2X_DIV_SEL_MASK REG_GENMASK(23, 22) 4064 #define BXT_CDCLK_CD2X_DIV_SEL_1 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0) 4065 #define BXT_CDCLK_CD2X_DIV_SEL_1_5 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1) 4066 #define BXT_CDCLK_CD2X_DIV_SEL_2 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 2) 4067 #define BXT_CDCLK_CD2X_DIV_SEL_4 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 3) 4068 #define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20) 4069 #define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19) 4070 #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3) 4071 #define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19) 4072 #define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19) 4073 #define TGL_CDCLK_CD2X_PIPE(pipe) BXT_CDCLK_CD2X_PIPE(pipe) 4074 #define TGL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE_NONE 4075 #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16) 4076 #define CDCLK_FREQ_DECIMAL_MASK (0x7ff) 4077 4078 /* CDCLK_SQUASH_CTL */ 4079 #define CDCLK_SQUASH_CTL _MMIO(0x46008) 4080 #define CDCLK_SQUASH_ENABLE REG_BIT(31) 4081 #define CDCLK_SQUASH_WINDOW_SIZE_MASK REG_GENMASK(27, 24) 4082 #define CDCLK_SQUASH_WINDOW_SIZE(x) REG_FIELD_PREP(CDCLK_SQUASH_WINDOW_SIZE_MASK, (x)) 4083 #define CDCLK_SQUASH_WAVEFORM_MASK REG_GENMASK(15, 0) 4084 #define CDCLK_SQUASH_WAVEFORM(x) REG_FIELD_PREP(CDCLK_SQUASH_WAVEFORM_MASK, (x)) 4085 4086 /* LCPLL_CTL */ 4087 #define LCPLL1_CTL _MMIO(0x46010) 4088 #define LCPLL2_CTL _MMIO(0x46014) 4089 #define LCPLL_PLL_ENABLE (1 << 31) 4090 4091 /* DPLL control1 */ 4092 #define DPLL_CTRL1 _MMIO(0x6C058) 4093 #define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5)) 4094 #define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4)) 4095 #define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1)) 4096 #define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1) 4097 #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1)) 4098 #define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6)) 4099 #define DPLL_CTRL1_LINK_RATE_2700 0 4100 #define DPLL_CTRL1_LINK_RATE_1350 1 4101 #define DPLL_CTRL1_LINK_RATE_810 2 4102 #define DPLL_CTRL1_LINK_RATE_1620 3 4103 #define DPLL_CTRL1_LINK_RATE_1080 4 4104 #define DPLL_CTRL1_LINK_RATE_2160 5 4105 4106 /* DPLL control2 */ 4107 #define DPLL_CTRL2 _MMIO(0x6C05C) 4108 #define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15)) 4109 #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1)) 4110 #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1) 4111 #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1)) 4112 #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3)) 4113 4114 /* DPLL Status */ 4115 #define DPLL_STATUS _MMIO(0x6C060) 4116 #define DPLL_LOCK(id) (1 << ((id) * 8)) 4117 4118 /* DPLL cfg */ 4119 #define _DPLL1_CFGCR1 0x6C040 4120 #define _DPLL2_CFGCR1 0x6C048 4121 #define _DPLL3_CFGCR1 0x6C050 4122 #define DPLL_CFGCR1_FREQ_ENABLE (1 << 31) 4123 #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9) 4124 #define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9) 4125 #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff) 4126 4127 #define _DPLL1_CFGCR2 0x6C044 4128 #define _DPLL2_CFGCR2 0x6C04C 4129 #define _DPLL3_CFGCR2 0x6C054 4130 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8) 4131 #define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8) 4132 #define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7) 4133 #define DPLL_CFGCR2_KDIV_MASK (3 << 5) 4134 #define DPLL_CFGCR2_KDIV(x) ((x) << 5) 4135 #define DPLL_CFGCR2_KDIV_5 (0 << 5) 4136 #define DPLL_CFGCR2_KDIV_2 (1 << 5) 4137 #define DPLL_CFGCR2_KDIV_3 (2 << 5) 4138 #define DPLL_CFGCR2_KDIV_1 (3 << 5) 4139 #define DPLL_CFGCR2_PDIV_MASK (7 << 2) 4140 #define DPLL_CFGCR2_PDIV(x) ((x) << 2) 4141 #define DPLL_CFGCR2_PDIV_1 (0 << 2) 4142 #define DPLL_CFGCR2_PDIV_2 (1 << 2) 4143 #define DPLL_CFGCR2_PDIV_3 (2 << 2) 4144 #define DPLL_CFGCR2_PDIV_7 (4 << 2) 4145 #define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2) 4146 #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3) 4147 4148 #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1) 4149 #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2) 4150 4151 /* ICL Clocks */ 4152 #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280) 4153 #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24, 4, 5)) 4154 #define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10) 4155 #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \ 4156 (tc_port) + 12 : \ 4157 (tc_port) - TC_PORT_4 + 21)) 4158 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2) 4159 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 4160 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 4161 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27) 4162 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \ 4163 (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 4164 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \ 4165 ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 4166 4167 /* 4168 * DG1 Clocks 4169 * First registers controls the first A and B, while the second register 4170 * controls the phy C and D. The bits on these registers are the 4171 * same, but refer to different phys 4172 */ 4173 #define _DG1_DPCLKA_CFGCR0 0x164280 4174 #define _DG1_DPCLKA1_CFGCR0 0x16C280 4175 #define _DG1_DPCLKA_PHY_IDX(phy) ((phy) % 2) 4176 #define _DG1_DPCLKA_PLL_IDX(pll) ((pll) % 2) 4177 #define DG1_DPCLKA_CFGCR0(phy) _MMIO_PHY((phy) / 2, \ 4178 _DG1_DPCLKA_CFGCR0, \ 4179 _DG1_DPCLKA1_CFGCR0) 4180 #define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT(_DG1_DPCLKA_PHY_IDX(phy) + 10) 4181 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) (_DG1_DPCLKA_PHY_IDX(phy) * 2) 4182 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (_DG1_DPCLKA_PLL_IDX(pll) << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 4183 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 4184 4185 /* ADLS Clocks */ 4186 #define _ADLS_DPCLKA_CFGCR0 0x164280 4187 #define _ADLS_DPCLKA_CFGCR1 0x1642BC 4188 #define ADLS_DPCLKA_CFGCR(phy) _MMIO_PHY((phy) / 3, \ 4189 _ADLS_DPCLKA_CFGCR0, \ 4190 _ADLS_DPCLKA_CFGCR1) 4191 #define ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy) (((phy) % 3) * 2) 4192 /* ADLS DPCLKA_CFGCR0 DDI mask */ 4193 #define ADLS_DPCLKA_DDII_SEL_MASK REG_GENMASK(5, 4) 4194 #define ADLS_DPCLKA_DDIB_SEL_MASK REG_GENMASK(3, 2) 4195 #define ADLS_DPCLKA_DDIA_SEL_MASK REG_GENMASK(1, 0) 4196 /* ADLS DPCLKA_CFGCR1 DDI mask */ 4197 #define ADLS_DPCLKA_DDIK_SEL_MASK REG_GENMASK(3, 2) 4198 #define ADLS_DPCLKA_DDIJ_SEL_MASK REG_GENMASK(1, 0) 4199 #define ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy) _PICK((phy), \ 4200 ADLS_DPCLKA_DDIA_SEL_MASK, \ 4201 ADLS_DPCLKA_DDIB_SEL_MASK, \ 4202 ADLS_DPCLKA_DDII_SEL_MASK, \ 4203 ADLS_DPCLKA_DDIJ_SEL_MASK, \ 4204 ADLS_DPCLKA_DDIK_SEL_MASK) 4205 4206 /* ICL PLL */ 4207 #define _DPLL0_ENABLE 0x46010 4208 #define _DPLL1_ENABLE 0x46014 4209 #define _ADLS_DPLL2_ENABLE 0x46018 4210 #define _ADLS_DPLL3_ENABLE 0x46030 4211 #define PLL_ENABLE REG_BIT(31) 4212 #define PLL_LOCK REG_BIT(30) 4213 #define PLL_POWER_ENABLE REG_BIT(27) 4214 #define PLL_POWER_STATE REG_BIT(26) 4215 #define ICL_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \ 4216 _DPLL0_ENABLE, _DPLL1_ENABLE, \ 4217 _ADLS_DPLL3_ENABLE, _ADLS_DPLL3_ENABLE)) 4218 4219 #define _DG2_PLL3_ENABLE 0x4601C 4220 4221 #define DG2_PLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \ 4222 _DPLL0_ENABLE, _DPLL1_ENABLE, \ 4223 _DG2_PLL3_ENABLE, _DG2_PLL3_ENABLE)) 4224 4225 #define TBT_PLL_ENABLE _MMIO(0x46020) 4226 4227 #define _MG_PLL1_ENABLE 0x46030 4228 #define _MG_PLL2_ENABLE 0x46034 4229 #define _MG_PLL3_ENABLE 0x46038 4230 #define _MG_PLL4_ENABLE 0x4603C 4231 /* Bits are the same as _DPLL0_ENABLE */ 4232 #define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \ 4233 _MG_PLL2_ENABLE) 4234 4235 /* DG1 PLL */ 4236 #define DG1_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ 4237 _DPLL0_ENABLE, _DPLL1_ENABLE, \ 4238 _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)) 4239 4240 /* ADL-P Type C PLL */ 4241 #define PORTTC1_PLL_ENABLE 0x46038 4242 #define PORTTC2_PLL_ENABLE 0x46040 4243 4244 #define ADLP_PORTTC_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), \ 4245 PORTTC1_PLL_ENABLE, \ 4246 PORTTC2_PLL_ENABLE) 4247 4248 #define _ICL_DPLL0_CFGCR0 0x164000 4249 #define _ICL_DPLL1_CFGCR0 0x164080 4250 #define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \ 4251 _ICL_DPLL1_CFGCR0) 4252 #define DPLL_CFGCR0_HDMI_MODE (1 << 30) 4253 #define DPLL_CFGCR0_SSC_ENABLE (1 << 29) 4254 #define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25) 4255 #define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25) 4256 #define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25) 4257 #define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25) 4258 #define DPLL_CFGCR0_LINK_RATE_810 (2 << 25) 4259 #define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25) 4260 #define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25) 4261 #define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25) 4262 #define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25) 4263 #define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25) 4264 #define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10) 4265 #define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10) 4266 #define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10) 4267 #define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff) 4268 4269 #define _ICL_DPLL0_CFGCR1 0x164004 4270 #define _ICL_DPLL1_CFGCR1 0x164084 4271 #define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \ 4272 _ICL_DPLL1_CFGCR1) 4273 #define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10) 4274 #define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10) 4275 #define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10) 4276 #define DPLL_CFGCR1_QDIV_MODE_SHIFT (9) 4277 #define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9) 4278 #define DPLL_CFGCR1_KDIV_MASK (7 << 6) 4279 #define DPLL_CFGCR1_KDIV_SHIFT (6) 4280 #define DPLL_CFGCR1_KDIV(x) ((x) << 6) 4281 #define DPLL_CFGCR1_KDIV_1 (1 << 6) 4282 #define DPLL_CFGCR1_KDIV_2 (2 << 6) 4283 #define DPLL_CFGCR1_KDIV_3 (4 << 6) 4284 #define DPLL_CFGCR1_PDIV_MASK (0xf << 2) 4285 #define DPLL_CFGCR1_PDIV_SHIFT (2) 4286 #define DPLL_CFGCR1_PDIV(x) ((x) << 2) 4287 #define DPLL_CFGCR1_PDIV_2 (1 << 2) 4288 #define DPLL_CFGCR1_PDIV_3 (2 << 2) 4289 #define DPLL_CFGCR1_PDIV_5 (4 << 2) 4290 #define DPLL_CFGCR1_PDIV_7 (8 << 2) 4291 #define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0) 4292 #define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0) 4293 #define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0) 4294 4295 #define _TGL_DPLL0_CFGCR0 0x164284 4296 #define _TGL_DPLL1_CFGCR0 0x16428C 4297 #define _TGL_TBTPLL_CFGCR0 0x16429C 4298 #define TGL_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ 4299 _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \ 4300 _TGL_TBTPLL_CFGCR0, _TGL_TBTPLL_CFGCR0)) 4301 #define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \ 4302 _TGL_DPLL1_CFGCR0) 4303 4304 #define _TGL_DPLL0_DIV0 0x164B00 4305 #define _TGL_DPLL1_DIV0 0x164C00 4306 #define TGL_DPLL0_DIV0(pll) _MMIO_PLL(pll, _TGL_DPLL0_DIV0, _TGL_DPLL1_DIV0) 4307 #define TGL_DPLL0_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25) 4308 #define TGL_DPLL0_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(TGL_DPLL0_DIV0_AFC_STARTUP_MASK, (val)) 4309 4310 #define _TGL_DPLL0_CFGCR1 0x164288 4311 #define _TGL_DPLL1_CFGCR1 0x164290 4312 #define _TGL_TBTPLL_CFGCR1 0x1642A0 4313 #define TGL_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ 4314 _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \ 4315 _TGL_TBTPLL_CFGCR1, _TGL_TBTPLL_CFGCR1)) 4316 #define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \ 4317 _TGL_DPLL1_CFGCR1) 4318 4319 #define _DG1_DPLL2_CFGCR0 0x16C284 4320 #define _DG1_DPLL3_CFGCR0 0x16C28C 4321 #define DG1_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ 4322 _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \ 4323 _DG1_DPLL2_CFGCR0, _DG1_DPLL3_CFGCR0)) 4324 4325 #define _DG1_DPLL2_CFGCR1 0x16C288 4326 #define _DG1_DPLL3_CFGCR1 0x16C290 4327 #define DG1_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ 4328 _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \ 4329 _DG1_DPLL2_CFGCR1, _DG1_DPLL3_CFGCR1)) 4330 4331 /* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */ 4332 #define _ADLS_DPLL4_CFGCR0 0x164294 4333 #define _ADLS_DPLL3_CFGCR0 0x1642C0 4334 #define ADLS_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ 4335 _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \ 4336 _ADLS_DPLL4_CFGCR0, _ADLS_DPLL3_CFGCR0)) 4337 4338 #define _ADLS_DPLL4_CFGCR1 0x164298 4339 #define _ADLS_DPLL3_CFGCR1 0x1642C4 4340 #define ADLS_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ 4341 _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \ 4342 _ADLS_DPLL4_CFGCR1, _ADLS_DPLL3_CFGCR1)) 4343 4344 /* BXT display engine PLL */ 4345 #define BXT_DE_PLL_CTL _MMIO(0x6d000) 4346 #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */ 4347 #define BXT_DE_PLL_RATIO_MASK 0xff 4348 4349 #define BXT_DE_PLL_ENABLE _MMIO(0x46070) 4350 #define BXT_DE_PLL_PLL_ENABLE (1 << 31) 4351 #define BXT_DE_PLL_LOCK (1 << 30) 4352 #define BXT_DE_PLL_FREQ_REQ (1 << 23) 4353 #define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22) 4354 #define ICL_CDCLK_PLL_RATIO(x) (x) 4355 #define ICL_CDCLK_PLL_RATIO_MASK 0xff 4356 4357 /* GEN9 DC */ 4358 #define DC_STATE_EN _MMIO(0x45504) 4359 #define DC_STATE_DISABLE 0 4360 #define DC_STATE_EN_DC3CO REG_BIT(30) 4361 #define DC_STATE_DC3CO_STATUS REG_BIT(29) 4362 #define HOLD_PHY_CLKREQ_PG1_LATCH REG_BIT(21) 4363 #define HOLD_PHY_PG1_LATCH REG_BIT(20) 4364 #define DC_STATE_EN_UPTO_DC5 (1 << 0) 4365 #define DC_STATE_EN_DC9 (1 << 3) 4366 #define DC_STATE_EN_UPTO_DC6 (2 << 0) 4367 #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3 4368 4369 #define DC_STATE_DEBUG _MMIO(0x45520) 4370 #define DC_STATE_DEBUG_MASK_CORES (1 << 0) 4371 #define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1) 4372 4373 #define D_COMP_BDW _MMIO(0x138144) 4374 4375 /* Pipe WM_LINETIME - watermark line time */ 4376 #define _WM_LINETIME_A 0x45270 4377 #define _WM_LINETIME_B 0x45274 4378 #define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B) 4379 #define HSW_LINETIME_MASK REG_GENMASK(8, 0) 4380 #define HSW_LINETIME(x) REG_FIELD_PREP(HSW_LINETIME_MASK, (x)) 4381 #define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16) 4382 #define HSW_IPS_LINETIME(x) REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x)) 4383 4384 /* SFUSE_STRAP */ 4385 #define SFUSE_STRAP _MMIO(0xc2014) 4386 #define SFUSE_STRAP_FUSE_LOCK (1 << 13) 4387 #define SFUSE_STRAP_RAW_FREQUENCY (1 << 8) 4388 #define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7) 4389 #define SFUSE_STRAP_CRT_DISABLED (1 << 6) 4390 #define SFUSE_STRAP_DDIF_DETECTED (1 << 3) 4391 #define SFUSE_STRAP_DDIB_DETECTED (1 << 2) 4392 #define SFUSE_STRAP_DDIC_DETECTED (1 << 1) 4393 #define SFUSE_STRAP_DDID_DETECTED (1 << 0) 4394 4395 #define WM_MISC _MMIO(0x45260) 4396 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0) 4397 4398 #define WM_DBG _MMIO(0x45280) 4399 #define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0) 4400 #define WM_DBG_DISALLOW_MAXFIFO (1 << 1) 4401 #define WM_DBG_DISALLOW_SPRITE (1 << 2) 4402 4403 /* Gen4+ Timestamp and Pipe Frame time stamp registers */ 4404 #define GEN4_TIMESTAMP _MMIO(0x2358) 4405 #define ILK_TIMESTAMP_HI _MMIO(0x70070) 4406 #define IVB_TIMESTAMP_CTR _MMIO(0x44070) 4407 4408 #define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074) 4409 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0 4410 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff 4411 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12 4412 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12) 4413 4414 /* g4x+, except vlv/chv! */ 4415 #define _PIPE_FRMTMSTMP_A 0x70048 4416 #define _PIPE_FRMTMSTMP_B 0x71048 4417 #define PIPE_FRMTMSTMP(pipe) \ 4418 _MMIO_PIPE(pipe, _PIPE_FRMTMSTMP_A, _PIPE_FRMTMSTMP_B) 4419 4420 /* g4x+, except vlv/chv! */ 4421 #define _PIPE_FLIPTMSTMP_A 0x7004C 4422 #define _PIPE_FLIPTMSTMP_B 0x7104C 4423 #define PIPE_FLIPTMSTMP(pipe) \ 4424 _MMIO_PIPE(pipe, _PIPE_FLIPTMSTMP_A, _PIPE_FLIPTMSTMP_B) 4425 4426 /* tgl+ */ 4427 #define _PIPE_FLIPDONETMSTMP_A 0x70054 4428 #define _PIPE_FLIPDONETMSTMP_B 0x71054 4429 #define PIPE_FLIPDONETIMSTMP(pipe) \ 4430 _MMIO_PIPE(pipe, _PIPE_FLIPDONETMSTMP_A, _PIPE_FLIPDONETMSTMP_B) 4431 4432 #define _VLV_PIPE_MSA_MISC_A 0x70048 4433 #define VLV_PIPE_MSA_MISC(pipe) \ 4434 _MMIO_PIPE2(dev_priv, pipe, _VLV_PIPE_MSA_MISC_A) 4435 #define VLV_MSA_MISC1_HW_ENABLE REG_BIT(31) 4436 #define VLV_MSA_MISC1_SW_S3D_MASK REG_GENMASK(2, 0) /* MSA MISC1 3:1 */ 4437 4438 #define GGC _MMIO(0x108040) 4439 #define GMS_MASK REG_GENMASK(15, 8) 4440 #define GGMS_MASK REG_GENMASK(7, 6) 4441 4442 #define GEN6_GSMBASE _MMIO(0x108100) 4443 #define GEN6_DSMBASE _MMIO(0x1080C0) 4444 #define GEN6_BDSM_MASK REG_GENMASK64(31, 20) 4445 #define GEN11_BDSM_MASK REG_GENMASK64(63, 20) 4446 4447 #define XEHP_CLOCK_GATE_DIS _MMIO(0x101014) 4448 #define SGSI_SIDECLK_DIS REG_BIT(17) 4449 #define SGGI_DIS REG_BIT(15) 4450 #define SGR_DIS REG_BIT(13) 4451 4452 #define _ICL_PHY_MISC_A 0x64C00 4453 #define _ICL_PHY_MISC_B 0x64C04 4454 #define _DG2_PHY_MISC_TC1 0x64C14 /* TC1="PHY E" but offset as if "PHY F" */ 4455 #define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, _ICL_PHY_MISC_B) 4456 #define DG2_PHY_MISC(port) ((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \ 4457 ICL_PHY_MISC(port)) 4458 #define ICL_PHY_MISC_MUX_DDID (1 << 28) 4459 #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23) 4460 #define DG2_PHY_DP_TX_ACK_MASK REG_GENMASK(23, 20) 4461 4462 #define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0) 4463 #define MODULAR_FIA_MASK (1 << 4) 4464 #define TC_LIVE_STATE_TBT(idx) (1 << ((idx) * 8 + 6)) 4465 #define TC_LIVE_STATE_TC(idx) (1 << ((idx) * 8 + 5)) 4466 #define DP_LANE_ASSIGNMENT_SHIFT(idx) ((idx) * 8) 4467 #define DP_LANE_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 8)) 4468 #define DP_LANE_ASSIGNMENT(idx, x) ((x) << ((idx) * 8)) 4469 4470 #define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890) 4471 #define DP_PHY_MODE_STATUS_COMPLETED(idx) (1 << (idx)) 4472 4473 #define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894) 4474 #define DP_PHY_MODE_STATUS_NOT_SAFE(idx) (1 << (idx)) 4475 4476 #define PORT_TX_DFLEXPA1(fia) _MMIO_FIA((fia), 0x00880) 4477 #define DP_PIN_ASSIGNMENT_SHIFT(idx) ((idx) * 4) 4478 #define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4)) 4479 #define DP_PIN_ASSIGNMENT(idx, x) ((x) << ((idx) * 4)) 4480 4481 #define _TCSS_DDI_STATUS_1 0x161500 4482 #define _TCSS_DDI_STATUS_2 0x161504 4483 #define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \ 4484 _TCSS_DDI_STATUS_1, \ 4485 _TCSS_DDI_STATUS_2)) 4486 #define TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK REG_GENMASK(28, 25) 4487 #define TCSS_DDI_STATUS_READY REG_BIT(2) 4488 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1) 4489 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0) 4490 4491 #define PRIMARY_SPI_TRIGGER _MMIO(0x102040) 4492 #define PRIMARY_SPI_ADDRESS _MMIO(0x102080) 4493 #define PRIMARY_SPI_REGIONID _MMIO(0x102084) 4494 #define SPI_STATIC_REGIONS _MMIO(0x102090) 4495 #define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0) 4496 #define OROM_OFFSET _MMIO(0x1020c0) 4497 #define OROM_OFFSET_MASK REG_GENMASK(20, 16) 4498 4499 #define CLKREQ_POLICY _MMIO(0x101038) 4500 #define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1) 4501 4502 #define CLKGATE_DIS_MISC _MMIO(0x46534) 4503 #define CLKGATE_DIS_MISC_DMASC_GATING_DIS REG_BIT(21) 4504 4505 #define _MTL_CLKGATE_DIS_TRANS_A 0x604E8 4506 #define _MTL_CLKGATE_DIS_TRANS_B 0x614E8 4507 #define MTL_CLKGATE_DIS_TRANS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _MTL_CLKGATE_DIS_TRANS_A) 4508 #define MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS REG_BIT(7) 4509 4510 #define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700) 4511 #define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8) 4512 #define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4) 4513 #define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0) 4514 4515 #define MTL_MEM_SS_INFO_QGV_POINT_OFFSET 0x45710 4516 #define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8) 4517 #define MTL_TRCD_MASK REG_GENMASK(31, 24) 4518 #define MTL_TRP_MASK REG_GENMASK(23, 16) 4519 #define MTL_DCLK_MASK REG_GENMASK(15, 0) 4520 4521 #define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8 + 4) 4522 #define MTL_TRAS_MASK REG_GENMASK(16, 8) 4523 #define MTL_TRDPRE_MASK REG_GENMASK(7, 0) 4524 4525 #define MTL_MEDIA_GSI_BASE 0x380000 4526 4527 #endif /* _I915_REG_H_ */ 4528