1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 2 * All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef _I915_REG_H_ 26 #define _I915_REG_H_ 27 28 #include "i915_reg_defs.h" 29 30 /** 31 * DOC: The i915 register macro definition style guide 32 * 33 * Follow the style described here for new macros, and while changing existing 34 * macros. Do **not** mass change existing definitions just to update the style. 35 * 36 * File Layout 37 * ~~~~~~~~~~~ 38 * 39 * Keep helper macros near the top. For example, _PIPE() and friends. 40 * 41 * Prefix macros that generally should not be used outside of this file with 42 * underscore '_'. For example, _PIPE() and friends, single instances of 43 * registers that are defined solely for the use by function-like macros. 44 * 45 * Avoid using the underscore prefixed macros outside of this file. There are 46 * exceptions, but keep them to a minimum. 47 * 48 * There are two basic types of register definitions: Single registers and 49 * register groups. Register groups are registers which have two or more 50 * instances, for example one per pipe, port, transcoder, etc. Register groups 51 * should be defined using function-like macros. 52 * 53 * For single registers, define the register offset first, followed by register 54 * contents. 55 * 56 * For register groups, define the register instance offsets first, prefixed 57 * with underscore, followed by a function-like macro choosing the right 58 * instance based on the parameter, followed by register contents. 59 * 60 * Define the register contents (i.e. bit and bit field macros) from most 61 * significant to least significant bit. Indent the register content macros 62 * using two extra spaces between ``#define`` and the macro name. 63 * 64 * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents 65 * using ``REG_FIELD_PREP(mask, value)``. This will define the values already 66 * shifted in place, so they can be directly OR'd together. For convenience, 67 * function-like macros may be used to define bit fields, but do note that the 68 * macros may be needed to read as well as write the register contents. 69 * 70 * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name. 71 * 72 * Group the register and its contents together without blank lines, separate 73 * from other registers and their contents with one blank line. 74 * 75 * Indent macro values from macro names using TABs. Align values vertically. Use 76 * braces in macro values as needed to avoid unintended precedence after macro 77 * substitution. Use spaces in macro values according to kernel coding 78 * style. Use lower case in hexadecimal values. 79 * 80 * Naming 81 * ~~~~~~ 82 * 83 * Try to name registers according to the specs. If the register name changes in 84 * the specs from platform to another, stick to the original name. 85 * 86 * Try to re-use existing register macro definitions. Only add new macros for 87 * new register offsets, or when the register contents have changed enough to 88 * warrant a full redefinition. 89 * 90 * When a register macro changes for a new platform, prefix the new macro using 91 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The 92 * prefix signifies the start platform/generation using the register. 93 * 94 * When a bit (field) macro changes or gets added for a new platform, while 95 * retaining the existing register macro, add a platform acronym or generation 96 * suffix to the name. For example, ``_SKL`` or ``_GEN8``. 97 * 98 * Examples 99 * ~~~~~~~~ 100 * 101 * (Note that the values in the example are indented using spaces instead of 102 * TABs to avoid misalignment in generated documentation. Use TABs in the 103 * definitions.):: 104 * 105 * #define _FOO_A 0xf000 106 * #define _FOO_B 0xf001 107 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B) 108 * #define FOO_ENABLE REG_BIT(31) 109 * #define FOO_MODE_MASK REG_GENMASK(19, 16) 110 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0) 111 * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1) 112 * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2) 113 * 114 * #define BAR _MMIO(0xb000) 115 * #define GEN8_BAR _MMIO(0xb888) 116 */ 117 118 #define VLV_MIPI_BASE VLV_DISPLAY_BASE 119 #define BXT_MIPI_BASE 0x60000 120 121 #define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display_mmio_offset) 122 123 /* 124 * Given the first two numbers __a and __b of arbitrarily many evenly spaced 125 * numbers, pick the 0-based __index'th value. 126 * 127 * Always prefer this over _PICK() if the numbers are evenly spaced. 128 */ 129 #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a))) 130 131 /* 132 * Given the arbitrary numbers in varargs, pick the 0-based __index'th number. 133 * 134 * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced. 135 */ 136 #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index]) 137 138 /* 139 * Named helper wrappers around _PICK_EVEN() and _PICK(). 140 */ 141 #define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b) 142 #define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b) 143 #define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b) 144 #define _PORT(port, a, b) _PICK_EVEN(port, a, b) 145 #define _PLL(pll, a, b) _PICK_EVEN(pll, a, b) 146 #define _PHY(phy, a, b) _PICK_EVEN(phy, a, b) 147 148 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) 149 #define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b)) 150 #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b)) 151 #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b)) 152 #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) 153 #define _MMIO_PHY(phy, a, b) _MMIO(_PHY(phy, a, b)) 154 155 #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__) 156 157 #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) 158 #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) 159 #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) 160 #define _MMIO_PLL3(pll, ...) _MMIO(_PICK(pll, __VA_ARGS__)) 161 162 163 /* 164 * Device info offset array based helpers for groups of registers with unevenly 165 * spaced base offsets. 166 */ 167 #define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \ 168 INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \ 169 DISPLAY_MMIO_BASE(dev_priv)) 170 #define _TRANS2(tran, reg) (INTEL_INFO(dev_priv)->trans_offsets[(tran)] - \ 171 INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \ 172 DISPLAY_MMIO_BASE(dev_priv)) 173 #define _MMIO_TRANS2(tran, reg) _MMIO(_TRANS2(tran, reg)) 174 #define _CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \ 175 INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \ 176 DISPLAY_MMIO_BASE(dev_priv)) 177 178 #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value)) 179 #define _MASKED_FIELD(mask, value) ({ \ 180 if (__builtin_constant_p(mask)) \ 181 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \ 182 if (__builtin_constant_p(value)) \ 183 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \ 184 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \ 185 BUILD_BUG_ON_MSG((value) & ~(mask), \ 186 "Incorrect value for mask"); \ 187 __MASKED_FIELD(mask, value); }) 188 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) 189 #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0)) 190 191 #define GU_CNTL _MMIO(0x101010) 192 #define LMEM_INIT REG_BIT(7) 193 194 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0) 195 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20) 196 #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18) 197 #define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4) 198 #define GEN6_STOLEN_RESERVED_1M (0 << 4) 199 #define GEN6_STOLEN_RESERVED_512K (1 << 4) 200 #define GEN6_STOLEN_RESERVED_256K (2 << 4) 201 #define GEN6_STOLEN_RESERVED_128K (3 << 4) 202 #define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5) 203 #define GEN7_STOLEN_RESERVED_1M (0 << 5) 204 #define GEN7_STOLEN_RESERVED_256K (1 << 5) 205 #define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7) 206 #define GEN8_STOLEN_RESERVED_1M (0 << 7) 207 #define GEN8_STOLEN_RESERVED_2M (1 << 7) 208 #define GEN8_STOLEN_RESERVED_4M (2 << 7) 209 #define GEN8_STOLEN_RESERVED_8M (3 << 7) 210 #define GEN6_STOLEN_RESERVED_ENABLE (1 << 0) 211 #define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20) 212 213 #define _VGA_MSR_WRITE _MMIO(0x3c2) 214 215 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 216 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 217 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL) 218 219 /* 220 * Reset registers 221 */ 222 #define DEBUG_RESET_I830 _MMIO(0x6070) 223 #define DEBUG_RESET_FULL (1 << 7) 224 #define DEBUG_RESET_RENDER (1 << 8) 225 #define DEBUG_RESET_DISPLAY (1 << 9) 226 227 /* 228 * IOSF sideband 229 */ 230 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100) 231 #define IOSF_DEVFN_SHIFT 24 232 #define IOSF_OPCODE_SHIFT 16 233 #define IOSF_PORT_SHIFT 8 234 #define IOSF_BYTE_ENABLES_SHIFT 4 235 #define IOSF_BAR_SHIFT 1 236 #define IOSF_SB_BUSY (1 << 0) 237 #define IOSF_PORT_BUNIT 0x03 238 #define IOSF_PORT_PUNIT 0x04 239 #define IOSF_PORT_NC 0x11 240 #define IOSF_PORT_DPIO 0x12 241 #define IOSF_PORT_GPIO_NC 0x13 242 #define IOSF_PORT_CCK 0x14 243 #define IOSF_PORT_DPIO_2 0x1a 244 #define IOSF_PORT_FLISDSI 0x1b 245 #define IOSF_PORT_GPIO_SC 0x48 246 #define IOSF_PORT_GPIO_SUS 0xa8 247 #define IOSF_PORT_CCU 0xa9 248 #define CHV_IOSF_PORT_GPIO_N 0x13 249 #define CHV_IOSF_PORT_GPIO_SE 0x48 250 #define CHV_IOSF_PORT_GPIO_E 0xa8 251 #define CHV_IOSF_PORT_GPIO_SW 0xb2 252 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104) 253 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108) 254 255 /* DPIO registers */ 256 #define DPIO_DEVFN 0 257 258 #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110) 259 #define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */ 260 #define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */ 261 #define DPIO_SFR_BYPASS (1 << 1) 262 #define DPIO_CMNRST (1 << 0) 263 264 #define DPIO_PHY(pipe) ((pipe) >> 1) 265 266 /* 267 * Per pipe/PLL DPIO regs 268 */ 269 #define _VLV_PLL_DW3_CH0 0x800c 270 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ 271 #define DPIO_POST_DIV_DAC 0 272 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ 273 #define DPIO_POST_DIV_LVDS1 2 274 #define DPIO_POST_DIV_LVDS2 3 275 #define DPIO_K_SHIFT (24) /* 4 bits */ 276 #define DPIO_P1_SHIFT (21) /* 3 bits */ 277 #define DPIO_P2_SHIFT (16) /* 5 bits */ 278 #define DPIO_N_SHIFT (12) /* 4 bits */ 279 #define DPIO_ENABLE_CALIBRATION (1 << 11) 280 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ 281 #define DPIO_M2DIV_MASK 0xff 282 #define _VLV_PLL_DW3_CH1 0x802c 283 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1) 284 285 #define _VLV_PLL_DW5_CH0 0x8014 286 #define DPIO_REFSEL_OVERRIDE 27 287 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ 288 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ 289 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ 290 #define DPIO_PLL_REFCLK_SEL_MASK 3 291 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ 292 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ 293 #define _VLV_PLL_DW5_CH1 0x8034 294 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1) 295 296 #define _VLV_PLL_DW7_CH0 0x801c 297 #define _VLV_PLL_DW7_CH1 0x803c 298 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1) 299 300 #define _VLV_PLL_DW8_CH0 0x8040 301 #define _VLV_PLL_DW8_CH1 0x8060 302 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1) 303 304 #define VLV_PLL_DW9_BCAST 0xc044 305 #define _VLV_PLL_DW9_CH0 0x8044 306 #define _VLV_PLL_DW9_CH1 0x8064 307 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1) 308 309 #define _VLV_PLL_DW10_CH0 0x8048 310 #define _VLV_PLL_DW10_CH1 0x8068 311 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1) 312 313 #define _VLV_PLL_DW11_CH0 0x804c 314 #define _VLV_PLL_DW11_CH1 0x806c 315 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1) 316 317 /* Spec for ref block start counts at DW10 */ 318 #define VLV_REF_DW13 0x80ac 319 320 #define VLV_CMN_DW0 0x8100 321 322 /* 323 * Per DDI channel DPIO regs 324 */ 325 326 #define _VLV_PCS_DW0_CH0 0x8200 327 #define _VLV_PCS_DW0_CH1 0x8400 328 #define DPIO_PCS_TX_LANE2_RESET (1 << 16) 329 #define DPIO_PCS_TX_LANE1_RESET (1 << 7) 330 #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4) 331 #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3) 332 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1) 333 334 #define _VLV_PCS01_DW0_CH0 0x200 335 #define _VLV_PCS23_DW0_CH0 0x400 336 #define _VLV_PCS01_DW0_CH1 0x2600 337 #define _VLV_PCS23_DW0_CH1 0x2800 338 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1) 339 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1) 340 341 #define _VLV_PCS_DW1_CH0 0x8204 342 #define _VLV_PCS_DW1_CH1 0x8404 343 #define CHV_PCS_REQ_SOFTRESET_EN (1 << 23) 344 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22) 345 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21) 346 #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) 347 #define DPIO_PCS_CLK_SOFT_RESET (1 << 5) 348 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1) 349 350 #define _VLV_PCS01_DW1_CH0 0x204 351 #define _VLV_PCS23_DW1_CH0 0x404 352 #define _VLV_PCS01_DW1_CH1 0x2604 353 #define _VLV_PCS23_DW1_CH1 0x2804 354 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1) 355 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1) 356 357 #define _VLV_PCS_DW8_CH0 0x8220 358 #define _VLV_PCS_DW8_CH1 0x8420 359 #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20) 360 #define CHV_PCS_USEDCLKCHANNEL (1 << 21) 361 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1) 362 363 #define _VLV_PCS01_DW8_CH0 0x0220 364 #define _VLV_PCS23_DW8_CH0 0x0420 365 #define _VLV_PCS01_DW8_CH1 0x2620 366 #define _VLV_PCS23_DW8_CH1 0x2820 367 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1) 368 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1) 369 370 #define _VLV_PCS_DW9_CH0 0x8224 371 #define _VLV_PCS_DW9_CH1 0x8424 372 #define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13) 373 #define DPIO_PCS_TX2MARGIN_000 (0 << 13) 374 #define DPIO_PCS_TX2MARGIN_101 (1 << 13) 375 #define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10) 376 #define DPIO_PCS_TX1MARGIN_000 (0 << 10) 377 #define DPIO_PCS_TX1MARGIN_101 (1 << 10) 378 #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1) 379 380 #define _VLV_PCS01_DW9_CH0 0x224 381 #define _VLV_PCS23_DW9_CH0 0x424 382 #define _VLV_PCS01_DW9_CH1 0x2624 383 #define _VLV_PCS23_DW9_CH1 0x2824 384 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1) 385 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1) 386 387 #define _CHV_PCS_DW10_CH0 0x8228 388 #define _CHV_PCS_DW10_CH1 0x8428 389 #define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30) 390 #define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31) 391 #define DPIO_PCS_TX2DEEMP_MASK (0xf << 24) 392 #define DPIO_PCS_TX2DEEMP_9P5 (0 << 24) 393 #define DPIO_PCS_TX2DEEMP_6P0 (2 << 24) 394 #define DPIO_PCS_TX1DEEMP_MASK (0xf << 16) 395 #define DPIO_PCS_TX1DEEMP_9P5 (0 << 16) 396 #define DPIO_PCS_TX1DEEMP_6P0 (2 << 16) 397 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1) 398 399 #define _VLV_PCS01_DW10_CH0 0x0228 400 #define _VLV_PCS23_DW10_CH0 0x0428 401 #define _VLV_PCS01_DW10_CH1 0x2628 402 #define _VLV_PCS23_DW10_CH1 0x2828 403 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1) 404 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1) 405 406 #define _VLV_PCS_DW11_CH0 0x822c 407 #define _VLV_PCS_DW11_CH1 0x842c 408 #define DPIO_TX2_STAGGER_MASK(x) ((x) << 24) 409 #define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3) 410 #define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1) 411 #define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0) 412 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1) 413 414 #define _VLV_PCS01_DW11_CH0 0x022c 415 #define _VLV_PCS23_DW11_CH0 0x042c 416 #define _VLV_PCS01_DW11_CH1 0x262c 417 #define _VLV_PCS23_DW11_CH1 0x282c 418 #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1) 419 #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1) 420 421 #define _VLV_PCS01_DW12_CH0 0x0230 422 #define _VLV_PCS23_DW12_CH0 0x0430 423 #define _VLV_PCS01_DW12_CH1 0x2630 424 #define _VLV_PCS23_DW12_CH1 0x2830 425 #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1) 426 #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1) 427 428 #define _VLV_PCS_DW12_CH0 0x8230 429 #define _VLV_PCS_DW12_CH1 0x8430 430 #define DPIO_TX2_STAGGER_MULT(x) ((x) << 20) 431 #define DPIO_TX1_STAGGER_MULT(x) ((x) << 16) 432 #define DPIO_TX1_STAGGER_MASK(x) ((x) << 8) 433 #define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6) 434 #define DPIO_LANESTAGGER_STRAP(x) ((x) << 0) 435 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1) 436 437 #define _VLV_PCS_DW14_CH0 0x8238 438 #define _VLV_PCS_DW14_CH1 0x8438 439 #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1) 440 441 #define _VLV_PCS_DW23_CH0 0x825c 442 #define _VLV_PCS_DW23_CH1 0x845c 443 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1) 444 445 #define _VLV_TX_DW2_CH0 0x8288 446 #define _VLV_TX_DW2_CH1 0x8488 447 #define DPIO_SWING_MARGIN000_SHIFT 16 448 #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT) 449 #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8 450 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1) 451 452 #define _VLV_TX_DW3_CH0 0x828c 453 #define _VLV_TX_DW3_CH1 0x848c 454 /* The following bit for CHV phy */ 455 #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27) 456 #define DPIO_SWING_MARGIN101_SHIFT 16 457 #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT) 458 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1) 459 460 #define _VLV_TX_DW4_CH0 0x8290 461 #define _VLV_TX_DW4_CH1 0x8490 462 #define DPIO_SWING_DEEMPH9P5_SHIFT 24 463 #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT) 464 #define DPIO_SWING_DEEMPH6P0_SHIFT 16 465 #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT) 466 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1) 467 468 #define _VLV_TX3_DW4_CH0 0x690 469 #define _VLV_TX3_DW4_CH1 0x2a90 470 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1) 471 472 #define _VLV_TX_DW5_CH0 0x8294 473 #define _VLV_TX_DW5_CH1 0x8494 474 #define DPIO_TX_OCALINIT_EN (1 << 31) 475 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1) 476 477 #define _VLV_TX_DW11_CH0 0x82ac 478 #define _VLV_TX_DW11_CH1 0x84ac 479 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1) 480 481 #define _VLV_TX_DW14_CH0 0x82b8 482 #define _VLV_TX_DW14_CH1 0x84b8 483 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1) 484 485 /* CHV dpPhy registers */ 486 #define _CHV_PLL_DW0_CH0 0x8000 487 #define _CHV_PLL_DW0_CH1 0x8180 488 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1) 489 490 #define _CHV_PLL_DW1_CH0 0x8004 491 #define _CHV_PLL_DW1_CH1 0x8184 492 #define DPIO_CHV_N_DIV_SHIFT 8 493 #define DPIO_CHV_M1_DIV_BY_2 (0 << 0) 494 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1) 495 496 #define _CHV_PLL_DW2_CH0 0x8008 497 #define _CHV_PLL_DW2_CH1 0x8188 498 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1) 499 500 #define _CHV_PLL_DW3_CH0 0x800c 501 #define _CHV_PLL_DW3_CH1 0x818c 502 #define DPIO_CHV_FRAC_DIV_EN (1 << 16) 503 #define DPIO_CHV_FIRST_MOD (0 << 8) 504 #define DPIO_CHV_SECOND_MOD (1 << 8) 505 #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0 506 #define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0) 507 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1) 508 509 #define _CHV_PLL_DW6_CH0 0x8018 510 #define _CHV_PLL_DW6_CH1 0x8198 511 #define DPIO_CHV_GAIN_CTRL_SHIFT 16 512 #define DPIO_CHV_INT_COEFF_SHIFT 8 513 #define DPIO_CHV_PROP_COEFF_SHIFT 0 514 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1) 515 516 #define _CHV_PLL_DW8_CH0 0x8020 517 #define _CHV_PLL_DW8_CH1 0x81A0 518 #define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0 519 #define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0) 520 #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1) 521 522 #define _CHV_PLL_DW9_CH0 0x8024 523 #define _CHV_PLL_DW9_CH1 0x81A4 524 #define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */ 525 #define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1) 526 #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */ 527 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1) 528 529 #define _CHV_CMN_DW0_CH0 0x8100 530 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19 531 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18 532 #define DPIO_ALLDL_POWERDOWN (1 << 1) 533 #define DPIO_ANYDL_POWERDOWN (1 << 0) 534 535 #define _CHV_CMN_DW5_CH0 0x8114 536 #define CHV_BUFRIGHTENA1_DISABLE (0 << 20) 537 #define CHV_BUFRIGHTENA1_NORMAL (1 << 20) 538 #define CHV_BUFRIGHTENA1_FORCE (3 << 20) 539 #define CHV_BUFRIGHTENA1_MASK (3 << 20) 540 #define CHV_BUFLEFTENA1_DISABLE (0 << 22) 541 #define CHV_BUFLEFTENA1_NORMAL (1 << 22) 542 #define CHV_BUFLEFTENA1_FORCE (3 << 22) 543 #define CHV_BUFLEFTENA1_MASK (3 << 22) 544 545 #define _CHV_CMN_DW13_CH0 0x8134 546 #define _CHV_CMN_DW0_CH1 0x8080 547 #define DPIO_CHV_S1_DIV_SHIFT 21 548 #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */ 549 #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */ 550 #define DPIO_CHV_K_DIV_SHIFT 4 551 #define DPIO_PLL_FREQLOCK (1 << 1) 552 #define DPIO_PLL_LOCK (1 << 0) 553 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1) 554 555 #define _CHV_CMN_DW14_CH0 0x8138 556 #define _CHV_CMN_DW1_CH1 0x8084 557 #define DPIO_AFC_RECAL (1 << 14) 558 #define DPIO_DCLKP_EN (1 << 13) 559 #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */ 560 #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */ 561 #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */ 562 #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */ 563 #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */ 564 #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */ 565 #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */ 566 #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */ 567 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1) 568 569 #define _CHV_CMN_DW19_CH0 0x814c 570 #define _CHV_CMN_DW6_CH1 0x8098 571 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */ 572 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */ 573 #define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */ 574 #define CHV_CMN_USEDCLKCHANNEL (1 << 13) 575 576 #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1) 577 578 #define CHV_CMN_DW28 0x8170 579 #define DPIO_CL1POWERDOWNEN (1 << 23) 580 #define DPIO_DYNPWRDOWNEN_CH0 (1 << 22) 581 #define DPIO_SUS_CLK_CONFIG_ON (0 << 0) 582 #define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0) 583 #define DPIO_SUS_CLK_CONFIG_GATE (2 << 0) 584 #define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0) 585 586 #define CHV_CMN_DW30 0x8178 587 #define DPIO_CL2_LDOFUSE_PWRENB (1 << 6) 588 #define DPIO_LRC_BYPASS (1 << 3) 589 590 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \ 591 (lane) * 0x200 + (offset)) 592 593 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80) 594 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84) 595 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88) 596 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c) 597 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90) 598 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94) 599 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98) 600 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c) 601 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0) 602 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4) 603 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8) 604 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac) 605 #define DPIO_FRC_LATENCY_SHFIT 8 606 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8) 607 #define DPIO_UPAR_SHIFT 30 608 609 /* BXT PHY registers */ 610 #define _BXT_PHY0_BASE 0x6C000 611 #define _BXT_PHY1_BASE 0x162000 612 #define _BXT_PHY2_BASE 0x163000 613 #define BXT_PHY_BASE(phy) _PHY3((phy), _BXT_PHY0_BASE, \ 614 _BXT_PHY1_BASE, \ 615 _BXT_PHY2_BASE) 616 617 #define _BXT_PHY(phy, reg) \ 618 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg)) 619 620 #define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \ 621 (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \ 622 (reg_ch1) - _BXT_PHY0_BASE)) 623 #define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \ 624 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)) 625 626 #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090) 627 #define MIPIO_RST_CTRL (1 << 2) 628 629 #define _BXT_PHY_CTL_DDI_A 0x64C00 630 #define _BXT_PHY_CTL_DDI_B 0x64C10 631 #define _BXT_PHY_CTL_DDI_C 0x64C20 632 #define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10) 633 #define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9) 634 #define BXT_PHY_LANE_ENABLED (1 << 8) 635 #define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \ 636 _BXT_PHY_CTL_DDI_B) 637 638 #define _PHY_CTL_FAMILY_EDP 0x64C80 639 #define _PHY_CTL_FAMILY_DDI 0x64C90 640 #define _PHY_CTL_FAMILY_DDI_C 0x64CA0 641 #define COMMON_RESET_DIS (1 << 31) 642 #define BXT_PHY_CTL_FAMILY(phy) _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \ 643 _PHY_CTL_FAMILY_EDP, \ 644 _PHY_CTL_FAMILY_DDI_C) 645 646 /* BXT PHY PLL registers */ 647 #define _PORT_PLL_A 0x46074 648 #define _PORT_PLL_B 0x46078 649 #define _PORT_PLL_C 0x4607c 650 #define PORT_PLL_ENABLE (1 << 31) 651 #define PORT_PLL_LOCK (1 << 30) 652 #define PORT_PLL_REF_SEL (1 << 27) 653 #define PORT_PLL_POWER_ENABLE (1 << 26) 654 #define PORT_PLL_POWER_STATE (1 << 25) 655 #define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B) 656 657 #define _PORT_PLL_EBB_0_A 0x162034 658 #define _PORT_PLL_EBB_0_B 0x6C034 659 #define _PORT_PLL_EBB_0_C 0x6C340 660 #define PORT_PLL_P1_SHIFT 13 661 #define PORT_PLL_P1_MASK (0x07 << PORT_PLL_P1_SHIFT) 662 #define PORT_PLL_P1(x) ((x) << PORT_PLL_P1_SHIFT) 663 #define PORT_PLL_P2_SHIFT 8 664 #define PORT_PLL_P2_MASK (0x1f << PORT_PLL_P2_SHIFT) 665 #define PORT_PLL_P2(x) ((x) << PORT_PLL_P2_SHIFT) 666 #define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 667 _PORT_PLL_EBB_0_B, \ 668 _PORT_PLL_EBB_0_C) 669 670 #define _PORT_PLL_EBB_4_A 0x162038 671 #define _PORT_PLL_EBB_4_B 0x6C038 672 #define _PORT_PLL_EBB_4_C 0x6C344 673 #define PORT_PLL_10BIT_CLK_ENABLE (1 << 13) 674 #define PORT_PLL_RECALIBRATE (1 << 14) 675 #define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 676 _PORT_PLL_EBB_4_B, \ 677 _PORT_PLL_EBB_4_C) 678 679 #define _PORT_PLL_0_A 0x162100 680 #define _PORT_PLL_0_B 0x6C100 681 #define _PORT_PLL_0_C 0x6C380 682 /* PORT_PLL_0_A */ 683 #define PORT_PLL_M2_MASK 0xFF 684 /* PORT_PLL_1_A */ 685 #define PORT_PLL_N_SHIFT 8 686 #define PORT_PLL_N_MASK (0x0F << PORT_PLL_N_SHIFT) 687 #define PORT_PLL_N(x) ((x) << PORT_PLL_N_SHIFT) 688 /* PORT_PLL_2_A */ 689 #define PORT_PLL_M2_FRAC_MASK 0x3FFFFF 690 /* PORT_PLL_3_A */ 691 #define PORT_PLL_M2_FRAC_ENABLE (1 << 16) 692 /* PORT_PLL_6_A */ 693 #define PORT_PLL_PROP_COEFF_MASK 0xF 694 #define PORT_PLL_INT_COEFF_MASK (0x1F << 8) 695 #define PORT_PLL_INT_COEFF(x) ((x) << 8) 696 #define PORT_PLL_GAIN_CTL_MASK (0x07 << 16) 697 #define PORT_PLL_GAIN_CTL(x) ((x) << 16) 698 /* PORT_PLL_8_A */ 699 #define PORT_PLL_TARGET_CNT_MASK 0x3FF 700 /* PORT_PLL_9_A */ 701 #define PORT_PLL_LOCK_THRESHOLD_SHIFT 1 702 #define PORT_PLL_LOCK_THRESHOLD_MASK (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT) 703 /* PORT_PLL_10_A */ 704 #define PORT_PLL_DCO_AMP_OVR_EN_H (1 << 27) 705 #define PORT_PLL_DCO_AMP_DEFAULT 15 706 #define PORT_PLL_DCO_AMP_MASK 0x3c00 707 #define PORT_PLL_DCO_AMP(x) ((x) << 10) 708 #define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \ 709 _PORT_PLL_0_B, \ 710 _PORT_PLL_0_C) 711 #define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \ 712 (idx) * 4) 713 714 /* BXT PHY common lane registers */ 715 #define _PORT_CL1CM_DW0_A 0x162000 716 #define _PORT_CL1CM_DW0_BC 0x6C000 717 #define PHY_POWER_GOOD (1 << 16) 718 #define PHY_RESERVED (1 << 7) 719 #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC) 720 721 #define _PORT_CL1CM_DW9_A 0x162024 722 #define _PORT_CL1CM_DW9_BC 0x6C024 723 #define IREF0RC_OFFSET_SHIFT 8 724 #define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT) 725 #define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC) 726 727 #define _PORT_CL1CM_DW10_A 0x162028 728 #define _PORT_CL1CM_DW10_BC 0x6C028 729 #define IREF1RC_OFFSET_SHIFT 8 730 #define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT) 731 #define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC) 732 733 #define _PORT_CL1CM_DW28_A 0x162070 734 #define _PORT_CL1CM_DW28_BC 0x6C070 735 #define OCL1_POWER_DOWN_EN (1 << 23) 736 #define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22) 737 #define SUS_CLK_CONFIG 0x3 738 #define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC) 739 740 #define _PORT_CL1CM_DW30_A 0x162078 741 #define _PORT_CL1CM_DW30_BC 0x6C078 742 #define OCL2_LDOFUSE_PWR_DIS (1 << 6) 743 #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC) 744 745 /* The spec defines this only for BXT PHY0, but lets assume that this 746 * would exist for PHY1 too if it had a second channel. 747 */ 748 #define _PORT_CL2CM_DW6_A 0x162358 749 #define _PORT_CL2CM_DW6_BC 0x6C358 750 #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC) 751 #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28) 752 753 /* BXT PHY Ref registers */ 754 #define _PORT_REF_DW3_A 0x16218C 755 #define _PORT_REF_DW3_BC 0x6C18C 756 #define GRC_DONE (1 << 22) 757 #define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC) 758 759 #define _PORT_REF_DW6_A 0x162198 760 #define _PORT_REF_DW6_BC 0x6C198 761 #define GRC_CODE_SHIFT 24 762 #define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT) 763 #define GRC_CODE_FAST_SHIFT 16 764 #define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT) 765 #define GRC_CODE_SLOW_SHIFT 8 766 #define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT) 767 #define GRC_CODE_NOM_MASK 0xFF 768 #define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC) 769 770 #define _PORT_REF_DW8_A 0x1621A0 771 #define _PORT_REF_DW8_BC 0x6C1A0 772 #define GRC_DIS (1 << 15) 773 #define GRC_RDY_OVRD (1 << 1) 774 #define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC) 775 776 /* BXT PHY PCS registers */ 777 #define _PORT_PCS_DW10_LN01_A 0x162428 778 #define _PORT_PCS_DW10_LN01_B 0x6C428 779 #define _PORT_PCS_DW10_LN01_C 0x6C828 780 #define _PORT_PCS_DW10_GRP_A 0x162C28 781 #define _PORT_PCS_DW10_GRP_B 0x6CC28 782 #define _PORT_PCS_DW10_GRP_C 0x6CE28 783 #define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 784 _PORT_PCS_DW10_LN01_B, \ 785 _PORT_PCS_DW10_LN01_C) 786 #define BXT_PORT_PCS_DW10_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 787 _PORT_PCS_DW10_GRP_B, \ 788 _PORT_PCS_DW10_GRP_C) 789 790 #define TX2_SWING_CALC_INIT (1 << 31) 791 #define TX1_SWING_CALC_INIT (1 << 30) 792 793 #define _PORT_PCS_DW12_LN01_A 0x162430 794 #define _PORT_PCS_DW12_LN01_B 0x6C430 795 #define _PORT_PCS_DW12_LN01_C 0x6C830 796 #define _PORT_PCS_DW12_LN23_A 0x162630 797 #define _PORT_PCS_DW12_LN23_B 0x6C630 798 #define _PORT_PCS_DW12_LN23_C 0x6CA30 799 #define _PORT_PCS_DW12_GRP_A 0x162c30 800 #define _PORT_PCS_DW12_GRP_B 0x6CC30 801 #define _PORT_PCS_DW12_GRP_C 0x6CE30 802 #define LANESTAGGER_STRAP_OVRD (1 << 6) 803 #define LANE_STAGGER_MASK 0x1F 804 #define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 805 _PORT_PCS_DW12_LN01_B, \ 806 _PORT_PCS_DW12_LN01_C) 807 #define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 808 _PORT_PCS_DW12_LN23_B, \ 809 _PORT_PCS_DW12_LN23_C) 810 #define BXT_PORT_PCS_DW12_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 811 _PORT_PCS_DW12_GRP_B, \ 812 _PORT_PCS_DW12_GRP_C) 813 814 /* BXT PHY TX registers */ 815 #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \ 816 ((lane) & 1) * 0x80) 817 818 #define _PORT_TX_DW2_LN0_A 0x162508 819 #define _PORT_TX_DW2_LN0_B 0x6C508 820 #define _PORT_TX_DW2_LN0_C 0x6C908 821 #define _PORT_TX_DW2_GRP_A 0x162D08 822 #define _PORT_TX_DW2_GRP_B 0x6CD08 823 #define _PORT_TX_DW2_GRP_C 0x6CF08 824 #define BXT_PORT_TX_DW2_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 825 _PORT_TX_DW2_LN0_B, \ 826 _PORT_TX_DW2_LN0_C) 827 #define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 828 _PORT_TX_DW2_GRP_B, \ 829 _PORT_TX_DW2_GRP_C) 830 #define MARGIN_000_SHIFT 16 831 #define MARGIN_000 (0xFF << MARGIN_000_SHIFT) 832 #define UNIQ_TRANS_SCALE_SHIFT 8 833 #define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT) 834 835 #define _PORT_TX_DW3_LN0_A 0x16250C 836 #define _PORT_TX_DW3_LN0_B 0x6C50C 837 #define _PORT_TX_DW3_LN0_C 0x6C90C 838 #define _PORT_TX_DW3_GRP_A 0x162D0C 839 #define _PORT_TX_DW3_GRP_B 0x6CD0C 840 #define _PORT_TX_DW3_GRP_C 0x6CF0C 841 #define BXT_PORT_TX_DW3_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 842 _PORT_TX_DW3_LN0_B, \ 843 _PORT_TX_DW3_LN0_C) 844 #define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 845 _PORT_TX_DW3_GRP_B, \ 846 _PORT_TX_DW3_GRP_C) 847 #define SCALE_DCOMP_METHOD (1 << 26) 848 #define UNIQUE_TRANGE_EN_METHOD (1 << 27) 849 850 #define _PORT_TX_DW4_LN0_A 0x162510 851 #define _PORT_TX_DW4_LN0_B 0x6C510 852 #define _PORT_TX_DW4_LN0_C 0x6C910 853 #define _PORT_TX_DW4_GRP_A 0x162D10 854 #define _PORT_TX_DW4_GRP_B 0x6CD10 855 #define _PORT_TX_DW4_GRP_C 0x6CF10 856 #define BXT_PORT_TX_DW4_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 857 _PORT_TX_DW4_LN0_B, \ 858 _PORT_TX_DW4_LN0_C) 859 #define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 860 _PORT_TX_DW4_GRP_B, \ 861 _PORT_TX_DW4_GRP_C) 862 #define DEEMPH_SHIFT 24 863 #define DE_EMPHASIS (0xFF << DEEMPH_SHIFT) 864 865 #define _PORT_TX_DW5_LN0_A 0x162514 866 #define _PORT_TX_DW5_LN0_B 0x6C514 867 #define _PORT_TX_DW5_LN0_C 0x6C914 868 #define _PORT_TX_DW5_GRP_A 0x162D14 869 #define _PORT_TX_DW5_GRP_B 0x6CD14 870 #define _PORT_TX_DW5_GRP_C 0x6CF14 871 #define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 872 _PORT_TX_DW5_LN0_B, \ 873 _PORT_TX_DW5_LN0_C) 874 #define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 875 _PORT_TX_DW5_GRP_B, \ 876 _PORT_TX_DW5_GRP_C) 877 #define DCC_DELAY_RANGE_1 (1 << 9) 878 #define DCC_DELAY_RANGE_2 (1 << 8) 879 880 #define _PORT_TX_DW14_LN0_A 0x162538 881 #define _PORT_TX_DW14_LN0_B 0x6C538 882 #define _PORT_TX_DW14_LN0_C 0x6C938 883 #define LATENCY_OPTIM_SHIFT 30 884 #define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT) 885 #define BXT_PORT_TX_DW14_LN(phy, ch, lane) \ 886 _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \ 887 _PORT_TX_DW14_LN0_C) + \ 888 _BXT_LANE_OFFSET(lane)) 889 890 /* UAIMI scratch pad register 1 */ 891 #define UAIMI_SPR1 _MMIO(0x4F074) 892 /* SKL VccIO mask */ 893 #define SKL_VCCIO_MASK 0x1 894 /* SKL balance leg register */ 895 #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C) 896 /* I_boost values */ 897 #define BALANCE_LEG_SHIFT(port) (8 + 3 * (port)) 898 #define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port))) 899 /* Balance leg disable bits */ 900 #define BALANCE_LEG_DISABLE_SHIFT 23 901 #define BALANCE_LEG_DISABLE(port) (1 << (23 + (port))) 902 903 /* 904 * Fence registers 905 * [0-7] @ 0x2000 gen2,gen3 906 * [8-15] @ 0x3000 945,g33,pnv 907 * 908 * [0-15] @ 0x3000 gen4,gen5 909 * 910 * [0-15] @ 0x100000 gen6,vlv,chv 911 * [0-31] @ 0x100000 gen7+ 912 */ 913 #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4) 914 #define I830_FENCE_START_MASK 0x07f80000 915 #define I830_FENCE_TILING_Y_SHIFT 12 916 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 917 #define I830_FENCE_PITCH_SHIFT 4 918 #define I830_FENCE_REG_VALID (1 << 0) 919 #define I915_FENCE_MAX_PITCH_VAL 4 920 #define I830_FENCE_MAX_PITCH_VAL 6 921 #define I830_FENCE_MAX_SIZE_VAL (1 << 8) 922 923 #define I915_FENCE_START_MASK 0x0ff00000 924 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) 925 926 #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8) 927 #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4) 928 #define I965_FENCE_PITCH_SHIFT 2 929 #define I965_FENCE_TILING_Y_SHIFT 1 930 #define I965_FENCE_REG_VALID (1 << 0) 931 #define I965_FENCE_MAX_PITCH_VAL 0x0400 932 933 #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8) 934 #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4) 935 #define GEN6_FENCE_PITCH_SHIFT 32 936 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 937 938 939 /* control register for cpu gtt access */ 940 #define TILECTL _MMIO(0x101000) 941 #define TILECTL_SWZCTL (1 << 0) 942 #define TILECTL_TLBPF (1 << 1) 943 #define TILECTL_TLB_PREFETCH_DIS (1 << 2) 944 #define TILECTL_BACKSNOOP_DIS (1 << 3) 945 946 /* 947 * Instruction and interrupt control regs 948 */ 949 #define PGTBL_CTL _MMIO(0x02020) 950 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ 951 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ 952 #define PGTBL_ER _MMIO(0x02024) 953 #define PRB0_BASE (0x2030 - 0x30) 954 #define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */ 955 #define PRB2_BASE (0x2050 - 0x30) /* gen3 */ 956 #define SRB0_BASE (0x2100 - 0x30) /* gen2 */ 957 #define SRB1_BASE (0x2110 - 0x30) /* gen2 */ 958 #define SRB2_BASE (0x2120 - 0x30) /* 830 */ 959 #define SRB3_BASE (0x2130 - 0x30) /* 830 */ 960 #define RENDER_RING_BASE 0x02000 961 #define BSD_RING_BASE 0x04000 962 #define GEN6_BSD_RING_BASE 0x12000 963 #define GEN8_BSD2_RING_BASE 0x1c000 964 #define GEN11_BSD_RING_BASE 0x1c0000 965 #define GEN11_BSD2_RING_BASE 0x1c4000 966 #define GEN11_BSD3_RING_BASE 0x1d0000 967 #define GEN11_BSD4_RING_BASE 0x1d4000 968 #define XEHP_BSD5_RING_BASE 0x1e0000 969 #define XEHP_BSD6_RING_BASE 0x1e4000 970 #define XEHP_BSD7_RING_BASE 0x1f0000 971 #define XEHP_BSD8_RING_BASE 0x1f4000 972 #define VEBOX_RING_BASE 0x1a000 973 #define GEN11_VEBOX_RING_BASE 0x1c8000 974 #define GEN11_VEBOX2_RING_BASE 0x1d8000 975 #define XEHP_VEBOX3_RING_BASE 0x1e8000 976 #define XEHP_VEBOX4_RING_BASE 0x1f8000 977 #define BLT_RING_BASE 0x22000 978 979 980 981 #define HSW_GTT_CACHE_EN _MMIO(0x4024) 982 #define GTT_CACHE_EN_ALL 0xF0007FFF 983 #define GEN7_WR_WATERMARK _MMIO(0x4028) 984 #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C) 985 #define ARB_MODE _MMIO(0x4030) 986 #define ARB_MODE_SWIZZLE_SNB (1 << 4) 987 #define ARB_MODE_SWIZZLE_IVB (1 << 5) 988 #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034) 989 #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038) 990 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ 991 #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4) 992 #define GEN7_LRA_LIMITS_REG_NUM 13 993 #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070) 994 #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074) 995 996 #define GEN7_ERR_INT _MMIO(0x44040) 997 #define ERR_INT_POISON (1 << 31) 998 #define ERR_INT_MMIO_UNCLAIMED (1 << 13) 999 #define ERR_INT_PIPE_CRC_DONE_C (1 << 8) 1000 #define ERR_INT_FIFO_UNDERRUN_C (1 << 6) 1001 #define ERR_INT_PIPE_CRC_DONE_B (1 << 5) 1002 #define ERR_INT_FIFO_UNDERRUN_B (1 << 3) 1003 #define ERR_INT_PIPE_CRC_DONE_A (1 << 2) 1004 #define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3)) 1005 #define ERR_INT_FIFO_UNDERRUN_A (1 << 0) 1006 #define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) 1007 1008 #define FPGA_DBG _MMIO(0x42300) 1009 #define FPGA_DBG_RM_NOCLAIM REG_BIT(31) 1010 1011 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028) 1012 #define CLAIM_ER_CLR REG_BIT(31) 1013 #define CLAIM_ER_OVERFLOW REG_BIT(16) 1014 #define CLAIM_ER_CTR_MASK REG_GENMASK(15, 0) 1015 1016 #define DERRMR _MMIO(0x44050) 1017 /* Note that HBLANK events are reserved on bdw+ */ 1018 #define DERRMR_PIPEA_SCANLINE (1 << 0) 1019 #define DERRMR_PIPEA_PRI_FLIP_DONE (1 << 1) 1020 #define DERRMR_PIPEA_SPR_FLIP_DONE (1 << 2) 1021 #define DERRMR_PIPEA_VBLANK (1 << 3) 1022 #define DERRMR_PIPEA_HBLANK (1 << 5) 1023 #define DERRMR_PIPEB_SCANLINE (1 << 8) 1024 #define DERRMR_PIPEB_PRI_FLIP_DONE (1 << 9) 1025 #define DERRMR_PIPEB_SPR_FLIP_DONE (1 << 10) 1026 #define DERRMR_PIPEB_VBLANK (1 << 11) 1027 #define DERRMR_PIPEB_HBLANK (1 << 13) 1028 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */ 1029 #define DERRMR_PIPEC_SCANLINE (1 << 14) 1030 #define DERRMR_PIPEC_PRI_FLIP_DONE (1 << 15) 1031 #define DERRMR_PIPEC_SPR_FLIP_DONE (1 << 20) 1032 #define DERRMR_PIPEC_VBLANK (1 << 21) 1033 #define DERRMR_PIPEC_HBLANK (1 << 22) 1034 1035 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030) 1036 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034) 1037 #define SCPD0 _MMIO(0x209c) /* 915+ only */ 1038 #define SCPD_FBC_IGNORE_3D (1 << 6) 1039 #define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5) 1040 #define GEN2_IER _MMIO(0x20a0) 1041 #define GEN2_IIR _MMIO(0x20a4) 1042 #define GEN2_IMR _MMIO(0x20a8) 1043 #define GEN2_ISR _MMIO(0x20ac) 1044 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060) 1045 #define GINT_DIS (1 << 22) 1046 #define GCFG_DIS (1 << 8) 1047 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064) 1048 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084) 1049 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0) 1050 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4) 1051 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8) 1052 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac) 1053 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120) 1054 #define VLV_PCBR_ADDR_SHIFT 12 1055 1056 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */ 1057 #define EIR _MMIO(0x20b0) 1058 #define EMR _MMIO(0x20b4) 1059 #define ESR _MMIO(0x20b8) 1060 #define GM45_ERROR_PAGE_TABLE (1 << 5) 1061 #define GM45_ERROR_MEM_PRIV (1 << 4) 1062 #define I915_ERROR_PAGE_TABLE (1 << 4) 1063 #define GM45_ERROR_CP_PRIV (1 << 3) 1064 #define I915_ERROR_MEMORY_REFRESH (1 << 1) 1065 #define I915_ERROR_INSTRUCTION (1 << 0) 1066 #define INSTPM _MMIO(0x20c0) 1067 #define INSTPM_SELF_EN (1 << 12) /* 915GM only */ 1068 #define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts 1069 will not assert AGPBUSY# and will only 1070 be delivered when out of C3. */ 1071 #define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */ 1072 #define INSTPM_TLB_INVALIDATE (1 << 9) 1073 #define INSTPM_SYNC_FLUSH (1 << 5) 1074 #define MEM_MODE _MMIO(0x20cc) 1075 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */ 1076 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */ 1077 #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */ 1078 #define FW_BLC _MMIO(0x20d8) 1079 #define FW_BLC2 _MMIO(0x20dc) 1080 #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */ 1081 #define FW_BLC_SELF_EN_MASK (1 << 31) 1082 #define FW_BLC_SELF_FIFO_MASK (1 << 16) /* 945 only */ 1083 #define FW_BLC_SELF_EN (1 << 15) /* 945 only */ 1084 #define MM_BURST_LENGTH 0x00700000 1085 #define MM_FIFO_WATERMARK 0x0001F000 1086 #define LM_BURST_LENGTH 0x00000700 1087 #define LM_FIFO_WATERMARK 0x0000001F 1088 #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */ 1089 1090 #define _MBUS_ABOX0_CTL 0x45038 1091 #define _MBUS_ABOX1_CTL 0x45048 1092 #define _MBUS_ABOX2_CTL 0x4504C 1093 #define MBUS_ABOX_CTL(x) _MMIO(_PICK(x, _MBUS_ABOX0_CTL, \ 1094 _MBUS_ABOX1_CTL, \ 1095 _MBUS_ABOX2_CTL)) 1096 #define MBUS_ABOX_BW_CREDIT_MASK (3 << 20) 1097 #define MBUS_ABOX_BW_CREDIT(x) ((x) << 20) 1098 #define MBUS_ABOX_B_CREDIT_MASK (0xF << 16) 1099 #define MBUS_ABOX_B_CREDIT(x) ((x) << 16) 1100 #define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8) 1101 #define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8) 1102 #define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0) 1103 #define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0) 1104 1105 #define _PIPEA_MBUS_DBOX_CTL 0x7003C 1106 #define _PIPEB_MBUS_DBOX_CTL 0x7103C 1107 #define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \ 1108 _PIPEB_MBUS_DBOX_CTL) 1109 #define MBUS_DBOX_BW_CREDIT_MASK (3 << 14) 1110 #define MBUS_DBOX_BW_CREDIT(x) ((x) << 14) 1111 #define MBUS_DBOX_B_CREDIT_MASK (0x1F << 8) 1112 #define MBUS_DBOX_B_CREDIT(x) ((x) << 8) 1113 #define MBUS_DBOX_A_CREDIT_MASK (0xF << 0) 1114 #define MBUS_DBOX_A_CREDIT(x) ((x) << 0) 1115 1116 #define MBUS_UBOX_CTL _MMIO(0x4503C) 1117 #define MBUS_BBOX_CTL_S1 _MMIO(0x45040) 1118 #define MBUS_BBOX_CTL_S2 _MMIO(0x45044) 1119 1120 #define MBUS_CTL _MMIO(0x4438C) 1121 #define MBUS_JOIN REG_BIT(31) 1122 #define MBUS_HASHING_MODE_MASK REG_BIT(30) 1123 #define MBUS_HASHING_MODE_2x2 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0) 1124 #define MBUS_HASHING_MODE_1x4 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1) 1125 #define MBUS_JOIN_PIPE_SELECT_MASK REG_GENMASK(28, 26) 1126 #define MBUS_JOIN_PIPE_SELECT(pipe) REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe) 1127 #define MBUS_JOIN_PIPE_SELECT_NONE MBUS_JOIN_PIPE_SELECT(7) 1128 1129 #define HDPORT_STATE _MMIO(0x45050) 1130 #define HDPORT_DPLL_USED_MASK REG_GENMASK(15, 12) 1131 #define HDPORT_DDI_USED(phy) REG_BIT(2 * (phy) + 1) 1132 #define HDPORT_ENABLED REG_BIT(0) 1133 1134 /* Make render/texture TLB fetches lower priorty than associated data 1135 * fetches. This is not turned on by default 1136 */ 1137 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) 1138 1139 /* Isoch request wait on GTT enable (Display A/B/C streams). 1140 * Make isoch requests stall on the TLB update. May cause 1141 * display underruns (test mode only) 1142 */ 1143 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) 1144 1145 /* Block grant count for isoch requests when block count is 1146 * set to a finite value. 1147 */ 1148 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) 1149 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ 1150 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ 1151 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ 1152 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ 1153 1154 /* Enable render writes to complete in C2/C3/C4 power states. 1155 * If this isn't enabled, render writes are prevented in low 1156 * power states. That seems bad to me. 1157 */ 1158 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) 1159 1160 /* This acknowledges an async flip immediately instead 1161 * of waiting for 2TLB fetches. 1162 */ 1163 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) 1164 1165 /* Enables non-sequential data reads through arbiter 1166 */ 1167 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) 1168 1169 /* Disable FSB snooping of cacheable write cycles from binner/render 1170 * command stream 1171 */ 1172 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) 1173 1174 /* Arbiter time slice for non-isoch streams */ 1175 #define MI_ARB_TIME_SLICE_MASK (7 << 5) 1176 #define MI_ARB_TIME_SLICE_1 (0 << 5) 1177 #define MI_ARB_TIME_SLICE_2 (1 << 5) 1178 #define MI_ARB_TIME_SLICE_4 (2 << 5) 1179 #define MI_ARB_TIME_SLICE_6 (3 << 5) 1180 #define MI_ARB_TIME_SLICE_8 (4 << 5) 1181 #define MI_ARB_TIME_SLICE_10 (5 << 5) 1182 #define MI_ARB_TIME_SLICE_14 (6 << 5) 1183 #define MI_ARB_TIME_SLICE_16 (7 << 5) 1184 1185 /* Low priority grace period page size */ 1186 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ 1187 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) 1188 1189 /* Disable display A/B trickle feed */ 1190 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) 1191 1192 /* Set display plane priority */ 1193 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ 1194 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ 1195 1196 #define MI_STATE _MMIO(0x20e4) /* gen2 only */ 1197 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */ 1198 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */ 1199 1200 /* On modern GEN architectures interrupt control consists of two sets 1201 * of registers. The first set pertains to the ring generating the 1202 * interrupt. The second control is for the functional block generating the 1203 * interrupt. These are PM, GT, DE, etc. 1204 * 1205 * Luckily *knocks on wood* all the ring interrupt bits match up with the 1206 * GT interrupt bits, so we don't need to duplicate the defines. 1207 * 1208 * These defines should cover us well from SNB->HSW with minor exceptions 1209 * it can also work on ILK. 1210 */ 1211 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) 1212 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25) 1213 #define GT_BLT_USER_INTERRUPT (1 << 22) 1214 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15) 1215 #define GT_BSD_USER_INTERRUPT (1 << 12) 1216 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */ 1217 #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) /* bdw+ */ 1218 #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8) 1219 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */ 1220 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) 1221 #define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3) 1222 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2) 1223 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1) 1224 #define GT_RENDER_USER_INTERRUPT (1 << 0) 1225 1226 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */ 1227 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */ 1228 1229 #define GT_PARITY_ERROR(dev_priv) \ 1230 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \ 1231 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0)) 1232 1233 /* These are all the "old" interrupts */ 1234 #define ILK_BSD_USER_INTERRUPT (1 << 5) 1235 1236 #define I915_PM_INTERRUPT (1 << 31) 1237 #define I915_ISP_INTERRUPT (1 << 22) 1238 #define I915_LPE_PIPE_B_INTERRUPT (1 << 21) 1239 #define I915_LPE_PIPE_A_INTERRUPT (1 << 20) 1240 #define I915_MIPIC_INTERRUPT (1 << 19) 1241 #define I915_MIPIA_INTERRUPT (1 << 18) 1242 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18) 1243 #define I915_DISPLAY_PORT_INTERRUPT (1 << 17) 1244 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16) 1245 #define I915_MASTER_ERROR_INTERRUPT (1 << 15) 1246 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14) 1247 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */ 1248 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13) 1249 #define I915_HWB_OOM_INTERRUPT (1 << 13) 1250 #define I915_LPE_PIPE_C_INTERRUPT (1 << 12) 1251 #define I915_SYNC_STATUS_INTERRUPT (1 << 12) 1252 #define I915_MISC_INTERRUPT (1 << 11) 1253 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11) 1254 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10) 1255 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10) 1256 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9) 1257 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9) 1258 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8) 1259 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8) 1260 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7) 1261 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6) 1262 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5) 1263 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4) 1264 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3) 1265 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2) 1266 #define I915_DEBUG_INTERRUPT (1 << 2) 1267 #define I915_WINVALID_INTERRUPT (1 << 1) 1268 #define I915_USER_INTERRUPT (1 << 1) 1269 #define I915_ASLE_INTERRUPT (1 << 0) 1270 #define I915_BSD_USER_INTERRUPT (1 << 25) 1271 1272 #define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000) 1273 #define I915_HDMI_LPE_AUDIO_SIZE 0x1000 1274 1275 /* DisplayPort Audio w/ LPE */ 1276 #define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38) 1277 #define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0) 1278 1279 #define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20) 1280 #define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30) 1281 #define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34) 1282 #define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \ 1283 _VLV_AUD_PORT_EN_B_DBG, \ 1284 _VLV_AUD_PORT_EN_C_DBG, \ 1285 _VLV_AUD_PORT_EN_D_DBG) 1286 #define VLV_AMP_MUTE (1 << 1) 1287 1288 #define GEN6_BSD_RNCID _MMIO(0x12198) 1289 1290 #define GEN7_FF_THREAD_MODE _MMIO(0x20a0) 1291 #define GEN7_FF_SCHED_MASK 0x0077070 1292 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19) 1293 #define GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19) 1294 #define GEN7_FF_TS_SCHED_HS1 (0x5 << 16) 1295 #define GEN7_FF_TS_SCHED_HS0 (0x3 << 16) 1296 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16) 1297 #define GEN7_FF_TS_SCHED_HW (0x0 << 16) /* Default */ 1298 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15) 1299 #define GEN7_FF_VS_SCHED_HS1 (0x5 << 12) 1300 #define GEN7_FF_VS_SCHED_HS0 (0x3 << 12) 1301 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */ 1302 #define GEN7_FF_VS_SCHED_HW (0x0 << 12) 1303 #define GEN7_FF_DS_SCHED_HS1 (0x5 << 4) 1304 #define GEN7_FF_DS_SCHED_HS0 (0x3 << 4) 1305 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */ 1306 #define GEN7_FF_DS_SCHED_HW (0x0 << 4) 1307 1308 /* 1309 * Framebuffer compression (915+ only) 1310 */ 1311 1312 #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */ 1313 #define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */ 1314 #define FBC_CONTROL _MMIO(0x3208) 1315 #define FBC_CTL_EN REG_BIT(31) 1316 #define FBC_CTL_PERIODIC REG_BIT(30) 1317 #define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16) 1318 #define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x)) 1319 #define FBC_CTL_STOP_ON_MOD REG_BIT(15) 1320 #define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */ 1321 #define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm only */ 1322 #define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5) 1323 #define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x)) 1324 #define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0) 1325 #define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x)) 1326 #define FBC_COMMAND _MMIO(0x320c) 1327 #define FBC_CMD_COMPRESS REG_BIT(0) 1328 #define FBC_STATUS _MMIO(0x3210) 1329 #define FBC_STAT_COMPRESSING REG_BIT(31) 1330 #define FBC_STAT_COMPRESSED REG_BIT(30) 1331 #define FBC_STAT_MODIFIED REG_BIT(29) 1332 #define FBC_STAT_CURRENT_LINE_MASK REG_GENMASK(10, 0) 1333 #define FBC_CONTROL2 _MMIO(0x3214) /* i965gm only */ 1334 #define FBC_CTL_FENCE_DBL REG_BIT(4) 1335 #define FBC_CTL_IDLE_MASK REG_GENMASK(3, 2) 1336 #define FBC_CTL_IDLE_IMM REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0) 1337 #define FBC_CTL_IDLE_FULL REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 1) 1338 #define FBC_CTL_IDLE_LINE REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 2) 1339 #define FBC_CTL_IDLE_DEBUG REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 3) 1340 #define FBC_CTL_CPU_FENCE_EN REG_BIT(1) 1341 #define FBC_CTL_PLANE_MASK REG_GENMASK(1, 0) 1342 #define FBC_CTL_PLANE(i9xx_plane) REG_FIELD_PREP(FBC_CTL_PLANE_MASK, (i9xx_plane)) 1343 #define FBC_FENCE_OFF _MMIO(0x3218) /* i965gm only, BSpec typo has 321Bh */ 1344 #define FBC_MOD_NUM _MMIO(0x3220) /* i965gm only */ 1345 #define FBC_MOD_NUM_MASK REG_GENMASK(31, 1) 1346 #define FBC_MOD_NUM_VALID REG_BIT(0) 1347 #define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) /* 49 reisters */ 1348 #define FBC_TAG_MASK REG_GENMASK(1, 0) /* 16 tags per register */ 1349 #define FBC_TAG_MODIFIED REG_FIELD_PREP(FBC_TAG_MASK, 0) 1350 #define FBC_TAG_UNCOMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 1) 1351 #define FBC_TAG_UNCOMPRESSIBLE REG_FIELD_PREP(FBC_TAG_MASK, 2) 1352 #define FBC_TAG_COMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 3) 1353 1354 #define FBC_LL_SIZE (1536) 1355 1356 /* Framebuffer compression for GM45+ */ 1357 #define DPFC_CB_BASE _MMIO(0x3200) 1358 #define ILK_DPFC_CB_BASE(fbc_id) _MMIO_PIPE((fbc_id), 0x43200, 0x43240) 1359 #define DPFC_CONTROL _MMIO(0x3208) 1360 #define ILK_DPFC_CONTROL(fbc_id) _MMIO_PIPE((fbc_id), 0x43208, 0x43248) 1361 #define DPFC_CTL_EN REG_BIT(31) 1362 #define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */ 1363 #define DPFC_CTL_PLANE_G4X(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane)) 1364 #define DPFC_CTL_FENCE_EN_G4X REG_BIT(29) /* g4x-snb */ 1365 #define DPFC_CTL_PLANE_MASK_IVB REG_GENMASK(30, 29) /* ivb only */ 1366 #define DPFC_CTL_PLANE_IVB(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_IVB, (i9xx_plane)) 1367 #define DPFC_CTL_FENCE_EN_IVB REG_BIT(28) /* ivb+ */ 1368 #define DPFC_CTL_PERSISTENT_MODE REG_BIT(25) /* g4x-snb */ 1369 #define DPFC_CTL_FALSE_COLOR REG_BIT(10) /* ivb+ */ 1370 #define DPFC_CTL_SR_EN REG_BIT(10) /* g4x only */ 1371 #define DPFC_CTL_SR_EXIT_DIS REG_BIT(9) /* g4x only */ 1372 #define DPFC_CTL_LIMIT_MASK REG_GENMASK(7, 6) 1373 #define DPFC_CTL_LIMIT_1X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 0) 1374 #define DPFC_CTL_LIMIT_2X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 1) 1375 #define DPFC_CTL_LIMIT_4X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2) 1376 #define DPFC_CTL_FENCENO_MASK REG_GENMASK(3, 0) 1377 #define DPFC_CTL_FENCENO(fence) REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence)) 1378 #define DPFC_RECOMP_CTL _MMIO(0x320c) 1379 #define ILK_DPFC_RECOMP_CTL(fbc_id) _MMIO_PIPE((fbc_id), 0x4320c, 0x4324c) 1380 #define DPFC_RECOMP_STALL_EN REG_BIT(27) 1381 #define DPFC_RECOMP_STALL_WM_MASK REG_GENMASK(26, 16) 1382 #define DPFC_RECOMP_TIMER_COUNT_MASK REG_GENMASK(5, 0) 1383 #define DPFC_STATUS _MMIO(0x3210) 1384 #define ILK_DPFC_STATUS(fbc_id) _MMIO_PIPE((fbc_id), 0x43210, 0x43250) 1385 #define DPFC_INVAL_SEG_MASK REG_GENMASK(26, 16) 1386 #define DPFC_COMP_SEG_MASK REG_GENMASK(10, 0) 1387 #define DPFC_STATUS2 _MMIO(0x3214) 1388 #define ILK_DPFC_STATUS2(fbc_id) _MMIO_PIPE((fbc_id), 0x43214, 0x43254) 1389 #define DPFC_COMP_SEG_MASK_IVB REG_GENMASK(11, 0) 1390 #define DPFC_FENCE_YOFF _MMIO(0x3218) 1391 #define ILK_DPFC_FENCE_YOFF(fbc_id) _MMIO_PIPE((fbc_id), 0x43218, 0x43258) 1392 #define DPFC_CHICKEN _MMIO(0x3224) 1393 #define ILK_DPFC_CHICKEN(fbc_id) _MMIO_PIPE((fbc_id), 0x43224, 0x43264) 1394 #define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */ 1395 #define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */ 1396 #define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */ 1397 #define DPFC_DISABLE_DUMMY0 REG_BIT(8) /* ivb+ */ 1398 1399 #define GLK_FBC_STRIDE(fbc_id) _MMIO_PIPE((fbc_id), 0x43228, 0x43268) 1400 #define FBC_STRIDE_OVERRIDE REG_BIT(15) 1401 #define FBC_STRIDE_MASK REG_GENMASK(14, 0) 1402 #define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x)) 1403 1404 #define ILK_FBC_RT_BASE _MMIO(0x2128) 1405 #define ILK_FBC_RT_VALID REG_BIT(0) 1406 #define SNB_FBC_FRONT_BUFFER REG_BIT(1) 1407 1408 #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000) 1409 #define ILK_FBCQ_DIS (1 << 22) 1410 #define ILK_PABSTRETCH_DIS REG_BIT(21) 1411 #define ILK_SABSTRETCH_DIS REG_BIT(20) 1412 #define IVB_PRI_STRETCH_MAX_MASK REG_GENMASK(21, 20) 1413 #define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0) 1414 #define IVB_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1) 1415 #define IVB_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2) 1416 #define IVB_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3) 1417 #define IVB_SPR_STRETCH_MAX_MASK REG_GENMASK(19, 18) 1418 #define IVB_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0) 1419 #define IVB_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1) 1420 #define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2) 1421 #define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3) 1422 1423 1424 /* 1425 * Framebuffer compression for Sandybridge 1426 * 1427 * The following two registers are of type GTTMMADR 1428 */ 1429 #define SNB_DPFC_CTL_SA _MMIO(0x100100) 1430 #define SNB_DPFC_FENCE_EN REG_BIT(29) 1431 #define SNB_DPFC_FENCENO_MASK REG_GENMASK(4, 0) 1432 #define SNB_DPFC_FENCENO(fence) REG_FIELD_PREP(SNB_DPFC_FENCENO_MASK, (fence)) 1433 #define SNB_DPFC_CPU_FENCE_OFFSET _MMIO(0x100104) 1434 1435 /* Framebuffer compression for Ivybridge */ 1436 #define IVB_FBC_RT_BASE _MMIO(0x7020) 1437 #define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024) 1438 1439 #define IPS_CTL _MMIO(0x43408) 1440 #define IPS_ENABLE (1 << 31) 1441 1442 #define MSG_FBC_REND_STATE(fbc_id) _MMIO_PIPE((fbc_id), 0x50380, 0x50384) 1443 #define FBC_REND_NUKE REG_BIT(2) 1444 #define FBC_REND_CACHE_CLEAN REG_BIT(1) 1445 1446 /* 1447 * GPIO regs 1448 */ 1449 #define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \ 1450 4 * (gpio)) 1451 1452 # define GPIO_CLOCK_DIR_MASK (1 << 0) 1453 # define GPIO_CLOCK_DIR_IN (0 << 1) 1454 # define GPIO_CLOCK_DIR_OUT (1 << 1) 1455 # define GPIO_CLOCK_VAL_MASK (1 << 2) 1456 # define GPIO_CLOCK_VAL_OUT (1 << 3) 1457 # define GPIO_CLOCK_VAL_IN (1 << 4) 1458 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 1459 # define GPIO_DATA_DIR_MASK (1 << 8) 1460 # define GPIO_DATA_DIR_IN (0 << 9) 1461 # define GPIO_DATA_DIR_OUT (1 << 9) 1462 # define GPIO_DATA_VAL_MASK (1 << 10) 1463 # define GPIO_DATA_VAL_OUT (1 << 11) 1464 # define GPIO_DATA_VAL_IN (1 << 12) 1465 # define GPIO_DATA_PULLUP_DISABLE (1 << 13) 1466 1467 #define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */ 1468 #define GMBUS_AKSV_SELECT (1 << 11) 1469 #define GMBUS_RATE_100KHZ (0 << 8) 1470 #define GMBUS_RATE_50KHZ (1 << 8) 1471 #define GMBUS_RATE_400KHZ (2 << 8) /* reserved on Pineview */ 1472 #define GMBUS_RATE_1MHZ (3 << 8) /* reserved on Pineview */ 1473 #define GMBUS_HOLD_EXT (1 << 7) /* 300ns hold time, rsvd on Pineview */ 1474 #define GMBUS_BYTE_CNT_OVERRIDE (1 << 6) 1475 1476 #define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */ 1477 #define GMBUS_SW_CLR_INT (1 << 31) 1478 #define GMBUS_SW_RDY (1 << 30) 1479 #define GMBUS_ENT (1 << 29) /* enable timeout */ 1480 #define GMBUS_CYCLE_NONE (0 << 25) 1481 #define GMBUS_CYCLE_WAIT (1 << 25) 1482 #define GMBUS_CYCLE_INDEX (2 << 25) 1483 #define GMBUS_CYCLE_STOP (4 << 25) 1484 #define GMBUS_BYTE_COUNT_SHIFT 16 1485 #define GMBUS_BYTE_COUNT_MAX 256U 1486 #define GEN9_GMBUS_BYTE_COUNT_MAX 511U 1487 #define GMBUS_SLAVE_INDEX_SHIFT 8 1488 #define GMBUS_SLAVE_ADDR_SHIFT 1 1489 #define GMBUS_SLAVE_READ (1 << 0) 1490 #define GMBUS_SLAVE_WRITE (0 << 0) 1491 #define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */ 1492 #define GMBUS_INUSE (1 << 15) 1493 #define GMBUS_HW_WAIT_PHASE (1 << 14) 1494 #define GMBUS_STALL_TIMEOUT (1 << 13) 1495 #define GMBUS_INT (1 << 12) 1496 #define GMBUS_HW_RDY (1 << 11) 1497 #define GMBUS_SATOER (1 << 10) 1498 #define GMBUS_ACTIVE (1 << 9) 1499 #define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */ 1500 #define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */ 1501 #define GMBUS_SLAVE_TIMEOUT_EN (1 << 4) 1502 #define GMBUS_NAK_EN (1 << 3) 1503 #define GMBUS_IDLE_EN (1 << 2) 1504 #define GMBUS_HW_WAIT_EN (1 << 1) 1505 #define GMBUS_HW_RDY_EN (1 << 0) 1506 #define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */ 1507 #define GMBUS_2BYTE_INDEX_EN (1 << 31) 1508 1509 /* 1510 * Clock control & power management 1511 */ 1512 #define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014) 1513 #define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018) 1514 #define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030) 1515 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) 1516 1517 #define VGA0 _MMIO(0x6000) 1518 #define VGA1 _MMIO(0x6004) 1519 #define VGA_PD _MMIO(0x6010) 1520 #define VGA0_PD_P2_DIV_4 (1 << 7) 1521 #define VGA0_PD_P1_DIV_2 (1 << 5) 1522 #define VGA0_PD_P1_SHIFT 0 1523 #define VGA0_PD_P1_MASK (0x1f << 0) 1524 #define VGA1_PD_P2_DIV_4 (1 << 15) 1525 #define VGA1_PD_P1_DIV_2 (1 << 13) 1526 #define VGA1_PD_P1_SHIFT 8 1527 #define VGA1_PD_P1_MASK (0x1f << 8) 1528 #define DPLL_VCO_ENABLE (1 << 31) 1529 #define DPLL_SDVO_HIGH_SPEED (1 << 30) 1530 #define DPLL_DVO_2X_MODE (1 << 30) 1531 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) 1532 #define DPLL_SYNCLOCK_ENABLE (1 << 29) 1533 #define DPLL_REF_CLK_ENABLE_VLV (1 << 29) 1534 #define DPLL_VGA_MODE_DIS (1 << 28) 1535 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 1536 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 1537 #define DPLL_MODE_MASK (3 << 26) 1538 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 1539 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 1540 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 1541 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 1542 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 1543 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 1544 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ 1545 #define DPLL_LOCK_VLV (1 << 15) 1546 #define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14) 1547 #define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13) 1548 #define DPLL_SSC_REF_CLK_CHV (1 << 13) 1549 #define DPLL_PORTC_READY_MASK (0xf << 4) 1550 #define DPLL_PORTB_READY_MASK (0xf) 1551 1552 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 1553 1554 /* Additional CHV pll/phy registers */ 1555 #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240) 1556 #define DPLL_PORTD_READY_MASK (0xf) 1557 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100) 1558 #define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27)) 1559 #define PHY_LDO_DELAY_0NS 0x0 1560 #define PHY_LDO_DELAY_200NS 0x1 1561 #define PHY_LDO_DELAY_600NS 0x2 1562 #define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23)) 1563 #define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11)) 1564 #define PHY_CH_SU_PSR 0x1 1565 #define PHY_CH_DEEP_PSR 0x7 1566 #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2)) 1567 #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy)) 1568 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104) 1569 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30)) 1570 #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch)))) 1571 #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline)))) 1572 1573 /* 1574 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 1575 * this field (only one bit may be set). 1576 */ 1577 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 1578 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 1579 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 1580 /* i830, required in DVO non-gang */ 1581 #define PLL_P2_DIVIDE_BY_4 (1 << 23) 1582 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 1583 #define PLL_REF_INPUT_DREFCLK (0 << 13) 1584 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 1585 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 1586 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 1587 #define PLL_REF_INPUT_MASK (3 << 13) 1588 #define PLL_LOAD_PULSE_PHASE_SHIFT 9 1589 /* Ironlake */ 1590 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 1591 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) 1592 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9) 1593 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 1594 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff 1595 1596 /* 1597 * Parallel to Serial Load Pulse phase selection. 1598 * Selects the phase for the 10X DPLL clock for the PCIe 1599 * digital display port. The range is 4 to 13; 10 or more 1600 * is just a flip delay. The default is 6 1601 */ 1602 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 1603 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 1604 /* 1605 * SDVO multiplier for 945G/GM. Not used on 965. 1606 */ 1607 #define SDVO_MULTIPLIER_MASK 0x000000ff 1608 #define SDVO_MULTIPLIER_SHIFT_HIRES 4 1609 #define SDVO_MULTIPLIER_SHIFT_VGA 0 1610 1611 #define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c) 1612 #define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020) 1613 #define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c) 1614 #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) 1615 1616 /* 1617 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 1618 * 1619 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 1620 */ 1621 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 1622 #define DPLL_MD_UDI_DIVIDER_SHIFT 24 1623 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 1624 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 1625 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 1626 /* 1627 * SDVO/UDI pixel multiplier. 1628 * 1629 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 1630 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 1631 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 1632 * dummy bytes in the datastream at an increased clock rate, with both sides of 1633 * the link knowing how many bytes are fill. 1634 * 1635 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 1636 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 1637 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 1638 * through an SDVO command. 1639 * 1640 * This register field has values of multiplication factor minus 1, with 1641 * a maximum multiplier of 5 for SDVO. 1642 */ 1643 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 1644 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 1645 /* 1646 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 1647 * This best be set to the default value (3) or the CRT won't work. No, 1648 * I don't entirely understand what this does... 1649 */ 1650 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 1651 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 1652 1653 #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024) 1654 1655 #define _FPA0 0x6040 1656 #define _FPA1 0x6044 1657 #define _FPB0 0x6048 1658 #define _FPB1 0x604c 1659 #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0) 1660 #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1) 1661 #define FP_N_DIV_MASK 0x003f0000 1662 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 1663 #define FP_N_DIV_SHIFT 16 1664 #define FP_M1_DIV_MASK 0x00003f00 1665 #define FP_M1_DIV_SHIFT 8 1666 #define FP_M2_DIV_MASK 0x0000003f 1667 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff 1668 #define FP_M2_DIV_SHIFT 0 1669 #define DPLL_TEST _MMIO(0x606c) 1670 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 1671 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 1672 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 1673 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 1674 #define DPLLB_TEST_N_BYPASS (1 << 19) 1675 #define DPLLB_TEST_M_BYPASS (1 << 18) 1676 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 1677 #define DPLLA_TEST_N_BYPASS (1 << 3) 1678 #define DPLLA_TEST_M_BYPASS (1 << 2) 1679 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 1680 #define D_STATE _MMIO(0x6104) 1681 #define DSTATE_GFX_RESET_I830 (1 << 6) 1682 #define DSTATE_PLL_D3_OFF (1 << 3) 1683 #define DSTATE_GFX_CLOCK_GATING (1 << 1) 1684 #define DSTATE_DOT_CLOCK_GATING (1 << 0) 1685 #define DSPCLK_GATE_D _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x6200) 1686 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 1687 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 1688 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 1689 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ 1690 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ 1691 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ 1692 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ 1693 # define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */ 1694 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ 1695 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ 1696 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ 1697 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ 1698 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ 1699 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ 1700 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ 1701 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ 1702 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ 1703 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ 1704 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ 1705 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ 1706 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 1707 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) 1708 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) 1709 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) 1710 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ 1711 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ 1712 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ 1713 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) 1714 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) 1715 /* 1716 * This bit must be set on the 830 to prevent hangs when turning off the 1717 * overlay scaler. 1718 */ 1719 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 1720 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) 1721 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) 1722 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ 1723 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ 1724 1725 #define RENCLK_GATE_D1 _MMIO(0x6204) 1726 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ 1727 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ 1728 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) 1729 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) 1730 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) 1731 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) 1732 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) 1733 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) 1734 # define MAG_CLOCK_GATE_DISABLE (1 << 5) 1735 /* This bit must be unset on 855,865 */ 1736 # define MECI_CLOCK_GATE_DISABLE (1 << 4) 1737 # define DCMP_CLOCK_GATE_DISABLE (1 << 3) 1738 # define MEC_CLOCK_GATE_DISABLE (1 << 2) 1739 # define MECO_CLOCK_GATE_DISABLE (1 << 1) 1740 /* This bit must be set on 855,865. */ 1741 # define SV_CLOCK_GATE_DISABLE (1 << 0) 1742 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) 1743 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) 1744 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) 1745 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) 1746 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) 1747 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) 1748 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) 1749 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) 1750 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) 1751 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) 1752 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) 1753 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) 1754 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) 1755 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) 1756 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) 1757 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) 1758 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) 1759 1760 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) 1761 /* This bit must always be set on 965G/965GM */ 1762 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) 1763 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) 1764 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) 1765 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) 1766 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) 1767 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) 1768 /* This bit must always be set on 965G */ 1769 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) 1770 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) 1771 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) 1772 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) 1773 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) 1774 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) 1775 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) 1776 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) 1777 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) 1778 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) 1779 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) 1780 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) 1781 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) 1782 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) 1783 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) 1784 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) 1785 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) 1786 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) 1787 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) 1788 1789 #define RENCLK_GATE_D2 _MMIO(0x6208) 1790 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) 1791 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) 1792 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) 1793 1794 #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */ 1795 #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4) 1796 1797 #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */ 1798 #define DEUC _MMIO(0x6214) /* CRL only */ 1799 1800 #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500) 1801 #define FW_CSPWRDWNEN (1 << 15) 1802 1803 #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504) 1804 1805 #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508) 1806 #define CDCLK_FREQ_SHIFT 4 1807 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT) 1808 #define CZCLK_FREQ_MASK 0xf 1809 1810 #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C) 1811 #define PFI_CREDIT_63 (9 << 28) /* chv only */ 1812 #define PFI_CREDIT_31 (8 << 28) /* chv only */ 1813 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */ 1814 #define PFI_CREDIT_RESEND (1 << 27) 1815 #define VGA_FAST_MODE_DISABLE (1 << 14) 1816 1817 #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510) 1818 1819 /* 1820 * Palette regs 1821 */ 1822 #define _PALETTE_A 0xa000 1823 #define _PALETTE_B 0xa800 1824 #define _CHV_PALETTE_C 0xc000 1825 #define PALETTE_RED_MASK REG_GENMASK(23, 16) 1826 #define PALETTE_GREEN_MASK REG_GENMASK(15, 8) 1827 #define PALETTE_BLUE_MASK REG_GENMASK(7, 0) 1828 #define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \ 1829 _PICK((pipe), _PALETTE_A, \ 1830 _PALETTE_B, _CHV_PALETTE_C) + \ 1831 (i) * 4) 1832 1833 /* MCH MMIO space */ 1834 1835 /* 1836 * MCHBAR mirror. 1837 * 1838 * This mirrors the MCHBAR MMIO space whose location is determined by 1839 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in 1840 * every way. It is not accessible from the CP register read instructions. 1841 * 1842 * Starting from Haswell, you can't write registers using the MCHBAR mirror, 1843 * just read. 1844 */ 1845 #define MCHBAR_MIRROR_BASE 0x10000 1846 1847 #define MCHBAR_MIRROR_BASE_SNB 0x140000 1848 1849 #define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34) 1850 #define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48) 1851 #define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16) 1852 #define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4) 1853 #define G4X_STOLEN_RESERVED_ENABLE (1 << 0) 1854 1855 /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */ 1856 #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04) 1857 1858 /* 915-945 and GM965 MCH register controlling DRAM channel access */ 1859 #define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200) 1860 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) 1861 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) 1862 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) 1863 #define DCC_ADDRESSING_MODE_MASK (3 << 0) 1864 #define DCC_CHANNEL_XOR_DISABLE (1 << 10) 1865 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9) 1866 #define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204) 1867 #define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20) 1868 1869 /* Pineview MCH register contains DDR3 setting */ 1870 #define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8) 1871 #define CSHRDDR3CTL_DDR3 (1 << 2) 1872 1873 /* 965 MCH register controlling DRAM channel configuration */ 1874 #define C0DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x206) 1875 #define C1DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x606) 1876 1877 /* snb MCH registers for reading the DRAM channel configuration */ 1878 #define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004) 1879 #define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008) 1880 #define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C) 1881 #define MAD_DIMM_ECC_MASK (0x3 << 24) 1882 #define MAD_DIMM_ECC_OFF (0x0 << 24) 1883 #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24) 1884 #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24) 1885 #define MAD_DIMM_ECC_ON (0x3 << 24) 1886 #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22) 1887 #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21) 1888 #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */ 1889 #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */ 1890 #define MAD_DIMM_B_DUAL_RANK (0x1 << 18) 1891 #define MAD_DIMM_A_DUAL_RANK (0x1 << 17) 1892 #define MAD_DIMM_A_SELECT (0x1 << 16) 1893 /* DIMM sizes are in multiples of 256mb. */ 1894 #define MAD_DIMM_B_SIZE_SHIFT 8 1895 #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT) 1896 #define MAD_DIMM_A_SIZE_SHIFT 0 1897 #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) 1898 1899 /* snb MCH registers for priority tuning */ 1900 #define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10) 1901 #define MCH_SSKPD_WM0_MASK 0x3f 1902 #define MCH_SSKPD_WM0_VAL 0xc 1903 1904 /* Clocking configuration register */ 1905 #define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00) 1906 #define CLKCFG_FSB_400 (0 << 0) /* hrawclk 100 */ 1907 #define CLKCFG_FSB_400_ALT (5 << 0) /* hrawclk 100 */ 1908 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */ 1909 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */ 1910 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */ 1911 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */ 1912 #define CLKCFG_FSB_1067_ALT (0 << 0) /* hrawclk 266 */ 1913 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */ 1914 #define CLKCFG_FSB_1333_ALT (4 << 0) /* hrawclk 333 */ 1915 #define CLKCFG_FSB_1600_ALT (6 << 0) /* hrawclk 400 */ 1916 #define CLKCFG_FSB_MASK (7 << 0) 1917 #define CLKCFG_MEM_533 (1 << 4) 1918 #define CLKCFG_MEM_667 (2 << 4) 1919 #define CLKCFG_MEM_800 (3 << 4) 1920 #define CLKCFG_MEM_MASK (7 << 4) 1921 1922 #define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38) 1923 #define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f) 1924 1925 #define TSC1 _MMIO(0x11001) 1926 #define TSE (1 << 0) 1927 #define TR1 _MMIO(0x11006) 1928 #define TSFS _MMIO(0x11020) 1929 #define TSFS_SLOPE_MASK 0x0000ff00 1930 #define TSFS_SLOPE_SHIFT 8 1931 #define TSFS_INTR_MASK 0x000000ff 1932 1933 #define CSIPLL0 _MMIO(0x12c10) 1934 #define DDRMPLL1 _MMIO(0X12c20) 1935 #define PEG_BAND_GAP_DATA _MMIO(0x14d68) 1936 1937 #define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948) 1938 #define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070) 1939 #define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994) 1940 #define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998) 1941 #define RP0_CAP_MASK REG_GENMASK(7, 0) 1942 #define RP1_CAP_MASK REG_GENMASK(15, 8) 1943 #define RPN_CAP_MASK REG_GENMASK(23, 16) 1944 #define BXT_RP_STATE_CAP _MMIO(0x138170) 1945 #define GEN9_RP_STATE_LIMITS _MMIO(0x138148) 1946 #define XEHPSDV_RP_STATE_CAP _MMIO(0x250014) 1947 1948 #define CHV_CLK_CTL1 _MMIO(0x101100) 1949 #define VLV_CLK_CTL2 _MMIO(0x101104) 1950 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28 1951 1952 /* 1953 * Overlay regs 1954 */ 1955 1956 #define OVADD _MMIO(0x30000) 1957 #define DOVSTA _MMIO(0x30008) 1958 #define OC_BUF (0x3 << 20) 1959 #define OGAMC5 _MMIO(0x30010) 1960 #define OGAMC4 _MMIO(0x30014) 1961 #define OGAMC3 _MMIO(0x30018) 1962 #define OGAMC2 _MMIO(0x3001c) 1963 #define OGAMC1 _MMIO(0x30020) 1964 #define OGAMC0 _MMIO(0x30024) 1965 1966 /* 1967 * GEN9 clock gating regs 1968 */ 1969 #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530) 1970 #define DARBF_GATING_DIS (1 << 27) 1971 #define PWM2_GATING_DIS (1 << 14) 1972 #define PWM1_GATING_DIS (1 << 13) 1973 1974 #define GEN9_CLKGATE_DIS_3 _MMIO(0x46538) 1975 #define TGL_VRH_GATING_DIS REG_BIT(31) 1976 #define DPT_GATING_DIS REG_BIT(22) 1977 1978 #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C) 1979 #define BXT_GMBUS_GATING_DIS (1 << 14) 1980 1981 #define GEN9_CLKGATE_DIS_5 _MMIO(0x46540) 1982 #define DPCE_GATING_DIS REG_BIT(17) 1983 1984 #define _CLKGATE_DIS_PSL_A 0x46520 1985 #define _CLKGATE_DIS_PSL_B 0x46524 1986 #define _CLKGATE_DIS_PSL_C 0x46528 1987 #define DUPS1_GATING_DIS (1 << 15) 1988 #define DUPS2_GATING_DIS (1 << 19) 1989 #define DUPS3_GATING_DIS (1 << 23) 1990 #define CURSOR_GATING_DIS REG_BIT(28) 1991 #define DPF_GATING_DIS (1 << 10) 1992 #define DPF_RAM_GATING_DIS (1 << 9) 1993 #define DPFR_GATING_DIS (1 << 8) 1994 1995 #define CLKGATE_DIS_PSL(pipe) \ 1996 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B) 1997 1998 /* 1999 * Display engine regs 2000 */ 2001 2002 /* Pipe A CRC regs */ 2003 #define _PIPE_CRC_CTL_A 0x60050 2004 #define PIPE_CRC_ENABLE REG_BIT(31) 2005 /* skl+ source selection */ 2006 #define PIPE_CRC_SOURCE_MASK_SKL REG_GENMASK(30, 28) 2007 #define PIPE_CRC_SOURCE_PLANE_1_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 0) 2008 #define PIPE_CRC_SOURCE_PLANE_2_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 2) 2009 #define PIPE_CRC_SOURCE_DMUX_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 4) 2010 #define PIPE_CRC_SOURCE_PLANE_3_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 6) 2011 #define PIPE_CRC_SOURCE_PLANE_4_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 7) 2012 #define PIPE_CRC_SOURCE_PLANE_5_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 5) 2013 #define PIPE_CRC_SOURCE_PLANE_6_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 3) 2014 #define PIPE_CRC_SOURCE_PLANE_7_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 1) 2015 /* ivb+ source selection */ 2016 #define PIPE_CRC_SOURCE_MASK_IVB REG_GENMASK(30, 29) 2017 #define PIPE_CRC_SOURCE_PRIMARY_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 0) 2018 #define PIPE_CRC_SOURCE_SPRITE_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 1) 2019 #define PIPE_CRC_SOURCE_PF_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 2) 2020 /* ilk+ source selection */ 2021 #define PIPE_CRC_SOURCE_MASK_ILK REG_GENMASK(30, 28) 2022 #define PIPE_CRC_SOURCE_PRIMARY_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 0) 2023 #define PIPE_CRC_SOURCE_SPRITE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 1) 2024 #define PIPE_CRC_SOURCE_PIPE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 2) 2025 /* embedded DP port on the north display block */ 2026 #define PIPE_CRC_SOURCE_PORT_A_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 4) 2027 #define PIPE_CRC_SOURCE_FDI_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 5) 2028 /* vlv source selection */ 2029 #define PIPE_CRC_SOURCE_MASK_VLV REG_GENMASK(30, 27) 2030 #define PIPE_CRC_SOURCE_PIPE_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 0) 2031 #define PIPE_CRC_SOURCE_HDMIB_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 1) 2032 #define PIPE_CRC_SOURCE_HDMIC_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 2) 2033 /* with DP port the pipe source is invalid */ 2034 #define PIPE_CRC_SOURCE_DP_D_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 3) 2035 #define PIPE_CRC_SOURCE_DP_B_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 6) 2036 #define PIPE_CRC_SOURCE_DP_C_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 7) 2037 /* gen3+ source selection */ 2038 #define PIPE_CRC_SOURCE_MASK_I9XX REG_GENMASK(30, 28) 2039 #define PIPE_CRC_SOURCE_PIPE_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 0) 2040 #define PIPE_CRC_SOURCE_SDVOB_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 1) 2041 #define PIPE_CRC_SOURCE_SDVOC_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 2) 2042 /* with DP/TV port the pipe source is invalid */ 2043 #define PIPE_CRC_SOURCE_DP_D_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 3) 2044 #define PIPE_CRC_SOURCE_TV_PRE REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 4) 2045 #define PIPE_CRC_SOURCE_TV_POST REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 5) 2046 #define PIPE_CRC_SOURCE_DP_B_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 6) 2047 #define PIPE_CRC_SOURCE_DP_C_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 7) 2048 /* gen2 doesn't have source selection bits */ 2049 #define PIPE_CRC_INCLUDE_BORDER_I8XX REG_BIT(30) 2050 2051 #define _PIPE_CRC_RES_1_A_IVB 0x60064 2052 #define _PIPE_CRC_RES_2_A_IVB 0x60068 2053 #define _PIPE_CRC_RES_3_A_IVB 0x6006c 2054 #define _PIPE_CRC_RES_4_A_IVB 0x60070 2055 #define _PIPE_CRC_RES_5_A_IVB 0x60074 2056 2057 #define _PIPE_CRC_RES_RED_A 0x60060 2058 #define _PIPE_CRC_RES_GREEN_A 0x60064 2059 #define _PIPE_CRC_RES_BLUE_A 0x60068 2060 #define _PIPE_CRC_RES_RES1_A_I915 0x6006c 2061 #define _PIPE_CRC_RES_RES2_A_G4X 0x60080 2062 2063 /* Pipe B CRC regs */ 2064 #define _PIPE_CRC_RES_1_B_IVB 0x61064 2065 #define _PIPE_CRC_RES_2_B_IVB 0x61068 2066 #define _PIPE_CRC_RES_3_B_IVB 0x6106c 2067 #define _PIPE_CRC_RES_4_B_IVB 0x61070 2068 #define _PIPE_CRC_RES_5_B_IVB 0x61074 2069 2070 #define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A) 2071 #define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB) 2072 #define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB) 2073 #define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB) 2074 #define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB) 2075 #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB) 2076 2077 #define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A) 2078 #define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A) 2079 #define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A) 2080 #define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915) 2081 #define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X) 2082 2083 /* Pipe A timing regs */ 2084 #define _HTOTAL_A 0x60000 2085 #define _HBLANK_A 0x60004 2086 #define _HSYNC_A 0x60008 2087 #define _VTOTAL_A 0x6000c 2088 #define _VBLANK_A 0x60010 2089 #define _VSYNC_A 0x60014 2090 #define _EXITLINE_A 0x60018 2091 #define _PIPEASRC 0x6001c 2092 #define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16) 2093 #define PIPESRC_WIDTH(w) REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w)) 2094 #define PIPESRC_HEIGHT_MASK REG_GENMASK(15, 0) 2095 #define PIPESRC_HEIGHT(h) REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h)) 2096 #define _BCLRPAT_A 0x60020 2097 #define _VSYNCSHIFT_A 0x60028 2098 #define _PIPE_MULT_A 0x6002c 2099 2100 /* Pipe B timing regs */ 2101 #define _HTOTAL_B 0x61000 2102 #define _HBLANK_B 0x61004 2103 #define _HSYNC_B 0x61008 2104 #define _VTOTAL_B 0x6100c 2105 #define _VBLANK_B 0x61010 2106 #define _VSYNC_B 0x61014 2107 #define _PIPEBSRC 0x6101c 2108 #define _BCLRPAT_B 0x61020 2109 #define _VSYNCSHIFT_B 0x61028 2110 #define _PIPE_MULT_B 0x6102c 2111 2112 /* DSI 0 timing regs */ 2113 #define _HTOTAL_DSI0 0x6b000 2114 #define _HSYNC_DSI0 0x6b008 2115 #define _VTOTAL_DSI0 0x6b00c 2116 #define _VSYNC_DSI0 0x6b014 2117 #define _VSYNCSHIFT_DSI0 0x6b028 2118 2119 /* DSI 1 timing regs */ 2120 #define _HTOTAL_DSI1 0x6b800 2121 #define _HSYNC_DSI1 0x6b808 2122 #define _VTOTAL_DSI1 0x6b80c 2123 #define _VSYNC_DSI1 0x6b814 2124 #define _VSYNCSHIFT_DSI1 0x6b828 2125 2126 #define TRANSCODER_A_OFFSET 0x60000 2127 #define TRANSCODER_B_OFFSET 0x61000 2128 #define TRANSCODER_C_OFFSET 0x62000 2129 #define CHV_TRANSCODER_C_OFFSET 0x63000 2130 #define TRANSCODER_D_OFFSET 0x63000 2131 #define TRANSCODER_EDP_OFFSET 0x6f000 2132 #define TRANSCODER_DSI0_OFFSET 0x6b000 2133 #define TRANSCODER_DSI1_OFFSET 0x6b800 2134 2135 #define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A) 2136 #define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A) 2137 #define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A) 2138 #define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A) 2139 #define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A) 2140 #define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A) 2141 #define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A) 2142 #define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A) 2143 #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC) 2144 #define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A) 2145 2146 #define EXITLINE(trans) _MMIO_TRANS2(trans, _EXITLINE_A) 2147 #define EXITLINE_ENABLE REG_BIT(31) 2148 #define EXITLINE_MASK REG_GENMASK(12, 0) 2149 #define EXITLINE_SHIFT 0 2150 2151 /* VRR registers */ 2152 #define _TRANS_VRR_CTL_A 0x60420 2153 #define _TRANS_VRR_CTL_B 0x61420 2154 #define _TRANS_VRR_CTL_C 0x62420 2155 #define _TRANS_VRR_CTL_D 0x63420 2156 #define TRANS_VRR_CTL(trans) _MMIO_TRANS2(trans, _TRANS_VRR_CTL_A) 2157 #define VRR_CTL_VRR_ENABLE REG_BIT(31) 2158 #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) 2159 #define VRR_CTL_FLIP_LINE_EN REG_BIT(29) 2160 #define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3) 2161 #define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x)) 2162 #define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0) 2163 #define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0) 2164 #define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x)) 2165 2166 #define _TRANS_VRR_VMAX_A 0x60424 2167 #define _TRANS_VRR_VMAX_B 0x61424 2168 #define _TRANS_VRR_VMAX_C 0x62424 2169 #define _TRANS_VRR_VMAX_D 0x63424 2170 #define TRANS_VRR_VMAX(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMAX_A) 2171 #define VRR_VMAX_MASK REG_GENMASK(19, 0) 2172 2173 #define _TRANS_VRR_VMIN_A 0x60434 2174 #define _TRANS_VRR_VMIN_B 0x61434 2175 #define _TRANS_VRR_VMIN_C 0x62434 2176 #define _TRANS_VRR_VMIN_D 0x63434 2177 #define TRANS_VRR_VMIN(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMIN_A) 2178 #define VRR_VMIN_MASK REG_GENMASK(15, 0) 2179 2180 #define _TRANS_VRR_VMAXSHIFT_A 0x60428 2181 #define _TRANS_VRR_VMAXSHIFT_B 0x61428 2182 #define _TRANS_VRR_VMAXSHIFT_C 0x62428 2183 #define _TRANS_VRR_VMAXSHIFT_D 0x63428 2184 #define TRANS_VRR_VMAXSHIFT(trans) _MMIO_TRANS2(trans, \ 2185 _TRANS_VRR_VMAXSHIFT_A) 2186 #define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16) 2187 #define VRR_VMAXSHIFT_DEC REG_BIT(16) 2188 #define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0) 2189 2190 #define _TRANS_VRR_STATUS_A 0x6042C 2191 #define _TRANS_VRR_STATUS_B 0x6142C 2192 #define _TRANS_VRR_STATUS_C 0x6242C 2193 #define _TRANS_VRR_STATUS_D 0x6342C 2194 #define TRANS_VRR_STATUS(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS_A) 2195 #define VRR_STATUS_VMAX_REACHED REG_BIT(31) 2196 #define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30) 2197 #define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29) 2198 #define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28) 2199 #define VRR_STATUS_VRR_EN_LIVE REG_BIT(27) 2200 #define VRR_STATUS_FLIPS_SERVICED REG_BIT(26) 2201 #define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20) 2202 #define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0) 2203 #define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1) 2204 #define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2) 2205 #define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3) 2206 #define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4) 2207 #define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5) 2208 #define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6) 2209 2210 #define _TRANS_VRR_VTOTAL_PREV_A 0x60480 2211 #define _TRANS_VRR_VTOTAL_PREV_B 0x61480 2212 #define _TRANS_VRR_VTOTAL_PREV_C 0x62480 2213 #define _TRANS_VRR_VTOTAL_PREV_D 0x63480 2214 #define TRANS_VRR_VTOTAL_PREV(trans) _MMIO_TRANS2(trans, \ 2215 _TRANS_VRR_VTOTAL_PREV_A) 2216 #define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31) 2217 #define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30) 2218 #define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29) 2219 #define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0) 2220 2221 #define _TRANS_VRR_FLIPLINE_A 0x60438 2222 #define _TRANS_VRR_FLIPLINE_B 0x61438 2223 #define _TRANS_VRR_FLIPLINE_C 0x62438 2224 #define _TRANS_VRR_FLIPLINE_D 0x63438 2225 #define TRANS_VRR_FLIPLINE(trans) _MMIO_TRANS2(trans, \ 2226 _TRANS_VRR_FLIPLINE_A) 2227 #define VRR_FLIPLINE_MASK REG_GENMASK(19, 0) 2228 2229 #define _TRANS_VRR_STATUS2_A 0x6043C 2230 #define _TRANS_VRR_STATUS2_B 0x6143C 2231 #define _TRANS_VRR_STATUS2_C 0x6243C 2232 #define _TRANS_VRR_STATUS2_D 0x6343C 2233 #define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A) 2234 #define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0) 2235 2236 #define _TRANS_PUSH_A 0x60A70 2237 #define _TRANS_PUSH_B 0x61A70 2238 #define _TRANS_PUSH_C 0x62A70 2239 #define _TRANS_PUSH_D 0x63A70 2240 #define TRANS_PUSH(trans) _MMIO_TRANS2(trans, _TRANS_PUSH_A) 2241 #define TRANS_PUSH_EN REG_BIT(31) 2242 #define TRANS_PUSH_SEND REG_BIT(30) 2243 2244 /* 2245 * HSW+ eDP PSR registers 2246 * 2247 * HSW PSR registers are relative to DDIA(_DDI_BUF_CTL_A + 0x800) with just one 2248 * instance of it 2249 */ 2250 #define _SRD_CTL_A 0x60800 2251 #define _SRD_CTL_EDP 0x6f800 2252 #define EDP_PSR_CTL(tran) _MMIO(_TRANS2(tran, _SRD_CTL_A)) 2253 #define EDP_PSR_ENABLE (1 << 31) 2254 #define BDW_PSR_SINGLE_FRAME (1 << 30) 2255 #define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1 << 29) /* SW can't modify */ 2256 #define EDP_PSR_LINK_STANDBY (1 << 27) 2257 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3 << 25) 2258 #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0 << 25) 2259 #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1 << 25) 2260 #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2 << 25) 2261 #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3 << 25) 2262 #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20 2263 #define EDP_PSR_SKIP_AUX_EXIT (1 << 12) 2264 #define EDP_PSR_TP1_TP2_SEL (0 << 11) 2265 #define EDP_PSR_TP1_TP3_SEL (1 << 11) 2266 #define EDP_PSR_CRC_ENABLE (1 << 10) /* BDW+ */ 2267 #define EDP_PSR_TP2_TP3_TIME_500us (0 << 8) 2268 #define EDP_PSR_TP2_TP3_TIME_100us (1 << 8) 2269 #define EDP_PSR_TP2_TP3_TIME_2500us (2 << 8) 2270 #define EDP_PSR_TP2_TP3_TIME_0us (3 << 8) 2271 #define EDP_PSR_TP4_TIME_0US (3 << 6) /* ICL+ */ 2272 #define EDP_PSR_TP1_TIME_500us (0 << 4) 2273 #define EDP_PSR_TP1_TIME_100us (1 << 4) 2274 #define EDP_PSR_TP1_TIME_2500us (2 << 4) 2275 #define EDP_PSR_TP1_TIME_0us (3 << 4) 2276 #define EDP_PSR_IDLE_FRAME_SHIFT 0 2277 2278 /* 2279 * Until TGL, IMR/IIR are fixed at 0x648xx. On TGL+ those registers are relative 2280 * to transcoder and bits defined for each one as if using no shift (i.e. as if 2281 * it was for TRANSCODER_EDP) 2282 */ 2283 #define EDP_PSR_IMR _MMIO(0x64834) 2284 #define EDP_PSR_IIR _MMIO(0x64838) 2285 #define _PSR_IMR_A 0x60814 2286 #define _PSR_IIR_A 0x60818 2287 #define TRANS_PSR_IMR(tran) _MMIO_TRANS2(tran, _PSR_IMR_A) 2288 #define TRANS_PSR_IIR(tran) _MMIO_TRANS2(tran, _PSR_IIR_A) 2289 #define _EDP_PSR_TRANS_SHIFT(trans) ((trans) == TRANSCODER_EDP ? \ 2290 0 : ((trans) - TRANSCODER_A + 1) * 8) 2291 #define EDP_PSR_TRANS_MASK(trans) (0x7 << _EDP_PSR_TRANS_SHIFT(trans)) 2292 #define EDP_PSR_ERROR(trans) (0x4 << _EDP_PSR_TRANS_SHIFT(trans)) 2293 #define EDP_PSR_POST_EXIT(trans) (0x2 << _EDP_PSR_TRANS_SHIFT(trans)) 2294 #define EDP_PSR_PRE_ENTRY(trans) (0x1 << _EDP_PSR_TRANS_SHIFT(trans)) 2295 2296 #define _SRD_AUX_DATA_A 0x60814 2297 #define _SRD_AUX_DATA_EDP 0x6f814 2298 #define EDP_PSR_AUX_DATA(tran, i) _MMIO(_TRANS2(tran, _SRD_AUX_DATA_A) + (i) + 4) /* 5 registers */ 2299 2300 #define _SRD_STATUS_A 0x60840 2301 #define _SRD_STATUS_EDP 0x6f840 2302 #define EDP_PSR_STATUS(tran) _MMIO(_TRANS2(tran, _SRD_STATUS_A)) 2303 #define EDP_PSR_STATUS_STATE_MASK (7 << 29) 2304 #define EDP_PSR_STATUS_STATE_SHIFT 29 2305 #define EDP_PSR_STATUS_STATE_IDLE (0 << 29) 2306 #define EDP_PSR_STATUS_STATE_SRDONACK (1 << 29) 2307 #define EDP_PSR_STATUS_STATE_SRDENT (2 << 29) 2308 #define EDP_PSR_STATUS_STATE_BUFOFF (3 << 29) 2309 #define EDP_PSR_STATUS_STATE_BUFON (4 << 29) 2310 #define EDP_PSR_STATUS_STATE_AUXACK (5 << 29) 2311 #define EDP_PSR_STATUS_STATE_SRDOFFACK (6 << 29) 2312 #define EDP_PSR_STATUS_LINK_MASK (3 << 26) 2313 #define EDP_PSR_STATUS_LINK_FULL_OFF (0 << 26) 2314 #define EDP_PSR_STATUS_LINK_FULL_ON (1 << 26) 2315 #define EDP_PSR_STATUS_LINK_STANDBY (2 << 26) 2316 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20 2317 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f 2318 #define EDP_PSR_STATUS_COUNT_SHIFT 16 2319 #define EDP_PSR_STATUS_COUNT_MASK 0xf 2320 #define EDP_PSR_STATUS_AUX_ERROR (1 << 15) 2321 #define EDP_PSR_STATUS_AUX_SENDING (1 << 12) 2322 #define EDP_PSR_STATUS_SENDING_IDLE (1 << 9) 2323 #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1 << 8) 2324 #define EDP_PSR_STATUS_SENDING_TP1 (1 << 4) 2325 #define EDP_PSR_STATUS_IDLE_MASK 0xf 2326 2327 #define _SRD_PERF_CNT_A 0x60844 2328 #define _SRD_PERF_CNT_EDP 0x6f844 2329 #define EDP_PSR_PERF_CNT(tran) _MMIO(_TRANS2(tran, _SRD_PERF_CNT_A)) 2330 #define EDP_PSR_PERF_CNT_MASK 0xffffff 2331 2332 /* PSR_MASK on SKL+ */ 2333 #define _SRD_DEBUG_A 0x60860 2334 #define _SRD_DEBUG_EDP 0x6f860 2335 #define EDP_PSR_DEBUG(tran) _MMIO(_TRANS2(tran, _SRD_DEBUG_A)) 2336 #define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1 << 28) 2337 #define EDP_PSR_DEBUG_MASK_LPSP (1 << 27) 2338 #define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26) 2339 #define EDP_PSR_DEBUG_MASK_HPD (1 << 25) 2340 #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ */ 2341 #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */ 2342 2343 #define _PSR2_CTL_A 0x60900 2344 #define _PSR2_CTL_EDP 0x6f900 2345 #define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A) 2346 #define EDP_PSR2_ENABLE (1 << 31) 2347 #define EDP_SU_TRACK_ENABLE (1 << 30) /* up to adl-p */ 2348 #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28) 2349 #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28) 2350 #define EDP_Y_COORDINATE_ENABLE REG_BIT(25) /* display 10, 11 and 12 */ 2351 #define EDP_PSR2_SU_SDP_SCANLINE REG_BIT(25) /* display 13+ */ 2352 #define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20) 2353 #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20) 2354 #define EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES 8 2355 #define EDP_PSR2_IO_BUFFER_WAKE(lines) ((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) << 13) 2356 #define EDP_PSR2_IO_BUFFER_WAKE_MASK (3 << 13) 2357 #define TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5 2358 #define TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT 13 2359 #define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) (((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT) 2360 #define TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK (7 << 13) 2361 #define EDP_PSR2_FAST_WAKE_MAX_LINES 8 2362 #define EDP_PSR2_FAST_WAKE(lines) ((EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) << 11) 2363 #define EDP_PSR2_FAST_WAKE_MASK (3 << 11) 2364 #define TGL_EDP_PSR2_FAST_WAKE_MIN_LINES 5 2365 #define TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT 10 2366 #define TGL_EDP_PSR2_FAST_WAKE(lines) (((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT) 2367 #define TGL_EDP_PSR2_FAST_WAKE_MASK (7 << 10) 2368 #define EDP_PSR2_TP2_TIME_500us (0 << 8) 2369 #define EDP_PSR2_TP2_TIME_100us (1 << 8) 2370 #define EDP_PSR2_TP2_TIME_2500us (2 << 8) 2371 #define EDP_PSR2_TP2_TIME_50us (3 << 8) 2372 #define EDP_PSR2_TP2_TIME_MASK (3 << 8) 2373 #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 2374 #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4) 2375 #define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4) 2376 #define EDP_PSR2_IDLE_FRAME_MASK 0xf 2377 #define EDP_PSR2_IDLE_FRAME_SHIFT 0 2378 2379 #define _PSR_EVENT_TRANS_A 0x60848 2380 #define _PSR_EVENT_TRANS_B 0x61848 2381 #define _PSR_EVENT_TRANS_C 0x62848 2382 #define _PSR_EVENT_TRANS_D 0x63848 2383 #define _PSR_EVENT_TRANS_EDP 0x6f848 2384 #define PSR_EVENT(tran) _MMIO_TRANS2(tran, _PSR_EVENT_TRANS_A) 2385 #define PSR_EVENT_PSR2_WD_TIMER_EXPIRE (1 << 17) 2386 #define PSR_EVENT_PSR2_DISABLED (1 << 16) 2387 #define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN (1 << 15) 2388 #define PSR_EVENT_SU_CRC_FIFO_UNDERRUN (1 << 14) 2389 #define PSR_EVENT_GRAPHICS_RESET (1 << 12) 2390 #define PSR_EVENT_PCH_INTERRUPT (1 << 11) 2391 #define PSR_EVENT_MEMORY_UP (1 << 10) 2392 #define PSR_EVENT_FRONT_BUFFER_MODIFY (1 << 9) 2393 #define PSR_EVENT_WD_TIMER_EXPIRE (1 << 8) 2394 #define PSR_EVENT_PIPE_REGISTERS_UPDATE (1 << 6) 2395 #define PSR_EVENT_REGISTER_UPDATE (1 << 5) /* Reserved in ICL+ */ 2396 #define PSR_EVENT_HDCP_ENABLE (1 << 4) 2397 #define PSR_EVENT_KVMR_SESSION_ENABLE (1 << 3) 2398 #define PSR_EVENT_VBI_ENABLE (1 << 2) 2399 #define PSR_EVENT_LPSP_MODE_EXIT (1 << 1) 2400 #define PSR_EVENT_PSR_DISABLE (1 << 0) 2401 2402 #define _PSR2_STATUS_A 0x60940 2403 #define _PSR2_STATUS_EDP 0x6f940 2404 #define EDP_PSR2_STATUS(tran) _MMIO_TRANS2(tran, _PSR2_STATUS_A) 2405 #define EDP_PSR2_STATUS_STATE_MASK REG_GENMASK(31, 28) 2406 #define EDP_PSR2_STATUS_STATE_DEEP_SLEEP REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x8) 2407 2408 #define _PSR2_SU_STATUS_A 0x60914 2409 #define _PSR2_SU_STATUS_EDP 0x6f914 2410 #define _PSR2_SU_STATUS(tran, index) _MMIO(_TRANS2(tran, _PSR2_SU_STATUS_A) + (index) * 4) 2411 #define PSR2_SU_STATUS(tran, frame) (_PSR2_SU_STATUS(tran, (frame) / 3)) 2412 #define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10) 2413 #define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame)) 2414 #define PSR2_SU_STATUS_FRAMES 8 2415 2416 #define _PSR2_MAN_TRK_CTL_A 0x60910 2417 #define _PSR2_MAN_TRK_CTL_EDP 0x6f910 2418 #define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A) 2419 #define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31) 2420 #define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21) 2421 #define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val) 2422 #define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(20, 11) 2423 #define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val) 2424 #define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3) 2425 #define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2) 2426 #define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1) 2427 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(28, 16) 2428 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val) 2429 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(12, 0) 2430 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val) 2431 #define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(14) 2432 #define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13) 2433 2434 /* Icelake DSC Rate Control Range Parameter Registers */ 2435 #define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240) 2436 #define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4) 2437 #define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40) 2438 #define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4) 2439 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208) 2440 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4) 2441 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308) 2442 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4) 2443 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408) 2444 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4) 2445 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508) 2446 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4) 2447 #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2448 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \ 2449 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC) 2450 #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2451 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \ 2452 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC) 2453 #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2454 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \ 2455 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC) 2456 #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2457 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \ 2458 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC) 2459 #define RC_BPG_OFFSET_SHIFT 10 2460 #define RC_MAX_QP_SHIFT 5 2461 #define RC_MIN_QP_SHIFT 0 2462 2463 #define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248) 2464 #define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4) 2465 #define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48) 2466 #define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4) 2467 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210) 2468 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4) 2469 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310) 2470 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4) 2471 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410) 2472 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4) 2473 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510) 2474 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4) 2475 #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2476 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \ 2477 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC) 2478 #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2479 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \ 2480 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC) 2481 #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2482 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \ 2483 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC) 2484 #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2485 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \ 2486 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC) 2487 2488 #define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250) 2489 #define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4) 2490 #define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50) 2491 #define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4) 2492 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218) 2493 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4) 2494 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318) 2495 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4) 2496 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418) 2497 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4) 2498 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518) 2499 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4) 2500 #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2501 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \ 2502 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC) 2503 #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2504 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \ 2505 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC) 2506 #define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2507 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \ 2508 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC) 2509 #define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2510 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \ 2511 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC) 2512 2513 #define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258) 2514 #define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4) 2515 #define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58) 2516 #define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4) 2517 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220) 2518 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4) 2519 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320) 2520 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4) 2521 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420) 2522 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4) 2523 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520) 2524 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4) 2525 #define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2526 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \ 2527 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC) 2528 #define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2529 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \ 2530 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC) 2531 #define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2532 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \ 2533 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC) 2534 #define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2535 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \ 2536 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC) 2537 2538 /* VGA port control */ 2539 #define ADPA _MMIO(0x61100) 2540 #define PCH_ADPA _MMIO(0xe1100) 2541 #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100) 2542 2543 #define ADPA_DAC_ENABLE (1 << 31) 2544 #define ADPA_DAC_DISABLE 0 2545 #define ADPA_PIPE_SEL_SHIFT 30 2546 #define ADPA_PIPE_SEL_MASK (1 << 30) 2547 #define ADPA_PIPE_SEL(pipe) ((pipe) << 30) 2548 #define ADPA_PIPE_SEL_SHIFT_CPT 29 2549 #define ADPA_PIPE_SEL_MASK_CPT (3 << 29) 2550 #define ADPA_PIPE_SEL_CPT(pipe) ((pipe) << 29) 2551 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ 2552 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0 << 24) 2553 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3 << 24) 2554 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24) 2555 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2 << 24) 2556 #define ADPA_CRT_HOTPLUG_ENABLE (1 << 23) 2557 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0 << 22) 2558 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1 << 22) 2559 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0 << 21) 2560 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1 << 21) 2561 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0 << 20) 2562 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1 << 20) 2563 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0 << 18) 2564 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1 << 18) 2565 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2 << 18) 2566 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3 << 18) 2567 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0 << 17) 2568 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1 << 17) 2569 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16) 2570 #define ADPA_USE_VGA_HVPOLARITY (1 << 15) 2571 #define ADPA_SETS_HVPOLARITY 0 2572 #define ADPA_VSYNC_CNTL_DISABLE (1 << 10) 2573 #define ADPA_VSYNC_CNTL_ENABLE 0 2574 #define ADPA_HSYNC_CNTL_DISABLE (1 << 11) 2575 #define ADPA_HSYNC_CNTL_ENABLE 0 2576 #define ADPA_VSYNC_ACTIVE_HIGH (1 << 4) 2577 #define ADPA_VSYNC_ACTIVE_LOW 0 2578 #define ADPA_HSYNC_ACTIVE_HIGH (1 << 3) 2579 #define ADPA_HSYNC_ACTIVE_LOW 0 2580 #define ADPA_DPMS_MASK (~(3 << 10)) 2581 #define ADPA_DPMS_ON (0 << 10) 2582 #define ADPA_DPMS_SUSPEND (1 << 10) 2583 #define ADPA_DPMS_STANDBY (2 << 10) 2584 #define ADPA_DPMS_OFF (3 << 10) 2585 2586 2587 /* Hotplug control (945+ only) */ 2588 #define PORT_HOTPLUG_EN _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110) 2589 #define PORTB_HOTPLUG_INT_EN (1 << 29) 2590 #define PORTC_HOTPLUG_INT_EN (1 << 28) 2591 #define PORTD_HOTPLUG_INT_EN (1 << 27) 2592 #define SDVOB_HOTPLUG_INT_EN (1 << 26) 2593 #define SDVOC_HOTPLUG_INT_EN (1 << 25) 2594 #define TV_HOTPLUG_INT_EN (1 << 18) 2595 #define CRT_HOTPLUG_INT_EN (1 << 9) 2596 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \ 2597 PORTC_HOTPLUG_INT_EN | \ 2598 PORTD_HOTPLUG_INT_EN | \ 2599 SDVOC_HOTPLUG_INT_EN | \ 2600 SDVOB_HOTPLUG_INT_EN | \ 2601 CRT_HOTPLUG_INT_EN) 2602 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 2603 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 2604 /* must use period 64 on GM45 according to docs */ 2605 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 2606 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 2607 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 2608 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 2609 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 2610 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 2611 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 2612 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 2613 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 2614 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 2615 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 2616 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 2617 2618 #define PORT_HOTPLUG_STAT _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114) 2619 /* 2620 * HDMI/DP bits are g4x+ 2621 * 2622 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused. 2623 * Please check the detailed lore in the commit message for for experimental 2624 * evidence. 2625 */ 2626 /* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */ 2627 #define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29) 2628 #define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28) 2629 #define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27) 2630 /* G4X/VLV/CHV DP/HDMI bits again match Bspec */ 2631 #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27) 2632 #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) 2633 #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29) 2634 #define PORTD_HOTPLUG_INT_STATUS (3 << 21) 2635 #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21) 2636 #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21) 2637 #define PORTC_HOTPLUG_INT_STATUS (3 << 19) 2638 #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19) 2639 #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19) 2640 #define PORTB_HOTPLUG_INT_STATUS (3 << 17) 2641 #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17) 2642 #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17) 2643 /* CRT/TV common between gen3+ */ 2644 #define CRT_HOTPLUG_INT_STATUS (1 << 11) 2645 #define TV_HOTPLUG_INT_STATUS (1 << 10) 2646 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 2647 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 2648 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 2649 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 2650 #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6) 2651 #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5) 2652 #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4) 2653 #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4) 2654 2655 /* SDVO is different across gen3/4 */ 2656 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) 2657 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) 2658 /* 2659 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, 2660 * since reality corrobates that they're the same as on gen3. But keep these 2661 * bits here (and the comment!) to help any other lost wanderers back onto the 2662 * right tracks. 2663 */ 2664 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) 2665 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) 2666 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) 2667 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) 2668 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \ 2669 SDVOB_HOTPLUG_INT_STATUS_G4X | \ 2670 SDVOC_HOTPLUG_INT_STATUS_G4X | \ 2671 PORTB_HOTPLUG_INT_STATUS | \ 2672 PORTC_HOTPLUG_INT_STATUS | \ 2673 PORTD_HOTPLUG_INT_STATUS) 2674 2675 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \ 2676 SDVOB_HOTPLUG_INT_STATUS_I915 | \ 2677 SDVOC_HOTPLUG_INT_STATUS_I915 | \ 2678 PORTB_HOTPLUG_INT_STATUS | \ 2679 PORTC_HOTPLUG_INT_STATUS | \ 2680 PORTD_HOTPLUG_INT_STATUS) 2681 2682 /* SDVO and HDMI port control. 2683 * The same register may be used for SDVO or HDMI */ 2684 #define _GEN3_SDVOB 0x61140 2685 #define _GEN3_SDVOC 0x61160 2686 #define GEN3_SDVOB _MMIO(_GEN3_SDVOB) 2687 #define GEN3_SDVOC _MMIO(_GEN3_SDVOC) 2688 #define GEN4_HDMIB GEN3_SDVOB 2689 #define GEN4_HDMIC GEN3_SDVOC 2690 #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140) 2691 #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160) 2692 #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C) 2693 #define PCH_SDVOB _MMIO(0xe1140) 2694 #define PCH_HDMIB PCH_SDVOB 2695 #define PCH_HDMIC _MMIO(0xe1150) 2696 #define PCH_HDMID _MMIO(0xe1160) 2697 2698 #define PORT_DFT_I9XX _MMIO(0x61150) 2699 #define DC_BALANCE_RESET (1 << 25) 2700 #define PORT_DFT2_G4X _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154) 2701 #define DC_BALANCE_RESET_VLV (1 << 31) 2702 #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0)) 2703 #define PIPE_C_SCRAMBLE_RESET REG_BIT(14) /* chv */ 2704 #define PIPE_B_SCRAMBLE_RESET REG_BIT(1) 2705 #define PIPE_A_SCRAMBLE_RESET REG_BIT(0) 2706 2707 /* Gen 3 SDVO bits: */ 2708 #define SDVO_ENABLE (1 << 31) 2709 #define SDVO_PIPE_SEL_SHIFT 30 2710 #define SDVO_PIPE_SEL_MASK (1 << 30) 2711 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30) 2712 #define SDVO_STALL_SELECT (1 << 29) 2713 #define SDVO_INTERRUPT_ENABLE (1 << 26) 2714 /* 2715 * 915G/GM SDVO pixel multiplier. 2716 * Programmed value is multiplier - 1, up to 5x. 2717 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 2718 */ 2719 #define SDVO_PORT_MULTIPLY_MASK (7 << 23) 2720 #define SDVO_PORT_MULTIPLY_SHIFT 23 2721 #define SDVO_PHASE_SELECT_MASK (15 << 19) 2722 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 2723 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 2724 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */ 2725 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */ 2726 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */ 2727 #define SDVO_DETECTED (1 << 2) 2728 /* Bits to be preserved when writing */ 2729 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \ 2730 SDVO_INTERRUPT_ENABLE) 2731 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE) 2732 2733 /* Gen 4 SDVO/HDMI bits: */ 2734 #define SDVO_COLOR_FORMAT_8bpc (0 << 26) 2735 #define SDVO_COLOR_FORMAT_MASK (7 << 26) 2736 #define SDVO_ENCODING_SDVO (0 << 10) 2737 #define SDVO_ENCODING_HDMI (2 << 10) 2738 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */ 2739 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */ 2740 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */ 2741 #define HDMI_AUDIO_ENABLE (1 << 6) /* HDMI only */ 2742 /* VSYNC/HSYNC bits new with 965, default is to be set */ 2743 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) 2744 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) 2745 2746 /* Gen 5 (IBX) SDVO/HDMI bits: */ 2747 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */ 2748 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */ 2749 2750 /* Gen 6 (CPT) SDVO/HDMI bits: */ 2751 #define SDVO_PIPE_SEL_SHIFT_CPT 29 2752 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29) 2753 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29) 2754 2755 /* CHV SDVO/HDMI bits: */ 2756 #define SDVO_PIPE_SEL_SHIFT_CHV 24 2757 #define SDVO_PIPE_SEL_MASK_CHV (3 << 24) 2758 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24) 2759 2760 2761 /* DVO port control */ 2762 #define _DVOA 0x61120 2763 #define DVOA _MMIO(_DVOA) 2764 #define _DVOB 0x61140 2765 #define DVOB _MMIO(_DVOB) 2766 #define _DVOC 0x61160 2767 #define DVOC _MMIO(_DVOC) 2768 #define DVO_ENABLE (1 << 31) 2769 #define DVO_PIPE_SEL_SHIFT 30 2770 #define DVO_PIPE_SEL_MASK (1 << 30) 2771 #define DVO_PIPE_SEL(pipe) ((pipe) << 30) 2772 #define DVO_PIPE_STALL_UNUSED (0 << 28) 2773 #define DVO_PIPE_STALL (1 << 28) 2774 #define DVO_PIPE_STALL_TV (2 << 28) 2775 #define DVO_PIPE_STALL_MASK (3 << 28) 2776 #define DVO_USE_VGA_SYNC (1 << 15) 2777 #define DVO_DATA_ORDER_I740 (0 << 14) 2778 #define DVO_DATA_ORDER_FP (1 << 14) 2779 #define DVO_VSYNC_DISABLE (1 << 11) 2780 #define DVO_HSYNC_DISABLE (1 << 10) 2781 #define DVO_VSYNC_TRISTATE (1 << 9) 2782 #define DVO_HSYNC_TRISTATE (1 << 8) 2783 #define DVO_BORDER_ENABLE (1 << 7) 2784 #define DVO_DATA_ORDER_GBRG (1 << 6) 2785 #define DVO_DATA_ORDER_RGGB (0 << 6) 2786 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) 2787 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) 2788 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4) 2789 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3) 2790 #define DVO_BLANK_ACTIVE_HIGH (1 << 2) 2791 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ 2792 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ 2793 #define DVO_PRESERVE_MASK (0x7 << 24) 2794 #define DVOA_SRCDIM _MMIO(0x61124) 2795 #define DVOB_SRCDIM _MMIO(0x61144) 2796 #define DVOC_SRCDIM _MMIO(0x61164) 2797 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12 2798 #define DVO_SRCDIM_VERTICAL_SHIFT 0 2799 2800 /* LVDS port control */ 2801 #define LVDS _MMIO(0x61180) 2802 /* 2803 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 2804 * the DPLL semantics change when the LVDS is assigned to that pipe. 2805 */ 2806 #define LVDS_PORT_EN (1 << 31) 2807 /* Selects pipe B for LVDS data. Must be set on pre-965. */ 2808 #define LVDS_PIPE_SEL_SHIFT 30 2809 #define LVDS_PIPE_SEL_MASK (1 << 30) 2810 #define LVDS_PIPE_SEL(pipe) ((pipe) << 30) 2811 #define LVDS_PIPE_SEL_SHIFT_CPT 29 2812 #define LVDS_PIPE_SEL_MASK_CPT (3 << 29) 2813 #define LVDS_PIPE_SEL_CPT(pipe) ((pipe) << 29) 2814 /* LVDS dithering flag on 965/g4x platform */ 2815 #define LVDS_ENABLE_DITHER (1 << 25) 2816 /* LVDS sync polarity flags. Set to invert (i.e. negative) */ 2817 #define LVDS_VSYNC_POLARITY (1 << 21) 2818 #define LVDS_HSYNC_POLARITY (1 << 20) 2819 2820 /* Enable border for unscaled (or aspect-scaled) display */ 2821 #define LVDS_BORDER_ENABLE (1 << 15) 2822 /* 2823 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 2824 * pixel. 2825 */ 2826 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 2827 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 2828 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 2829 /* 2830 * Controls the A3 data pair, which contains the additional LSBs for 24 bit 2831 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 2832 * on. 2833 */ 2834 #define LVDS_A3_POWER_MASK (3 << 6) 2835 #define LVDS_A3_POWER_DOWN (0 << 6) 2836 #define LVDS_A3_POWER_UP (3 << 6) 2837 /* 2838 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 2839 * is set. 2840 */ 2841 #define LVDS_CLKB_POWER_MASK (3 << 4) 2842 #define LVDS_CLKB_POWER_DOWN (0 << 4) 2843 #define LVDS_CLKB_POWER_UP (3 << 4) 2844 /* 2845 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 2846 * setting for whether we are in dual-channel mode. The B3 pair will 2847 * additionally only be powered up when LVDS_A3_POWER_UP is set. 2848 */ 2849 #define LVDS_B0B3_POWER_MASK (3 << 2) 2850 #define LVDS_B0B3_POWER_DOWN (0 << 2) 2851 #define LVDS_B0B3_POWER_UP (3 << 2) 2852 2853 /* Video Data Island Packet control */ 2854 #define VIDEO_DIP_DATA _MMIO(0x61178) 2855 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC 2856 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte 2857 * of the infoframe structure specified by CEA-861. */ 2858 #define VIDEO_DIP_DATA_SIZE 32 2859 #define VIDEO_DIP_GMP_DATA_SIZE 36 2860 #define VIDEO_DIP_VSC_DATA_SIZE 36 2861 #define VIDEO_DIP_PPS_DATA_SIZE 132 2862 #define VIDEO_DIP_CTL _MMIO(0x61170) 2863 /* Pre HSW: */ 2864 #define VIDEO_DIP_ENABLE (1 << 31) 2865 #define VIDEO_DIP_PORT(port) ((port) << 29) 2866 #define VIDEO_DIP_PORT_MASK (3 << 29) 2867 #define VIDEO_DIP_ENABLE_GCP (1 << 25) /* ilk+ */ 2868 #define VIDEO_DIP_ENABLE_AVI (1 << 21) 2869 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) 2870 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) /* ilk+ */ 2871 #define VIDEO_DIP_ENABLE_SPD (8 << 21) 2872 #define VIDEO_DIP_SELECT_AVI (0 << 19) 2873 #define VIDEO_DIP_SELECT_VENDOR (1 << 19) 2874 #define VIDEO_DIP_SELECT_GAMUT (2 << 19) 2875 #define VIDEO_DIP_SELECT_SPD (3 << 19) 2876 #define VIDEO_DIP_SELECT_MASK (3 << 19) 2877 #define VIDEO_DIP_FREQ_ONCE (0 << 16) 2878 #define VIDEO_DIP_FREQ_VSYNC (1 << 16) 2879 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) 2880 #define VIDEO_DIP_FREQ_MASK (3 << 16) 2881 /* HSW and later: */ 2882 #define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28) 2883 #define PSR_VSC_BIT_7_SET (1 << 27) 2884 #define VSC_SELECT_MASK (0x3 << 25) 2885 #define VSC_SELECT_SHIFT 25 2886 #define VSC_DIP_HW_HEA_DATA (0 << 25) 2887 #define VSC_DIP_HW_HEA_SW_DATA (1 << 25) 2888 #define VSC_DIP_HW_DATA_SW_HEA (2 << 25) 2889 #define VSC_DIP_SW_HEA_DATA (3 << 25) 2890 #define VDIP_ENABLE_PPS (1 << 24) 2891 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) 2892 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) 2893 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) 2894 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) 2895 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) 2896 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) 2897 2898 /* Panel power sequencing */ 2899 #define PPS_BASE 0x61200 2900 #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE) 2901 #define PCH_PPS_BASE 0xC7200 2902 2903 #define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \ 2904 PPS_BASE + (reg) + \ 2905 (pps_idx) * 0x100) 2906 2907 #define _PP_STATUS 0x61200 2908 #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS) 2909 #define PP_ON REG_BIT(31) 2910 /* 2911 * Indicates that all dependencies of the panel are on: 2912 * 2913 * - PLL enabled 2914 * - pipe enabled 2915 * - LVDS/DVOB/DVOC on 2916 */ 2917 #define PP_READY REG_BIT(30) 2918 #define PP_SEQUENCE_MASK REG_GENMASK(29, 28) 2919 #define PP_SEQUENCE_NONE REG_FIELD_PREP(PP_SEQUENCE_MASK, 0) 2920 #define PP_SEQUENCE_POWER_UP REG_FIELD_PREP(PP_SEQUENCE_MASK, 1) 2921 #define PP_SEQUENCE_POWER_DOWN REG_FIELD_PREP(PP_SEQUENCE_MASK, 2) 2922 #define PP_CYCLE_DELAY_ACTIVE REG_BIT(27) 2923 #define PP_SEQUENCE_STATE_MASK REG_GENMASK(3, 0) 2924 #define PP_SEQUENCE_STATE_OFF_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0) 2925 #define PP_SEQUENCE_STATE_OFF_S0_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1) 2926 #define PP_SEQUENCE_STATE_OFF_S0_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2) 2927 #define PP_SEQUENCE_STATE_OFF_S0_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3) 2928 #define PP_SEQUENCE_STATE_ON_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8) 2929 #define PP_SEQUENCE_STATE_ON_S1_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9) 2930 #define PP_SEQUENCE_STATE_ON_S1_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa) 2931 #define PP_SEQUENCE_STATE_ON_S1_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb) 2932 #define PP_SEQUENCE_STATE_RESET REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf) 2933 2934 #define _PP_CONTROL 0x61204 2935 #define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL) 2936 #define PANEL_UNLOCK_MASK REG_GENMASK(31, 16) 2937 #define PANEL_UNLOCK_REGS REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd) 2938 #define BXT_POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4) 2939 #define EDP_FORCE_VDD REG_BIT(3) 2940 #define EDP_BLC_ENABLE REG_BIT(2) 2941 #define PANEL_POWER_RESET REG_BIT(1) 2942 #define PANEL_POWER_ON REG_BIT(0) 2943 2944 #define _PP_ON_DELAYS 0x61208 2945 #define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS) 2946 #define PANEL_PORT_SELECT_MASK REG_GENMASK(31, 30) 2947 #define PANEL_PORT_SELECT_LVDS REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0) 2948 #define PANEL_PORT_SELECT_DPA REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1) 2949 #define PANEL_PORT_SELECT_DPC REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 2) 2950 #define PANEL_PORT_SELECT_DPD REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 3) 2951 #define PANEL_PORT_SELECT_VLV(port) REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, port) 2952 #define PANEL_POWER_UP_DELAY_MASK REG_GENMASK(28, 16) 2953 #define PANEL_LIGHT_ON_DELAY_MASK REG_GENMASK(12, 0) 2954 2955 #define _PP_OFF_DELAYS 0x6120C 2956 #define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS) 2957 #define PANEL_POWER_DOWN_DELAY_MASK REG_GENMASK(28, 16) 2958 #define PANEL_LIGHT_OFF_DELAY_MASK REG_GENMASK(12, 0) 2959 2960 #define _PP_DIVISOR 0x61210 2961 #define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR) 2962 #define PP_REFERENCE_DIVIDER_MASK REG_GENMASK(31, 8) 2963 #define PANEL_POWER_CYCLE_DELAY_MASK REG_GENMASK(4, 0) 2964 2965 /* Panel fitting */ 2966 #define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230) 2967 #define PFIT_ENABLE (1 << 31) 2968 #define PFIT_PIPE_MASK (3 << 29) 2969 #define PFIT_PIPE_SHIFT 29 2970 #define PFIT_PIPE(pipe) ((pipe) << 29) 2971 #define VERT_INTERP_DISABLE (0 << 10) 2972 #define VERT_INTERP_BILINEAR (1 << 10) 2973 #define VERT_INTERP_MASK (3 << 10) 2974 #define VERT_AUTO_SCALE (1 << 9) 2975 #define HORIZ_INTERP_DISABLE (0 << 6) 2976 #define HORIZ_INTERP_BILINEAR (1 << 6) 2977 #define HORIZ_INTERP_MASK (3 << 6) 2978 #define HORIZ_AUTO_SCALE (1 << 5) 2979 #define PANEL_8TO6_DITHER_ENABLE (1 << 3) 2980 #define PFIT_FILTER_FUZZY (0 << 24) 2981 #define PFIT_SCALING_AUTO (0 << 26) 2982 #define PFIT_SCALING_PROGRAMMED (1 << 26) 2983 #define PFIT_SCALING_PILLAR (2 << 26) 2984 #define PFIT_SCALING_LETTER (3 << 26) 2985 #define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234) 2986 /* Pre-965 */ 2987 #define PFIT_VERT_SCALE_SHIFT 20 2988 #define PFIT_VERT_SCALE_MASK 0xfff00000 2989 #define PFIT_HORIZ_SCALE_SHIFT 4 2990 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 2991 /* 965+ */ 2992 #define PFIT_VERT_SCALE_SHIFT_965 16 2993 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000 2994 #define PFIT_HORIZ_SCALE_SHIFT_965 0 2995 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff 2996 2997 #define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238) 2998 2999 #define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250) 3000 #define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350) 3001 #define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \ 3002 _VLV_BLC_PWM_CTL2_B) 3003 3004 #define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61254) 3005 #define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61354) 3006 #define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \ 3007 _VLV_BLC_PWM_CTL_B) 3008 3009 #define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260) 3010 #define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360) 3011 #define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \ 3012 _VLV_BLC_HIST_CTL_B) 3013 3014 /* Backlight control */ 3015 #define BLC_PWM_CTL2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+ only */ 3016 #define BLM_PWM_ENABLE (1 << 31) 3017 #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ 3018 #define BLM_PIPE_SELECT (1 << 29) 3019 #define BLM_PIPE_SELECT_IVB (3 << 29) 3020 #define BLM_PIPE_A (0 << 29) 3021 #define BLM_PIPE_B (1 << 29) 3022 #define BLM_PIPE_C (2 << 29) /* ivb + */ 3023 #define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */ 3024 #define BLM_TRANSCODER_B BLM_PIPE_B 3025 #define BLM_TRANSCODER_C BLM_PIPE_C 3026 #define BLM_TRANSCODER_EDP (3 << 29) 3027 #define BLM_PIPE(pipe) ((pipe) << 29) 3028 #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */ 3029 #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26) 3030 #define BLM_PHASE_IN_ENABLE (1 << 25) 3031 #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24) 3032 #define BLM_PHASE_IN_TIME_BASE_SHIFT (16) 3033 #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16) 3034 #define BLM_PHASE_IN_COUNT_SHIFT (8) 3035 #define BLM_PHASE_IN_COUNT_MASK (0xff << 8) 3036 #define BLM_PHASE_IN_INCR_SHIFT (0) 3037 #define BLM_PHASE_IN_INCR_MASK (0xff << 0) 3038 #define BLC_PWM_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254) 3039 /* 3040 * This is the most significant 15 bits of the number of backlight cycles in a 3041 * complete cycle of the modulated backlight control. 3042 * 3043 * The actual value is this field multiplied by two. 3044 */ 3045 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 3046 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) 3047 #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */ 3048 /* 3049 * This is the number of cycles out of the backlight modulation cycle for which 3050 * the backlight is on. 3051 * 3052 * This field must be no greater than the number of cycles in the complete 3053 * backlight modulation cycle. 3054 */ 3055 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) 3056 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) 3057 #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) 3058 #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ 3059 3060 #define BLC_HIST_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260) 3061 #define BLM_HISTOGRAM_ENABLE (1 << 31) 3062 3063 /* New registers for PCH-split platforms. Safe where new bits show up, the 3064 * register layout machtes with gen4 BLC_PWM_CTL[12]. */ 3065 #define BLC_PWM_CPU_CTL2 _MMIO(0x48250) 3066 #define BLC_PWM_CPU_CTL _MMIO(0x48254) 3067 3068 #define HSW_BLC_PWM2_CTL _MMIO(0x48350) 3069 3070 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is 3071 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */ 3072 #define BLC_PWM_PCH_CTL1 _MMIO(0xc8250) 3073 #define BLM_PCH_PWM_ENABLE (1 << 31) 3074 #define BLM_PCH_OVERRIDE_ENABLE (1 << 30) 3075 #define BLM_PCH_POLARITY (1 << 29) 3076 #define BLC_PWM_PCH_CTL2 _MMIO(0xc8254) 3077 3078 #define UTIL_PIN_CTL _MMIO(0x48400) 3079 #define UTIL_PIN_ENABLE (1 << 31) 3080 #define UTIL_PIN_PIPE_MASK (3 << 29) 3081 #define UTIL_PIN_PIPE(x) ((x) << 29) 3082 #define UTIL_PIN_MODE_MASK (0xf << 24) 3083 #define UTIL_PIN_MODE_DATA (0 << 24) 3084 #define UTIL_PIN_MODE_PWM (1 << 24) 3085 #define UTIL_PIN_MODE_VBLANK (4 << 24) 3086 #define UTIL_PIN_MODE_VSYNC (5 << 24) 3087 #define UTIL_PIN_MODE_EYE_LEVEL (8 << 24) 3088 #define UTIL_PIN_OUTPUT_DATA (1 << 23) 3089 #define UTIL_PIN_POLARITY (1 << 22) 3090 #define UTIL_PIN_DIRECTION_INPUT (1 << 19) 3091 #define UTIL_PIN_INPUT_DATA (1 << 16) 3092 3093 /* BXT backlight register definition. */ 3094 #define _BXT_BLC_PWM_CTL1 0xC8250 3095 #define BXT_BLC_PWM_ENABLE (1 << 31) 3096 #define BXT_BLC_PWM_POLARITY (1 << 29) 3097 #define _BXT_BLC_PWM_FREQ1 0xC8254 3098 #define _BXT_BLC_PWM_DUTY1 0xC8258 3099 3100 #define _BXT_BLC_PWM_CTL2 0xC8350 3101 #define _BXT_BLC_PWM_FREQ2 0xC8354 3102 #define _BXT_BLC_PWM_DUTY2 0xC8358 3103 3104 #define BXT_BLC_PWM_CTL(controller) _MMIO_PIPE(controller, \ 3105 _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2) 3106 #define BXT_BLC_PWM_FREQ(controller) _MMIO_PIPE(controller, \ 3107 _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2) 3108 #define BXT_BLC_PWM_DUTY(controller) _MMIO_PIPE(controller, \ 3109 _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2) 3110 3111 #define PCH_GTC_CTL _MMIO(0xe7000) 3112 #define PCH_GTC_ENABLE (1 << 31) 3113 3114 /* TV port control */ 3115 #define TV_CTL _MMIO(0x68000) 3116 /* Enables the TV encoder */ 3117 # define TV_ENC_ENABLE (1 << 31) 3118 /* Sources the TV encoder input from pipe B instead of A. */ 3119 # define TV_ENC_PIPE_SEL_SHIFT 30 3120 # define TV_ENC_PIPE_SEL_MASK (1 << 30) 3121 # define TV_ENC_PIPE_SEL(pipe) ((pipe) << 30) 3122 /* Outputs composite video (DAC A only) */ 3123 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) 3124 /* Outputs SVideo video (DAC B/C) */ 3125 # define TV_ENC_OUTPUT_SVIDEO (1 << 28) 3126 /* Outputs Component video (DAC A/B/C) */ 3127 # define TV_ENC_OUTPUT_COMPONENT (2 << 28) 3128 /* Outputs Composite and SVideo (DAC A/B/C) */ 3129 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) 3130 # define TV_TRILEVEL_SYNC (1 << 21) 3131 /* Enables slow sync generation (945GM only) */ 3132 # define TV_SLOW_SYNC (1 << 20) 3133 /* Selects 4x oversampling for 480i and 576p */ 3134 # define TV_OVERSAMPLE_4X (0 << 18) 3135 /* Selects 2x oversampling for 720p and 1080i */ 3136 # define TV_OVERSAMPLE_2X (1 << 18) 3137 /* Selects no oversampling for 1080p */ 3138 # define TV_OVERSAMPLE_NONE (2 << 18) 3139 /* Selects 8x oversampling */ 3140 # define TV_OVERSAMPLE_8X (3 << 18) 3141 # define TV_OVERSAMPLE_MASK (3 << 18) 3142 /* Selects progressive mode rather than interlaced */ 3143 # define TV_PROGRESSIVE (1 << 17) 3144 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */ 3145 # define TV_PAL_BURST (1 << 16) 3146 /* Field for setting delay of Y compared to C */ 3147 # define TV_YC_SKEW_MASK (7 << 12) 3148 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */ 3149 # define TV_ENC_SDP_FIX (1 << 11) 3150 /* 3151 * Enables a fix for the 915GM only. 3152 * 3153 * Not sure what it does. 3154 */ 3155 # define TV_ENC_C0_FIX (1 << 10) 3156 /* Bits that must be preserved by software */ 3157 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) 3158 # define TV_FUSE_STATE_MASK (3 << 4) 3159 /* Read-only state that reports all features enabled */ 3160 # define TV_FUSE_STATE_ENABLED (0 << 4) 3161 /* Read-only state that reports that Macrovision is disabled in hardware*/ 3162 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) 3163 /* Read-only state that reports that TV-out is disabled in hardware. */ 3164 # define TV_FUSE_STATE_DISABLED (2 << 4) 3165 /* Normal operation */ 3166 # define TV_TEST_MODE_NORMAL (0 << 0) 3167 /* Encoder test pattern 1 - combo pattern */ 3168 # define TV_TEST_MODE_PATTERN_1 (1 << 0) 3169 /* Encoder test pattern 2 - full screen vertical 75% color bars */ 3170 # define TV_TEST_MODE_PATTERN_2 (2 << 0) 3171 /* Encoder test pattern 3 - full screen horizontal 75% color bars */ 3172 # define TV_TEST_MODE_PATTERN_3 (3 << 0) 3173 /* Encoder test pattern 4 - random noise */ 3174 # define TV_TEST_MODE_PATTERN_4 (4 << 0) 3175 /* Encoder test pattern 5 - linear color ramps */ 3176 # define TV_TEST_MODE_PATTERN_5 (5 << 0) 3177 /* 3178 * This test mode forces the DACs to 50% of full output. 3179 * 3180 * This is used for load detection in combination with TVDAC_SENSE_MASK 3181 */ 3182 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) 3183 # define TV_TEST_MODE_MASK (7 << 0) 3184 3185 #define TV_DAC _MMIO(0x68004) 3186 # define TV_DAC_SAVE 0x00ffff00 3187 /* 3188 * Reports that DAC state change logic has reported change (RO). 3189 * 3190 * This gets cleared when TV_DAC_STATE_EN is cleared 3191 */ 3192 # define TVDAC_STATE_CHG (1 << 31) 3193 # define TVDAC_SENSE_MASK (7 << 28) 3194 /* Reports that DAC A voltage is above the detect threshold */ 3195 # define TVDAC_A_SENSE (1 << 30) 3196 /* Reports that DAC B voltage is above the detect threshold */ 3197 # define TVDAC_B_SENSE (1 << 29) 3198 /* Reports that DAC C voltage is above the detect threshold */ 3199 # define TVDAC_C_SENSE (1 << 28) 3200 /* 3201 * Enables DAC state detection logic, for load-based TV detection. 3202 * 3203 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set 3204 * to off, for load detection to work. 3205 */ 3206 # define TVDAC_STATE_CHG_EN (1 << 27) 3207 /* Sets the DAC A sense value to high */ 3208 # define TVDAC_A_SENSE_CTL (1 << 26) 3209 /* Sets the DAC B sense value to high */ 3210 # define TVDAC_B_SENSE_CTL (1 << 25) 3211 /* Sets the DAC C sense value to high */ 3212 # define TVDAC_C_SENSE_CTL (1 << 24) 3213 /* Overrides the ENC_ENABLE and DAC voltage levels */ 3214 # define DAC_CTL_OVERRIDE (1 << 7) 3215 /* Sets the slew rate. Must be preserved in software */ 3216 # define ENC_TVDAC_SLEW_FAST (1 << 6) 3217 # define DAC_A_1_3_V (0 << 4) 3218 # define DAC_A_1_1_V (1 << 4) 3219 # define DAC_A_0_7_V (2 << 4) 3220 # define DAC_A_MASK (3 << 4) 3221 # define DAC_B_1_3_V (0 << 2) 3222 # define DAC_B_1_1_V (1 << 2) 3223 # define DAC_B_0_7_V (2 << 2) 3224 # define DAC_B_MASK (3 << 2) 3225 # define DAC_C_1_3_V (0 << 0) 3226 # define DAC_C_1_1_V (1 << 0) 3227 # define DAC_C_0_7_V (2 << 0) 3228 # define DAC_C_MASK (3 << 0) 3229 3230 /* 3231 * CSC coefficients are stored in a floating point format with 9 bits of 3232 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, 3233 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with 3234 * -1 (0x3) being the only legal negative value. 3235 */ 3236 #define TV_CSC_Y _MMIO(0x68010) 3237 # define TV_RY_MASK 0x07ff0000 3238 # define TV_RY_SHIFT 16 3239 # define TV_GY_MASK 0x00000fff 3240 # define TV_GY_SHIFT 0 3241 3242 #define TV_CSC_Y2 _MMIO(0x68014) 3243 # define TV_BY_MASK 0x07ff0000 3244 # define TV_BY_SHIFT 16 3245 /* 3246 * Y attenuation for component video. 3247 * 3248 * Stored in 1.9 fixed point. 3249 */ 3250 # define TV_AY_MASK 0x000003ff 3251 # define TV_AY_SHIFT 0 3252 3253 #define TV_CSC_U _MMIO(0x68018) 3254 # define TV_RU_MASK 0x07ff0000 3255 # define TV_RU_SHIFT 16 3256 # define TV_GU_MASK 0x000007ff 3257 # define TV_GU_SHIFT 0 3258 3259 #define TV_CSC_U2 _MMIO(0x6801c) 3260 # define TV_BU_MASK 0x07ff0000 3261 # define TV_BU_SHIFT 16 3262 /* 3263 * U attenuation for component video. 3264 * 3265 * Stored in 1.9 fixed point. 3266 */ 3267 # define TV_AU_MASK 0x000003ff 3268 # define TV_AU_SHIFT 0 3269 3270 #define TV_CSC_V _MMIO(0x68020) 3271 # define TV_RV_MASK 0x0fff0000 3272 # define TV_RV_SHIFT 16 3273 # define TV_GV_MASK 0x000007ff 3274 # define TV_GV_SHIFT 0 3275 3276 #define TV_CSC_V2 _MMIO(0x68024) 3277 # define TV_BV_MASK 0x07ff0000 3278 # define TV_BV_SHIFT 16 3279 /* 3280 * V attenuation for component video. 3281 * 3282 * Stored in 1.9 fixed point. 3283 */ 3284 # define TV_AV_MASK 0x000007ff 3285 # define TV_AV_SHIFT 0 3286 3287 #define TV_CLR_KNOBS _MMIO(0x68028) 3288 /* 2s-complement brightness adjustment */ 3289 # define TV_BRIGHTNESS_MASK 0xff000000 3290 # define TV_BRIGHTNESS_SHIFT 24 3291 /* Contrast adjustment, as a 2.6 unsigned floating point number */ 3292 # define TV_CONTRAST_MASK 0x00ff0000 3293 # define TV_CONTRAST_SHIFT 16 3294 /* Saturation adjustment, as a 2.6 unsigned floating point number */ 3295 # define TV_SATURATION_MASK 0x0000ff00 3296 # define TV_SATURATION_SHIFT 8 3297 /* Hue adjustment, as an integer phase angle in degrees */ 3298 # define TV_HUE_MASK 0x000000ff 3299 # define TV_HUE_SHIFT 0 3300 3301 #define TV_CLR_LEVEL _MMIO(0x6802c) 3302 /* Controls the DAC level for black */ 3303 # define TV_BLACK_LEVEL_MASK 0x01ff0000 3304 # define TV_BLACK_LEVEL_SHIFT 16 3305 /* Controls the DAC level for blanking */ 3306 # define TV_BLANK_LEVEL_MASK 0x000001ff 3307 # define TV_BLANK_LEVEL_SHIFT 0 3308 3309 #define TV_H_CTL_1 _MMIO(0x68030) 3310 /* Number of pixels in the hsync. */ 3311 # define TV_HSYNC_END_MASK 0x1fff0000 3312 # define TV_HSYNC_END_SHIFT 16 3313 /* Total number of pixels minus one in the line (display and blanking). */ 3314 # define TV_HTOTAL_MASK 0x00001fff 3315 # define TV_HTOTAL_SHIFT 0 3316 3317 #define TV_H_CTL_2 _MMIO(0x68034) 3318 /* Enables the colorburst (needed for non-component color) */ 3319 # define TV_BURST_ENA (1 << 31) 3320 /* Offset of the colorburst from the start of hsync, in pixels minus one. */ 3321 # define TV_HBURST_START_SHIFT 16 3322 # define TV_HBURST_START_MASK 0x1fff0000 3323 /* Length of the colorburst */ 3324 # define TV_HBURST_LEN_SHIFT 0 3325 # define TV_HBURST_LEN_MASK 0x0001fff 3326 3327 #define TV_H_CTL_3 _MMIO(0x68038) 3328 /* End of hblank, measured in pixels minus one from start of hsync */ 3329 # define TV_HBLANK_END_SHIFT 16 3330 # define TV_HBLANK_END_MASK 0x1fff0000 3331 /* Start of hblank, measured in pixels minus one from start of hsync */ 3332 # define TV_HBLANK_START_SHIFT 0 3333 # define TV_HBLANK_START_MASK 0x0001fff 3334 3335 #define TV_V_CTL_1 _MMIO(0x6803c) 3336 /* XXX */ 3337 # define TV_NBR_END_SHIFT 16 3338 # define TV_NBR_END_MASK 0x07ff0000 3339 /* XXX */ 3340 # define TV_VI_END_F1_SHIFT 8 3341 # define TV_VI_END_F1_MASK 0x00003f00 3342 /* XXX */ 3343 # define TV_VI_END_F2_SHIFT 0 3344 # define TV_VI_END_F2_MASK 0x0000003f 3345 3346 #define TV_V_CTL_2 _MMIO(0x68040) 3347 /* Length of vsync, in half lines */ 3348 # define TV_VSYNC_LEN_MASK 0x07ff0000 3349 # define TV_VSYNC_LEN_SHIFT 16 3350 /* Offset of the start of vsync in field 1, measured in one less than the 3351 * number of half lines. 3352 */ 3353 # define TV_VSYNC_START_F1_MASK 0x00007f00 3354 # define TV_VSYNC_START_F1_SHIFT 8 3355 /* 3356 * Offset of the start of vsync in field 2, measured in one less than the 3357 * number of half lines. 3358 */ 3359 # define TV_VSYNC_START_F2_MASK 0x0000007f 3360 # define TV_VSYNC_START_F2_SHIFT 0 3361 3362 #define TV_V_CTL_3 _MMIO(0x68044) 3363 /* Enables generation of the equalization signal */ 3364 # define TV_EQUAL_ENA (1 << 31) 3365 /* Length of vsync, in half lines */ 3366 # define TV_VEQ_LEN_MASK 0x007f0000 3367 # define TV_VEQ_LEN_SHIFT 16 3368 /* Offset of the start of equalization in field 1, measured in one less than 3369 * the number of half lines. 3370 */ 3371 # define TV_VEQ_START_F1_MASK 0x0007f00 3372 # define TV_VEQ_START_F1_SHIFT 8 3373 /* 3374 * Offset of the start of equalization in field 2, measured in one less than 3375 * the number of half lines. 3376 */ 3377 # define TV_VEQ_START_F2_MASK 0x000007f 3378 # define TV_VEQ_START_F2_SHIFT 0 3379 3380 #define TV_V_CTL_4 _MMIO(0x68048) 3381 /* 3382 * Offset to start of vertical colorburst, measured in one less than the 3383 * number of lines from vertical start. 3384 */ 3385 # define TV_VBURST_START_F1_MASK 0x003f0000 3386 # define TV_VBURST_START_F1_SHIFT 16 3387 /* 3388 * Offset to the end of vertical colorburst, measured in one less than the 3389 * number of lines from the start of NBR. 3390 */ 3391 # define TV_VBURST_END_F1_MASK 0x000000ff 3392 # define TV_VBURST_END_F1_SHIFT 0 3393 3394 #define TV_V_CTL_5 _MMIO(0x6804c) 3395 /* 3396 * Offset to start of vertical colorburst, measured in one less than the 3397 * number of lines from vertical start. 3398 */ 3399 # define TV_VBURST_START_F2_MASK 0x003f0000 3400 # define TV_VBURST_START_F2_SHIFT 16 3401 /* 3402 * Offset to the end of vertical colorburst, measured in one less than the 3403 * number of lines from the start of NBR. 3404 */ 3405 # define TV_VBURST_END_F2_MASK 0x000000ff 3406 # define TV_VBURST_END_F2_SHIFT 0 3407 3408 #define TV_V_CTL_6 _MMIO(0x68050) 3409 /* 3410 * Offset to start of vertical colorburst, measured in one less than the 3411 * number of lines from vertical start. 3412 */ 3413 # define TV_VBURST_START_F3_MASK 0x003f0000 3414 # define TV_VBURST_START_F3_SHIFT 16 3415 /* 3416 * Offset to the end of vertical colorburst, measured in one less than the 3417 * number of lines from the start of NBR. 3418 */ 3419 # define TV_VBURST_END_F3_MASK 0x000000ff 3420 # define TV_VBURST_END_F3_SHIFT 0 3421 3422 #define TV_V_CTL_7 _MMIO(0x68054) 3423 /* 3424 * Offset to start of vertical colorburst, measured in one less than the 3425 * number of lines from vertical start. 3426 */ 3427 # define TV_VBURST_START_F4_MASK 0x003f0000 3428 # define TV_VBURST_START_F4_SHIFT 16 3429 /* 3430 * Offset to the end of vertical colorburst, measured in one less than the 3431 * number of lines from the start of NBR. 3432 */ 3433 # define TV_VBURST_END_F4_MASK 0x000000ff 3434 # define TV_VBURST_END_F4_SHIFT 0 3435 3436 #define TV_SC_CTL_1 _MMIO(0x68060) 3437 /* Turns on the first subcarrier phase generation DDA */ 3438 # define TV_SC_DDA1_EN (1 << 31) 3439 /* Turns on the first subcarrier phase generation DDA */ 3440 # define TV_SC_DDA2_EN (1 << 30) 3441 /* Turns on the first subcarrier phase generation DDA */ 3442 # define TV_SC_DDA3_EN (1 << 29) 3443 /* Sets the subcarrier DDA to reset frequency every other field */ 3444 # define TV_SC_RESET_EVERY_2 (0 << 24) 3445 /* Sets the subcarrier DDA to reset frequency every fourth field */ 3446 # define TV_SC_RESET_EVERY_4 (1 << 24) 3447 /* Sets the subcarrier DDA to reset frequency every eighth field */ 3448 # define TV_SC_RESET_EVERY_8 (2 << 24) 3449 /* Sets the subcarrier DDA to never reset the frequency */ 3450 # define TV_SC_RESET_NEVER (3 << 24) 3451 /* Sets the peak amplitude of the colorburst.*/ 3452 # define TV_BURST_LEVEL_MASK 0x00ff0000 3453 # define TV_BURST_LEVEL_SHIFT 16 3454 /* Sets the increment of the first subcarrier phase generation DDA */ 3455 # define TV_SCDDA1_INC_MASK 0x00000fff 3456 # define TV_SCDDA1_INC_SHIFT 0 3457 3458 #define TV_SC_CTL_2 _MMIO(0x68064) 3459 /* Sets the rollover for the second subcarrier phase generation DDA */ 3460 # define TV_SCDDA2_SIZE_MASK 0x7fff0000 3461 # define TV_SCDDA2_SIZE_SHIFT 16 3462 /* Sets the increent of the second subcarrier phase generation DDA */ 3463 # define TV_SCDDA2_INC_MASK 0x00007fff 3464 # define TV_SCDDA2_INC_SHIFT 0 3465 3466 #define TV_SC_CTL_3 _MMIO(0x68068) 3467 /* Sets the rollover for the third subcarrier phase generation DDA */ 3468 # define TV_SCDDA3_SIZE_MASK 0x7fff0000 3469 # define TV_SCDDA3_SIZE_SHIFT 16 3470 /* Sets the increent of the third subcarrier phase generation DDA */ 3471 # define TV_SCDDA3_INC_MASK 0x00007fff 3472 # define TV_SCDDA3_INC_SHIFT 0 3473 3474 #define TV_WIN_POS _MMIO(0x68070) 3475 /* X coordinate of the display from the start of horizontal active */ 3476 # define TV_XPOS_MASK 0x1fff0000 3477 # define TV_XPOS_SHIFT 16 3478 /* Y coordinate of the display from the start of vertical active (NBR) */ 3479 # define TV_YPOS_MASK 0x00000fff 3480 # define TV_YPOS_SHIFT 0 3481 3482 #define TV_WIN_SIZE _MMIO(0x68074) 3483 /* Horizontal size of the display window, measured in pixels*/ 3484 # define TV_XSIZE_MASK 0x1fff0000 3485 # define TV_XSIZE_SHIFT 16 3486 /* 3487 * Vertical size of the display window, measured in pixels. 3488 * 3489 * Must be even for interlaced modes. 3490 */ 3491 # define TV_YSIZE_MASK 0x00000fff 3492 # define TV_YSIZE_SHIFT 0 3493 3494 #define TV_FILTER_CTL_1 _MMIO(0x68080) 3495 /* 3496 * Enables automatic scaling calculation. 3497 * 3498 * If set, the rest of the registers are ignored, and the calculated values can 3499 * be read back from the register. 3500 */ 3501 # define TV_AUTO_SCALE (1 << 31) 3502 /* 3503 * Disables the vertical filter. 3504 * 3505 * This is required on modes more than 1024 pixels wide */ 3506 # define TV_V_FILTER_BYPASS (1 << 29) 3507 /* Enables adaptive vertical filtering */ 3508 # define TV_VADAPT (1 << 28) 3509 # define TV_VADAPT_MODE_MASK (3 << 26) 3510 /* Selects the least adaptive vertical filtering mode */ 3511 # define TV_VADAPT_MODE_LEAST (0 << 26) 3512 /* Selects the moderately adaptive vertical filtering mode */ 3513 # define TV_VADAPT_MODE_MODERATE (1 << 26) 3514 /* Selects the most adaptive vertical filtering mode */ 3515 # define TV_VADAPT_MODE_MOST (3 << 26) 3516 /* 3517 * Sets the horizontal scaling factor. 3518 * 3519 * This should be the fractional part of the horizontal scaling factor divided 3520 * by the oversampling rate. TV_HSCALE should be less than 1, and set to: 3521 * 3522 * (src width - 1) / ((oversample * dest width) - 1) 3523 */ 3524 # define TV_HSCALE_FRAC_MASK 0x00003fff 3525 # define TV_HSCALE_FRAC_SHIFT 0 3526 3527 #define TV_FILTER_CTL_2 _MMIO(0x68084) 3528 /* 3529 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 3530 * 3531 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) 3532 */ 3533 # define TV_VSCALE_INT_MASK 0x00038000 3534 # define TV_VSCALE_INT_SHIFT 15 3535 /* 3536 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 3537 * 3538 * \sa TV_VSCALE_INT_MASK 3539 */ 3540 # define TV_VSCALE_FRAC_MASK 0x00007fff 3541 # define TV_VSCALE_FRAC_SHIFT 0 3542 3543 #define TV_FILTER_CTL_3 _MMIO(0x68088) 3544 /* 3545 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 3546 * 3547 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) 3548 * 3549 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 3550 */ 3551 # define TV_VSCALE_IP_INT_MASK 0x00038000 3552 # define TV_VSCALE_IP_INT_SHIFT 15 3553 /* 3554 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 3555 * 3556 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 3557 * 3558 * \sa TV_VSCALE_IP_INT_MASK 3559 */ 3560 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff 3561 # define TV_VSCALE_IP_FRAC_SHIFT 0 3562 3563 #define TV_CC_CONTROL _MMIO(0x68090) 3564 # define TV_CC_ENABLE (1 << 31) 3565 /* 3566 * Specifies which field to send the CC data in. 3567 * 3568 * CC data is usually sent in field 0. 3569 */ 3570 # define TV_CC_FID_MASK (1 << 27) 3571 # define TV_CC_FID_SHIFT 27 3572 /* Sets the horizontal position of the CC data. Usually 135. */ 3573 # define TV_CC_HOFF_MASK 0x03ff0000 3574 # define TV_CC_HOFF_SHIFT 16 3575 /* Sets the vertical position of the CC data. Usually 21 */ 3576 # define TV_CC_LINE_MASK 0x0000003f 3577 # define TV_CC_LINE_SHIFT 0 3578 3579 #define TV_CC_DATA _MMIO(0x68094) 3580 # define TV_CC_RDY (1 << 31) 3581 /* Second word of CC data to be transmitted. */ 3582 # define TV_CC_DATA_2_MASK 0x007f0000 3583 # define TV_CC_DATA_2_SHIFT 16 3584 /* First word of CC data to be transmitted. */ 3585 # define TV_CC_DATA_1_MASK 0x0000007f 3586 # define TV_CC_DATA_1_SHIFT 0 3587 3588 #define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */ 3589 #define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */ 3590 #define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */ 3591 #define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */ 3592 3593 /* Display Port */ 3594 #define DP_A _MMIO(0x64000) /* eDP */ 3595 #define DP_B _MMIO(0x64100) 3596 #define DP_C _MMIO(0x64200) 3597 #define DP_D _MMIO(0x64300) 3598 3599 #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100) 3600 #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200) 3601 #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300) 3602 3603 #define DP_PORT_EN (1 << 31) 3604 #define DP_PIPE_SEL_SHIFT 30 3605 #define DP_PIPE_SEL_MASK (1 << 30) 3606 #define DP_PIPE_SEL(pipe) ((pipe) << 30) 3607 #define DP_PIPE_SEL_SHIFT_IVB 29 3608 #define DP_PIPE_SEL_MASK_IVB (3 << 29) 3609 #define DP_PIPE_SEL_IVB(pipe) ((pipe) << 29) 3610 #define DP_PIPE_SEL_SHIFT_CHV 16 3611 #define DP_PIPE_SEL_MASK_CHV (3 << 16) 3612 #define DP_PIPE_SEL_CHV(pipe) ((pipe) << 16) 3613 3614 /* Link training mode - select a suitable mode for each stage */ 3615 #define DP_LINK_TRAIN_PAT_1 (0 << 28) 3616 #define DP_LINK_TRAIN_PAT_2 (1 << 28) 3617 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) 3618 #define DP_LINK_TRAIN_OFF (3 << 28) 3619 #define DP_LINK_TRAIN_MASK (3 << 28) 3620 #define DP_LINK_TRAIN_SHIFT 28 3621 3622 /* CPT Link training mode */ 3623 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) 3624 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) 3625 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) 3626 #define DP_LINK_TRAIN_OFF_CPT (3 << 8) 3627 #define DP_LINK_TRAIN_MASK_CPT (7 << 8) 3628 #define DP_LINK_TRAIN_SHIFT_CPT 8 3629 3630 /* Signal voltages. These are mostly controlled by the other end */ 3631 #define DP_VOLTAGE_0_4 (0 << 25) 3632 #define DP_VOLTAGE_0_6 (1 << 25) 3633 #define DP_VOLTAGE_0_8 (2 << 25) 3634 #define DP_VOLTAGE_1_2 (3 << 25) 3635 #define DP_VOLTAGE_MASK (7 << 25) 3636 #define DP_VOLTAGE_SHIFT 25 3637 3638 /* Signal pre-emphasis levels, like voltages, the other end tells us what 3639 * they want 3640 */ 3641 #define DP_PRE_EMPHASIS_0 (0 << 22) 3642 #define DP_PRE_EMPHASIS_3_5 (1 << 22) 3643 #define DP_PRE_EMPHASIS_6 (2 << 22) 3644 #define DP_PRE_EMPHASIS_9_5 (3 << 22) 3645 #define DP_PRE_EMPHASIS_MASK (7 << 22) 3646 #define DP_PRE_EMPHASIS_SHIFT 22 3647 3648 /* How many wires to use. I guess 3 was too hard */ 3649 #define DP_PORT_WIDTH(width) (((width) - 1) << 19) 3650 #define DP_PORT_WIDTH_MASK (7 << 19) 3651 #define DP_PORT_WIDTH_SHIFT 19 3652 3653 /* Mystic DPCD version 1.1 special mode */ 3654 #define DP_ENHANCED_FRAMING (1 << 18) 3655 3656 /* eDP */ 3657 #define DP_PLL_FREQ_270MHZ (0 << 16) 3658 #define DP_PLL_FREQ_162MHZ (1 << 16) 3659 #define DP_PLL_FREQ_MASK (3 << 16) 3660 3661 /* locked once port is enabled */ 3662 #define DP_PORT_REVERSAL (1 << 15) 3663 3664 /* eDP */ 3665 #define DP_PLL_ENABLE (1 << 14) 3666 3667 /* sends the clock on lane 15 of the PEG for debug */ 3668 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 3669 3670 #define DP_SCRAMBLING_DISABLE (1 << 12) 3671 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) 3672 3673 /* limit RGB values to avoid confusing TVs */ 3674 #define DP_COLOR_RANGE_16_235 (1 << 8) 3675 3676 /* Turn on the audio link */ 3677 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) 3678 3679 /* vs and hs sync polarity */ 3680 #define DP_SYNC_VS_HIGH (1 << 4) 3681 #define DP_SYNC_HS_HIGH (1 << 3) 3682 3683 /* A fantasy */ 3684 #define DP_DETECTED (1 << 2) 3685 3686 /* The aux channel provides a way to talk to the 3687 * signal sink for DDC etc. Max packet size supported 3688 * is 20 bytes in each direction, hence the 5 fixed 3689 * data registers 3690 */ 3691 #define _DPA_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64010) 3692 #define _DPA_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64014) 3693 3694 #define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110) 3695 #define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114) 3696 3697 #define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL) 3698 #define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ 3699 3700 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) 3701 #define DP_AUX_CH_CTL_DONE (1 << 30) 3702 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) 3703 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) 3704 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) 3705 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) 3706 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) 3707 #define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */ 3708 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) 3709 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) 3710 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) 3711 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 3712 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) 3713 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 3714 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) 3715 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) 3716 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) 3717 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) 3718 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) 3719 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) 3720 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 3721 #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14) 3722 #define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13) 3723 #define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12) 3724 #define DP_AUX_CH_CTL_TBT_IO (1 << 11) 3725 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5) 3726 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5) 3727 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1) 3728 3729 /* 3730 * Computing GMCH M and N values for the Display Port link 3731 * 3732 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes 3733 * 3734 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) 3735 * 3736 * The GMCH value is used internally 3737 * 3738 * bytes_per_pixel is the number of bytes coming out of the plane, 3739 * which is after the LUTs, so we want the bytes for our color format. 3740 * For our current usage, this is always 3, one byte for R, G and B. 3741 */ 3742 #define _PIPEA_DATA_M_G4X 0x70050 3743 #define _PIPEB_DATA_M_G4X 0x71050 3744 3745 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 3746 #define TU_SIZE_MASK REG_GENMASK(30, 25) 3747 #define TU_SIZE(x) REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */ 3748 3749 #define DATA_LINK_M_N_MASK REG_GENMASK(23, 0) 3750 #define DATA_LINK_N_MAX (0x800000) 3751 3752 #define _PIPEA_DATA_N_G4X 0x70054 3753 #define _PIPEB_DATA_N_G4X 0x71054 3754 3755 /* 3756 * Computing Link M and N values for the Display Port link 3757 * 3758 * Link M / N = pixel_clock / ls_clk 3759 * 3760 * (the DP spec calls pixel_clock the 'strm_clk') 3761 * 3762 * The Link value is transmitted in the Main Stream 3763 * Attributes and VB-ID. 3764 */ 3765 3766 #define _PIPEA_LINK_M_G4X 0x70060 3767 #define _PIPEB_LINK_M_G4X 0x71060 3768 #define _PIPEA_LINK_N_G4X 0x70064 3769 #define _PIPEB_LINK_N_G4X 0x71064 3770 3771 #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X) 3772 #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X) 3773 #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X) 3774 #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X) 3775 3776 /* Display & cursor control */ 3777 3778 /* Pipe A */ 3779 #define _PIPEADSL 0x70000 3780 #define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */ 3781 #define PIPEDSL_LINE_MASK REG_GENMASK(19, 0) 3782 #define _PIPEACONF 0x70008 3783 #define PIPECONF_ENABLE REG_BIT(31) 3784 #define PIPECONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */ 3785 #define PIPECONF_STATE_ENABLE REG_BIT(30) /* i965+ */ 3786 #define PIPECONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv & pipe A only */ 3787 #define PIPECONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */ 3788 #define PIPECONF_FRAME_START_DELAY(x) REG_FIELD_PREP(PIPECONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */ 3789 #define PIPECONF_PIPE_LOCKED REG_BIT(25) 3790 #define PIPECONF_FORCE_BORDER REG_BIT(25) 3791 #define PIPECONF_GAMMA_MODE_MASK_I9XX REG_BIT(24) /* gmch */ 3792 #define PIPECONF_GAMMA_MODE_MASK_ILK REG_GENMASK(25, 24) /* ilk-ivb */ 3793 #define PIPECONF_GAMMA_MODE_8BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK, 0) 3794 #define PIPECONF_GAMMA_MODE_10BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK, 1) 3795 #define PIPECONF_GAMMA_MODE_12BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */ 3796 #define PIPECONF_GAMMA_MODE_SPLIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */ 3797 #define PIPECONF_GAMMA_MODE(x) REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */ 3798 #define PIPECONF_INTERLACE_MASK REG_GENMASK(23, 21) /* gen3+ */ 3799 #define PIPECONF_INTERLACE_PROGRESSIVE REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 0) 3800 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 4) /* gen4 only */ 3801 #define PIPECONF_INTERLACE_W_SYNC_SHIFT REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 5) /* gen4 only */ 3802 #define PIPECONF_INTERLACE_W_FIELD_INDICATION REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 6) 3803 #define PIPECONF_INTERLACE_FIELD_0_ONLY REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 7) /* gen3 only */ 3804 /* 3805 * ilk+: PF/D=progressive fetch/display, IF/D=interlaced fetch/display, 3806 * DBL=power saving pixel doubling, PF-ID* requires panel fitter 3807 */ 3808 #define PIPECONF_INTERLACE_MASK_ILK REG_GENMASK(23, 21) /* ilk+ */ 3809 #define PIPECONF_INTERLACE_MASK_HSW REG_GENMASK(22, 21) /* hsw+ */ 3810 #define PIPECONF_INTERLACE_PF_PD_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 0) 3811 #define PIPECONF_INTERLACE_PF_ID_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 1) 3812 #define PIPECONF_INTERLACE_IF_ID_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 3) 3813 #define PIPECONF_INTERLACE_IF_ID_DBL_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */ 3814 #define PIPECONF_INTERLACE_PF_ID_DBL_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */ 3815 #define PIPECONF_EDP_RR_MODE_SWITCH REG_BIT(20) 3816 #define PIPECONF_CXSR_DOWNCLOCK REG_BIT(16) 3817 #define PIPECONF_EDP_RR_MODE_SWITCH_VLV REG_BIT(14) 3818 #define PIPECONF_COLOR_RANGE_SELECT REG_BIT(13) 3819 #define PIPECONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */ 3820 #define PIPECONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */ 3821 #define PIPECONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */ 3822 #define PIPECONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */ 3823 #define PIPECONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11) /* hsw only */ 3824 #define PIPECONF_BPC_MASK REG_GENMASK(7, 5) /* ctg-ivb */ 3825 #define PIPECONF_BPC_8 REG_FIELD_PREP(PIPECONF_BPC_MASK, 0) 3826 #define PIPECONF_BPC_10 REG_FIELD_PREP(PIPECONF_BPC_MASK, 1) 3827 #define PIPECONF_BPC_6 REG_FIELD_PREP(PIPECONF_BPC_MASK, 2) 3828 #define PIPECONF_BPC_12 REG_FIELD_PREP(PIPECONF_BPC_MASK, 3) 3829 #define PIPECONF_DITHER_EN REG_BIT(4) 3830 #define PIPECONF_DITHER_TYPE_MASK REG_GENMASK(3, 2) 3831 #define PIPECONF_DITHER_TYPE_SP REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 0) 3832 #define PIPECONF_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 1) 3833 #define PIPECONF_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 2) 3834 #define PIPECONF_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 3) 3835 #define _PIPEASTAT 0x70024 3836 #define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31) 3837 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30) 3838 #define PIPE_CRC_ERROR_ENABLE (1UL << 29) 3839 #define PIPE_CRC_DONE_ENABLE (1UL << 28) 3840 #define PERF_COUNTER2_INTERRUPT_EN (1UL << 27) 3841 #define PIPE_GMBUS_EVENT_ENABLE (1UL << 27) 3842 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26) 3843 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26) 3844 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25) 3845 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24) 3846 #define PIPE_DPST_EVENT_ENABLE (1UL << 23) 3847 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22) 3848 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22) 3849 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21) 3850 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20) 3851 #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL << 19) 3852 #define PERF_COUNTER_INTERRUPT_EN (1UL << 19) 3853 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */ 3854 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) /* 965 or later */ 3855 #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL << 17) 3856 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17) 3857 #define PIPEA_HBLANK_INT_EN_VLV (1UL << 16) 3858 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16) 3859 #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL << 15) 3860 #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL << 14) 3861 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13) 3862 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12) 3863 #define PERF_COUNTER2_INTERRUPT_STATUS (1UL << 11) 3864 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11) 3865 #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL << 10) 3866 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10) 3867 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9) 3868 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8) 3869 #define PIPE_DPST_EVENT_STATUS (1UL << 7) 3870 #define PIPE_A_PSR_STATUS_VLV (1UL << 6) 3871 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6) 3872 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5) 3873 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4) 3874 #define PIPE_B_PSR_STATUS_VLV (1UL << 3) 3875 #define PERF_COUNTER_INTERRUPT_STATUS (1UL << 3) 3876 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */ 3877 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) /* 965 or later */ 3878 #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL << 1) 3879 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1) 3880 #define PIPE_HBLANK_INT_STATUS (1UL << 0) 3881 #define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0) 3882 3883 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 3884 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff 3885 3886 #define PIPE_A_OFFSET 0x70000 3887 #define PIPE_B_OFFSET 0x71000 3888 #define PIPE_C_OFFSET 0x72000 3889 #define PIPE_D_OFFSET 0x73000 3890 #define CHV_PIPE_C_OFFSET 0x74000 3891 /* 3892 * There's actually no pipe EDP. Some pipe registers have 3893 * simply shifted from the pipe to the transcoder, while 3894 * keeping their original offset. Thus we need PIPE_EDP_OFFSET 3895 * to access such registers in transcoder EDP. 3896 */ 3897 #define PIPE_EDP_OFFSET 0x7f000 3898 3899 /* ICL DSI 0 and 1 */ 3900 #define PIPE_DSI0_OFFSET 0x7b000 3901 #define PIPE_DSI1_OFFSET 0x7b800 3902 3903 #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF) 3904 #define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL) 3905 #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH) 3906 #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL) 3907 #define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT) 3908 3909 #define _PIPEAGCMAX 0x70010 3910 #define _PIPEBGCMAX 0x71010 3911 #define PIPEGCMAX(pipe, i) _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4) 3912 3913 #define _PIPE_ARB_CTL_A 0x70028 /* icl+ */ 3914 #define PIPE_ARB_CTL(pipe) _MMIO_PIPE2(pipe, _PIPE_ARB_CTL_A) 3915 #define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13) 3916 3917 #define _PIPE_MISC_A 0x70030 3918 #define _PIPE_MISC_B 0x71030 3919 #define PIPEMISC_YUV420_ENABLE REG_BIT(27) /* glk+ */ 3920 #define PIPEMISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */ 3921 #define PIPEMISC_HDR_MODE_PRECISION REG_BIT(23) /* icl+ */ 3922 #define PIPEMISC_OUTPUT_COLORSPACE_YUV REG_BIT(11) 3923 #define PIPEMISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */ 3924 /* 3925 * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with 3926 * valid values of: 6, 8, 10 BPC. 3927 * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of: 3928 * 6, 8, 10, 12 BPC. 3929 */ 3930 #define PIPEMISC_BPC_MASK REG_GENMASK(7, 5) 3931 #define PIPEMISC_BPC_8 REG_FIELD_PREP(PIPEMISC_BPC_MASK, 0) 3932 #define PIPEMISC_BPC_10 REG_FIELD_PREP(PIPEMISC_BPC_MASK, 1) 3933 #define PIPEMISC_BPC_6 REG_FIELD_PREP(PIPEMISC_BPC_MASK, 2) 3934 #define PIPEMISC_BPC_12_ADLP REG_FIELD_PREP(PIPEMISC_BPC_MASK, 4) /* adlp+ */ 3935 #define PIPEMISC_DITHER_ENABLE REG_BIT(4) 3936 #define PIPEMISC_DITHER_TYPE_MASK REG_GENMASK(3, 2) 3937 #define PIPEMISC_DITHER_TYPE_SP REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 0) 3938 #define PIPEMISC_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 1) 3939 #define PIPEMISC_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 2) 3940 #define PIPEMISC_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 3) 3941 #define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A) 3942 3943 #define _PIPE_MISC2_A 0x7002C 3944 #define _PIPE_MISC2_B 0x7102C 3945 #define PIPE_MISC2_BUBBLE_COUNTER_MASK REG_GENMASK(31, 24) 3946 #define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80) 3947 #define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20) 3948 #define PIPE_MISC2(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC2_A) 3949 3950 /* Skylake+ pipe bottom (background) color */ 3951 #define _SKL_BOTTOM_COLOR_A 0x70034 3952 #define SKL_BOTTOM_COLOR_GAMMA_ENABLE REG_BIT(31) 3953 #define SKL_BOTTOM_COLOR_CSC_ENABLE REG_BIT(30) 3954 #define SKL_BOTTOM_COLOR(pipe) _MMIO_PIPE2(pipe, _SKL_BOTTOM_COLOR_A) 3955 3956 #define _ICL_PIPE_A_STATUS 0x70058 3957 #define ICL_PIPESTATUS(pipe) _MMIO_PIPE2(pipe, _ICL_PIPE_A_STATUS) 3958 #define PIPE_STATUS_UNDERRUN REG_BIT(31) 3959 #define PIPE_STATUS_SOFT_UNDERRUN_XELPD REG_BIT(28) 3960 #define PIPE_STATUS_HARD_UNDERRUN_XELPD REG_BIT(27) 3961 #define PIPE_STATUS_PORT_UNDERRUN_XELPD REG_BIT(26) 3962 3963 #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028) 3964 #define PIPEB_LINE_COMPARE_INT_EN REG_BIT(29) 3965 #define PIPEB_HLINE_INT_EN REG_BIT(28) 3966 #define PIPEB_VBLANK_INT_EN REG_BIT(27) 3967 #define SPRITED_FLIP_DONE_INT_EN REG_BIT(26) 3968 #define SPRITEC_FLIP_DONE_INT_EN REG_BIT(25) 3969 #define PLANEB_FLIP_DONE_INT_EN REG_BIT(24) 3970 #define PIPE_PSR_INT_EN REG_BIT(22) 3971 #define PIPEA_LINE_COMPARE_INT_EN REG_BIT(21) 3972 #define PIPEA_HLINE_INT_EN REG_BIT(20) 3973 #define PIPEA_VBLANK_INT_EN REG_BIT(19) 3974 #define SPRITEB_FLIP_DONE_INT_EN REG_BIT(18) 3975 #define SPRITEA_FLIP_DONE_INT_EN REG_BIT(17) 3976 #define PLANEA_FLIPDONE_INT_EN REG_BIT(16) 3977 #define PIPEC_LINE_COMPARE_INT_EN REG_BIT(13) 3978 #define PIPEC_HLINE_INT_EN REG_BIT(12) 3979 #define PIPEC_VBLANK_INT_EN REG_BIT(11) 3980 #define SPRITEF_FLIPDONE_INT_EN REG_BIT(10) 3981 #define SPRITEE_FLIPDONE_INT_EN REG_BIT(9) 3982 #define PLANEC_FLIPDONE_INT_EN REG_BIT(8) 3983 3984 #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ 3985 #define DPINVGTT_EN_MASK_CHV REG_GENMASK(27, 16) 3986 #define DPINVGTT_EN_MASK_VLV REG_GENMASK(23, 16) 3987 #define SPRITEF_INVALID_GTT_INT_EN REG_BIT(27) 3988 #define SPRITEE_INVALID_GTT_INT_EN REG_BIT(26) 3989 #define PLANEC_INVALID_GTT_INT_EN REG_BIT(25) 3990 #define CURSORC_INVALID_GTT_INT_EN REG_BIT(24) 3991 #define CURSORB_INVALID_GTT_INT_EN REG_BIT(23) 3992 #define CURSORA_INVALID_GTT_INT_EN REG_BIT(22) 3993 #define SPRITED_INVALID_GTT_INT_EN REG_BIT(21) 3994 #define SPRITEC_INVALID_GTT_INT_EN REG_BIT(20) 3995 #define PLANEB_INVALID_GTT_INT_EN REG_BIT(19) 3996 #define SPRITEB_INVALID_GTT_INT_EN REG_BIT(18) 3997 #define SPRITEA_INVALID_GTT_INT_EN REG_BIT(17) 3998 #define PLANEA_INVALID_GTT_INT_EN REG_BIT(16) 3999 #define DPINVGTT_STATUS_MASK_CHV REG_GENMASK(11, 0) 4000 #define DPINVGTT_STATUS_MASK_VLV REG_GENMASK(7, 0) 4001 #define SPRITEF_INVALID_GTT_STATUS REG_BIT(11) 4002 #define SPRITEE_INVALID_GTT_STATUS REG_BIT(10) 4003 #define PLANEC_INVALID_GTT_STATUS REG_BIT(9) 4004 #define CURSORC_INVALID_GTT_STATUS REG_BIT(8) 4005 #define CURSORB_INVALID_GTT_STATUS REG_BIT(7) 4006 #define CURSORA_INVALID_GTT_STATUS REG_BIT(6) 4007 #define SPRITED_INVALID_GTT_STATUS REG_BIT(5) 4008 #define SPRITEC_INVALID_GTT_STATUS REG_BIT(4) 4009 #define PLANEB_INVALID_GTT_STATUS REG_BIT(3) 4010 #define SPRITEB_INVALID_GTT_STATUS REG_BIT(2) 4011 #define SPRITEA_INVALID_GTT_STATUS REG_BIT(1) 4012 #define PLANEA_INVALID_GTT_STATUS REG_BIT(0) 4013 4014 #define DSPARB _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030) 4015 #define DSPARB_CSTART_MASK (0x7f << 7) 4016 #define DSPARB_CSTART_SHIFT 7 4017 #define DSPARB_BSTART_MASK (0x7f) 4018 #define DSPARB_BSTART_SHIFT 0 4019 #define DSPARB_BEND_SHIFT 9 /* on 855 */ 4020 #define DSPARB_AEND_SHIFT 0 4021 #define DSPARB_SPRITEA_SHIFT_VLV 0 4022 #define DSPARB_SPRITEA_MASK_VLV (0xff << 0) 4023 #define DSPARB_SPRITEB_SHIFT_VLV 8 4024 #define DSPARB_SPRITEB_MASK_VLV (0xff << 8) 4025 #define DSPARB_SPRITEC_SHIFT_VLV 16 4026 #define DSPARB_SPRITEC_MASK_VLV (0xff << 16) 4027 #define DSPARB_SPRITED_SHIFT_VLV 24 4028 #define DSPARB_SPRITED_MASK_VLV (0xff << 24) 4029 #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */ 4030 #define DSPARB_SPRITEA_HI_SHIFT_VLV 0 4031 #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0) 4032 #define DSPARB_SPRITEB_HI_SHIFT_VLV 4 4033 #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4) 4034 #define DSPARB_SPRITEC_HI_SHIFT_VLV 8 4035 #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8) 4036 #define DSPARB_SPRITED_HI_SHIFT_VLV 12 4037 #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12) 4038 #define DSPARB_SPRITEE_HI_SHIFT_VLV 16 4039 #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16) 4040 #define DSPARB_SPRITEF_HI_SHIFT_VLV 20 4041 #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20) 4042 #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */ 4043 #define DSPARB_SPRITEE_SHIFT_VLV 0 4044 #define DSPARB_SPRITEE_MASK_VLV (0xff << 0) 4045 #define DSPARB_SPRITEF_SHIFT_VLV 8 4046 #define DSPARB_SPRITEF_MASK_VLV (0xff << 8) 4047 4048 /* pnv/gen4/g4x/vlv/chv */ 4049 #define DSPFW1 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034) 4050 #define DSPFW_SR_SHIFT 23 4051 #define DSPFW_SR_MASK (0x1ff << 23) 4052 #define DSPFW_CURSORB_SHIFT 16 4053 #define DSPFW_CURSORB_MASK (0x3f << 16) 4054 #define DSPFW_PLANEB_SHIFT 8 4055 #define DSPFW_PLANEB_MASK (0x7f << 8) 4056 #define DSPFW_PLANEB_MASK_VLV (0xff << 8) /* vlv/chv */ 4057 #define DSPFW_PLANEA_SHIFT 0 4058 #define DSPFW_PLANEA_MASK (0x7f << 0) 4059 #define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */ 4060 #define DSPFW2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038) 4061 #define DSPFW_FBC_SR_EN (1 << 31) /* g4x */ 4062 #define DSPFW_FBC_SR_SHIFT 28 4063 #define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */ 4064 #define DSPFW_FBC_HPLL_SR_SHIFT 24 4065 #define DSPFW_FBC_HPLL_SR_MASK (0xf << 24) /* g4x */ 4066 #define DSPFW_SPRITEB_SHIFT (16) 4067 #define DSPFW_SPRITEB_MASK (0x7f << 16) /* g4x */ 4068 #define DSPFW_SPRITEB_MASK_VLV (0xff << 16) /* vlv/chv */ 4069 #define DSPFW_CURSORA_SHIFT 8 4070 #define DSPFW_CURSORA_MASK (0x3f << 8) 4071 #define DSPFW_PLANEC_OLD_SHIFT 0 4072 #define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */ 4073 #define DSPFW_SPRITEA_SHIFT 0 4074 #define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */ 4075 #define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */ 4076 #define DSPFW3 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c) 4077 #define DSPFW_HPLL_SR_EN (1 << 31) 4078 #define PINEVIEW_SELF_REFRESH_EN (1 << 30) 4079 #define DSPFW_CURSOR_SR_SHIFT 24 4080 #define DSPFW_CURSOR_SR_MASK (0x3f << 24) 4081 #define DSPFW_HPLL_CURSOR_SHIFT 16 4082 #define DSPFW_HPLL_CURSOR_MASK (0x3f << 16) 4083 #define DSPFW_HPLL_SR_SHIFT 0 4084 #define DSPFW_HPLL_SR_MASK (0x1ff << 0) 4085 4086 /* vlv/chv */ 4087 #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070) 4088 #define DSPFW_SPRITEB_WM1_SHIFT 16 4089 #define DSPFW_SPRITEB_WM1_MASK (0xff << 16) 4090 #define DSPFW_CURSORA_WM1_SHIFT 8 4091 #define DSPFW_CURSORA_WM1_MASK (0x3f << 8) 4092 #define DSPFW_SPRITEA_WM1_SHIFT 0 4093 #define DSPFW_SPRITEA_WM1_MASK (0xff << 0) 4094 #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074) 4095 #define DSPFW_PLANEB_WM1_SHIFT 24 4096 #define DSPFW_PLANEB_WM1_MASK (0xff << 24) 4097 #define DSPFW_PLANEA_WM1_SHIFT 16 4098 #define DSPFW_PLANEA_WM1_MASK (0xff << 16) 4099 #define DSPFW_CURSORB_WM1_SHIFT 8 4100 #define DSPFW_CURSORB_WM1_MASK (0x3f << 8) 4101 #define DSPFW_CURSOR_SR_WM1_SHIFT 0 4102 #define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0) 4103 #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078) 4104 #define DSPFW_SR_WM1_SHIFT 0 4105 #define DSPFW_SR_WM1_MASK (0x1ff << 0) 4106 #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c) 4107 #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */ 4108 #define DSPFW_SPRITED_WM1_SHIFT 24 4109 #define DSPFW_SPRITED_WM1_MASK (0xff << 24) 4110 #define DSPFW_SPRITED_SHIFT 16 4111 #define DSPFW_SPRITED_MASK_VLV (0xff << 16) 4112 #define DSPFW_SPRITEC_WM1_SHIFT 8 4113 #define DSPFW_SPRITEC_WM1_MASK (0xff << 8) 4114 #define DSPFW_SPRITEC_SHIFT 0 4115 #define DSPFW_SPRITEC_MASK_VLV (0xff << 0) 4116 #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8) 4117 #define DSPFW_SPRITEF_WM1_SHIFT 24 4118 #define DSPFW_SPRITEF_WM1_MASK (0xff << 24) 4119 #define DSPFW_SPRITEF_SHIFT 16 4120 #define DSPFW_SPRITEF_MASK_VLV (0xff << 16) 4121 #define DSPFW_SPRITEE_WM1_SHIFT 8 4122 #define DSPFW_SPRITEE_WM1_MASK (0xff << 8) 4123 #define DSPFW_SPRITEE_SHIFT 0 4124 #define DSPFW_SPRITEE_MASK_VLV (0xff << 0) 4125 #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */ 4126 #define DSPFW_PLANEC_WM1_SHIFT 24 4127 #define DSPFW_PLANEC_WM1_MASK (0xff << 24) 4128 #define DSPFW_PLANEC_SHIFT 16 4129 #define DSPFW_PLANEC_MASK_VLV (0xff << 16) 4130 #define DSPFW_CURSORC_WM1_SHIFT 8 4131 #define DSPFW_CURSORC_WM1_MASK (0x3f << 16) 4132 #define DSPFW_CURSORC_SHIFT 0 4133 #define DSPFW_CURSORC_MASK (0x3f << 0) 4134 4135 /* vlv/chv high order bits */ 4136 #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064) 4137 #define DSPFW_SR_HI_SHIFT 24 4138 #define DSPFW_SR_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */ 4139 #define DSPFW_SPRITEF_HI_SHIFT 23 4140 #define DSPFW_SPRITEF_HI_MASK (1 << 23) 4141 #define DSPFW_SPRITEE_HI_SHIFT 22 4142 #define DSPFW_SPRITEE_HI_MASK (1 << 22) 4143 #define DSPFW_PLANEC_HI_SHIFT 21 4144 #define DSPFW_PLANEC_HI_MASK (1 << 21) 4145 #define DSPFW_SPRITED_HI_SHIFT 20 4146 #define DSPFW_SPRITED_HI_MASK (1 << 20) 4147 #define DSPFW_SPRITEC_HI_SHIFT 16 4148 #define DSPFW_SPRITEC_HI_MASK (1 << 16) 4149 #define DSPFW_PLANEB_HI_SHIFT 12 4150 #define DSPFW_PLANEB_HI_MASK (1 << 12) 4151 #define DSPFW_SPRITEB_HI_SHIFT 8 4152 #define DSPFW_SPRITEB_HI_MASK (1 << 8) 4153 #define DSPFW_SPRITEA_HI_SHIFT 4 4154 #define DSPFW_SPRITEA_HI_MASK (1 << 4) 4155 #define DSPFW_PLANEA_HI_SHIFT 0 4156 #define DSPFW_PLANEA_HI_MASK (1 << 0) 4157 #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068) 4158 #define DSPFW_SR_WM1_HI_SHIFT 24 4159 #define DSPFW_SR_WM1_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */ 4160 #define DSPFW_SPRITEF_WM1_HI_SHIFT 23 4161 #define DSPFW_SPRITEF_WM1_HI_MASK (1 << 23) 4162 #define DSPFW_SPRITEE_WM1_HI_SHIFT 22 4163 #define DSPFW_SPRITEE_WM1_HI_MASK (1 << 22) 4164 #define DSPFW_PLANEC_WM1_HI_SHIFT 21 4165 #define DSPFW_PLANEC_WM1_HI_MASK (1 << 21) 4166 #define DSPFW_SPRITED_WM1_HI_SHIFT 20 4167 #define DSPFW_SPRITED_WM1_HI_MASK (1 << 20) 4168 #define DSPFW_SPRITEC_WM1_HI_SHIFT 16 4169 #define DSPFW_SPRITEC_WM1_HI_MASK (1 << 16) 4170 #define DSPFW_PLANEB_WM1_HI_SHIFT 12 4171 #define DSPFW_PLANEB_WM1_HI_MASK (1 << 12) 4172 #define DSPFW_SPRITEB_WM1_HI_SHIFT 8 4173 #define DSPFW_SPRITEB_WM1_HI_MASK (1 << 8) 4174 #define DSPFW_SPRITEA_WM1_HI_SHIFT 4 4175 #define DSPFW_SPRITEA_WM1_HI_MASK (1 << 4) 4176 #define DSPFW_PLANEA_WM1_HI_SHIFT 0 4177 #define DSPFW_PLANEA_WM1_HI_MASK (1 << 0) 4178 4179 /* drain latency register values*/ 4180 #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe)) 4181 #define DDL_CURSOR_SHIFT 24 4182 #define DDL_SPRITE_SHIFT(sprite) (8 + 8 * (sprite)) 4183 #define DDL_PLANE_SHIFT 0 4184 #define DDL_PRECISION_HIGH (1 << 7) 4185 #define DDL_PRECISION_LOW (0 << 7) 4186 #define DRAIN_LATENCY_MASK 0x7f 4187 4188 #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400) 4189 #define CBR_PND_DEADLINE_DISABLE (1 << 31) 4190 #define CBR_PWM_CLOCK_MUX_SELECT (1 << 30) 4191 4192 #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450) 4193 #define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */ 4194 4195 /* FIFO watermark sizes etc */ 4196 #define G4X_FIFO_LINE_SIZE 64 4197 #define I915_FIFO_LINE_SIZE 64 4198 #define I830_FIFO_LINE_SIZE 32 4199 4200 #define VALLEYVIEW_FIFO_SIZE 255 4201 #define G4X_FIFO_SIZE 127 4202 #define I965_FIFO_SIZE 512 4203 #define I945_FIFO_SIZE 127 4204 #define I915_FIFO_SIZE 95 4205 #define I855GM_FIFO_SIZE 127 /* In cachelines */ 4206 #define I830_FIFO_SIZE 95 4207 4208 #define VALLEYVIEW_MAX_WM 0xff 4209 #define G4X_MAX_WM 0x3f 4210 #define I915_MAX_WM 0x3f 4211 4212 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ 4213 #define PINEVIEW_FIFO_LINE_SIZE 64 4214 #define PINEVIEW_MAX_WM 0x1ff 4215 #define PINEVIEW_DFT_WM 0x3f 4216 #define PINEVIEW_DFT_HPLLOFF_WM 0 4217 #define PINEVIEW_GUARD_WM 10 4218 #define PINEVIEW_CURSOR_FIFO 64 4219 #define PINEVIEW_CURSOR_MAX_WM 0x3f 4220 #define PINEVIEW_CURSOR_DFT_WM 0 4221 #define PINEVIEW_CURSOR_GUARD_WM 5 4222 4223 #define VALLEYVIEW_CURSOR_MAX_WM 64 4224 #define I965_CURSOR_FIFO 64 4225 #define I965_CURSOR_MAX_WM 32 4226 #define I965_CURSOR_DFT_WM 8 4227 4228 /* Watermark register definitions for SKL */ 4229 #define _CUR_WM_A_0 0x70140 4230 #define _CUR_WM_B_0 0x71140 4231 #define _CUR_WM_SAGV_A 0x70158 4232 #define _CUR_WM_SAGV_B 0x71158 4233 #define _CUR_WM_SAGV_TRANS_A 0x7015C 4234 #define _CUR_WM_SAGV_TRANS_B 0x7115C 4235 #define _CUR_WM_TRANS_A 0x70168 4236 #define _CUR_WM_TRANS_B 0x71168 4237 #define _PLANE_WM_1_A_0 0x70240 4238 #define _PLANE_WM_1_B_0 0x71240 4239 #define _PLANE_WM_2_A_0 0x70340 4240 #define _PLANE_WM_2_B_0 0x71340 4241 #define _PLANE_WM_SAGV_1_A 0x70258 4242 #define _PLANE_WM_SAGV_1_B 0x71258 4243 #define _PLANE_WM_SAGV_2_A 0x70358 4244 #define _PLANE_WM_SAGV_2_B 0x71358 4245 #define _PLANE_WM_SAGV_TRANS_1_A 0x7025C 4246 #define _PLANE_WM_SAGV_TRANS_1_B 0x7125C 4247 #define _PLANE_WM_SAGV_TRANS_2_A 0x7035C 4248 #define _PLANE_WM_SAGV_TRANS_2_B 0x7135C 4249 #define _PLANE_WM_TRANS_1_A 0x70268 4250 #define _PLANE_WM_TRANS_1_B 0x71268 4251 #define _PLANE_WM_TRANS_2_A 0x70368 4252 #define _PLANE_WM_TRANS_2_B 0x71368 4253 #define PLANE_WM_EN (1 << 31) 4254 #define PLANE_WM_IGNORE_LINES (1 << 30) 4255 #define PLANE_WM_LINES_MASK REG_GENMASK(26, 14) 4256 #define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0) 4257 4258 #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0) 4259 #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level))) 4260 #define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B) 4261 #define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B) 4262 #define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B) 4263 #define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0) 4264 #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0) 4265 #define _PLANE_WM_BASE(pipe, plane) \ 4266 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe)) 4267 #define PLANE_WM(pipe, plane, level) \ 4268 _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level))) 4269 #define _PLANE_WM_SAGV_1(pipe) \ 4270 _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B) 4271 #define _PLANE_WM_SAGV_2(pipe) \ 4272 _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B) 4273 #define PLANE_WM_SAGV(pipe, plane) \ 4274 _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe))) 4275 #define _PLANE_WM_SAGV_TRANS_1(pipe) \ 4276 _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B) 4277 #define _PLANE_WM_SAGV_TRANS_2(pipe) \ 4278 _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B) 4279 #define PLANE_WM_SAGV_TRANS(pipe, plane) \ 4280 _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe))) 4281 #define _PLANE_WM_TRANS_1(pipe) \ 4282 _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B) 4283 #define _PLANE_WM_TRANS_2(pipe) \ 4284 _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B) 4285 #define PLANE_WM_TRANS(pipe, plane) \ 4286 _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))) 4287 4288 /* define the Watermark register on Ironlake */ 4289 #define _WM0_PIPEA_ILK 0x45100 4290 #define _WM0_PIPEB_ILK 0x45104 4291 #define _WM0_PIPEC_IVB 0x45200 4292 #define WM0_PIPE_ILK(pipe) _MMIO_PIPE3((pipe), _WM0_PIPEA_ILK, \ 4293 _WM0_PIPEB_ILK, _WM0_PIPEC_IVB) 4294 #define WM0_PIPE_PLANE_MASK (0xffff << 16) 4295 #define WM0_PIPE_PLANE_SHIFT 16 4296 #define WM0_PIPE_SPRITE_MASK (0xff << 8) 4297 #define WM0_PIPE_SPRITE_SHIFT 8 4298 #define WM0_PIPE_CURSOR_MASK (0xff) 4299 #define WM1_LP_ILK _MMIO(0x45108) 4300 #define WM1_LP_SR_EN (1 << 31) 4301 #define WM1_LP_LATENCY_SHIFT 24 4302 #define WM1_LP_LATENCY_MASK (0x7f << 24) 4303 #define WM1_LP_FBC_MASK (0xf << 20) 4304 #define WM1_LP_FBC_SHIFT 20 4305 #define WM1_LP_FBC_SHIFT_BDW 19 4306 #define WM1_LP_SR_MASK (0x7ff << 8) 4307 #define WM1_LP_SR_SHIFT 8 4308 #define WM1_LP_CURSOR_MASK (0xff) 4309 #define WM2_LP_ILK _MMIO(0x4510c) 4310 #define WM2_LP_EN (1 << 31) 4311 #define WM3_LP_ILK _MMIO(0x45110) 4312 #define WM3_LP_EN (1 << 31) 4313 #define WM1S_LP_ILK _MMIO(0x45120) 4314 #define WM2S_LP_IVB _MMIO(0x45124) 4315 #define WM3S_LP_IVB _MMIO(0x45128) 4316 #define WM1S_LP_EN (1 << 31) 4317 4318 #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \ 4319 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \ 4320 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur)) 4321 4322 /* Memory latency timer register */ 4323 #define MLTR_ILK _MMIO(0x11222) 4324 #define MLTR_WM1_SHIFT 0 4325 #define MLTR_WM2_SHIFT 8 4326 /* the unit of memory self-refresh latency time is 0.5us */ 4327 #define ILK_SRLT_MASK 0x3f 4328 4329 4330 /* the address where we get all kinds of latency value */ 4331 #define SSKPD _MMIO(0x5d10) 4332 #define SSKPD_WM_MASK 0x3f 4333 #define SSKPD_WM0_SHIFT 0 4334 #define SSKPD_WM1_SHIFT 8 4335 #define SSKPD_WM2_SHIFT 16 4336 #define SSKPD_WM3_SHIFT 24 4337 4338 /* 4339 * The two pipe frame counter registers are not synchronized, so 4340 * reading a stable value is somewhat tricky. The following code 4341 * should work: 4342 * 4343 * do { 4344 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 4345 * PIPE_FRAME_HIGH_SHIFT; 4346 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 4347 * PIPE_FRAME_LOW_SHIFT); 4348 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 4349 * PIPE_FRAME_HIGH_SHIFT); 4350 * } while (high1 != high2); 4351 * frame = (high1 << 8) | low1; 4352 */ 4353 #define _PIPEAFRAMEHIGH 0x70040 4354 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 4355 #define PIPE_FRAME_HIGH_SHIFT 0 4356 #define _PIPEAFRAMEPIXEL 0x70044 4357 #define PIPE_FRAME_LOW_MASK 0xff000000 4358 #define PIPE_FRAME_LOW_SHIFT 24 4359 #define PIPE_PIXEL_MASK 0x00ffffff 4360 #define PIPE_PIXEL_SHIFT 0 4361 /* GM45+ just has to be different */ 4362 #define _PIPEA_FRMCOUNT_G4X 0x70040 4363 #define _PIPEA_FLIPCOUNT_G4X 0x70044 4364 #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X) 4365 #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X) 4366 4367 /* Cursor A & B regs */ 4368 #define _CURACNTR 0x70080 4369 /* Old style CUR*CNTR flags (desktop 8xx) */ 4370 #define CURSOR_ENABLE REG_BIT(31) 4371 #define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30) 4372 #define CURSOR_STRIDE_MASK REG_GENMASK(29, 28) 4373 #define CURSOR_STRIDE(stride) REG_FIELD_PREP(CURSOR_STRIDE_MASK, ffs(stride) - 9) /* 256,512,1k,2k */ 4374 #define CURSOR_FORMAT_MASK REG_GENMASK(26, 24) 4375 #define CURSOR_FORMAT_2C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 0) 4376 #define CURSOR_FORMAT_3C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 1) 4377 #define CURSOR_FORMAT_4C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 2) 4378 #define CURSOR_FORMAT_ARGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 4) 4379 #define CURSOR_FORMAT_XRGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 5) 4380 /* New style CUR*CNTR flags */ 4381 #define MCURSOR_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ 4382 #define MCURSOR_ARB_SLOTS(x) REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */ 4383 #define MCURSOR_PIPE_SEL_MASK REG_GENMASK(29, 28) 4384 #define MCURSOR_PIPE_SEL(pipe) REG_FIELD_PREP(MCURSOR_PIPE_SEL_MASK, (pipe)) 4385 #define MCURSOR_PIPE_GAMMA_ENABLE REG_BIT(26) 4386 #define MCURSOR_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ 4387 #define MCURSOR_ROTATE_180 REG_BIT(15) 4388 #define MCURSOR_TRICKLE_FEED_DISABLE REG_BIT(14) 4389 #define MCURSOR_MODE_MASK 0x27 4390 #define MCURSOR_MODE_DISABLE 0x00 4391 #define MCURSOR_MODE_128_32B_AX 0x02 4392 #define MCURSOR_MODE_256_32B_AX 0x03 4393 #define MCURSOR_MODE_64_32B_AX 0x07 4394 #define MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX) 4395 #define MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX) 4396 #define MCURSOR_MODE_64_ARGB_AX (0x20 | MCURSOR_MODE_64_32B_AX) 4397 #define _CURABASE 0x70084 4398 #define _CURAPOS 0x70088 4399 #define CURSOR_POS_Y_SIGN REG_BIT(31) 4400 #define CURSOR_POS_Y_MASK REG_GENMASK(30, 16) 4401 #define CURSOR_POS_Y(y) REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y)) 4402 #define CURSOR_POS_X_SIGN REG_BIT(15) 4403 #define CURSOR_POS_X_MASK REG_GENMASK(14, 0) 4404 #define CURSOR_POS_X(x) REG_FIELD_PREP(CURSOR_POS_X_MASK, (x)) 4405 #define _CURASIZE 0x700a0 /* 845/865 */ 4406 #define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12) 4407 #define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h)) 4408 #define CURSOR_WIDTH_MASK REG_GENMASK(9, 0) 4409 #define CURSOR_WIDTH(w) REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w)) 4410 #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */ 4411 #define CUR_FBC_EN REG_BIT(31) 4412 #define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0) 4413 #define CUR_FBC_HEIGHT(h) REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h)) 4414 #define _CURASURFLIVE 0x700ac /* g4x+ */ 4415 #define _CURBCNTR 0x700c0 4416 #define _CURBBASE 0x700c4 4417 #define _CURBPOS 0x700c8 4418 4419 #define _CURBCNTR_IVB 0x71080 4420 #define _CURBBASE_IVB 0x71084 4421 #define _CURBPOS_IVB 0x71088 4422 4423 #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR) 4424 #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE) 4425 #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS) 4426 #define CURSIZE(pipe) _CURSOR2(pipe, _CURASIZE) 4427 #define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A) 4428 #define CURSURFLIVE(pipe) _CURSOR2(pipe, _CURASURFLIVE) 4429 4430 #define CURSOR_A_OFFSET 0x70080 4431 #define CURSOR_B_OFFSET 0x700c0 4432 #define CHV_CURSOR_C_OFFSET 0x700e0 4433 #define IVB_CURSOR_B_OFFSET 0x71080 4434 #define IVB_CURSOR_C_OFFSET 0x72080 4435 #define TGL_CURSOR_D_OFFSET 0x73080 4436 4437 /* Display A control */ 4438 #define _DSPAADDR_VLV 0x7017C /* vlv/chv */ 4439 #define _DSPACNTR 0x70180 4440 #define DISP_ENABLE REG_BIT(31) 4441 #define DISP_PIPE_GAMMA_ENABLE REG_BIT(30) 4442 #define DISP_FORMAT_MASK REG_GENMASK(29, 26) 4443 #define DISP_FORMAT_8BPP REG_FIELD_PREP(DISP_FORMAT_MASK, 2) 4444 #define DISP_FORMAT_BGRA555 REG_FIELD_PREP(DISP_FORMAT_MASK, 3) 4445 #define DISP_FORMAT_BGRX555 REG_FIELD_PREP(DISP_FORMAT_MASK, 4) 4446 #define DISP_FORMAT_BGRX565 REG_FIELD_PREP(DISP_FORMAT_MASK, 5) 4447 #define DISP_FORMAT_BGRX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 6) 4448 #define DISP_FORMAT_BGRA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 7) 4449 #define DISP_FORMAT_RGBX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 8) 4450 #define DISP_FORMAT_RGBA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 9) 4451 #define DISP_FORMAT_BGRX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 10) 4452 #define DISP_FORMAT_BGRA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 11) 4453 #define DISP_FORMAT_RGBX161616 REG_FIELD_PREP(DISP_FORMAT_MASK, 12) 4454 #define DISP_FORMAT_RGBX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 14) 4455 #define DISP_FORMAT_RGBA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 15) 4456 #define DISP_STEREO_ENABLE REG_BIT(25) 4457 #define DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ 4458 #define DISP_PIPE_SEL_MASK REG_GENMASK(25, 24) 4459 #define DISP_PIPE_SEL(pipe) REG_FIELD_PREP(DISP_PIPE_SEL_MASK, (pipe)) 4460 #define DISP_SRC_KEY_ENABLE REG_BIT(22) 4461 #define DISP_LINE_DOUBLE REG_BIT(20) 4462 #define DISP_STEREO_POLARITY_SECOND REG_BIT(18) 4463 #define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */ 4464 #define DISP_ROTATE_180 REG_BIT(15) 4465 #define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */ 4466 #define DISP_TILED REG_BIT(10) 4467 #define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */ 4468 #define DISP_MIRROR REG_BIT(8) /* CHV pipe B */ 4469 #define _DSPAADDR 0x70184 4470 #define _DSPASTRIDE 0x70188 4471 #define _DSPAPOS 0x7018C /* reserved */ 4472 #define DISP_POS_Y_MASK REG_GENMASK(31, 0) 4473 #define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y)) 4474 #define DISP_POS_X_MASK REG_GENMASK(15, 0) 4475 #define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x)) 4476 #define _DSPASIZE 0x70190 4477 #define DISP_HEIGHT_MASK REG_GENMASK(31, 0) 4478 #define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h)) 4479 #define DISP_WIDTH_MASK REG_GENMASK(15, 0) 4480 #define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w)) 4481 #define _DSPASURF 0x7019C /* 965+ only */ 4482 #define DISP_ADDR_MASK REG_GENMASK(31, 12) 4483 #define _DSPATILEOFF 0x701A4 /* 965+ only */ 4484 #define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16) 4485 #define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y)) 4486 #define DISP_OFFSET_X_MASK REG_GENMASK(15, 0) 4487 #define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x)) 4488 #define _DSPAOFFSET 0x701A4 /* HSW */ 4489 #define _DSPASURFLIVE 0x701AC 4490 #define _DSPAGAMC 0x701E0 4491 4492 #define DSPADDR_VLV(plane) _MMIO_PIPE2(plane, _DSPAADDR_VLV) 4493 #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR) 4494 #define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR) 4495 #define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE) 4496 #define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS) 4497 #define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE) 4498 #define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF) 4499 #define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF) 4500 #define DSPLINOFF(plane) DSPADDR(plane) 4501 #define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET) 4502 #define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE) 4503 #define DSPGAMC(plane, i) _MMIO(_PIPE2(plane, _DSPAGAMC) + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ 4504 4505 /* CHV pipe B blender and primary plane */ 4506 #define _CHV_BLEND_A 0x60a00 4507 #define CHV_BLEND_MASK REG_GENMASK(31, 30) 4508 #define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0) 4509 #define CHV_BLEND_ANDROID REG_FIELD_PREP(CHV_BLEND_MASK, 1) 4510 #define CHV_BLEND_MPO REG_FIELD_PREP(CHV_BLEND_MASK, 2) 4511 #define _CHV_CANVAS_A 0x60a04 4512 #define CHV_CANVAS_RED_MASK REG_GENMASK(29, 20) 4513 #define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10) 4514 #define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0) 4515 #define _PRIMPOS_A 0x60a08 4516 #define PRIM_POS_Y_MASK REG_GENMASK(31, 16) 4517 #define PRIM_POS_Y(y) REG_FIELD_PREP(PRIM_POS_Y_MASK, (y)) 4518 #define PRIM_POS_X_MASK REG_GENMASK(15, 0) 4519 #define PRIM_POS_X(x) REG_FIELD_PREP(PRIM_POS_X_MASK, (x)) 4520 #define _PRIMSIZE_A 0x60a0c 4521 #define PRIM_HEIGHT_MASK REG_GENMASK(31, 16) 4522 #define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h)) 4523 #define PRIM_WIDTH_MASK REG_GENMASK(15, 0) 4524 #define PRIM_WIDTH(w) REG_FIELD_PREP(PRIM_WIDTH_MASK, (w)) 4525 #define _PRIMCNSTALPHA_A 0x60a10 4526 #define PRIM_CONST_ALPHA_ENABLE REG_BIT(31) 4527 #define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0) 4528 #define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha)) 4529 4530 #define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A) 4531 #define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A) 4532 #define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A) 4533 #define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A) 4534 #define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A) 4535 4536 /* Display/Sprite base address macros */ 4537 #define DISP_BASEADDR_MASK (0xfffff000) 4538 #define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK) 4539 #define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK) 4540 4541 /* 4542 * VBIOS flags 4543 * gen2: 4544 * [00:06] alm,mgm 4545 * [10:16] all 4546 * [30:32] alm,mgm 4547 * gen3+: 4548 * [00:0f] all 4549 * [10:1f] all 4550 * [30:32] all 4551 */ 4552 #define SWF0(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4) 4553 #define SWF1(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4) 4554 #define SWF3(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4) 4555 #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) 4556 4557 /* Pipe B */ 4558 #define _PIPEBDSL (DISPLAY_MMIO_BASE(dev_priv) + 0x71000) 4559 #define _PIPEBCONF (DISPLAY_MMIO_BASE(dev_priv) + 0x71008) 4560 #define _PIPEBSTAT (DISPLAY_MMIO_BASE(dev_priv) + 0x71024) 4561 #define _PIPEBFRAMEHIGH 0x71040 4562 #define _PIPEBFRAMEPIXEL 0x71044 4563 #define _PIPEB_FRMCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71040) 4564 #define _PIPEB_FLIPCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71044) 4565 4566 4567 /* Display B control */ 4568 #define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180) 4569 #define DISP_ALPHA_TRANS_ENABLE REG_BIT(15) 4570 #define DISP_SPRITE_ABOVE_OVERLAY REG_BIT(0) 4571 #define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184) 4572 #define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188) 4573 #define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C) 4574 #define _DSPBSIZE (DISPLAY_MMIO_BASE(dev_priv) + 0x71190) 4575 #define _DSPBSURF (DISPLAY_MMIO_BASE(dev_priv) + 0x7119C) 4576 #define _DSPBTILEOFF (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) 4577 #define _DSPBOFFSET (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) 4578 #define _DSPBSURFLIVE (DISPLAY_MMIO_BASE(dev_priv) + 0x711AC) 4579 4580 /* ICL DSI 0 and 1 */ 4581 #define _PIPEDSI0CONF 0x7b008 4582 #define _PIPEDSI1CONF 0x7b808 4583 4584 /* Sprite A control */ 4585 #define _DVSACNTR 0x72180 4586 #define DVS_ENABLE REG_BIT(31) 4587 #define DVS_PIPE_GAMMA_ENABLE REG_BIT(30) 4588 #define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27) 4589 #define DVS_FORMAT_MASK REG_GENMASK(26, 25) 4590 #define DVS_FORMAT_YUV422 REG_FIELD_PREP(DVS_FORMAT_MASK, 0) 4591 #define DVS_FORMAT_RGBX101010 REG_FIELD_PREP(DVS_FORMAT_MASK, 1) 4592 #define DVS_FORMAT_RGBX888 REG_FIELD_PREP(DVS_FORMAT_MASK, 2) 4593 #define DVS_FORMAT_RGBX161616 REG_FIELD_PREP(DVS_FORMAT_MASK, 3) 4594 #define DVS_PIPE_CSC_ENABLE REG_BIT(24) 4595 #define DVS_SOURCE_KEY REG_BIT(22) 4596 #define DVS_RGB_ORDER_XBGR REG_BIT(20) 4597 #define DVS_YUV_FORMAT_BT709 REG_BIT(18) 4598 #define DVS_YUV_ORDER_MASK REG_GENMASK(17, 16) 4599 #define DVS_YUV_ORDER_YUYV REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 0) 4600 #define DVS_YUV_ORDER_UYVY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 1) 4601 #define DVS_YUV_ORDER_YVYU REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 2) 4602 #define DVS_YUV_ORDER_VYUY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 3) 4603 #define DVS_ROTATE_180 REG_BIT(15) 4604 #define DVS_TRICKLE_FEED_DISABLE REG_BIT(14) 4605 #define DVS_TILED REG_BIT(10) 4606 #define DVS_DEST_KEY REG_BIT(2) 4607 #define _DVSALINOFF 0x72184 4608 #define _DVSASTRIDE 0x72188 4609 #define _DVSAPOS 0x7218c 4610 #define DVS_POS_Y_MASK REG_GENMASK(31, 16) 4611 #define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, (y)) 4612 #define DVS_POS_X_MASK REG_GENMASK(15, 0) 4613 #define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, (x)) 4614 #define _DVSASIZE 0x72190 4615 #define DVS_HEIGHT_MASK REG_GENMASK(31, 16) 4616 #define DVS_HEIGHT(h) REG_FIELD_PREP(DVS_HEIGHT_MASK, (h)) 4617 #define DVS_WIDTH_MASK REG_GENMASK(15, 0) 4618 #define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, (w)) 4619 #define _DVSAKEYVAL 0x72194 4620 #define _DVSAKEYMSK 0x72198 4621 #define _DVSASURF 0x7219c 4622 #define DVS_ADDR_MASK REG_GENMASK(31, 12) 4623 #define _DVSAKEYMAXVAL 0x721a0 4624 #define _DVSATILEOFF 0x721a4 4625 #define DVS_OFFSET_Y_MASK REG_GENMASK(31, 16) 4626 #define DVS_OFFSET_Y(y) REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y)) 4627 #define DVS_OFFSET_X_MASK REG_GENMASK(15, 0) 4628 #define DVS_OFFSET_X(x) REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x)) 4629 #define _DVSASURFLIVE 0x721ac 4630 #define _DVSAGAMC_G4X 0x721e0 /* g4x */ 4631 #define _DVSASCALE 0x72204 4632 #define DVS_SCALE_ENABLE REG_BIT(31) 4633 #define DVS_FILTER_MASK REG_GENMASK(30, 29) 4634 #define DVS_FILTER_MEDIUM REG_FIELD_PREP(DVS_FILTER_MASK, 0) 4635 #define DVS_FILTER_ENHANCING REG_FIELD_PREP(DVS_FILTER_MASK, 1) 4636 #define DVS_FILTER_SOFTENING REG_FIELD_PREP(DVS_FILTER_MASK, 2) 4637 #define DVS_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */ 4638 #define DVS_VERTICAL_OFFSET_ENABLE REG_BIT(27) 4639 #define DVS_SRC_WIDTH_MASK REG_GENMASK(26, 16) 4640 #define DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w)) 4641 #define DVS_SRC_HEIGHT_MASK REG_GENMASK(10, 0) 4642 #define DVS_SRC_HEIGHT(h) REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h)) 4643 #define _DVSAGAMC_ILK 0x72300 /* ilk/snb */ 4644 #define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */ 4645 4646 #define _DVSBCNTR 0x73180 4647 #define _DVSBLINOFF 0x73184 4648 #define _DVSBSTRIDE 0x73188 4649 #define _DVSBPOS 0x7318c 4650 #define _DVSBSIZE 0x73190 4651 #define _DVSBKEYVAL 0x73194 4652 #define _DVSBKEYMSK 0x73198 4653 #define _DVSBSURF 0x7319c 4654 #define _DVSBKEYMAXVAL 0x731a0 4655 #define _DVSBTILEOFF 0x731a4 4656 #define _DVSBSURFLIVE 0x731ac 4657 #define _DVSBGAMC_G4X 0x731e0 /* g4x */ 4658 #define _DVSBSCALE 0x73204 4659 #define _DVSBGAMC_ILK 0x73300 /* ilk/snb */ 4660 #define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */ 4661 4662 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR) 4663 #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) 4664 #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) 4665 #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS) 4666 #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF) 4667 #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) 4668 #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE) 4669 #define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE) 4670 #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) 4671 #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) 4672 #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) 4673 #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) 4674 #define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */ 4675 #define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */ 4676 #define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */ 4677 4678 #define _SPRA_CTL 0x70280 4679 #define SPRITE_ENABLE REG_BIT(31) 4680 #define SPRITE_PIPE_GAMMA_ENABLE REG_BIT(30) 4681 #define SPRITE_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) 4682 #define SPRITE_FORMAT_MASK REG_GENMASK(27, 25) 4683 #define SPRITE_FORMAT_YUV422 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 0) 4684 #define SPRITE_FORMAT_RGBX101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 1) 4685 #define SPRITE_FORMAT_RGBX888 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 2) 4686 #define SPRITE_FORMAT_RGBX161616 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 3) 4687 #define SPRITE_FORMAT_YUV444 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 4) 4688 #define SPRITE_FORMAT_XR_BGR101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 5) /* Extended range */ 4689 #define SPRITE_PIPE_CSC_ENABLE REG_BIT(24) 4690 #define SPRITE_SOURCE_KEY REG_BIT(22) 4691 #define SPRITE_RGB_ORDER_RGBX REG_BIT(20) /* only for 888 and 161616 */ 4692 #define SPRITE_YUV_TO_RGB_CSC_DISABLE REG_BIT(19) 4693 #define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) /* 0 is BT601 */ 4694 #define SPRITE_YUV_ORDER_MASK REG_GENMASK(17, 16) 4695 #define SPRITE_YUV_ORDER_YUYV REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 0) 4696 #define SPRITE_YUV_ORDER_UYVY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 1) 4697 #define SPRITE_YUV_ORDER_YVYU REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 2) 4698 #define SPRITE_YUV_ORDER_VYUY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 3) 4699 #define SPRITE_ROTATE_180 REG_BIT(15) 4700 #define SPRITE_TRICKLE_FEED_DISABLE REG_BIT(14) 4701 #define SPRITE_PLANE_GAMMA_DISABLE REG_BIT(13) 4702 #define SPRITE_TILED REG_BIT(10) 4703 #define SPRITE_DEST_KEY REG_BIT(2) 4704 #define _SPRA_LINOFF 0x70284 4705 #define _SPRA_STRIDE 0x70288 4706 #define _SPRA_POS 0x7028c 4707 #define SPRITE_POS_Y_MASK REG_GENMASK(31, 16) 4708 #define SPRITE_POS_Y(y) REG_FIELD_PREP(SPRITE_POS_Y_MASK, (y)) 4709 #define SPRITE_POS_X_MASK REG_GENMASK(15, 0) 4710 #define SPRITE_POS_X(x) REG_FIELD_PREP(SPRITE_POS_X_MASK, (x)) 4711 #define _SPRA_SIZE 0x70290 4712 #define SPRITE_HEIGHT_MASK REG_GENMASK(31, 16) 4713 #define SPRITE_HEIGHT(h) REG_FIELD_PREP(SPRITE_HEIGHT_MASK, (h)) 4714 #define SPRITE_WIDTH_MASK REG_GENMASK(15, 0) 4715 #define SPRITE_WIDTH(w) REG_FIELD_PREP(SPRITE_WIDTH_MASK, (w)) 4716 #define _SPRA_KEYVAL 0x70294 4717 #define _SPRA_KEYMSK 0x70298 4718 #define _SPRA_SURF 0x7029c 4719 #define SPRITE_ADDR_MASK REG_GENMASK(31, 12) 4720 #define _SPRA_KEYMAX 0x702a0 4721 #define _SPRA_TILEOFF 0x702a4 4722 #define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16) 4723 #define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y)) 4724 #define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0) 4725 #define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x)) 4726 #define _SPRA_OFFSET 0x702a4 4727 #define _SPRA_SURFLIVE 0x702ac 4728 #define _SPRA_SCALE 0x70304 4729 #define SPRITE_SCALE_ENABLE REG_BIT(31) 4730 #define SPRITE_FILTER_MASK REG_GENMASK(30, 29) 4731 #define SPRITE_FILTER_MEDIUM REG_FIELD_PREP(SPRITE_FILTER_MASK, 0) 4732 #define SPRITE_FILTER_ENHANCING REG_FIELD_PREP(SPRITE_FILTER_MASK, 1) 4733 #define SPRITE_FILTER_SOFTENING REG_FIELD_PREP(SPRITE_FILTER_MASK, 2) 4734 #define SPRITE_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */ 4735 #define SPRITE_VERTICAL_OFFSET_ENABLE REG_BIT(27) 4736 #define SPRITE_SRC_WIDTH_MASK REG_GENMASK(26, 16) 4737 #define SPRITE_SRC_WIDTH(w) REG_FIELD_PREP(SPRITE_SRC_WIDTH_MASK, (w)) 4738 #define SPRITE_SRC_HEIGHT_MASK REG_GENMASK(10, 0) 4739 #define SPRITE_SRC_HEIGHT(h) REG_FIELD_PREP(SPRITE_SRC_HEIGHT_MASK, (h)) 4740 #define _SPRA_GAMC 0x70400 4741 #define _SPRA_GAMC16 0x70440 4742 #define _SPRA_GAMC17 0x7044c 4743 4744 #define _SPRB_CTL 0x71280 4745 #define _SPRB_LINOFF 0x71284 4746 #define _SPRB_STRIDE 0x71288 4747 #define _SPRB_POS 0x7128c 4748 #define _SPRB_SIZE 0x71290 4749 #define _SPRB_KEYVAL 0x71294 4750 #define _SPRB_KEYMSK 0x71298 4751 #define _SPRB_SURF 0x7129c 4752 #define _SPRB_KEYMAX 0x712a0 4753 #define _SPRB_TILEOFF 0x712a4 4754 #define _SPRB_OFFSET 0x712a4 4755 #define _SPRB_SURFLIVE 0x712ac 4756 #define _SPRB_SCALE 0x71304 4757 #define _SPRB_GAMC 0x71400 4758 #define _SPRB_GAMC16 0x71440 4759 #define _SPRB_GAMC17 0x7144c 4760 4761 #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL) 4762 #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) 4763 #define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) 4764 #define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS) 4765 #define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) 4766 #define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) 4767 #define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) 4768 #define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF) 4769 #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) 4770 #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) 4771 #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) 4772 #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) 4773 #define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */ 4774 #define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */ 4775 #define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */ 4776 #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) 4777 4778 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) 4779 #define SP_ENABLE REG_BIT(31) 4780 #define SP_PIPE_GAMMA_ENABLE REG_BIT(30) 4781 #define SP_FORMAT_MASK REG_GENMASK(29, 26) 4782 #define SP_FORMAT_YUV422 REG_FIELD_PREP(SP_FORMAT_MASK, 0) 4783 #define SP_FORMAT_8BPP REG_FIELD_PREP(SP_FORMAT_MASK, 2) 4784 #define SP_FORMAT_BGR565 REG_FIELD_PREP(SP_FORMAT_MASK, 5) 4785 #define SP_FORMAT_BGRX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 6) 4786 #define SP_FORMAT_BGRA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 7) 4787 #define SP_FORMAT_RGBX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 8) 4788 #define SP_FORMAT_RGBA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 9) 4789 #define SP_FORMAT_BGRX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 10) /* CHV pipe B */ 4790 #define SP_FORMAT_BGRA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 11) /* CHV pipe B */ 4791 #define SP_FORMAT_RGBX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 14) 4792 #define SP_FORMAT_RGBA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 15) 4793 #define SP_ALPHA_PREMULTIPLY REG_BIT(23) /* CHV pipe B */ 4794 #define SP_SOURCE_KEY REG_BIT(22) 4795 #define SP_YUV_FORMAT_BT709 REG_BIT(18) 4796 #define SP_YUV_ORDER_MASK REG_GENMASK(17, 16) 4797 #define SP_YUV_ORDER_YUYV REG_FIELD_PREP(SP_YUV_ORDER_MASK, 0) 4798 #define SP_YUV_ORDER_UYVY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 1) 4799 #define SP_YUV_ORDER_YVYU REG_FIELD_PREP(SP_YUV_ORDER_MASK, 2) 4800 #define SP_YUV_ORDER_VYUY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 3) 4801 #define SP_ROTATE_180 REG_BIT(15) 4802 #define SP_TILED REG_BIT(10) 4803 #define SP_MIRROR REG_BIT(8) /* CHV pipe B */ 4804 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) 4805 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) 4806 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c) 4807 #define SP_POS_Y_MASK REG_GENMASK(31, 16) 4808 #define SP_POS_Y(y) REG_FIELD_PREP(SP_POS_Y_MASK, (y)) 4809 #define SP_POS_X_MASK REG_GENMASK(15, 0) 4810 #define SP_POS_X(x) REG_FIELD_PREP(SP_POS_X_MASK, (x)) 4811 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190) 4812 #define SP_HEIGHT_MASK REG_GENMASK(31, 16) 4813 #define SP_HEIGHT(h) REG_FIELD_PREP(SP_HEIGHT_MASK, (h)) 4814 #define SP_WIDTH_MASK REG_GENMASK(15, 0) 4815 #define SP_WIDTH(w) REG_FIELD_PREP(SP_WIDTH_MASK, (w)) 4816 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194) 4817 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198) 4818 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c) 4819 #define SP_ADDR_MASK REG_GENMASK(31, 12) 4820 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0) 4821 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4) 4822 #define SP_OFFSET_Y_MASK REG_GENMASK(31, 16) 4823 #define SP_OFFSET_Y(y) REG_FIELD_PREP(SP_OFFSET_Y_MASK, (y)) 4824 #define SP_OFFSET_X_MASK REG_GENMASK(15, 0) 4825 #define SP_OFFSET_X(x) REG_FIELD_PREP(SP_OFFSET_X_MASK, (x)) 4826 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) 4827 #define SP_CONST_ALPHA_ENABLE REG_BIT(31) 4828 #define SP_CONST_ALPHA_MASK REG_GENMASK(7, 0) 4829 #define SP_CONST_ALPHA(alpha) REG_FIELD_PREP(SP_CONST_ALPHA_MASK, (alpha)) 4830 #define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0) 4831 #define SP_CONTRAST_MASK REG_GENMASK(26, 18) 4832 #define SP_CONTRAST(x) REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /* u3.6 */ 4833 #define SP_BRIGHTNESS_MASK REG_GENMASK(7, 0) 4834 #define SP_BRIGHTNESS(x) REG_FIELD_PREP(SP_BRIGHTNESS_MASK, (x)) /* s8 */ 4835 #define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4) 4836 #define SP_SH_SIN_MASK REG_GENMASK(26, 16) 4837 #define SP_SH_SIN(x) REG_FIELD_PREP(SP_SH_SIN_MASK, (x)) /* s4.7 */ 4838 #define SP_SH_COS_MASK REG_GENMASK(9, 0) 4839 #define SP_SH_COS(x) REG_FIELD_PREP(SP_SH_COS_MASK, (x)) /* u3.7 */ 4840 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0) 4841 4842 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) 4843 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) 4844 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) 4845 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c) 4846 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) 4847 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294) 4848 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) 4849 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) 4850 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) 4851 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) 4852 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) 4853 #define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0) 4854 #define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4) 4855 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0) 4856 4857 #define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \ 4858 _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b)) 4859 #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \ 4860 _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b))) 4861 4862 #define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR) 4863 #define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF) 4864 #define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE) 4865 #define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS) 4866 #define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE) 4867 #define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL) 4868 #define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK) 4869 #define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF) 4870 #define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL) 4871 #define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF) 4872 #define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA) 4873 #define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0) 4874 #define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1) 4875 #define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */ 4876 4877 /* 4878 * CHV pipe B sprite CSC 4879 * 4880 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff| 4881 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff| 4882 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff| 4883 */ 4884 #define _MMIO_CHV_SPCSC(plane_id, reg) \ 4885 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg)) 4886 4887 #define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900) 4888 #define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904) 4889 #define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908) 4890 #define SPCSC_OOFF_MASK REG_GENMASK(26, 16) 4891 #define SPCSC_OOFF(x) REG_FIELD_PREP(SPCSC_OOFF_MASK, (x) & 0x7ff) /* s11 */ 4892 #define SPCSC_IOFF_MASK REG_GENMASK(10, 0) 4893 #define SPCSC_IOFF(x) REG_FIELD_PREP(SPCSC_IOFF_MASK, (x) & 0x7ff) /* s11 */ 4894 4895 #define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c) 4896 #define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910) 4897 #define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914) 4898 #define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918) 4899 #define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c) 4900 #define SPCSC_C1_MASK REG_GENMASK(30, 16) 4901 #define SPCSC_C1(x) REG_FIELD_PREP(SPCSC_C1_MASK, (x) & 0x7fff) /* s3.12 */ 4902 #define SPCSC_C0_MASK REG_GENMASK(14, 0) 4903 #define SPCSC_C0(x) REG_FIELD_PREP(SPCSC_C0_MASK, (x) & 0x7fff) /* s3.12 */ 4904 4905 #define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920) 4906 #define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924) 4907 #define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928) 4908 #define SPCSC_IMAX_MASK REG_GENMASK(26, 16) 4909 #define SPCSC_IMAX(x) REG_FIELD_PREP(SPCSC_IMAX_MASK, (x) & 0x7ff) /* s11 */ 4910 #define SPCSC_IMIN_MASK REG_GENMASK(10, 0) 4911 #define SPCSC_IMIN(x) REG_FIELD_PREP(SPCSC_IMIN_MASK, (x) & 0x7ff) /* s11 */ 4912 4913 #define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c) 4914 #define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930) 4915 #define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934) 4916 #define SPCSC_OMAX_MASK REG_GENMASK(25, 16) 4917 #define SPCSC_OMAX(x) REG_FIELD_PREP(SPCSC_OMAX_MASK, (x)) /* u10 */ 4918 #define SPCSC_OMIN_MASK REG_GENMASK(9, 0) 4919 #define SPCSC_OMIN(x) REG_FIELD_PREP(SPCSC_OMIN_MASK, (x)) /* u10 */ 4920 4921 /* Skylake plane registers */ 4922 4923 #define _PLANE_CTL_1_A 0x70180 4924 #define _PLANE_CTL_2_A 0x70280 4925 #define _PLANE_CTL_3_A 0x70380 4926 #define PLANE_CTL_ENABLE REG_BIT(31) 4927 #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ 4928 #define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */ 4929 #define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */ 4930 #define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) 4931 /* 4932 * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition 4933 * expanded to include bit 23 as well. However, the shift-24 based values 4934 * correctly map to the same formats in ICL, as long as bit 23 is set to 0 4935 */ 4936 #define PLANE_CTL_FORMAT_MASK_SKL REG_GENMASK(27, 24) /* pre-icl */ 4937 #define PLANE_CTL_FORMAT_MASK_ICL REG_GENMASK(27, 23) /* icl+ */ 4938 #define PLANE_CTL_FORMAT_YUV422 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0) 4939 #define PLANE_CTL_FORMAT_NV12 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 1) 4940 #define PLANE_CTL_FORMAT_XRGB_2101010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 2) 4941 #define PLANE_CTL_FORMAT_P010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 3) 4942 #define PLANE_CTL_FORMAT_XRGB_8888 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 4) 4943 #define PLANE_CTL_FORMAT_P012 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 5) 4944 #define PLANE_CTL_FORMAT_XRGB_16161616F REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 6) 4945 #define PLANE_CTL_FORMAT_P016 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 7) 4946 #define PLANE_CTL_FORMAT_XYUV REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 8) 4947 #define PLANE_CTL_FORMAT_INDEXED REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 12) 4948 #define PLANE_CTL_FORMAT_RGB_565 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 14) 4949 #define PLANE_CTL_FORMAT_Y210 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 1) 4950 #define PLANE_CTL_FORMAT_Y212 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 3) 4951 #define PLANE_CTL_FORMAT_Y216 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 5) 4952 #define PLANE_CTL_FORMAT_Y410 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 7) 4953 #define PLANE_CTL_FORMAT_Y412 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 9) 4954 #define PLANE_CTL_FORMAT_Y416 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 11) 4955 #define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */ 4956 #define PLANE_CTL_KEY_ENABLE_MASK REG_GENMASK(22, 21) 4957 #define PLANE_CTL_KEY_ENABLE_SOURCE REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 1) 4958 #define PLANE_CTL_KEY_ENABLE_DESTINATION REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 2) 4959 #define PLANE_CTL_ORDER_RGBX REG_BIT(20) 4960 #define PLANE_CTL_YUV420_Y_PLANE REG_BIT(19) 4961 #define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) 4962 #define PLANE_CTL_YUV422_ORDER_MASK REG_GENMASK(17, 16) 4963 #define PLANE_CTL_YUV422_ORDER_YUYV REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0) 4964 #define PLANE_CTL_YUV422_ORDER_UYVY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 1) 4965 #define PLANE_CTL_YUV422_ORDER_YVYU REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 2) 4966 #define PLANE_CTL_YUV422_ORDER_VYUY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 3) 4967 #define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE REG_BIT(15) 4968 #define PLANE_CTL_TRICKLE_FEED_DISABLE REG_BIT(14) 4969 #define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */ 4970 #define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */ 4971 #define PLANE_CTL_TILED_MASK REG_GENMASK(12, 10) 4972 #define PLANE_CTL_TILED_LINEAR REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 0) 4973 #define PLANE_CTL_TILED_X REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 1) 4974 #define PLANE_CTL_TILED_Y REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 4) 4975 #define PLANE_CTL_TILED_YF REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5) 4976 #define PLANE_CTL_ASYNC_FLIP REG_BIT(9) 4977 #define PLANE_CTL_FLIP_HORIZONTAL REG_BIT(8) 4978 #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */ 4979 #define PLANE_CTL_ALPHA_MASK REG_GENMASK(5, 4) /* Pre-GLK */ 4980 #define PLANE_CTL_ALPHA_DISABLE REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 0) 4981 #define PLANE_CTL_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 2) 4982 #define PLANE_CTL_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 3) 4983 #define PLANE_CTL_ROTATE_MASK REG_GENMASK(1, 0) 4984 #define PLANE_CTL_ROTATE_0 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 0) 4985 #define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1) 4986 #define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2) 4987 #define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3) 4988 #define _PLANE_STRIDE_1_A 0x70188 4989 #define _PLANE_STRIDE_2_A 0x70288 4990 #define _PLANE_STRIDE_3_A 0x70388 4991 #define PLANE_STRIDE__MASK REG_GENMASK(11, 0) 4992 #define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride)) 4993 #define _PLANE_POS_1_A 0x7018c 4994 #define _PLANE_POS_2_A 0x7028c 4995 #define _PLANE_POS_3_A 0x7038c 4996 #define PLANE_POS_Y_MASK REG_GENMASK(31, 16) 4997 #define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y)) 4998 #define PLANE_POS_X_MASK REG_GENMASK(15, 0) 4999 #define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x)) 5000 #define _PLANE_SIZE_1_A 0x70190 5001 #define _PLANE_SIZE_2_A 0x70290 5002 #define _PLANE_SIZE_3_A 0x70390 5003 #define PLANE_HEIGHT_MASK REG_GENMASK(31, 16) 5004 #define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h)) 5005 #define PLANE_WIDTH_MASK REG_GENMASK(15, 0) 5006 #define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w)) 5007 #define _PLANE_SURF_1_A 0x7019c 5008 #define _PLANE_SURF_2_A 0x7029c 5009 #define _PLANE_SURF_3_A 0x7039c 5010 #define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12) 5011 #define PLANE_SURF_DECRYPT REG_BIT(2) 5012 #define _PLANE_OFFSET_1_A 0x701a4 5013 #define _PLANE_OFFSET_2_A 0x702a4 5014 #define _PLANE_OFFSET_3_A 0x703a4 5015 #define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16) 5016 #define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y)) 5017 #define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0) 5018 #define PLANE_OFFSET_X(x) REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x)) 5019 #define _PLANE_KEYVAL_1_A 0x70194 5020 #define _PLANE_KEYVAL_2_A 0x70294 5021 #define _PLANE_KEYMSK_1_A 0x70198 5022 #define _PLANE_KEYMSK_2_A 0x70298 5023 #define PLANE_KEYMSK_ALPHA_ENABLE (1 << 31) 5024 #define _PLANE_KEYMAX_1_A 0x701a0 5025 #define _PLANE_KEYMAX_2_A 0x702a0 5026 #define PLANE_KEYMAX_ALPHA(a) ((a) << 24) 5027 #define _PLANE_CC_VAL_1_A 0x701b4 5028 #define _PLANE_CC_VAL_2_A 0x702b4 5029 #define _PLANE_AUX_DIST_1_A 0x701c0 5030 #define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12) 5031 #define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0) 5032 #define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride)) 5033 #define _PLANE_AUX_DIST_2_A 0x702c0 5034 #define _PLANE_AUX_OFFSET_1_A 0x701c4 5035 #define _PLANE_AUX_OFFSET_2_A 0x702c4 5036 #define _PLANE_CUS_CTL_1_A 0x701c8 5037 #define _PLANE_CUS_CTL_2_A 0x702c8 5038 #define PLANE_CUS_ENABLE REG_BIT(31) 5039 #define PLANE_CUS_Y_PLANE_MASK REG_BIT(30) 5040 #define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) 5041 #define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) 5042 #define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) 5043 #define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) 5044 #define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19) 5045 #define PLANE_CUS_HPHASE_MASK REG_GENMASK(17, 16) 5046 #define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0) 5047 #define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1) 5048 #define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2) 5049 #define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15) 5050 #define PLANE_CUS_VPHASE_MASK REG_GENMASK(13, 12) 5051 #define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0) 5052 #define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1) 5053 #define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2) 5054 #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */ 5055 #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */ 5056 #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */ 5057 #define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */ 5058 #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) 5059 #define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */ 5060 #define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */ 5061 #define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */ 5062 #define PLANE_COLOR_CSC_MODE_MASK REG_GENMASK(19, 17) 5063 #define PLANE_COLOR_CSC_MODE_BYPASS REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0) 5064 #define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 1) 5065 #define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 2) 5066 #define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 3) 5067 #define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 4) 5068 #define PLANE_COLOR_PLANE_GAMMA_DISABLE REG_BIT(13) 5069 #define PLANE_COLOR_ALPHA_MASK REG_GENMASK(5, 4) 5070 #define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0) 5071 #define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2) 5072 #define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3) 5073 #define _PLANE_BUF_CFG_1_A 0x7027c 5074 #define _PLANE_BUF_CFG_2_A 0x7037c 5075 #define _PLANE_NV12_BUF_CFG_1_A 0x70278 5076 #define _PLANE_NV12_BUF_CFG_2_A 0x70378 5077 5078 #define _PLANE_CC_VAL_1_B 0x711b4 5079 #define _PLANE_CC_VAL_2_B 0x712b4 5080 #define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4) 5081 #define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4) 5082 #define PLANE_CC_VAL(pipe, plane, dw) \ 5083 _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw))) 5084 5085 /* Input CSC Register Definitions */ 5086 #define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0 5087 #define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0 5088 5089 #define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0 5090 #define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0 5091 5092 #define _PLANE_INPUT_CSC_RY_GY_1(pipe) \ 5093 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \ 5094 _PLANE_INPUT_CSC_RY_GY_1_B) 5095 #define _PLANE_INPUT_CSC_RY_GY_2(pipe) \ 5096 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \ 5097 _PLANE_INPUT_CSC_RY_GY_2_B) 5098 5099 #define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \ 5100 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \ 5101 _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4) 5102 5103 #define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8 5104 #define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8 5105 5106 #define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8 5107 #define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8 5108 5109 #define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \ 5110 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \ 5111 _PLANE_INPUT_CSC_PREOFF_HI_1_B) 5112 #define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \ 5113 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \ 5114 _PLANE_INPUT_CSC_PREOFF_HI_2_B) 5115 #define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \ 5116 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \ 5117 _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4) 5118 5119 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204 5120 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304 5121 5122 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204 5123 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304 5124 5125 #define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \ 5126 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \ 5127 _PLANE_INPUT_CSC_POSTOFF_HI_1_B) 5128 #define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \ 5129 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \ 5130 _PLANE_INPUT_CSC_POSTOFF_HI_2_B) 5131 #define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \ 5132 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \ 5133 _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4) 5134 5135 #define _PLANE_CTL_1_B 0x71180 5136 #define _PLANE_CTL_2_B 0x71280 5137 #define _PLANE_CTL_3_B 0x71380 5138 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) 5139 #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) 5140 #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B) 5141 #define PLANE_CTL(pipe, plane) \ 5142 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) 5143 5144 #define _PLANE_STRIDE_1_B 0x71188 5145 #define _PLANE_STRIDE_2_B 0x71288 5146 #define _PLANE_STRIDE_3_B 0x71388 5147 #define _PLANE_STRIDE_1(pipe) \ 5148 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) 5149 #define _PLANE_STRIDE_2(pipe) \ 5150 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) 5151 #define _PLANE_STRIDE_3(pipe) \ 5152 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B) 5153 #define PLANE_STRIDE(pipe, plane) \ 5154 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) 5155 5156 #define _PLANE_POS_1_B 0x7118c 5157 #define _PLANE_POS_2_B 0x7128c 5158 #define _PLANE_POS_3_B 0x7138c 5159 #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) 5160 #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) 5161 #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B) 5162 #define PLANE_POS(pipe, plane) \ 5163 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) 5164 5165 #define _PLANE_SIZE_1_B 0x71190 5166 #define _PLANE_SIZE_2_B 0x71290 5167 #define _PLANE_SIZE_3_B 0x71390 5168 #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) 5169 #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) 5170 #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B) 5171 #define PLANE_SIZE(pipe, plane) \ 5172 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) 5173 5174 #define _PLANE_SURF_1_B 0x7119c 5175 #define _PLANE_SURF_2_B 0x7129c 5176 #define _PLANE_SURF_3_B 0x7139c 5177 #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B) 5178 #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B) 5179 #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) 5180 #define PLANE_SURF(pipe, plane) \ 5181 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) 5182 5183 #define _PLANE_OFFSET_1_B 0x711a4 5184 #define _PLANE_OFFSET_2_B 0x712a4 5185 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B) 5186 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B) 5187 #define PLANE_OFFSET(pipe, plane) \ 5188 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe)) 5189 5190 #define _PLANE_KEYVAL_1_B 0x71194 5191 #define _PLANE_KEYVAL_2_B 0x71294 5192 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B) 5193 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) 5194 #define PLANE_KEYVAL(pipe, plane) \ 5195 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe)) 5196 5197 #define _PLANE_KEYMSK_1_B 0x71198 5198 #define _PLANE_KEYMSK_2_B 0x71298 5199 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B) 5200 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B) 5201 #define PLANE_KEYMSK(pipe, plane) \ 5202 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe)) 5203 5204 #define _PLANE_KEYMAX_1_B 0x711a0 5205 #define _PLANE_KEYMAX_2_B 0x712a0 5206 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B) 5207 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B) 5208 #define PLANE_KEYMAX(pipe, plane) \ 5209 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe)) 5210 5211 #define _PLANE_BUF_CFG_1_B 0x7127c 5212 #define _PLANE_BUF_CFG_2_B 0x7137c 5213 /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */ 5214 #define PLANE_BUF_END_MASK REG_GENMASK(27, 16) 5215 #define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end)) 5216 #define PLANE_BUF_START_MASK REG_GENMASK(11, 0) 5217 #define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start)) 5218 #define _PLANE_BUF_CFG_1(pipe) \ 5219 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B) 5220 #define _PLANE_BUF_CFG_2(pipe) \ 5221 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B) 5222 #define PLANE_BUF_CFG(pipe, plane) \ 5223 _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe)) 5224 5225 #define _PLANE_NV12_BUF_CFG_1_B 0x71278 5226 #define _PLANE_NV12_BUF_CFG_2_B 0x71378 5227 #define _PLANE_NV12_BUF_CFG_1(pipe) \ 5228 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B) 5229 #define _PLANE_NV12_BUF_CFG_2(pipe) \ 5230 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B) 5231 #define PLANE_NV12_BUF_CFG(pipe, plane) \ 5232 _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe)) 5233 5234 #define _PLANE_AUX_DIST_1_B 0x711c0 5235 #define _PLANE_AUX_DIST_2_B 0x712c0 5236 #define _PLANE_AUX_DIST_1(pipe) \ 5237 _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B) 5238 #define _PLANE_AUX_DIST_2(pipe) \ 5239 _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B) 5240 #define PLANE_AUX_DIST(pipe, plane) \ 5241 _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe)) 5242 5243 #define _PLANE_AUX_OFFSET_1_B 0x711c4 5244 #define _PLANE_AUX_OFFSET_2_B 0x712c4 5245 #define _PLANE_AUX_OFFSET_1(pipe) \ 5246 _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B) 5247 #define _PLANE_AUX_OFFSET_2(pipe) \ 5248 _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B) 5249 #define PLANE_AUX_OFFSET(pipe, plane) \ 5250 _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe)) 5251 5252 #define _PLANE_CUS_CTL_1_B 0x711c8 5253 #define _PLANE_CUS_CTL_2_B 0x712c8 5254 #define _PLANE_CUS_CTL_1(pipe) \ 5255 _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B) 5256 #define _PLANE_CUS_CTL_2(pipe) \ 5257 _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B) 5258 #define PLANE_CUS_CTL(pipe, plane) \ 5259 _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe)) 5260 5261 #define _PLANE_COLOR_CTL_1_B 0x711CC 5262 #define _PLANE_COLOR_CTL_2_B 0x712CC 5263 #define _PLANE_COLOR_CTL_3_B 0x713CC 5264 #define _PLANE_COLOR_CTL_1(pipe) \ 5265 _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B) 5266 #define _PLANE_COLOR_CTL_2(pipe) \ 5267 _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B) 5268 #define PLANE_COLOR_CTL(pipe, plane) \ 5269 _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe)) 5270 5271 #define _SEL_FETCH_PLANE_BASE_1_A 0x70890 5272 #define _SEL_FETCH_PLANE_BASE_2_A 0x708B0 5273 #define _SEL_FETCH_PLANE_BASE_3_A 0x708D0 5274 #define _SEL_FETCH_PLANE_BASE_4_A 0x708F0 5275 #define _SEL_FETCH_PLANE_BASE_5_A 0x70920 5276 #define _SEL_FETCH_PLANE_BASE_6_A 0x70940 5277 #define _SEL_FETCH_PLANE_BASE_7_A 0x70960 5278 #define _SEL_FETCH_PLANE_BASE_CUR_A 0x70880 5279 #define _SEL_FETCH_PLANE_BASE_1_B 0x70990 5280 5281 #define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \ 5282 _SEL_FETCH_PLANE_BASE_1_A, \ 5283 _SEL_FETCH_PLANE_BASE_2_A, \ 5284 _SEL_FETCH_PLANE_BASE_3_A, \ 5285 _SEL_FETCH_PLANE_BASE_4_A, \ 5286 _SEL_FETCH_PLANE_BASE_5_A, \ 5287 _SEL_FETCH_PLANE_BASE_6_A, \ 5288 _SEL_FETCH_PLANE_BASE_7_A, \ 5289 _SEL_FETCH_PLANE_BASE_CUR_A) 5290 #define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, _SEL_FETCH_PLANE_BASE_1_B) 5291 #define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \ 5292 _SEL_FETCH_PLANE_BASE_1_A + \ 5293 _SEL_FETCH_PLANE_BASE_A(plane)) 5294 5295 #define _SEL_FETCH_PLANE_CTL_1_A 0x70890 5296 #define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 5297 _SEL_FETCH_PLANE_CTL_1_A - \ 5298 _SEL_FETCH_PLANE_BASE_1_A) 5299 #define PLANE_SEL_FETCH_CTL_ENABLE REG_BIT(31) 5300 5301 #define _SEL_FETCH_PLANE_POS_1_A 0x70894 5302 #define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 5303 _SEL_FETCH_PLANE_POS_1_A - \ 5304 _SEL_FETCH_PLANE_BASE_1_A) 5305 5306 #define _SEL_FETCH_PLANE_SIZE_1_A 0x70898 5307 #define PLANE_SEL_FETCH_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 5308 _SEL_FETCH_PLANE_SIZE_1_A - \ 5309 _SEL_FETCH_PLANE_BASE_1_A) 5310 5311 #define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089C 5312 #define PLANE_SEL_FETCH_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 5313 _SEL_FETCH_PLANE_OFFSET_1_A - \ 5314 _SEL_FETCH_PLANE_BASE_1_A) 5315 5316 /* SKL new cursor registers */ 5317 #define _CUR_BUF_CFG_A 0x7017c 5318 #define _CUR_BUF_CFG_B 0x7117c 5319 #define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) 5320 5321 /* VBIOS regs */ 5322 #define VGACNTRL _MMIO(0x71400) 5323 # define VGA_DISP_DISABLE (1 << 31) 5324 # define VGA_2X_MODE (1 << 30) 5325 # define VGA_PIPE_B_SELECT (1 << 29) 5326 5327 #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400) 5328 5329 /* Ironlake */ 5330 5331 #define CPU_VGACNTRL _MMIO(0x41000) 5332 5333 #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030) 5334 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 5335 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */ 5336 #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */ 5337 #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */ 5338 #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */ 5339 #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */ 5340 #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0) 5341 #define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0) 5342 #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0) 5343 #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0) 5344 5345 /* refresh rate hardware control */ 5346 #define RR_HW_CTL _MMIO(0x45300) 5347 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff 5348 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 5349 5350 #define FDI_PLL_BIOS_0 _MMIO(0x46000) 5351 #define FDI_PLL_FB_CLOCK_MASK 0xff 5352 #define FDI_PLL_BIOS_1 _MMIO(0x46004) 5353 #define FDI_PLL_BIOS_2 _MMIO(0x46008) 5354 #define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c) 5355 #define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010) 5356 #define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014) 5357 5358 #define PCH_3DCGDIS0 _MMIO(0x46020) 5359 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) 5360 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) 5361 5362 #define PCH_3DCGDIS1 _MMIO(0x46024) 5363 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) 5364 5365 #define FDI_PLL_FREQ_CTL _MMIO(0x46030) 5366 #define FDI_PLL_FREQ_CHANGE_REQUEST (1 << 24) 5367 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 5368 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff 5369 5370 5371 #define _PIPEA_DATA_M1 0x60030 5372 #define _PIPEA_DATA_N1 0x60034 5373 #define _PIPEA_DATA_M2 0x60038 5374 #define _PIPEA_DATA_N2 0x6003c 5375 #define _PIPEA_LINK_M1 0x60040 5376 #define _PIPEA_LINK_N1 0x60044 5377 #define _PIPEA_LINK_M2 0x60048 5378 #define _PIPEA_LINK_N2 0x6004c 5379 5380 /* PIPEB timing regs are same start from 0x61000 */ 5381 5382 #define _PIPEB_DATA_M1 0x61030 5383 #define _PIPEB_DATA_N1 0x61034 5384 #define _PIPEB_DATA_M2 0x61038 5385 #define _PIPEB_DATA_N2 0x6103c 5386 #define _PIPEB_LINK_M1 0x61040 5387 #define _PIPEB_LINK_N1 0x61044 5388 #define _PIPEB_LINK_M2 0x61048 5389 #define _PIPEB_LINK_N2 0x6104c 5390 5391 #define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1) 5392 #define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1) 5393 #define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2) 5394 #define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2) 5395 #define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1) 5396 #define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1) 5397 #define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2) 5398 #define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2) 5399 5400 /* CPU panel fitter */ 5401 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ 5402 #define _PFA_CTL_1 0x68080 5403 #define _PFB_CTL_1 0x68880 5404 #define PF_ENABLE (1 << 31) 5405 #define PF_PIPE_SEL_MASK_IVB (3 << 29) 5406 #define PF_PIPE_SEL_IVB(pipe) ((pipe) << 29) 5407 #define PF_FILTER_MASK (3 << 23) 5408 #define PF_FILTER_PROGRAMMED (0 << 23) 5409 #define PF_FILTER_MED_3x3 (1 << 23) 5410 #define PF_FILTER_EDGE_ENHANCE (2 << 23) 5411 #define PF_FILTER_EDGE_SOFTEN (3 << 23) 5412 #define _PFA_WIN_SZ 0x68074 5413 #define _PFB_WIN_SZ 0x68874 5414 #define _PFA_WIN_POS 0x68070 5415 #define _PFB_WIN_POS 0x68870 5416 #define _PFA_VSCALE 0x68084 5417 #define _PFB_VSCALE 0x68884 5418 #define _PFA_HSCALE 0x68090 5419 #define _PFB_HSCALE 0x68890 5420 5421 #define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) 5422 #define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) 5423 #define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) 5424 #define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) 5425 #define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) 5426 5427 #define _PSA_CTL 0x68180 5428 #define _PSB_CTL 0x68980 5429 #define PS_ENABLE (1 << 31) 5430 #define _PSA_WIN_SZ 0x68174 5431 #define _PSB_WIN_SZ 0x68974 5432 #define _PSA_WIN_POS 0x68170 5433 #define _PSB_WIN_POS 0x68970 5434 5435 #define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL) 5436 #define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ) 5437 #define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS) 5438 5439 /* 5440 * Skylake scalers 5441 */ 5442 #define _PS_1A_CTRL 0x68180 5443 #define _PS_2A_CTRL 0x68280 5444 #define _PS_1B_CTRL 0x68980 5445 #define _PS_2B_CTRL 0x68A80 5446 #define _PS_1C_CTRL 0x69180 5447 #define PS_SCALER_EN (1 << 31) 5448 #define SKL_PS_SCALER_MODE_MASK (3 << 28) 5449 #define SKL_PS_SCALER_MODE_DYN (0 << 28) 5450 #define SKL_PS_SCALER_MODE_HQ (1 << 28) 5451 #define SKL_PS_SCALER_MODE_NV12 (2 << 28) 5452 #define PS_SCALER_MODE_PLANAR (1 << 29) 5453 #define PS_SCALER_MODE_NORMAL (0 << 29) 5454 #define PS_PLANE_SEL_MASK (7 << 25) 5455 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25) 5456 #define PS_FILTER_MASK (3 << 23) 5457 #define PS_FILTER_MEDIUM (0 << 23) 5458 #define PS_FILTER_PROGRAMMED (1 << 23) 5459 #define PS_FILTER_EDGE_ENHANCE (2 << 23) 5460 #define PS_FILTER_BILINEAR (3 << 23) 5461 #define PS_VERT3TAP (1 << 21) 5462 #define PS_VERT_INT_INVERT_FIELD1 (0 << 20) 5463 #define PS_VERT_INT_INVERT_FIELD0 (1 << 20) 5464 #define PS_PWRUP_PROGRESS (1 << 17) 5465 #define PS_V_FILTER_BYPASS (1 << 8) 5466 #define PS_VADAPT_EN (1 << 7) 5467 #define PS_VADAPT_MODE_MASK (3 << 5) 5468 #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5) 5469 #define PS_VADAPT_MODE_MOD_ADAPT (1 << 5) 5470 #define PS_VADAPT_MODE_MOST_ADAPT (3 << 5) 5471 #define PS_PLANE_Y_SEL_MASK (7 << 5) 5472 #define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5) 5473 #define PS_Y_VERT_FILTER_SELECT(set) ((set) << 4) 5474 #define PS_Y_HORZ_FILTER_SELECT(set) ((set) << 3) 5475 #define PS_UV_VERT_FILTER_SELECT(set) ((set) << 2) 5476 #define PS_UV_HORZ_FILTER_SELECT(set) ((set) << 1) 5477 5478 #define _PS_PWR_GATE_1A 0x68160 5479 #define _PS_PWR_GATE_2A 0x68260 5480 #define _PS_PWR_GATE_1B 0x68960 5481 #define _PS_PWR_GATE_2B 0x68A60 5482 #define _PS_PWR_GATE_1C 0x69160 5483 #define PS_PWR_GATE_DIS_OVERRIDE (1 << 31) 5484 #define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3) 5485 #define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3) 5486 #define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3) 5487 #define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3) 5488 #define PS_PWR_GATE_SLPEN_8 0 5489 #define PS_PWR_GATE_SLPEN_16 1 5490 #define PS_PWR_GATE_SLPEN_24 2 5491 #define PS_PWR_GATE_SLPEN_32 3 5492 5493 #define _PS_WIN_POS_1A 0x68170 5494 #define _PS_WIN_POS_2A 0x68270 5495 #define _PS_WIN_POS_1B 0x68970 5496 #define _PS_WIN_POS_2B 0x68A70 5497 #define _PS_WIN_POS_1C 0x69170 5498 5499 #define _PS_WIN_SZ_1A 0x68174 5500 #define _PS_WIN_SZ_2A 0x68274 5501 #define _PS_WIN_SZ_1B 0x68974 5502 #define _PS_WIN_SZ_2B 0x68A74 5503 #define _PS_WIN_SZ_1C 0x69174 5504 5505 #define _PS_VSCALE_1A 0x68184 5506 #define _PS_VSCALE_2A 0x68284 5507 #define _PS_VSCALE_1B 0x68984 5508 #define _PS_VSCALE_2B 0x68A84 5509 #define _PS_VSCALE_1C 0x69184 5510 5511 #define _PS_HSCALE_1A 0x68190 5512 #define _PS_HSCALE_2A 0x68290 5513 #define _PS_HSCALE_1B 0x68990 5514 #define _PS_HSCALE_2B 0x68A90 5515 #define _PS_HSCALE_1C 0x69190 5516 5517 #define _PS_VPHASE_1A 0x68188 5518 #define _PS_VPHASE_2A 0x68288 5519 #define _PS_VPHASE_1B 0x68988 5520 #define _PS_VPHASE_2B 0x68A88 5521 #define _PS_VPHASE_1C 0x69188 5522 #define PS_Y_PHASE(x) ((x) << 16) 5523 #define PS_UV_RGB_PHASE(x) ((x) << 0) 5524 #define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */ 5525 #define PS_PHASE_TRIP (1 << 0) 5526 5527 #define _PS_HPHASE_1A 0x68194 5528 #define _PS_HPHASE_2A 0x68294 5529 #define _PS_HPHASE_1B 0x68994 5530 #define _PS_HPHASE_2B 0x68A94 5531 #define _PS_HPHASE_1C 0x69194 5532 5533 #define _PS_ECC_STAT_1A 0x681D0 5534 #define _PS_ECC_STAT_2A 0x682D0 5535 #define _PS_ECC_STAT_1B 0x689D0 5536 #define _PS_ECC_STAT_2B 0x68AD0 5537 #define _PS_ECC_STAT_1C 0x691D0 5538 5539 #define _PS_COEF_SET0_INDEX_1A 0x68198 5540 #define _PS_COEF_SET0_INDEX_2A 0x68298 5541 #define _PS_COEF_SET0_INDEX_1B 0x68998 5542 #define _PS_COEF_SET0_INDEX_2B 0x68A98 5543 #define PS_COEE_INDEX_AUTO_INC (1 << 10) 5544 5545 #define _PS_COEF_SET0_DATA_1A 0x6819C 5546 #define _PS_COEF_SET0_DATA_2A 0x6829C 5547 #define _PS_COEF_SET0_DATA_1B 0x6899C 5548 #define _PS_COEF_SET0_DATA_2B 0x68A9C 5549 5550 #define _ID(id, a, b) _PICK_EVEN(id, a, b) 5551 #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \ 5552 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \ 5553 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL)) 5554 #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \ 5555 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \ 5556 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B)) 5557 #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \ 5558 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \ 5559 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B)) 5560 #define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \ 5561 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \ 5562 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B)) 5563 #define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \ 5564 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \ 5565 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B)) 5566 #define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \ 5567 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \ 5568 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B)) 5569 #define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \ 5570 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \ 5571 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B)) 5572 #define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \ 5573 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \ 5574 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B)) 5575 #define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \ 5576 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \ 5577 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)) 5578 #define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe, \ 5579 _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \ 5580 _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8) 5581 5582 #define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \ 5583 _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \ 5584 _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8) 5585 /* legacy palette */ 5586 #define _LGC_PALETTE_A 0x4a000 5587 #define _LGC_PALETTE_B 0x4a800 5588 #define LGC_PALETTE_RED_MASK REG_GENMASK(23, 16) 5589 #define LGC_PALETTE_GREEN_MASK REG_GENMASK(15, 8) 5590 #define LGC_PALETTE_BLUE_MASK REG_GENMASK(7, 0) 5591 #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4) 5592 5593 /* ilk/snb precision palette */ 5594 #define _PREC_PALETTE_A 0x4b000 5595 #define _PREC_PALETTE_B 0x4c000 5596 #define PREC_PALETTE_RED_MASK REG_GENMASK(29, 20) 5597 #define PREC_PALETTE_GREEN_MASK REG_GENMASK(19, 10) 5598 #define PREC_PALETTE_BLUE_MASK REG_GENMASK(9, 0) 5599 #define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4) 5600 5601 #define _PREC_PIPEAGCMAX 0x4d000 5602 #define _PREC_PIPEBGCMAX 0x4d010 5603 #define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4) 5604 5605 #define _GAMMA_MODE_A 0x4a480 5606 #define _GAMMA_MODE_B 0x4ac80 5607 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) 5608 #define PRE_CSC_GAMMA_ENABLE (1 << 31) 5609 #define POST_CSC_GAMMA_ENABLE (1 << 30) 5610 #define GAMMA_MODE_MODE_MASK (3 << 0) 5611 #define GAMMA_MODE_MODE_8BIT (0 << 0) 5612 #define GAMMA_MODE_MODE_10BIT (1 << 0) 5613 #define GAMMA_MODE_MODE_12BIT (2 << 0) 5614 #define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */ 5615 #define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */ 5616 5617 /* DMC */ 5618 #define DMC_PROGRAM(addr, i) _MMIO((addr) + (i) * 4) 5619 #define DMC_SSP_BASE_ADDR_GEN9 0x00002FC0 5620 #define DMC_HTP_ADDR_SKL 0x00500034 5621 #define DMC_SSP_BASE _MMIO(0x8F074) 5622 #define DMC_HTP_SKL _MMIO(0x8F004) 5623 #define DMC_LAST_WRITE _MMIO(0x8F034) 5624 #define DMC_LAST_WRITE_VALUE 0xc003b400 5625 /* MMIO address range for DMC program (0x80000 - 0x82FFF) */ 5626 #define DMC_MMIO_START_RANGE 0x80000 5627 #define DMC_MMIO_END_RANGE 0x8FFFF 5628 #define SKL_DMC_DC3_DC5_COUNT _MMIO(0x80030) 5629 #define SKL_DMC_DC5_DC6_COUNT _MMIO(0x8002C) 5630 #define BXT_DMC_DC3_DC5_COUNT _MMIO(0x80038) 5631 #define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084) 5632 #define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088) 5633 #define DG1_DMC_DEBUG_DC5_COUNT _MMIO(0x134154) 5634 5635 #define DMC_DEBUG3 _MMIO(0x101090) 5636 5637 /* Display Internal Timeout Register */ 5638 #define RM_TIMEOUT _MMIO(0x42060) 5639 #define MMIO_TIMEOUT_US(us) ((us) << 0) 5640 5641 /* interrupts */ 5642 #define DE_MASTER_IRQ_CONTROL (1 << 31) 5643 #define DE_SPRITEB_FLIP_DONE (1 << 29) 5644 #define DE_SPRITEA_FLIP_DONE (1 << 28) 5645 #define DE_PLANEB_FLIP_DONE (1 << 27) 5646 #define DE_PLANEA_FLIP_DONE (1 << 26) 5647 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane))) 5648 #define DE_PCU_EVENT (1 << 25) 5649 #define DE_GTT_FAULT (1 << 24) 5650 #define DE_POISON (1 << 23) 5651 #define DE_PERFORM_COUNTER (1 << 22) 5652 #define DE_PCH_EVENT (1 << 21) 5653 #define DE_AUX_CHANNEL_A (1 << 20) 5654 #define DE_DP_A_HOTPLUG (1 << 19) 5655 #define DE_GSE (1 << 18) 5656 #define DE_PIPEB_VBLANK (1 << 15) 5657 #define DE_PIPEB_EVEN_FIELD (1 << 14) 5658 #define DE_PIPEB_ODD_FIELD (1 << 13) 5659 #define DE_PIPEB_LINE_COMPARE (1 << 12) 5660 #define DE_PIPEB_VSYNC (1 << 11) 5661 #define DE_PIPEB_CRC_DONE (1 << 10) 5662 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) 5663 #define DE_PIPEA_VBLANK (1 << 7) 5664 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe))) 5665 #define DE_PIPEA_EVEN_FIELD (1 << 6) 5666 #define DE_PIPEA_ODD_FIELD (1 << 5) 5667 #define DE_PIPEA_LINE_COMPARE (1 << 4) 5668 #define DE_PIPEA_VSYNC (1 << 3) 5669 #define DE_PIPEA_CRC_DONE (1 << 2) 5670 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe))) 5671 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 5672 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe))) 5673 5674 /* More Ivybridge lolz */ 5675 #define DE_ERR_INT_IVB (1 << 30) 5676 #define DE_GSE_IVB (1 << 29) 5677 #define DE_PCH_EVENT_IVB (1 << 28) 5678 #define DE_DP_A_HOTPLUG_IVB (1 << 27) 5679 #define DE_AUX_CHANNEL_A_IVB (1 << 26) 5680 #define DE_EDP_PSR_INT_HSW (1 << 19) 5681 #define DE_SPRITEC_FLIP_DONE_IVB (1 << 14) 5682 #define DE_PLANEC_FLIP_DONE_IVB (1 << 13) 5683 #define DE_PIPEC_VBLANK_IVB (1 << 10) 5684 #define DE_SPRITEB_FLIP_DONE_IVB (1 << 9) 5685 #define DE_PLANEB_FLIP_DONE_IVB (1 << 8) 5686 #define DE_PIPEB_VBLANK_IVB (1 << 5) 5687 #define DE_SPRITEA_FLIP_DONE_IVB (1 << 4) 5688 #define DE_PLANEA_FLIP_DONE_IVB (1 << 3) 5689 #define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane))) 5690 #define DE_PIPEA_VBLANK_IVB (1 << 0) 5691 #define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5)) 5692 5693 #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */ 5694 #define MASTER_INTERRUPT_ENABLE (1 << 31) 5695 5696 #define DEISR _MMIO(0x44000) 5697 #define DEIMR _MMIO(0x44004) 5698 #define DEIIR _MMIO(0x44008) 5699 #define DEIER _MMIO(0x4400c) 5700 5701 #define GTISR _MMIO(0x44010) 5702 #define GTIMR _MMIO(0x44014) 5703 #define GTIIR _MMIO(0x44018) 5704 #define GTIER _MMIO(0x4401c) 5705 5706 #define GEN8_MASTER_IRQ _MMIO(0x44200) 5707 #define GEN8_MASTER_IRQ_CONTROL (1 << 31) 5708 #define GEN8_PCU_IRQ (1 << 30) 5709 #define GEN8_DE_PCH_IRQ (1 << 23) 5710 #define GEN8_DE_MISC_IRQ (1 << 22) 5711 #define GEN8_DE_PORT_IRQ (1 << 20) 5712 #define GEN8_DE_PIPE_C_IRQ (1 << 18) 5713 #define GEN8_DE_PIPE_B_IRQ (1 << 17) 5714 #define GEN8_DE_PIPE_A_IRQ (1 << 16) 5715 #define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe))) 5716 #define GEN8_GT_VECS_IRQ (1 << 6) 5717 #define GEN8_GT_GUC_IRQ (1 << 5) 5718 #define GEN8_GT_PM_IRQ (1 << 4) 5719 #define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */ 5720 #define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */ 5721 #define GEN8_GT_BCS_IRQ (1 << 1) 5722 #define GEN8_GT_RCS_IRQ (1 << 0) 5723 5724 #define XELPD_DISPLAY_ERR_FATAL_MASK _MMIO(0x4421c) 5725 5726 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which))) 5727 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which))) 5728 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which))) 5729 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which))) 5730 5731 #define GEN8_RCS_IRQ_SHIFT 0 5732 #define GEN8_BCS_IRQ_SHIFT 16 5733 #define GEN8_VCS0_IRQ_SHIFT 0 /* NB: VCS1 in bspec! */ 5734 #define GEN8_VCS1_IRQ_SHIFT 16 /* NB: VCS2 in bpsec! */ 5735 #define GEN8_VECS_IRQ_SHIFT 0 5736 #define GEN8_WD_IRQ_SHIFT 16 5737 5738 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe))) 5739 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe))) 5740 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe))) 5741 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe))) 5742 #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31) 5743 #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29) 5744 #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28) 5745 #define XELPD_PIPE_SOFT_UNDERRUN (1 << 22) 5746 #define XELPD_PIPE_HARD_UNDERRUN (1 << 21) 5747 #define GEN8_PIPE_CURSOR_FAULT (1 << 10) 5748 #define GEN8_PIPE_SPRITE_FAULT (1 << 9) 5749 #define GEN8_PIPE_PRIMARY_FAULT (1 << 8) 5750 #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5) 5751 #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4) 5752 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) 5753 #define GEN8_PIPE_VSYNC (1 << 1) 5754 #define GEN8_PIPE_VBLANK (1 << 0) 5755 #define GEN9_PIPE_CURSOR_FAULT (1 << 11) 5756 #define GEN11_PIPE_PLANE7_FAULT (1 << 22) 5757 #define GEN11_PIPE_PLANE6_FAULT (1 << 21) 5758 #define GEN11_PIPE_PLANE5_FAULT (1 << 20) 5759 #define GEN9_PIPE_PLANE4_FAULT (1 << 10) 5760 #define GEN9_PIPE_PLANE3_FAULT (1 << 9) 5761 #define GEN9_PIPE_PLANE2_FAULT (1 << 8) 5762 #define GEN9_PIPE_PLANE1_FAULT (1 << 7) 5763 #define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6) 5764 #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5) 5765 #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4) 5766 #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3) 5767 #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p))) 5768 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ 5769 (GEN8_PIPE_CURSOR_FAULT | \ 5770 GEN8_PIPE_SPRITE_FAULT | \ 5771 GEN8_PIPE_PRIMARY_FAULT) 5772 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \ 5773 (GEN9_PIPE_CURSOR_FAULT | \ 5774 GEN9_PIPE_PLANE4_FAULT | \ 5775 GEN9_PIPE_PLANE3_FAULT | \ 5776 GEN9_PIPE_PLANE2_FAULT | \ 5777 GEN9_PIPE_PLANE1_FAULT) 5778 #define GEN11_DE_PIPE_IRQ_FAULT_ERRORS \ 5779 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \ 5780 GEN11_PIPE_PLANE7_FAULT | \ 5781 GEN11_PIPE_PLANE6_FAULT | \ 5782 GEN11_PIPE_PLANE5_FAULT) 5783 #define RKL_DE_PIPE_IRQ_FAULT_ERRORS \ 5784 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \ 5785 GEN11_PIPE_PLANE5_FAULT) 5786 5787 #define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A) 5788 #define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1) 5789 5790 #define GEN8_DE_PORT_ISR _MMIO(0x44440) 5791 #define GEN8_DE_PORT_IMR _MMIO(0x44444) 5792 #define GEN8_DE_PORT_IIR _MMIO(0x44448) 5793 #define GEN8_DE_PORT_IER _MMIO(0x4444c) 5794 #define DSI1_NON_TE (1 << 31) 5795 #define DSI0_NON_TE (1 << 30) 5796 #define ICL_AUX_CHANNEL_E (1 << 29) 5797 #define ICL_AUX_CHANNEL_F (1 << 28) 5798 #define GEN9_AUX_CHANNEL_D (1 << 27) 5799 #define GEN9_AUX_CHANNEL_C (1 << 26) 5800 #define GEN9_AUX_CHANNEL_B (1 << 25) 5801 #define DSI1_TE (1 << 24) 5802 #define DSI0_TE (1 << 23) 5803 #define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin)) 5804 #define BXT_DE_PORT_HOTPLUG_MASK (GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \ 5805 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \ 5806 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)) 5807 #define BDW_DE_PORT_HOTPLUG_MASK GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) 5808 #define BXT_DE_PORT_GMBUS (1 << 1) 5809 #define GEN8_AUX_CHANNEL_A (1 << 0) 5810 #define TGL_DE_PORT_AUX_USBC6 REG_BIT(13) 5811 #define XELPD_DE_PORT_AUX_DDIE REG_BIT(13) 5812 #define TGL_DE_PORT_AUX_USBC5 REG_BIT(12) 5813 #define XELPD_DE_PORT_AUX_DDID REG_BIT(12) 5814 #define TGL_DE_PORT_AUX_USBC4 REG_BIT(11) 5815 #define TGL_DE_PORT_AUX_USBC3 REG_BIT(10) 5816 #define TGL_DE_PORT_AUX_USBC2 REG_BIT(9) 5817 #define TGL_DE_PORT_AUX_USBC1 REG_BIT(8) 5818 #define TGL_DE_PORT_AUX_DDIC REG_BIT(2) 5819 #define TGL_DE_PORT_AUX_DDIB REG_BIT(1) 5820 #define TGL_DE_PORT_AUX_DDIA REG_BIT(0) 5821 5822 #define GEN8_DE_MISC_ISR _MMIO(0x44460) 5823 #define GEN8_DE_MISC_IMR _MMIO(0x44464) 5824 #define GEN8_DE_MISC_IIR _MMIO(0x44468) 5825 #define GEN8_DE_MISC_IER _MMIO(0x4446c) 5826 #define GEN8_DE_MISC_GSE (1 << 27) 5827 #define GEN8_DE_EDP_PSR (1 << 19) 5828 5829 #define GEN8_PCU_ISR _MMIO(0x444e0) 5830 #define GEN8_PCU_IMR _MMIO(0x444e4) 5831 #define GEN8_PCU_IIR _MMIO(0x444e8) 5832 #define GEN8_PCU_IER _MMIO(0x444ec) 5833 5834 #define GEN11_GU_MISC_ISR _MMIO(0x444f0) 5835 #define GEN11_GU_MISC_IMR _MMIO(0x444f4) 5836 #define GEN11_GU_MISC_IIR _MMIO(0x444f8) 5837 #define GEN11_GU_MISC_IER _MMIO(0x444fc) 5838 #define GEN11_GU_MISC_GSE (1 << 27) 5839 5840 #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010) 5841 #define GEN11_MASTER_IRQ (1 << 31) 5842 #define GEN11_PCU_IRQ (1 << 30) 5843 #define GEN11_GU_MISC_IRQ (1 << 29) 5844 #define GEN11_DISPLAY_IRQ (1 << 16) 5845 #define GEN11_GT_DW_IRQ(x) (1 << (x)) 5846 #define GEN11_GT_DW1_IRQ (1 << 1) 5847 #define GEN11_GT_DW0_IRQ (1 << 0) 5848 5849 #define DG1_MSTR_TILE_INTR _MMIO(0x190008) 5850 #define DG1_MSTR_IRQ REG_BIT(31) 5851 #define DG1_MSTR_TILE(t) REG_BIT(t) 5852 5853 #define GEN11_DISPLAY_INT_CTL _MMIO(0x44200) 5854 #define GEN11_DISPLAY_IRQ_ENABLE (1 << 31) 5855 #define GEN11_AUDIO_CODEC_IRQ (1 << 24) 5856 #define GEN11_DE_PCH_IRQ (1 << 23) 5857 #define GEN11_DE_MISC_IRQ (1 << 22) 5858 #define GEN11_DE_HPD_IRQ (1 << 21) 5859 #define GEN11_DE_PORT_IRQ (1 << 20) 5860 #define GEN11_DE_PIPE_C (1 << 18) 5861 #define GEN11_DE_PIPE_B (1 << 17) 5862 #define GEN11_DE_PIPE_A (1 << 16) 5863 5864 #define GEN11_DE_HPD_ISR _MMIO(0x44470) 5865 #define GEN11_DE_HPD_IMR _MMIO(0x44474) 5866 #define GEN11_DE_HPD_IIR _MMIO(0x44478) 5867 #define GEN11_DE_HPD_IER _MMIO(0x4447c) 5868 #define GEN11_TC_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin)) 5869 #define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(HPD_PORT_TC6) | \ 5870 GEN11_TC_HOTPLUG(HPD_PORT_TC5) | \ 5871 GEN11_TC_HOTPLUG(HPD_PORT_TC4) | \ 5872 GEN11_TC_HOTPLUG(HPD_PORT_TC3) | \ 5873 GEN11_TC_HOTPLUG(HPD_PORT_TC2) | \ 5874 GEN11_TC_HOTPLUG(HPD_PORT_TC1)) 5875 #define GEN11_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin)) 5876 #define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(HPD_PORT_TC6) | \ 5877 GEN11_TBT_HOTPLUG(HPD_PORT_TC5) | \ 5878 GEN11_TBT_HOTPLUG(HPD_PORT_TC4) | \ 5879 GEN11_TBT_HOTPLUG(HPD_PORT_TC3) | \ 5880 GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \ 5881 GEN11_TBT_HOTPLUG(HPD_PORT_TC1)) 5882 5883 #define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030) 5884 #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038) 5885 #define GEN11_HOTPLUG_CTL_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4)) 5886 #define GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4)) 5887 #define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4)) 5888 #define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 << (_HPD_PIN_TC(hpd_pin) * 4)) 5889 5890 #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004) 5891 /* Required on all Ironlake and Sandybridge according to the B-Spec. */ 5892 #define ILK_ELPIN_409_SELECT (1 << 25) 5893 #define ILK_DPARB_GATE (1 << 22) 5894 #define ILK_VSDPFD_FULL (1 << 21) 5895 #define FUSE_STRAP _MMIO(0x42014) 5896 #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31) 5897 #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30) 5898 #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29) 5899 #define IVB_PIPE_C_DISABLE (1 << 28) 5900 #define ILK_HDCP_DISABLE (1 << 25) 5901 #define ILK_eDP_A_DISABLE (1 << 24) 5902 #define HSW_CDCLK_LIMIT (1 << 24) 5903 #define ILK_DESKTOP (1 << 23) 5904 #define HSW_CPU_SSC_ENABLE (1 << 21) 5905 5906 #define FUSE_STRAP3 _MMIO(0x42020) 5907 #define HSW_REF_CLK_SELECT (1 << 1) 5908 5909 #define ILK_DSPCLK_GATE_D _MMIO(0x42020) 5910 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) 5911 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) 5912 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) 5913 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7) 5914 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5) 5915 5916 #define IVB_CHICKEN3 _MMIO(0x4200c) 5917 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) 5918 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) 5919 5920 #define CHICKEN_PAR1_1 _MMIO(0x42080) 5921 #define IGNORE_KVMR_PIPE_A REG_BIT(23) 5922 #define KBL_ARB_FILL_SPARE_22 REG_BIT(22) 5923 #define DIS_RAM_BYPASS_PSR2_MAN_TRACK (1 << 16) 5924 #define SKL_DE_COMPRESSED_HASH_MODE (1 << 15) 5925 #define DPA_MASK_VBLANK_SRD (1 << 15) 5926 #define FORCE_ARB_IDLE_PLANES (1 << 14) 5927 #define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) 5928 #define IGNORE_PSR2_HW_TRACKING (1 << 1) 5929 5930 #define CHICKEN_PAR2_1 _MMIO(0x42090) 5931 #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14) 5932 5933 #define CHICKEN_MISC_2 _MMIO(0x42084) 5934 #define KBL_ARB_FILL_SPARE_14 REG_BIT(14) 5935 #define KBL_ARB_FILL_SPARE_13 REG_BIT(13) 5936 #define GLK_CL2_PWR_DOWN (1 << 12) 5937 #define GLK_CL1_PWR_DOWN (1 << 11) 5938 #define GLK_CL0_PWR_DOWN (1 << 10) 5939 5940 #define CHICKEN_MISC_4 _MMIO(0x4208c) 5941 #define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13) 5942 #define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0) 5943 #define CHICKEN_FBC_STRIDE(x) REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x)) 5944 5945 #define _CHICKEN_PIPESL_1_A 0x420b0 5946 #define _CHICKEN_PIPESL_1_B 0x420b4 5947 #define HSW_PRI_STRETCH_MAX_MASK REG_GENMASK(28, 27) 5948 #define HSW_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0) 5949 #define HSW_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1) 5950 #define HSW_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2) 5951 #define HSW_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3) 5952 #define HSW_SPR_STRETCH_MAX_MASK REG_GENMASK(26, 25) 5953 #define HSW_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0) 5954 #define HSW_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1) 5955 #define HSW_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2) 5956 #define HSW_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3) 5957 #define HSW_FBCQ_DIS (1 << 22) 5958 #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0) 5959 #define SKL_PLANE1_STRETCH_MAX_MASK REG_GENMASK(1, 0) 5960 #define SKL_PLANE1_STRETCH_MAX_X8 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0) 5961 #define SKL_PLANE1_STRETCH_MAX_X4 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1) 5962 #define SKL_PLANE1_STRETCH_MAX_X2 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2) 5963 #define SKL_PLANE1_STRETCH_MAX_X1 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3) 5964 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) 5965 5966 #define _CHICKEN_TRANS_A 0x420c0 5967 #define _CHICKEN_TRANS_B 0x420c4 5968 #define _CHICKEN_TRANS_C 0x420c8 5969 #define _CHICKEN_TRANS_EDP 0x420cc 5970 #define _CHICKEN_TRANS_D 0x420d8 5971 #define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \ 5972 [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \ 5973 [TRANSCODER_A] = _CHICKEN_TRANS_A, \ 5974 [TRANSCODER_B] = _CHICKEN_TRANS_B, \ 5975 [TRANSCODER_C] = _CHICKEN_TRANS_C, \ 5976 [TRANSCODER_D] = _CHICKEN_TRANS_D)) 5977 #define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) 5978 #define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x) 5979 #define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */ 5980 #define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23) 5981 #define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19) 5982 #define ADLP_1_BASED_X_GRANULARITY REG_BIT(18) 5983 #define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18) 5984 #define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */ 5985 #define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */ 5986 #define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15) 5987 #define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12) 5988 5989 #define DISP_ARB_CTL _MMIO(0x45000) 5990 #define DISP_FBC_MEMORY_WAKE (1 << 31) 5991 #define DISP_TILE_SURFACE_SWIZZLING (1 << 13) 5992 #define DISP_FBC_WM_DIS (1 << 15) 5993 #define DISP_ARB_CTL2 _MMIO(0x45004) 5994 #define DISP_DATA_PARTITION_5_6 (1 << 6) 5995 #define DISP_IPC_ENABLE (1 << 3) 5996 5997 /* 5998 * The below are numbered starting from "S1" on gen11/gen12, but starting 5999 * with display 13, the bspec switches to a 0-based numbering scheme 6000 * (although the addresses stay the same so new S0 = old S1, new S1 = old S2). 6001 * We'll just use the 0-based numbering here for all platforms since it's the 6002 * way things will be named by the hardware team going forward, plus it's more 6003 * consistent with how most of the rest of our registers are named. 6004 */ 6005 #define _DBUF_CTL_S0 0x45008 6006 #define _DBUF_CTL_S1 0x44FE8 6007 #define _DBUF_CTL_S2 0x44300 6008 #define _DBUF_CTL_S3 0x44304 6009 #define DBUF_CTL_S(slice) _MMIO(_PICK(slice, \ 6010 _DBUF_CTL_S0, \ 6011 _DBUF_CTL_S1, \ 6012 _DBUF_CTL_S2, \ 6013 _DBUF_CTL_S3)) 6014 #define DBUF_POWER_REQUEST REG_BIT(31) 6015 #define DBUF_POWER_STATE REG_BIT(30) 6016 #define DBUF_TRACKER_STATE_SERVICE_MASK REG_GENMASK(23, 19) 6017 #define DBUF_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x) 6018 #define DBUF_MIN_TRACKER_STATE_SERVICE_MASK REG_GENMASK(18, 16) /* ADL-P+ */ 6019 #define DBUF_MIN_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */ 6020 6021 #define GEN7_MSG_CTL _MMIO(0x45010) 6022 #define WAIT_FOR_PCH_RESET_ACK (1 << 1) 6023 #define WAIT_FOR_PCH_FLR_ACK (1 << 0) 6024 6025 #define _BW_BUDDY0_CTL 0x45130 6026 #define _BW_BUDDY1_CTL 0x45140 6027 #define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \ 6028 _BW_BUDDY0_CTL, \ 6029 _BW_BUDDY1_CTL)) 6030 #define BW_BUDDY_DISABLE REG_BIT(31) 6031 #define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16) 6032 #define BW_BUDDY_TLB_REQ_TIMER(x) REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x) 6033 6034 #define _BW_BUDDY0_PAGE_MASK 0x45134 6035 #define _BW_BUDDY1_PAGE_MASK 0x45144 6036 #define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \ 6037 _BW_BUDDY0_PAGE_MASK, \ 6038 _BW_BUDDY1_PAGE_MASK)) 6039 6040 #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) 6041 #define RESET_PCH_HANDSHAKE_ENABLE (1 << 4) 6042 6043 #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) 6044 #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30) 6045 #define ICL_DELAY_PMRSP REG_BIT(22) 6046 #define DISABLE_FLR_SRC REG_BIT(15) 6047 #define MASK_WAKEMEM REG_BIT(13) 6048 6049 #define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434) 6050 #define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27) 6051 #define DCPR_MASK_LPMODE REG_BIT(26) 6052 #define DCPR_SEND_RESP_IMM REG_BIT(25) 6053 #define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24) 6054 6055 #define SKL_DFSM _MMIO(0x51000) 6056 #define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27) 6057 #define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25) 6058 #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23) 6059 #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23) 6060 #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23) 6061 #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23) 6062 #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23) 6063 #define ICL_DFSM_DMC_DISABLE (1 << 23) 6064 #define SKL_DFSM_PIPE_A_DISABLE (1 << 30) 6065 #define SKL_DFSM_PIPE_B_DISABLE (1 << 21) 6066 #define SKL_DFSM_PIPE_C_DISABLE (1 << 28) 6067 #define TGL_DFSM_PIPE_D_DISABLE (1 << 22) 6068 #define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7) 6069 6070 #define SKL_DSSM _MMIO(0x51004) 6071 #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29) 6072 #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29) 6073 #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29) 6074 #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29) 6075 6076 /*GEN11 chicken */ 6077 #define _PIPEA_CHICKEN 0x70038 6078 #define _PIPEB_CHICKEN 0x71038 6079 #define _PIPEC_CHICKEN 0x72038 6080 #define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\ 6081 _PIPEB_CHICKEN) 6082 #define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30) 6083 #define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30) 6084 #define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15) 6085 #define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12) 6086 #define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7) 6087 6088 /* PCH */ 6089 6090 #define PCH_DISPLAY_BASE 0xc0000u 6091 6092 /* south display engine interrupt: IBX */ 6093 #define SDE_AUDIO_POWER_D (1 << 27) 6094 #define SDE_AUDIO_POWER_C (1 << 26) 6095 #define SDE_AUDIO_POWER_B (1 << 25) 6096 #define SDE_AUDIO_POWER_SHIFT (25) 6097 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) 6098 #define SDE_GMBUS (1 << 24) 6099 #define SDE_AUDIO_HDCP_TRANSB (1 << 23) 6100 #define SDE_AUDIO_HDCP_TRANSA (1 << 22) 6101 #define SDE_AUDIO_HDCP_MASK (3 << 22) 6102 #define SDE_AUDIO_TRANSB (1 << 21) 6103 #define SDE_AUDIO_TRANSA (1 << 20) 6104 #define SDE_AUDIO_TRANS_MASK (3 << 20) 6105 #define SDE_POISON (1 << 19) 6106 /* 18 reserved */ 6107 #define SDE_FDI_RXB (1 << 17) 6108 #define SDE_FDI_RXA (1 << 16) 6109 #define SDE_FDI_MASK (3 << 16) 6110 #define SDE_AUXD (1 << 15) 6111 #define SDE_AUXC (1 << 14) 6112 #define SDE_AUXB (1 << 13) 6113 #define SDE_AUX_MASK (7 << 13) 6114 /* 12 reserved */ 6115 #define SDE_CRT_HOTPLUG (1 << 11) 6116 #define SDE_PORTD_HOTPLUG (1 << 10) 6117 #define SDE_PORTC_HOTPLUG (1 << 9) 6118 #define SDE_PORTB_HOTPLUG (1 << 8) 6119 #define SDE_SDVOB_HOTPLUG (1 << 6) 6120 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \ 6121 SDE_SDVOB_HOTPLUG | \ 6122 SDE_PORTB_HOTPLUG | \ 6123 SDE_PORTC_HOTPLUG | \ 6124 SDE_PORTD_HOTPLUG) 6125 #define SDE_TRANSB_CRC_DONE (1 << 5) 6126 #define SDE_TRANSB_CRC_ERR (1 << 4) 6127 #define SDE_TRANSB_FIFO_UNDER (1 << 3) 6128 #define SDE_TRANSA_CRC_DONE (1 << 2) 6129 #define SDE_TRANSA_CRC_ERR (1 << 1) 6130 #define SDE_TRANSA_FIFO_UNDER (1 << 0) 6131 #define SDE_TRANS_MASK (0x3f) 6132 6133 /* south display engine interrupt: CPT - CNP */ 6134 #define SDE_AUDIO_POWER_D_CPT (1 << 31) 6135 #define SDE_AUDIO_POWER_C_CPT (1 << 30) 6136 #define SDE_AUDIO_POWER_B_CPT (1 << 29) 6137 #define SDE_AUDIO_POWER_SHIFT_CPT 29 6138 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29) 6139 #define SDE_AUXD_CPT (1 << 27) 6140 #define SDE_AUXC_CPT (1 << 26) 6141 #define SDE_AUXB_CPT (1 << 25) 6142 #define SDE_AUX_MASK_CPT (7 << 25) 6143 #define SDE_PORTE_HOTPLUG_SPT (1 << 25) 6144 #define SDE_PORTA_HOTPLUG_SPT (1 << 24) 6145 #define SDE_PORTD_HOTPLUG_CPT (1 << 23) 6146 #define SDE_PORTC_HOTPLUG_CPT (1 << 22) 6147 #define SDE_PORTB_HOTPLUG_CPT (1 << 21) 6148 #define SDE_CRT_HOTPLUG_CPT (1 << 19) 6149 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18) 6150 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ 6151 SDE_SDVOB_HOTPLUG_CPT | \ 6152 SDE_PORTD_HOTPLUG_CPT | \ 6153 SDE_PORTC_HOTPLUG_CPT | \ 6154 SDE_PORTB_HOTPLUG_CPT) 6155 #define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \ 6156 SDE_PORTD_HOTPLUG_CPT | \ 6157 SDE_PORTC_HOTPLUG_CPT | \ 6158 SDE_PORTB_HOTPLUG_CPT | \ 6159 SDE_PORTA_HOTPLUG_SPT) 6160 #define SDE_GMBUS_CPT (1 << 17) 6161 #define SDE_ERROR_CPT (1 << 16) 6162 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) 6163 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) 6164 #define SDE_FDI_RXC_CPT (1 << 8) 6165 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) 6166 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) 6167 #define SDE_FDI_RXB_CPT (1 << 4) 6168 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) 6169 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) 6170 #define SDE_FDI_RXA_CPT (1 << 0) 6171 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \ 6172 SDE_AUDIO_CP_REQ_B_CPT | \ 6173 SDE_AUDIO_CP_REQ_A_CPT) 6174 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \ 6175 SDE_AUDIO_CP_CHG_B_CPT | \ 6176 SDE_AUDIO_CP_CHG_A_CPT) 6177 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \ 6178 SDE_FDI_RXB_CPT | \ 6179 SDE_FDI_RXA_CPT) 6180 6181 /* south display engine interrupt: ICP/TGP */ 6182 #define SDE_GMBUS_ICP (1 << 23) 6183 #define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin)) 6184 #define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin)) 6185 #define SDE_DDI_HOTPLUG_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \ 6186 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \ 6187 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \ 6188 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A)) 6189 #define SDE_TC_HOTPLUG_MASK_ICP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \ 6190 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \ 6191 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \ 6192 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \ 6193 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \ 6194 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1)) 6195 6196 #define SDEISR _MMIO(0xc4000) 6197 #define SDEIMR _MMIO(0xc4004) 6198 #define SDEIIR _MMIO(0xc4008) 6199 #define SDEIER _MMIO(0xc400c) 6200 6201 #define SERR_INT _MMIO(0xc4040) 6202 #define SERR_INT_POISON (1 << 31) 6203 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) 6204 6205 /* digital port hotplug */ 6206 #define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */ 6207 #define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */ 6208 #define BXT_DDIA_HPD_INVERT (1 << 27) 6209 #define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */ 6210 #define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */ 6211 #define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */ 6212 #define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */ 6213 #define PORTD_HOTPLUG_ENABLE (1 << 20) 6214 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */ 6215 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */ 6216 #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */ 6217 #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */ 6218 #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */ 6219 #define PORTD_HOTPLUG_STATUS_MASK (3 << 16) 6220 #define PORTD_HOTPLUG_NO_DETECT (0 << 16) 6221 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) 6222 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16) 6223 #define PORTC_HOTPLUG_ENABLE (1 << 12) 6224 #define BXT_DDIC_HPD_INVERT (1 << 11) 6225 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */ 6226 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */ 6227 #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */ 6228 #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */ 6229 #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */ 6230 #define PORTC_HOTPLUG_STATUS_MASK (3 << 8) 6231 #define PORTC_HOTPLUG_NO_DETECT (0 << 8) 6232 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) 6233 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8) 6234 #define PORTB_HOTPLUG_ENABLE (1 << 4) 6235 #define BXT_DDIB_HPD_INVERT (1 << 3) 6236 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */ 6237 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */ 6238 #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */ 6239 #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */ 6240 #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */ 6241 #define PORTB_HOTPLUG_STATUS_MASK (3 << 0) 6242 #define PORTB_HOTPLUG_NO_DETECT (0 << 0) 6243 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) 6244 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0) 6245 #define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \ 6246 BXT_DDIB_HPD_INVERT | \ 6247 BXT_DDIC_HPD_INVERT) 6248 6249 #define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */ 6250 #define PORTE_HOTPLUG_ENABLE (1 << 4) 6251 #define PORTE_HOTPLUG_STATUS_MASK (3 << 0) 6252 #define PORTE_HOTPLUG_NO_DETECT (0 << 0) 6253 #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0) 6254 #define PORTE_HOTPLUG_LONG_DETECT (2 << 0) 6255 6256 /* This register is a reuse of PCH_PORT_HOTPLUG register. The 6257 * functionality covered in PCH_PORT_HOTPLUG is split into 6258 * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC. 6259 */ 6260 6261 #define SHOTPLUG_CTL_DDI _MMIO(0xc4030) 6262 #define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (_HPD_PIN_DDI(hpd_pin) * 4)) 6263 #define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4)) 6264 #define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin) (0x0 << (_HPD_PIN_DDI(hpd_pin) * 4)) 6265 #define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin) (0x1 << (_HPD_PIN_DDI(hpd_pin) * 4)) 6266 #define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin) (0x2 << (_HPD_PIN_DDI(hpd_pin) * 4)) 6267 #define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4)) 6268 6269 #define SHOTPLUG_CTL_TC _MMIO(0xc4034) 6270 #define ICP_TC_HPD_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4)) 6271 #define ICP_TC_HPD_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4)) 6272 #define ICP_TC_HPD_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4)) 6273 6274 #define SHPD_FILTER_CNT _MMIO(0xc4038) 6275 #define SHPD_FILTER_CNT_500_ADJ 0x001D9 6276 6277 #define _PCH_DPLL_A 0xc6014 6278 #define _PCH_DPLL_B 0xc6018 6279 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) 6280 6281 #define _PCH_FPA0 0xc6040 6282 #define FP_CB_TUNE (0x3 << 22) 6283 #define _PCH_FPA1 0xc6044 6284 #define _PCH_FPB0 0xc6048 6285 #define _PCH_FPB1 0xc604c 6286 #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0) 6287 #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1) 6288 6289 #define PCH_DPLL_TEST _MMIO(0xc606c) 6290 6291 #define PCH_DREF_CONTROL _MMIO(0xC6200) 6292 #define DREF_CONTROL_MASK 0x7fc3 6293 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13) 6294 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13) 6295 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13) 6296 #define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13) 6297 #define DREF_SSC_SOURCE_DISABLE (0 << 11) 6298 #define DREF_SSC_SOURCE_ENABLE (2 << 11) 6299 #define DREF_SSC_SOURCE_MASK (3 << 11) 6300 #define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9) 6301 #define DREF_NONSPREAD_CK505_ENABLE (1 << 9) 6302 #define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9) 6303 #define DREF_NONSPREAD_SOURCE_MASK (3 << 9) 6304 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7) 6305 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7) 6306 #define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7) 6307 #define DREF_SSC4_DOWNSPREAD (0 << 6) 6308 #define DREF_SSC4_CENTERSPREAD (1 << 6) 6309 #define DREF_SSC1_DISABLE (0 << 1) 6310 #define DREF_SSC1_ENABLE (1 << 1) 6311 #define DREF_SSC4_DISABLE (0) 6312 #define DREF_SSC4_ENABLE (1) 6313 6314 #define PCH_RAWCLK_FREQ _MMIO(0xc6204) 6315 #define FDL_TP1_TIMER_SHIFT 12 6316 #define FDL_TP1_TIMER_MASK (3 << 12) 6317 #define FDL_TP2_TIMER_SHIFT 10 6318 #define FDL_TP2_TIMER_MASK (3 << 10) 6319 #define RAWCLK_FREQ_MASK 0x3ff 6320 #define CNP_RAWCLK_DIV_MASK (0x3ff << 16) 6321 #define CNP_RAWCLK_DIV(div) ((div) << 16) 6322 #define CNP_RAWCLK_FRAC_MASK (0xf << 26) 6323 #define CNP_RAWCLK_DEN(den) ((den) << 26) 6324 #define ICP_RAWCLK_NUM(num) ((num) << 11) 6325 6326 #define PCH_DPLL_TMR_CFG _MMIO(0xc6208) 6327 6328 #define PCH_SSC4_PARMS _MMIO(0xc6210) 6329 #define PCH_SSC4_AUX_PARMS _MMIO(0xc6214) 6330 6331 #define PCH_DPLL_SEL _MMIO(0xc7000) 6332 #define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4)) 6333 #define TRANS_DPLLA_SEL(pipe) 0 6334 #define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3)) 6335 6336 /* transcoder */ 6337 6338 #define _PCH_TRANS_HTOTAL_A 0xe0000 6339 #define TRANS_HTOTAL_SHIFT 16 6340 #define TRANS_HACTIVE_SHIFT 0 6341 #define _PCH_TRANS_HBLANK_A 0xe0004 6342 #define TRANS_HBLANK_END_SHIFT 16 6343 #define TRANS_HBLANK_START_SHIFT 0 6344 #define _PCH_TRANS_HSYNC_A 0xe0008 6345 #define TRANS_HSYNC_END_SHIFT 16 6346 #define TRANS_HSYNC_START_SHIFT 0 6347 #define _PCH_TRANS_VTOTAL_A 0xe000c 6348 #define TRANS_VTOTAL_SHIFT 16 6349 #define TRANS_VACTIVE_SHIFT 0 6350 #define _PCH_TRANS_VBLANK_A 0xe0010 6351 #define TRANS_VBLANK_END_SHIFT 16 6352 #define TRANS_VBLANK_START_SHIFT 0 6353 #define _PCH_TRANS_VSYNC_A 0xe0014 6354 #define TRANS_VSYNC_END_SHIFT 16 6355 #define TRANS_VSYNC_START_SHIFT 0 6356 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028 6357 6358 #define _PCH_TRANSA_DATA_M1 0xe0030 6359 #define _PCH_TRANSA_DATA_N1 0xe0034 6360 #define _PCH_TRANSA_DATA_M2 0xe0038 6361 #define _PCH_TRANSA_DATA_N2 0xe003c 6362 #define _PCH_TRANSA_LINK_M1 0xe0040 6363 #define _PCH_TRANSA_LINK_N1 0xe0044 6364 #define _PCH_TRANSA_LINK_M2 0xe0048 6365 #define _PCH_TRANSA_LINK_N2 0xe004c 6366 6367 /* Per-transcoder DIP controls (PCH) */ 6368 #define _VIDEO_DIP_CTL_A 0xe0200 6369 #define _VIDEO_DIP_DATA_A 0xe0208 6370 #define _VIDEO_DIP_GCP_A 0xe0210 6371 #define GCP_COLOR_INDICATION (1 << 2) 6372 #define GCP_DEFAULT_PHASE_ENABLE (1 << 1) 6373 #define GCP_AV_MUTE (1 << 0) 6374 6375 #define _VIDEO_DIP_CTL_B 0xe1200 6376 #define _VIDEO_DIP_DATA_B 0xe1208 6377 #define _VIDEO_DIP_GCP_B 0xe1210 6378 6379 #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) 6380 #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) 6381 #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) 6382 6383 /* Per-transcoder DIP controls (VLV) */ 6384 #define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200) 6385 #define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208) 6386 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210) 6387 6388 #define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170) 6389 #define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174) 6390 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178) 6391 6392 #define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0) 6393 #define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4) 6394 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8) 6395 6396 #define VLV_TVIDEO_DIP_CTL(pipe) \ 6397 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \ 6398 _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C) 6399 #define VLV_TVIDEO_DIP_DATA(pipe) \ 6400 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \ 6401 _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C) 6402 #define VLV_TVIDEO_DIP_GCP(pipe) \ 6403 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \ 6404 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C) 6405 6406 /* Haswell DIP controls */ 6407 6408 #define _HSW_VIDEO_DIP_CTL_A 0x60200 6409 #define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220 6410 #define _HSW_VIDEO_DIP_VS_DATA_A 0x60260 6411 #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 6412 #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 6413 #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320 6414 #define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440 6415 #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240 6416 #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280 6417 #define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 6418 #define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300 6419 #define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344 6420 #define _HSW_VIDEO_DIP_GCP_A 0x60210 6421 6422 #define _HSW_VIDEO_DIP_CTL_B 0x61200 6423 #define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220 6424 #define _HSW_VIDEO_DIP_VS_DATA_B 0x61260 6425 #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 6426 #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 6427 #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320 6428 #define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440 6429 #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240 6430 #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280 6431 #define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 6432 #define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300 6433 #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344 6434 #define _HSW_VIDEO_DIP_GCP_B 0x61210 6435 6436 /* Icelake PPS_DATA and _ECC DIP Registers. 6437 * These are available for transcoders B,C and eDP. 6438 * Adding the _A so as to reuse the _MMIO_TRANS2 6439 * definition, with which it offsets to the right location. 6440 */ 6441 6442 #define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350 6443 #define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350 6444 #define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4 6445 #define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4 6446 6447 #define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A) 6448 #define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A) 6449 #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4) 6450 #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4) 6451 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) 6452 #define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4) 6453 #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) 6454 #define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4) 6455 #define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4) 6456 #define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4) 6457 6458 #define _HSW_STEREO_3D_CTL_A 0x70020 6459 #define S3D_ENABLE (1 << 31) 6460 #define _HSW_STEREO_3D_CTL_B 0x71020 6461 6462 #define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A) 6463 6464 #define _PCH_TRANS_HTOTAL_B 0xe1000 6465 #define _PCH_TRANS_HBLANK_B 0xe1004 6466 #define _PCH_TRANS_HSYNC_B 0xe1008 6467 #define _PCH_TRANS_VTOTAL_B 0xe100c 6468 #define _PCH_TRANS_VBLANK_B 0xe1010 6469 #define _PCH_TRANS_VSYNC_B 0xe1014 6470 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 6471 6472 #define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B) 6473 #define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B) 6474 #define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B) 6475 #define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B) 6476 #define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B) 6477 #define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B) 6478 #define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B) 6479 6480 #define _PCH_TRANSB_DATA_M1 0xe1030 6481 #define _PCH_TRANSB_DATA_N1 0xe1034 6482 #define _PCH_TRANSB_DATA_M2 0xe1038 6483 #define _PCH_TRANSB_DATA_N2 0xe103c 6484 #define _PCH_TRANSB_LINK_M1 0xe1040 6485 #define _PCH_TRANSB_LINK_N1 0xe1044 6486 #define _PCH_TRANSB_LINK_M2 0xe1048 6487 #define _PCH_TRANSB_LINK_N2 0xe104c 6488 6489 #define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1) 6490 #define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1) 6491 #define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2) 6492 #define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2) 6493 #define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1) 6494 #define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1) 6495 #define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2) 6496 #define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2) 6497 6498 #define _PCH_TRANSACONF 0xf0008 6499 #define _PCH_TRANSBCONF 0xf1008 6500 #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF) 6501 #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */ 6502 #define TRANS_ENABLE REG_BIT(31) 6503 #define TRANS_STATE_ENABLE REG_BIT(30) 6504 #define TRANS_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* ibx */ 6505 #define TRANS_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */ 6506 #define TRANS_INTERLACE_MASK REG_GENMASK(23, 21) 6507 #define TRANS_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0) 6508 #define TRANS_INTERLACE_LEGACY_VSYNC_IBX REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */ 6509 #define TRANS_INTERLACE_INTERLACED REG_FIELD_PREP(TRANS_INTERLACE_MASK, 3) 6510 #define TRANS_BPC_MASK REG_GENMASK(7, 5) /* ibx */ 6511 #define TRANS_BPC_8 REG_FIELD_PREP(TRANS_BPC_MASK, 0) 6512 #define TRANS_BPC_10 REG_FIELD_PREP(TRANS_BPC_MASK, 1) 6513 #define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2) 6514 #define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, 3) 6515 #define _TRANSA_CHICKEN1 0xf0060 6516 #define _TRANSB_CHICKEN1 0xf1060 6517 #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) 6518 #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1 << 10) 6519 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1 << 4) 6520 #define _TRANSA_CHICKEN2 0xf0064 6521 #define _TRANSB_CHICKEN2 0xf1064 6522 #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) 6523 #define TRANS_CHICKEN2_TIMING_OVERRIDE (1 << 31) 6524 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1 << 29) 6525 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3 << 27) 6526 #define TRANS_CHICKEN2_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */ 6527 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1 << 26) 6528 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1 << 25) 6529 6530 #define SOUTH_CHICKEN1 _MMIO(0xc2000) 6531 #define FDIA_PHASE_SYNC_SHIFT_OVR 19 6532 #define FDIA_PHASE_SYNC_SHIFT_EN 18 6533 #define INVERT_DDID_HPD (1 << 18) 6534 #define INVERT_DDIC_HPD (1 << 17) 6535 #define INVERT_DDIB_HPD (1 << 16) 6536 #define INVERT_DDIA_HPD (1 << 15) 6537 #define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) 6538 #define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) 6539 #define FDI_BC_BIFURCATION_SELECT (1 << 12) 6540 #define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8) 6541 #define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8) 6542 #define SBCLK_RUN_REFCLK_DIS (1 << 7) 6543 #define SPT_PWM_GRANULARITY (1 << 0) 6544 #define SOUTH_CHICKEN2 _MMIO(0xc2004) 6545 #define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13) 6546 #define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12) 6547 #define LPT_PWM_GRANULARITY (1 << 5) 6548 #define DPLS_EDP_PPS_FIX_DIS (1 << 0) 6549 6550 #define _FDI_RXA_CHICKEN 0xc200c 6551 #define _FDI_RXB_CHICKEN 0xc2010 6552 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1 << 1) 6553 #define FDI_RX_PHASE_SYNC_POINTER_EN (1 << 0) 6554 #define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) 6555 6556 #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020) 6557 #define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31) 6558 #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30) 6559 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29) 6560 #define PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15) 6561 #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14) 6562 #define CNP_PWM_CGE_GATING_DISABLE (1 << 13) 6563 #define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12) 6564 6565 /* CPU: FDI_TX */ 6566 #define _FDI_TXA_CTL 0x60100 6567 #define _FDI_TXB_CTL 0x61100 6568 #define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) 6569 #define FDI_TX_DISABLE (0 << 31) 6570 #define FDI_TX_ENABLE (1 << 31) 6571 #define FDI_LINK_TRAIN_PATTERN_1 (0 << 28) 6572 #define FDI_LINK_TRAIN_PATTERN_2 (1 << 28) 6573 #define FDI_LINK_TRAIN_PATTERN_IDLE (2 << 28) 6574 #define FDI_LINK_TRAIN_NONE (3 << 28) 6575 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0 << 25) 6576 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1 << 25) 6577 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2 << 25) 6578 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3 << 25) 6579 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22) 6580 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22) 6581 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22) 6582 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22) 6583 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. 6584 SNB has different settings. */ 6585 /* SNB A-stepping */ 6586 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) 6587 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) 6588 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) 6589 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22) 6590 /* SNB B-stepping */ 6591 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0 << 22) 6592 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a << 22) 6593 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39 << 22) 6594 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38 << 22) 6595 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f << 22) 6596 #define FDI_DP_PORT_WIDTH_SHIFT 19 6597 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT) 6598 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT) 6599 #define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18) 6600 /* Ironlake: hardwired to 1 */ 6601 #define FDI_TX_PLL_ENABLE (1 << 14) 6602 6603 /* Ivybridge has different bits for lolz */ 6604 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0 << 8) 6605 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1 << 8) 6606 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2 << 8) 6607 #define FDI_LINK_TRAIN_NONE_IVB (3 << 8) 6608 6609 /* both Tx and Rx */ 6610 #define FDI_COMPOSITE_SYNC (1 << 11) 6611 #define FDI_LINK_TRAIN_AUTO (1 << 10) 6612 #define FDI_SCRAMBLING_ENABLE (0 << 7) 6613 #define FDI_SCRAMBLING_DISABLE (1 << 7) 6614 6615 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */ 6616 #define _FDI_RXA_CTL 0xf000c 6617 #define _FDI_RXB_CTL 0xf100c 6618 #define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) 6619 #define FDI_RX_ENABLE (1 << 31) 6620 /* train, dp width same as FDI_TX */ 6621 #define FDI_FS_ERRC_ENABLE (1 << 27) 6622 #define FDI_FE_ERRC_ENABLE (1 << 26) 6623 #define FDI_RX_POLARITY_REVERSED_LPT (1 << 16) 6624 #define FDI_8BPC (0 << 16) 6625 #define FDI_10BPC (1 << 16) 6626 #define FDI_6BPC (2 << 16) 6627 #define FDI_12BPC (3 << 16) 6628 #define FDI_RX_LINK_REVERSAL_OVERRIDE (1 << 15) 6629 #define FDI_DMI_LINK_REVERSE_MASK (1 << 14) 6630 #define FDI_RX_PLL_ENABLE (1 << 13) 6631 #define FDI_FS_ERR_CORRECT_ENABLE (1 << 11) 6632 #define FDI_FE_ERR_CORRECT_ENABLE (1 << 10) 6633 #define FDI_FS_ERR_REPORT_ENABLE (1 << 9) 6634 #define FDI_FE_ERR_REPORT_ENABLE (1 << 8) 6635 #define FDI_RX_ENHANCE_FRAME_ENABLE (1 << 6) 6636 #define FDI_PCDCLK (1 << 4) 6637 /* CPT */ 6638 #define FDI_AUTO_TRAINING (1 << 10) 6639 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0 << 8) 6640 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1 << 8) 6641 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2 << 8) 6642 #define FDI_LINK_TRAIN_NORMAL_CPT (3 << 8) 6643 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3 << 8) 6644 6645 #define _FDI_RXA_MISC 0xf0010 6646 #define _FDI_RXB_MISC 0xf1010 6647 #define FDI_RX_PWRDN_LANE1_MASK (3 << 26) 6648 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x) << 26) 6649 #define FDI_RX_PWRDN_LANE0_MASK (3 << 24) 6650 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x) << 24) 6651 #define FDI_RX_TP1_TO_TP2_48 (2 << 20) 6652 #define FDI_RX_TP1_TO_TP2_64 (3 << 20) 6653 #define FDI_RX_FDI_DELAY_90 (0x90 << 0) 6654 #define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) 6655 6656 #define _FDI_RXA_TUSIZE1 0xf0030 6657 #define _FDI_RXA_TUSIZE2 0xf0038 6658 #define _FDI_RXB_TUSIZE1 0xf1030 6659 #define _FDI_RXB_TUSIZE2 0xf1038 6660 #define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) 6661 #define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) 6662 6663 /* FDI_RX interrupt register format */ 6664 #define FDI_RX_INTER_LANE_ALIGN (1 << 10) 6665 #define FDI_RX_SYMBOL_LOCK (1 << 9) /* train 2 */ 6666 #define FDI_RX_BIT_LOCK (1 << 8) /* train 1 */ 6667 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1 << 7) 6668 #define FDI_RX_FS_CODE_ERR (1 << 6) 6669 #define FDI_RX_FE_CODE_ERR (1 << 5) 6670 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1 << 4) 6671 #define FDI_RX_HDCP_LINK_FAIL (1 << 3) 6672 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1 << 2) 6673 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1 << 1) 6674 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1 << 0) 6675 6676 #define _FDI_RXA_IIR 0xf0014 6677 #define _FDI_RXA_IMR 0xf0018 6678 #define _FDI_RXB_IIR 0xf1014 6679 #define _FDI_RXB_IMR 0xf1018 6680 #define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) 6681 #define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) 6682 6683 #define FDI_PLL_CTL_1 _MMIO(0xfe000) 6684 #define FDI_PLL_CTL_2 _MMIO(0xfe004) 6685 6686 #define PCH_LVDS _MMIO(0xe1180) 6687 #define LVDS_DETECTED (1 << 1) 6688 6689 #define _PCH_DP_B 0xe4100 6690 #define PCH_DP_B _MMIO(_PCH_DP_B) 6691 #define _PCH_DPB_AUX_CH_CTL 0xe4110 6692 #define _PCH_DPB_AUX_CH_DATA1 0xe4114 6693 #define _PCH_DPB_AUX_CH_DATA2 0xe4118 6694 #define _PCH_DPB_AUX_CH_DATA3 0xe411c 6695 #define _PCH_DPB_AUX_CH_DATA4 0xe4120 6696 #define _PCH_DPB_AUX_CH_DATA5 0xe4124 6697 6698 #define _PCH_DP_C 0xe4200 6699 #define PCH_DP_C _MMIO(_PCH_DP_C) 6700 #define _PCH_DPC_AUX_CH_CTL 0xe4210 6701 #define _PCH_DPC_AUX_CH_DATA1 0xe4214 6702 #define _PCH_DPC_AUX_CH_DATA2 0xe4218 6703 #define _PCH_DPC_AUX_CH_DATA3 0xe421c 6704 #define _PCH_DPC_AUX_CH_DATA4 0xe4220 6705 #define _PCH_DPC_AUX_CH_DATA5 0xe4224 6706 6707 #define _PCH_DP_D 0xe4300 6708 #define PCH_DP_D _MMIO(_PCH_DP_D) 6709 #define _PCH_DPD_AUX_CH_CTL 0xe4310 6710 #define _PCH_DPD_AUX_CH_DATA1 0xe4314 6711 #define _PCH_DPD_AUX_CH_DATA2 0xe4318 6712 #define _PCH_DPD_AUX_CH_DATA3 0xe431c 6713 #define _PCH_DPD_AUX_CH_DATA4 0xe4320 6714 #define _PCH_DPD_AUX_CH_DATA5 0xe4324 6715 6716 #define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL) 6717 #define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ 6718 6719 /* CPT */ 6720 #define _TRANS_DP_CTL_A 0xe0300 6721 #define _TRANS_DP_CTL_B 0xe1300 6722 #define _TRANS_DP_CTL_C 0xe2300 6723 #define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B) 6724 #define TRANS_DP_OUTPUT_ENABLE REG_BIT(31) 6725 #define TRANS_DP_PORT_SEL_MASK REG_GENMASK(30, 29) 6726 #define TRANS_DP_PORT_SEL_NONE REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, 3) 6727 #define TRANS_DP_PORT_SEL(port) REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B) 6728 #define TRANS_DP_AUDIO_ONLY REG_BIT(26) 6729 #define TRANS_DP_ENH_FRAMING REG_BIT(18) 6730 #define TRANS_DP_BPC_MASK REG_GENMASK(10, 9) 6731 #define TRANS_DP_BPC_8 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0) 6732 #define TRANS_DP_BPC_10 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 1) 6733 #define TRANS_DP_BPC_6 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 2) 6734 #define TRANS_DP_BPC_12 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 3) 6735 #define TRANS_DP_VSYNC_ACTIVE_HIGH REG_BIT(4) 6736 #define TRANS_DP_HSYNC_ACTIVE_HIGH REG_BIT(3) 6737 6738 #define _TRANS_DP2_CTL_A 0x600a0 6739 #define _TRANS_DP2_CTL_B 0x610a0 6740 #define _TRANS_DP2_CTL_C 0x620a0 6741 #define _TRANS_DP2_CTL_D 0x630a0 6742 #define TRANS_DP2_CTL(trans) _MMIO_TRANS(trans, _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B) 6743 #define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31) 6744 #define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30) 6745 #define TRANS_DP2_DEBUG_ENABLE REG_BIT(23) 6746 6747 #define _TRANS_DP2_VFREQHIGH_A 0x600a4 6748 #define _TRANS_DP2_VFREQHIGH_B 0x610a4 6749 #define _TRANS_DP2_VFREQHIGH_C 0x620a4 6750 #define _TRANS_DP2_VFREQHIGH_D 0x630a4 6751 #define TRANS_DP2_VFREQHIGH(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQHIGH_A, _TRANS_DP2_VFREQHIGH_B) 6752 #define TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK REG_GENMASK(31, 8) 6753 #define TRANS_DP2_VFREQ_PIXEL_CLOCK(clk_hz) REG_FIELD_PREP(TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK, (clk_hz)) 6754 6755 #define _TRANS_DP2_VFREQLOW_A 0x600a8 6756 #define _TRANS_DP2_VFREQLOW_B 0x610a8 6757 #define _TRANS_DP2_VFREQLOW_C 0x620a8 6758 #define _TRANS_DP2_VFREQLOW_D 0x630a8 6759 #define TRANS_DP2_VFREQLOW(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQLOW_A, _TRANS_DP2_VFREQLOW_B) 6760 6761 /* SNB eDP training params */ 6762 /* SNB A-stepping */ 6763 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) 6764 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) 6765 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) 6766 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22) 6767 /* SNB B-stepping */ 6768 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22) 6769 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22) 6770 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22) 6771 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22) 6772 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22) 6773 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22) 6774 6775 /* IVB */ 6776 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22) 6777 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22) 6778 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22) 6779 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22) 6780 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22) 6781 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22) 6782 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22) 6783 6784 /* legacy values */ 6785 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22) 6786 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22) 6787 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22) 6788 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22) 6789 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22) 6790 6791 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22) 6792 6793 #define VLV_PMWGICZ _MMIO(0x1300a4) 6794 6795 #define HSW_EDRAM_CAP _MMIO(0x120010) 6796 #define EDRAM_ENABLED 0x1 6797 #define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf) 6798 #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7) 6799 #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3) 6800 6801 #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C) 6802 #define PIXEL_OVERLAP_CNT_MASK (3 << 30) 6803 #define PIXEL_OVERLAP_CNT_SHIFT 30 6804 6805 #define GEN6_PCODE_MAILBOX _MMIO(0x138124) 6806 #define GEN6_PCODE_READY (1 << 31) 6807 #define GEN6_PCODE_ERROR_MASK 0xFF 6808 #define GEN6_PCODE_SUCCESS 0x0 6809 #define GEN6_PCODE_ILLEGAL_CMD 0x1 6810 #define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2 6811 #define GEN6_PCODE_TIMEOUT 0x3 6812 #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF 6813 #define GEN7_PCODE_TIMEOUT 0x2 6814 #define GEN7_PCODE_ILLEGAL_DATA 0x3 6815 #define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4 6816 #define GEN11_PCODE_LOCKED 0x6 6817 #define GEN11_PCODE_REJECTED 0x11 6818 #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10 6819 #define GEN6_PCODE_WRITE_RC6VIDS 0x4 6820 #define GEN6_PCODE_READ_RC6VIDS 0x5 6821 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) 6822 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) 6823 #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18 6824 #define GEN9_PCODE_READ_MEM_LATENCY 0x6 6825 #define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF 6826 #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8 6827 #define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16 6828 #define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24 6829 #define SKL_PCODE_LOAD_HDCP_KEYS 0x5 6830 #define SKL_PCODE_CDCLK_CONTROL 0x7 6831 #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3 6832 #define SKL_CDCLK_READY_FOR_CHANGE 0x1 6833 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 6834 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 6835 #define GEN6_READ_OC_PARAMS 0xc 6836 #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd 6837 #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8) 6838 #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8)) 6839 #define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO ((0) | (0x2 << 8)) 6840 #define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe 6841 #define ICL_PCODE_POINTS_RESTRICTED 0x0 6842 #define ICL_PCODE_POINTS_RESTRICTED_MASK 0xf 6843 #define ADLS_PSF_PT_SHIFT 8 6844 #define ADLS_QGV_PT_MASK REG_GENMASK(7, 0) 6845 #define ADLS_PSF_PT_MASK REG_GENMASK(10, 8) 6846 #define GEN6_PCODE_READ_D_COMP 0x10 6847 #define GEN6_PCODE_WRITE_D_COMP 0x11 6848 #define ICL_PCODE_EXIT_TCCOLD 0x12 6849 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17 6850 #define DISPLAY_IPS_CONTROL 0x19 6851 #define TGL_PCODE_TCCOLD 0x26 6852 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0) 6853 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0 6854 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0) 6855 /* See also IPS_CTL */ 6856 #define IPS_PCODE_CONTROL (1 << 30) 6857 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A 6858 #define GEN9_PCODE_SAGV_CONTROL 0x21 6859 #define GEN9_SAGV_DISABLE 0x0 6860 #define GEN9_SAGV_IS_DISABLED 0x1 6861 #define GEN9_SAGV_ENABLE 0x3 6862 #define DG1_PCODE_STATUS 0x7E 6863 #define DG1_UNCORE_GET_INIT_STATUS 0x0 6864 #define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1 6865 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23 6866 #define GEN6_PCODE_DATA _MMIO(0x138128) 6867 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 6868 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 6869 #define GEN6_PCODE_DATA1 _MMIO(0x13812C) 6870 6871 /* IVYBRIDGE DPF */ 6872 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */ 6873 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14) 6874 #define GEN7_PARITY_ERROR_VALID (1 << 13) 6875 #define GEN7_L3CDERRST1_BANK_MASK (3 << 11) 6876 #define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8) 6877 #define GEN7_PARITY_ERROR_ROW(reg) \ 6878 (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14) 6879 #define GEN7_PARITY_ERROR_BANK(reg) \ 6880 (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11) 6881 #define GEN7_PARITY_ERROR_SUBBANK(reg) \ 6882 (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) 6883 #define GEN7_L3CDERRST1_ENABLE (1 << 7) 6884 6885 /* Audio */ 6886 #define G4X_AUD_VID_DID _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020) 6887 #define INTEL_AUDIO_DEVCL 0x808629FB 6888 #define INTEL_AUDIO_DEVBLC 0x80862801 6889 #define INTEL_AUDIO_DEVCTG 0x80862802 6890 6891 #define G4X_AUD_CNTL_ST _MMIO(0x620B4) 6892 #define G4X_ELDV_DEVCL_DEVBLC (1 << 13) 6893 #define G4X_ELDV_DEVCTG (1 << 14) 6894 #define G4X_ELD_ADDR_MASK (0xf << 5) 6895 #define G4X_ELD_ACK (1 << 4) 6896 #define G4X_HDMIW_HDMIEDID _MMIO(0x6210C) 6897 6898 #define _IBX_HDMIW_HDMIEDID_A 0xE2050 6899 #define _IBX_HDMIW_HDMIEDID_B 0xE2150 6900 #define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \ 6901 _IBX_HDMIW_HDMIEDID_B) 6902 #define _IBX_AUD_CNTL_ST_A 0xE20B4 6903 #define _IBX_AUD_CNTL_ST_B 0xE21B4 6904 #define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \ 6905 _IBX_AUD_CNTL_ST_B) 6906 #define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10) 6907 #define IBX_ELD_ADDRESS_MASK (0x1f << 5) 6908 #define IBX_ELD_ACK (1 << 4) 6909 #define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0) 6910 #define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4)) 6911 #define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4)) 6912 6913 #define _CPT_HDMIW_HDMIEDID_A 0xE5050 6914 #define _CPT_HDMIW_HDMIEDID_B 0xE5150 6915 #define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B) 6916 #define _CPT_AUD_CNTL_ST_A 0xE50B4 6917 #define _CPT_AUD_CNTL_ST_B 0xE51B4 6918 #define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B) 6919 #define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0) 6920 6921 #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050) 6922 #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150) 6923 #define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B) 6924 #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4) 6925 #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4) 6926 #define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B) 6927 #define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0) 6928 6929 /* These are the 4 32-bit write offset registers for each stream 6930 * output buffer. It determines the offset from the 6931 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. 6932 */ 6933 #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4) 6934 6935 #define _IBX_AUD_CONFIG_A 0xe2000 6936 #define _IBX_AUD_CONFIG_B 0xe2100 6937 #define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B) 6938 #define _CPT_AUD_CONFIG_A 0xe5000 6939 #define _CPT_AUD_CONFIG_B 0xe5100 6940 #define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B) 6941 #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000) 6942 #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100) 6943 #define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B) 6944 6945 #define AUD_CONFIG_N_VALUE_INDEX (1 << 29) 6946 #define AUD_CONFIG_N_PROG_ENABLE (1 << 28) 6947 #define AUD_CONFIG_UPPER_N_SHIFT 20 6948 #define AUD_CONFIG_UPPER_N_MASK (0xff << 20) 6949 #define AUD_CONFIG_LOWER_N_SHIFT 4 6950 #define AUD_CONFIG_LOWER_N_MASK (0xfff << 4) 6951 #define AUD_CONFIG_N_MASK (AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK) 6952 #define AUD_CONFIG_N(n) \ 6953 (((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) | \ 6954 (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT)) 6955 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 6956 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16) 6957 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16) 6958 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16) 6959 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16) 6960 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16) 6961 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16) 6962 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16) 6963 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16) 6964 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16) 6965 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16) 6966 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16) 6967 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 (10 << 16) 6968 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 (11 << 16) 6969 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 (12 << 16) 6970 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 (13 << 16) 6971 #define AUD_CONFIG_DISABLE_NCTS (1 << 3) 6972 6973 /* HSW Audio */ 6974 #define _HSW_AUD_CONFIG_A 0x65000 6975 #define _HSW_AUD_CONFIG_B 0x65100 6976 #define HSW_AUD_CFG(trans) _MMIO_TRANS(trans, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B) 6977 6978 #define _HSW_AUD_MISC_CTRL_A 0x65010 6979 #define _HSW_AUD_MISC_CTRL_B 0x65110 6980 #define HSW_AUD_MISC_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B) 6981 6982 #define _HSW_AUD_M_CTS_ENABLE_A 0x65028 6983 #define _HSW_AUD_M_CTS_ENABLE_B 0x65128 6984 #define HSW_AUD_M_CTS_ENABLE(trans) _MMIO_TRANS(trans, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B) 6985 #define AUD_M_CTS_M_VALUE_INDEX (1 << 21) 6986 #define AUD_M_CTS_M_PROG_ENABLE (1 << 20) 6987 #define AUD_CONFIG_M_MASK 0xfffff 6988 6989 #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 6990 #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 6991 #define HSW_AUD_DIP_ELD_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B) 6992 6993 /* Audio Digital Converter */ 6994 #define _HSW_AUD_DIG_CNVT_1 0x65080 6995 #define _HSW_AUD_DIG_CNVT_2 0x65180 6996 #define AUD_DIG_CNVT(trans) _MMIO_TRANS(trans, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2) 6997 #define DIP_PORT_SEL_MASK 0x3 6998 6999 #define _HSW_AUD_EDID_DATA_A 0x65050 7000 #define _HSW_AUD_EDID_DATA_B 0x65150 7001 #define HSW_AUD_EDID_DATA(trans) _MMIO_TRANS(trans, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B) 7002 7003 #define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c) 7004 #define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0) 7005 #define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4)) 7006 #define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4)) 7007 #define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4)) 7008 #define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4)) 7009 7010 #define _AUD_TCA_DP_2DOT0_CTRL 0x650bc 7011 #define _AUD_TCB_DP_2DOT0_CTRL 0x651bc 7012 #define AUD_DP_2DOT0_CTRL(trans) _MMIO_TRANS(trans, _AUD_TCA_DP_2DOT0_CTRL, _AUD_TCB_DP_2DOT0_CTRL) 7013 #define AUD_ENABLE_SDP_SPLIT REG_BIT(31) 7014 7015 #define HSW_AUD_CHICKENBIT _MMIO(0x65f10) 7016 #define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15) 7017 7018 #define AUD_FREQ_CNTRL _MMIO(0x65900) 7019 #define AUD_PIN_BUF_CTL _MMIO(0x48414) 7020 #define AUD_PIN_BUF_ENABLE REG_BIT(31) 7021 7022 #define AUD_TS_CDCLK_M _MMIO(0x65ea0) 7023 #define AUD_TS_CDCLK_M_EN REG_BIT(31) 7024 #define AUD_TS_CDCLK_N _MMIO(0x65ea4) 7025 7026 /* Display Audio Config Reg */ 7027 #define AUD_CONFIG_BE _MMIO(0x65ef0) 7028 #define HBLANK_EARLY_ENABLE_ICL(pipe) (0x1 << (20 - (pipe))) 7029 #define HBLANK_EARLY_ENABLE_TGL(pipe) (0x1 << (24 + (pipe))) 7030 #define HBLANK_START_COUNT_MASK(pipe) (0x7 << (3 + ((pipe) * 6))) 7031 #define HBLANK_START_COUNT(pipe, val) (((val) & 0x7) << (3 + ((pipe)) * 6)) 7032 #define NUMBER_SAMPLES_PER_LINE_MASK(pipe) (0x3 << ((pipe) * 6)) 7033 #define NUMBER_SAMPLES_PER_LINE(pipe, val) (((val) & 0x3) << ((pipe) * 6)) 7034 7035 #define HBLANK_START_COUNT_8 0 7036 #define HBLANK_START_COUNT_16 1 7037 #define HBLANK_START_COUNT_32 2 7038 #define HBLANK_START_COUNT_64 3 7039 #define HBLANK_START_COUNT_96 4 7040 #define HBLANK_START_COUNT_128 5 7041 7042 /* 7043 * HSW - ICL power wells 7044 * 7045 * Platforms have up to 3 power well control register sets, each set 7046 * controlling up to 16 power wells via a request/status HW flag tuple: 7047 * - main (HSW_PWR_WELL_CTL[1-4]) 7048 * - AUX (ICL_PWR_WELL_CTL_AUX[1-4]) 7049 * - DDI (ICL_PWR_WELL_CTL_DDI[1-4]) 7050 * Each control register set consists of up to 4 registers used by different 7051 * sources that can request a power well to be enabled: 7052 * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1) 7053 * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2) 7054 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set) 7055 * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4) 7056 */ 7057 #define HSW_PWR_WELL_CTL1 _MMIO(0x45400) 7058 #define HSW_PWR_WELL_CTL2 _MMIO(0x45404) 7059 #define HSW_PWR_WELL_CTL3 _MMIO(0x45408) 7060 #define HSW_PWR_WELL_CTL4 _MMIO(0x4540C) 7061 #define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2)) 7062 #define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2)) 7063 7064 /* HSW/BDW power well */ 7065 #define HSW_PW_CTL_IDX_GLOBAL 15 7066 7067 /* SKL/BXT/GLK power wells */ 7068 #define SKL_PW_CTL_IDX_PW_2 15 7069 #define SKL_PW_CTL_IDX_PW_1 14 7070 #define GLK_PW_CTL_IDX_AUX_C 10 7071 #define GLK_PW_CTL_IDX_AUX_B 9 7072 #define GLK_PW_CTL_IDX_AUX_A 8 7073 #define SKL_PW_CTL_IDX_DDI_D 4 7074 #define SKL_PW_CTL_IDX_DDI_C 3 7075 #define SKL_PW_CTL_IDX_DDI_B 2 7076 #define SKL_PW_CTL_IDX_DDI_A_E 1 7077 #define GLK_PW_CTL_IDX_DDI_A 1 7078 #define SKL_PW_CTL_IDX_MISC_IO 0 7079 7080 /* ICL/TGL - power wells */ 7081 #define TGL_PW_CTL_IDX_PW_5 4 7082 #define ICL_PW_CTL_IDX_PW_4 3 7083 #define ICL_PW_CTL_IDX_PW_3 2 7084 #define ICL_PW_CTL_IDX_PW_2 1 7085 #define ICL_PW_CTL_IDX_PW_1 0 7086 7087 /* XE_LPD - power wells */ 7088 #define XELPD_PW_CTL_IDX_PW_D 8 7089 #define XELPD_PW_CTL_IDX_PW_C 7 7090 #define XELPD_PW_CTL_IDX_PW_B 6 7091 #define XELPD_PW_CTL_IDX_PW_A 5 7092 7093 #define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440) 7094 #define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444) 7095 #define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C) 7096 #define TGL_PW_CTL_IDX_AUX_TBT6 14 7097 #define TGL_PW_CTL_IDX_AUX_TBT5 13 7098 #define TGL_PW_CTL_IDX_AUX_TBT4 12 7099 #define ICL_PW_CTL_IDX_AUX_TBT4 11 7100 #define TGL_PW_CTL_IDX_AUX_TBT3 11 7101 #define ICL_PW_CTL_IDX_AUX_TBT3 10 7102 #define TGL_PW_CTL_IDX_AUX_TBT2 10 7103 #define ICL_PW_CTL_IDX_AUX_TBT2 9 7104 #define TGL_PW_CTL_IDX_AUX_TBT1 9 7105 #define ICL_PW_CTL_IDX_AUX_TBT1 8 7106 #define TGL_PW_CTL_IDX_AUX_TC6 8 7107 #define XELPD_PW_CTL_IDX_AUX_E 8 7108 #define TGL_PW_CTL_IDX_AUX_TC5 7 7109 #define XELPD_PW_CTL_IDX_AUX_D 7 7110 #define TGL_PW_CTL_IDX_AUX_TC4 6 7111 #define ICL_PW_CTL_IDX_AUX_F 5 7112 #define TGL_PW_CTL_IDX_AUX_TC3 5 7113 #define ICL_PW_CTL_IDX_AUX_E 4 7114 #define TGL_PW_CTL_IDX_AUX_TC2 4 7115 #define ICL_PW_CTL_IDX_AUX_D 3 7116 #define TGL_PW_CTL_IDX_AUX_TC1 3 7117 #define ICL_PW_CTL_IDX_AUX_C 2 7118 #define ICL_PW_CTL_IDX_AUX_B 1 7119 #define ICL_PW_CTL_IDX_AUX_A 0 7120 7121 #define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450) 7122 #define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454) 7123 #define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C) 7124 #define XELPD_PW_CTL_IDX_DDI_E 8 7125 #define TGL_PW_CTL_IDX_DDI_TC6 8 7126 #define XELPD_PW_CTL_IDX_DDI_D 7 7127 #define TGL_PW_CTL_IDX_DDI_TC5 7 7128 #define TGL_PW_CTL_IDX_DDI_TC4 6 7129 #define ICL_PW_CTL_IDX_DDI_F 5 7130 #define TGL_PW_CTL_IDX_DDI_TC3 5 7131 #define ICL_PW_CTL_IDX_DDI_E 4 7132 #define TGL_PW_CTL_IDX_DDI_TC2 4 7133 #define ICL_PW_CTL_IDX_DDI_D 3 7134 #define TGL_PW_CTL_IDX_DDI_TC1 3 7135 #define ICL_PW_CTL_IDX_DDI_C 2 7136 #define ICL_PW_CTL_IDX_DDI_B 1 7137 #define ICL_PW_CTL_IDX_DDI_A 0 7138 7139 /* HSW - power well misc debug registers */ 7140 #define HSW_PWR_WELL_CTL5 _MMIO(0x45410) 7141 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31) 7142 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20) 7143 #define HSW_PWR_WELL_FORCE_ON (1 << 19) 7144 #define HSW_PWR_WELL_CTL6 _MMIO(0x45414) 7145 7146 /* SKL Fuse Status */ 7147 enum skl_power_gate { 7148 SKL_PG0, 7149 SKL_PG1, 7150 SKL_PG2, 7151 ICL_PG3, 7152 ICL_PG4, 7153 }; 7154 7155 #define SKL_FUSE_STATUS _MMIO(0x42000) 7156 #define SKL_FUSE_DOWNLOAD_STATUS (1 << 31) 7157 /* 7158 * PG0 is HW controlled, so doesn't have a corresponding power well control knob 7159 * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2 7160 */ 7161 #define SKL_PW_CTL_IDX_TO_PG(pw_idx) \ 7162 ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1) 7163 /* 7164 * PG0 is HW controlled, so doesn't have a corresponding power well control knob 7165 * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4 7166 */ 7167 #define ICL_PW_CTL_IDX_TO_PG(pw_idx) \ 7168 ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1) 7169 #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg))) 7170 7171 #define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A) 7172 #define _ICL_AUX_ANAOVRD1_A 0x162398 7173 #define _ICL_AUX_ANAOVRD1_B 0x6C398 7174 #define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \ 7175 _ICL_AUX_ANAOVRD1_A, \ 7176 _ICL_AUX_ANAOVRD1_B)) 7177 #define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7) 7178 #define ICL_AUX_ANAOVRD1_ENABLE (1 << 0) 7179 7180 /* HDCP Key Registers */ 7181 #define HDCP_KEY_CONF _MMIO(0x66c00) 7182 #define HDCP_AKSV_SEND_TRIGGER BIT(31) 7183 #define HDCP_CLEAR_KEYS_TRIGGER BIT(30) 7184 #define HDCP_KEY_LOAD_TRIGGER BIT(8) 7185 #define HDCP_KEY_STATUS _MMIO(0x66c04) 7186 #define HDCP_FUSE_IN_PROGRESS BIT(7) 7187 #define HDCP_FUSE_ERROR BIT(6) 7188 #define HDCP_FUSE_DONE BIT(5) 7189 #define HDCP_KEY_LOAD_STATUS BIT(1) 7190 #define HDCP_KEY_LOAD_DONE BIT(0) 7191 #define HDCP_AKSV_LO _MMIO(0x66c10) 7192 #define HDCP_AKSV_HI _MMIO(0x66c14) 7193 7194 /* HDCP Repeater Registers */ 7195 #define HDCP_REP_CTL _MMIO(0x66d00) 7196 #define HDCP_TRANSA_REP_PRESENT BIT(31) 7197 #define HDCP_TRANSB_REP_PRESENT BIT(30) 7198 #define HDCP_TRANSC_REP_PRESENT BIT(29) 7199 #define HDCP_TRANSD_REP_PRESENT BIT(28) 7200 #define HDCP_DDIB_REP_PRESENT BIT(30) 7201 #define HDCP_DDIA_REP_PRESENT BIT(29) 7202 #define HDCP_DDIC_REP_PRESENT BIT(28) 7203 #define HDCP_DDID_REP_PRESENT BIT(27) 7204 #define HDCP_DDIF_REP_PRESENT BIT(26) 7205 #define HDCP_DDIE_REP_PRESENT BIT(25) 7206 #define HDCP_TRANSA_SHA1_M0 (1 << 20) 7207 #define HDCP_TRANSB_SHA1_M0 (2 << 20) 7208 #define HDCP_TRANSC_SHA1_M0 (3 << 20) 7209 #define HDCP_TRANSD_SHA1_M0 (4 << 20) 7210 #define HDCP_DDIB_SHA1_M0 (1 << 20) 7211 #define HDCP_DDIA_SHA1_M0 (2 << 20) 7212 #define HDCP_DDIC_SHA1_M0 (3 << 20) 7213 #define HDCP_DDID_SHA1_M0 (4 << 20) 7214 #define HDCP_DDIF_SHA1_M0 (5 << 20) 7215 #define HDCP_DDIE_SHA1_M0 (6 << 20) /* Bspec says 5? */ 7216 #define HDCP_SHA1_BUSY BIT(16) 7217 #define HDCP_SHA1_READY BIT(17) 7218 #define HDCP_SHA1_COMPLETE BIT(18) 7219 #define HDCP_SHA1_V_MATCH BIT(19) 7220 #define HDCP_SHA1_TEXT_32 (1 << 1) 7221 #define HDCP_SHA1_COMPLETE_HASH (2 << 1) 7222 #define HDCP_SHA1_TEXT_24 (4 << 1) 7223 #define HDCP_SHA1_TEXT_16 (5 << 1) 7224 #define HDCP_SHA1_TEXT_8 (6 << 1) 7225 #define HDCP_SHA1_TEXT_0 (7 << 1) 7226 #define HDCP_SHA_V_PRIME_H0 _MMIO(0x66d04) 7227 #define HDCP_SHA_V_PRIME_H1 _MMIO(0x66d08) 7228 #define HDCP_SHA_V_PRIME_H2 _MMIO(0x66d0C) 7229 #define HDCP_SHA_V_PRIME_H3 _MMIO(0x66d10) 7230 #define HDCP_SHA_V_PRIME_H4 _MMIO(0x66d14) 7231 #define HDCP_SHA_V_PRIME(h) _MMIO((0x66d04 + (h) * 4)) 7232 #define HDCP_SHA_TEXT _MMIO(0x66d18) 7233 7234 /* HDCP Auth Registers */ 7235 #define _PORTA_HDCP_AUTHENC 0x66800 7236 #define _PORTB_HDCP_AUTHENC 0x66500 7237 #define _PORTC_HDCP_AUTHENC 0x66600 7238 #define _PORTD_HDCP_AUTHENC 0x66700 7239 #define _PORTE_HDCP_AUTHENC 0x66A00 7240 #define _PORTF_HDCP_AUTHENC 0x66900 7241 #define _PORT_HDCP_AUTHENC(port, x) _MMIO(_PICK(port, \ 7242 _PORTA_HDCP_AUTHENC, \ 7243 _PORTB_HDCP_AUTHENC, \ 7244 _PORTC_HDCP_AUTHENC, \ 7245 _PORTD_HDCP_AUTHENC, \ 7246 _PORTE_HDCP_AUTHENC, \ 7247 _PORTF_HDCP_AUTHENC) + (x)) 7248 #define PORT_HDCP_CONF(port) _PORT_HDCP_AUTHENC(port, 0x0) 7249 #define _TRANSA_HDCP_CONF 0x66400 7250 #define _TRANSB_HDCP_CONF 0x66500 7251 #define TRANS_HDCP_CONF(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_CONF, \ 7252 _TRANSB_HDCP_CONF) 7253 #define HDCP_CONF(dev_priv, trans, port) \ 7254 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7255 TRANS_HDCP_CONF(trans) : \ 7256 PORT_HDCP_CONF(port)) 7257 7258 #define HDCP_CONF_CAPTURE_AN BIT(0) 7259 #define HDCP_CONF_AUTH_AND_ENC (BIT(1) | BIT(0)) 7260 #define PORT_HDCP_ANINIT(port) _PORT_HDCP_AUTHENC(port, 0x4) 7261 #define _TRANSA_HDCP_ANINIT 0x66404 7262 #define _TRANSB_HDCP_ANINIT 0x66504 7263 #define TRANS_HDCP_ANINIT(trans) _MMIO_TRANS(trans, \ 7264 _TRANSA_HDCP_ANINIT, \ 7265 _TRANSB_HDCP_ANINIT) 7266 #define HDCP_ANINIT(dev_priv, trans, port) \ 7267 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7268 TRANS_HDCP_ANINIT(trans) : \ 7269 PORT_HDCP_ANINIT(port)) 7270 7271 #define PORT_HDCP_ANLO(port) _PORT_HDCP_AUTHENC(port, 0x8) 7272 #define _TRANSA_HDCP_ANLO 0x66408 7273 #define _TRANSB_HDCP_ANLO 0x66508 7274 #define TRANS_HDCP_ANLO(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANLO, \ 7275 _TRANSB_HDCP_ANLO) 7276 #define HDCP_ANLO(dev_priv, trans, port) \ 7277 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7278 TRANS_HDCP_ANLO(trans) : \ 7279 PORT_HDCP_ANLO(port)) 7280 7281 #define PORT_HDCP_ANHI(port) _PORT_HDCP_AUTHENC(port, 0xC) 7282 #define _TRANSA_HDCP_ANHI 0x6640C 7283 #define _TRANSB_HDCP_ANHI 0x6650C 7284 #define TRANS_HDCP_ANHI(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANHI, \ 7285 _TRANSB_HDCP_ANHI) 7286 #define HDCP_ANHI(dev_priv, trans, port) \ 7287 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7288 TRANS_HDCP_ANHI(trans) : \ 7289 PORT_HDCP_ANHI(port)) 7290 7291 #define PORT_HDCP_BKSVLO(port) _PORT_HDCP_AUTHENC(port, 0x10) 7292 #define _TRANSA_HDCP_BKSVLO 0x66410 7293 #define _TRANSB_HDCP_BKSVLO 0x66510 7294 #define TRANS_HDCP_BKSVLO(trans) _MMIO_TRANS(trans, \ 7295 _TRANSA_HDCP_BKSVLO, \ 7296 _TRANSB_HDCP_BKSVLO) 7297 #define HDCP_BKSVLO(dev_priv, trans, port) \ 7298 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7299 TRANS_HDCP_BKSVLO(trans) : \ 7300 PORT_HDCP_BKSVLO(port)) 7301 7302 #define PORT_HDCP_BKSVHI(port) _PORT_HDCP_AUTHENC(port, 0x14) 7303 #define _TRANSA_HDCP_BKSVHI 0x66414 7304 #define _TRANSB_HDCP_BKSVHI 0x66514 7305 #define TRANS_HDCP_BKSVHI(trans) _MMIO_TRANS(trans, \ 7306 _TRANSA_HDCP_BKSVHI, \ 7307 _TRANSB_HDCP_BKSVHI) 7308 #define HDCP_BKSVHI(dev_priv, trans, port) \ 7309 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7310 TRANS_HDCP_BKSVHI(trans) : \ 7311 PORT_HDCP_BKSVHI(port)) 7312 7313 #define PORT_HDCP_RPRIME(port) _PORT_HDCP_AUTHENC(port, 0x18) 7314 #define _TRANSA_HDCP_RPRIME 0x66418 7315 #define _TRANSB_HDCP_RPRIME 0x66518 7316 #define TRANS_HDCP_RPRIME(trans) _MMIO_TRANS(trans, \ 7317 _TRANSA_HDCP_RPRIME, \ 7318 _TRANSB_HDCP_RPRIME) 7319 #define HDCP_RPRIME(dev_priv, trans, port) \ 7320 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7321 TRANS_HDCP_RPRIME(trans) : \ 7322 PORT_HDCP_RPRIME(port)) 7323 7324 #define PORT_HDCP_STATUS(port) _PORT_HDCP_AUTHENC(port, 0x1C) 7325 #define _TRANSA_HDCP_STATUS 0x6641C 7326 #define _TRANSB_HDCP_STATUS 0x6651C 7327 #define TRANS_HDCP_STATUS(trans) _MMIO_TRANS(trans, \ 7328 _TRANSA_HDCP_STATUS, \ 7329 _TRANSB_HDCP_STATUS) 7330 #define HDCP_STATUS(dev_priv, trans, port) \ 7331 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7332 TRANS_HDCP_STATUS(trans) : \ 7333 PORT_HDCP_STATUS(port)) 7334 7335 #define HDCP_STATUS_STREAM_A_ENC BIT(31) 7336 #define HDCP_STATUS_STREAM_B_ENC BIT(30) 7337 #define HDCP_STATUS_STREAM_C_ENC BIT(29) 7338 #define HDCP_STATUS_STREAM_D_ENC BIT(28) 7339 #define HDCP_STATUS_AUTH BIT(21) 7340 #define HDCP_STATUS_ENC BIT(20) 7341 #define HDCP_STATUS_RI_MATCH BIT(19) 7342 #define HDCP_STATUS_R0_READY BIT(18) 7343 #define HDCP_STATUS_AN_READY BIT(17) 7344 #define HDCP_STATUS_CIPHER BIT(16) 7345 #define HDCP_STATUS_FRAME_CNT(x) (((x) >> 8) & 0xff) 7346 7347 /* HDCP2.2 Registers */ 7348 #define _PORTA_HDCP2_BASE 0x66800 7349 #define _PORTB_HDCP2_BASE 0x66500 7350 #define _PORTC_HDCP2_BASE 0x66600 7351 #define _PORTD_HDCP2_BASE 0x66700 7352 #define _PORTE_HDCP2_BASE 0x66A00 7353 #define _PORTF_HDCP2_BASE 0x66900 7354 #define _PORT_HDCP2_BASE(port, x) _MMIO(_PICK((port), \ 7355 _PORTA_HDCP2_BASE, \ 7356 _PORTB_HDCP2_BASE, \ 7357 _PORTC_HDCP2_BASE, \ 7358 _PORTD_HDCP2_BASE, \ 7359 _PORTE_HDCP2_BASE, \ 7360 _PORTF_HDCP2_BASE) + (x)) 7361 7362 #define PORT_HDCP2_AUTH(port) _PORT_HDCP2_BASE(port, 0x98) 7363 #define _TRANSA_HDCP2_AUTH 0x66498 7364 #define _TRANSB_HDCP2_AUTH 0x66598 7365 #define TRANS_HDCP2_AUTH(trans) _MMIO_TRANS(trans, _TRANSA_HDCP2_AUTH, \ 7366 _TRANSB_HDCP2_AUTH) 7367 #define AUTH_LINK_AUTHENTICATED BIT(31) 7368 #define AUTH_LINK_TYPE BIT(30) 7369 #define AUTH_FORCE_CLR_INPUTCTR BIT(19) 7370 #define AUTH_CLR_KEYS BIT(18) 7371 #define HDCP2_AUTH(dev_priv, trans, port) \ 7372 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7373 TRANS_HDCP2_AUTH(trans) : \ 7374 PORT_HDCP2_AUTH(port)) 7375 7376 #define PORT_HDCP2_CTL(port) _PORT_HDCP2_BASE(port, 0xB0) 7377 #define _TRANSA_HDCP2_CTL 0x664B0 7378 #define _TRANSB_HDCP2_CTL 0x665B0 7379 #define TRANS_HDCP2_CTL(trans) _MMIO_TRANS(trans, _TRANSA_HDCP2_CTL, \ 7380 _TRANSB_HDCP2_CTL) 7381 #define CTL_LINK_ENCRYPTION_REQ BIT(31) 7382 #define HDCP2_CTL(dev_priv, trans, port) \ 7383 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7384 TRANS_HDCP2_CTL(trans) : \ 7385 PORT_HDCP2_CTL(port)) 7386 7387 #define PORT_HDCP2_STATUS(port) _PORT_HDCP2_BASE(port, 0xB4) 7388 #define _TRANSA_HDCP2_STATUS 0x664B4 7389 #define _TRANSB_HDCP2_STATUS 0x665B4 7390 #define TRANS_HDCP2_STATUS(trans) _MMIO_TRANS(trans, \ 7391 _TRANSA_HDCP2_STATUS, \ 7392 _TRANSB_HDCP2_STATUS) 7393 #define LINK_TYPE_STATUS BIT(22) 7394 #define LINK_AUTH_STATUS BIT(21) 7395 #define LINK_ENCRYPTION_STATUS BIT(20) 7396 #define HDCP2_STATUS(dev_priv, trans, port) \ 7397 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7398 TRANS_HDCP2_STATUS(trans) : \ 7399 PORT_HDCP2_STATUS(port)) 7400 7401 #define _PIPEA_HDCP2_STREAM_STATUS 0x668C0 7402 #define _PIPEB_HDCP2_STREAM_STATUS 0x665C0 7403 #define _PIPEC_HDCP2_STREAM_STATUS 0x666C0 7404 #define _PIPED_HDCP2_STREAM_STATUS 0x667C0 7405 #define PIPE_HDCP2_STREAM_STATUS(pipe) _MMIO(_PICK((pipe), \ 7406 _PIPEA_HDCP2_STREAM_STATUS, \ 7407 _PIPEB_HDCP2_STREAM_STATUS, \ 7408 _PIPEC_HDCP2_STREAM_STATUS, \ 7409 _PIPED_HDCP2_STREAM_STATUS)) 7410 7411 #define _TRANSA_HDCP2_STREAM_STATUS 0x664C0 7412 #define _TRANSB_HDCP2_STREAM_STATUS 0x665C0 7413 #define TRANS_HDCP2_STREAM_STATUS(trans) _MMIO_TRANS(trans, \ 7414 _TRANSA_HDCP2_STREAM_STATUS, \ 7415 _TRANSB_HDCP2_STREAM_STATUS) 7416 #define STREAM_ENCRYPTION_STATUS BIT(31) 7417 #define STREAM_TYPE_STATUS BIT(30) 7418 #define HDCP2_STREAM_STATUS(dev_priv, trans, port) \ 7419 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7420 TRANS_HDCP2_STREAM_STATUS(trans) : \ 7421 PIPE_HDCP2_STREAM_STATUS(pipe)) 7422 7423 #define _PORTA_HDCP2_AUTH_STREAM 0x66F00 7424 #define _PORTB_HDCP2_AUTH_STREAM 0x66F04 7425 #define PORT_HDCP2_AUTH_STREAM(port) _MMIO_PORT(port, \ 7426 _PORTA_HDCP2_AUTH_STREAM, \ 7427 _PORTB_HDCP2_AUTH_STREAM) 7428 #define _TRANSA_HDCP2_AUTH_STREAM 0x66F00 7429 #define _TRANSB_HDCP2_AUTH_STREAM 0x66F04 7430 #define TRANS_HDCP2_AUTH_STREAM(trans) _MMIO_TRANS(trans, \ 7431 _TRANSA_HDCP2_AUTH_STREAM, \ 7432 _TRANSB_HDCP2_AUTH_STREAM) 7433 #define AUTH_STREAM_TYPE BIT(31) 7434 #define HDCP2_AUTH_STREAM(dev_priv, trans, port) \ 7435 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7436 TRANS_HDCP2_AUTH_STREAM(trans) : \ 7437 PORT_HDCP2_AUTH_STREAM(port)) 7438 7439 /* Per-pipe DDI Function Control */ 7440 #define _TRANS_DDI_FUNC_CTL_A 0x60400 7441 #define _TRANS_DDI_FUNC_CTL_B 0x61400 7442 #define _TRANS_DDI_FUNC_CTL_C 0x62400 7443 #define _TRANS_DDI_FUNC_CTL_D 0x63400 7444 #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400 7445 #define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400 7446 #define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00 7447 #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A) 7448 7449 #define TRANS_DDI_FUNC_ENABLE (1 << 31) 7450 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ 7451 #define TRANS_DDI_PORT_SHIFT 28 7452 #define TGL_TRANS_DDI_PORT_SHIFT 27 7453 #define TRANS_DDI_PORT_MASK (7 << TRANS_DDI_PORT_SHIFT) 7454 #define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT) 7455 #define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT) 7456 #define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT) 7457 #define TRANS_DDI_MODE_SELECT_MASK (7 << 24) 7458 #define TRANS_DDI_MODE_SELECT_HDMI (0 << 24) 7459 #define TRANS_DDI_MODE_SELECT_DVI (1 << 24) 7460 #define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24) 7461 #define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24) 7462 #define TRANS_DDI_MODE_SELECT_FDI_OR_128B132B (4 << 24) 7463 #define TRANS_DDI_BPC_MASK (7 << 20) 7464 #define TRANS_DDI_BPC_8 (0 << 20) 7465 #define TRANS_DDI_BPC_10 (1 << 20) 7466 #define TRANS_DDI_BPC_6 (2 << 20) 7467 #define TRANS_DDI_BPC_12 (3 << 20) 7468 #define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18) 7469 #define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x) REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x)) 7470 #define TRANS_DDI_PVSYNC (1 << 17) 7471 #define TRANS_DDI_PHSYNC (1 << 16) 7472 #define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15) 7473 #define TRANS_DDI_EDP_INPUT_MASK (7 << 12) 7474 #define TRANS_DDI_EDP_INPUT_A_ON (0 << 12) 7475 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12) 7476 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12) 7477 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12) 7478 #define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12) 7479 #define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10) 7480 #define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \ 7481 REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans) 7482 #define TRANS_DDI_HDCP_SIGNALLING (1 << 9) 7483 #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8) 7484 #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7) 7485 #define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6) 7486 #define TRANS_DDI_HDCP_SELECT REG_BIT(5) 7487 #define TRANS_DDI_BFI_ENABLE (1 << 4) 7488 #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4) 7489 #define TRANS_DDI_HDMI_SCRAMBLING (1 << 0) 7490 #define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \ 7491 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \ 7492 | TRANS_DDI_HDMI_SCRAMBLING) 7493 7494 #define _TRANS_DDI_FUNC_CTL2_A 0x60404 7495 #define _TRANS_DDI_FUNC_CTL2_B 0x61404 7496 #define _TRANS_DDI_FUNC_CTL2_C 0x62404 7497 #define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404 7498 #define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404 7499 #define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04 7500 #define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL2_A) 7501 #define PORT_SYNC_MODE_ENABLE REG_BIT(4) 7502 #define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0) 7503 #define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x)) 7504 7505 #define TRANS_CMTG_CHICKEN _MMIO(0x6fa90) 7506 #define DISABLE_DPT_CLK_GATING REG_BIT(1) 7507 7508 /* DisplayPort Transport Control */ 7509 #define _DP_TP_CTL_A 0x64040 7510 #define _DP_TP_CTL_B 0x64140 7511 #define _TGL_DP_TP_CTL_A 0x60540 7512 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) 7513 #define TGL_DP_TP_CTL(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_CTL_A) 7514 #define DP_TP_CTL_ENABLE (1 << 31) 7515 #define DP_TP_CTL_FEC_ENABLE (1 << 30) 7516 #define DP_TP_CTL_MODE_SST (0 << 27) 7517 #define DP_TP_CTL_MODE_MST (1 << 27) 7518 #define DP_TP_CTL_FORCE_ACT (1 << 25) 7519 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18) 7520 #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15) 7521 #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8) 7522 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8) 7523 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1 << 8) 7524 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4 << 8) 7525 #define DP_TP_CTL_LINK_TRAIN_PAT4 (5 << 8) 7526 #define DP_TP_CTL_LINK_TRAIN_IDLE (2 << 8) 7527 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3 << 8) 7528 #define DP_TP_CTL_SCRAMBLE_DISABLE (1 << 7) 7529 7530 /* DisplayPort Transport Status */ 7531 #define _DP_TP_STATUS_A 0x64044 7532 #define _DP_TP_STATUS_B 0x64144 7533 #define _TGL_DP_TP_STATUS_A 0x60544 7534 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B) 7535 #define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_STATUS_A) 7536 #define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28) 7537 #define DP_TP_STATUS_IDLE_DONE (1 << 25) 7538 #define DP_TP_STATUS_ACT_SENT (1 << 24) 7539 #define DP_TP_STATUS_MODE_STATUS_MST (1 << 23) 7540 #define DP_TP_STATUS_AUTOTRAIN_DONE (1 << 12) 7541 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8) 7542 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4) 7543 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0) 7544 7545 /* DDI Buffer Control */ 7546 #define _DDI_BUF_CTL_A 0x64000 7547 #define _DDI_BUF_CTL_B 0x64100 7548 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B) 7549 #define DDI_BUF_CTL_ENABLE (1 << 31) 7550 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24) 7551 #define DDI_BUF_EMP_MASK (0xf << 24) 7552 #define DDI_BUF_PHY_LINK_RATE(r) ((r) << 20) 7553 #define DDI_BUF_PORT_REVERSAL (1 << 16) 7554 #define DDI_BUF_IS_IDLE (1 << 7) 7555 #define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6) 7556 #define DDI_A_4_LANES (1 << 4) 7557 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) 7558 #define DDI_PORT_WIDTH_MASK (7 << 1) 7559 #define DDI_PORT_WIDTH_SHIFT 1 7560 #define DDI_INIT_DISPLAY_DETECTED (1 << 0) 7561 7562 /* DDI Buffer Translations */ 7563 #define _DDI_BUF_TRANS_A 0x64E00 7564 #define _DDI_BUF_TRANS_B 0x64E60 7565 #define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8) 7566 #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31) 7567 #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4) 7568 7569 /* DDI DP Compliance Control */ 7570 #define _DDI_DP_COMP_CTL_A 0x605F0 7571 #define _DDI_DP_COMP_CTL_B 0x615F0 7572 #define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B) 7573 #define DDI_DP_COMP_CTL_ENABLE (1 << 31) 7574 #define DDI_DP_COMP_CTL_D10_2 (0 << 28) 7575 #define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28) 7576 #define DDI_DP_COMP_CTL_PRBS7 (2 << 28) 7577 #define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28) 7578 #define DDI_DP_COMP_CTL_HBR2 (4 << 28) 7579 #define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28) 7580 #define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0) 7581 7582 /* DDI DP Compliance Pattern */ 7583 #define _DDI_DP_COMP_PAT_A 0x605F4 7584 #define _DDI_DP_COMP_PAT_B 0x615F4 7585 #define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4) 7586 7587 /* Sideband Interface (SBI) is programmed indirectly, via 7588 * SBI_ADDR, which contains the register offset; and SBI_DATA, 7589 * which contains the payload */ 7590 #define SBI_ADDR _MMIO(0xC6000) 7591 #define SBI_DATA _MMIO(0xC6004) 7592 #define SBI_CTL_STAT _MMIO(0xC6008) 7593 #define SBI_CTL_DEST_ICLK (0x0 << 16) 7594 #define SBI_CTL_DEST_MPHY (0x1 << 16) 7595 #define SBI_CTL_OP_IORD (0x2 << 8) 7596 #define SBI_CTL_OP_IOWR (0x3 << 8) 7597 #define SBI_CTL_OP_CRRD (0x6 << 8) 7598 #define SBI_CTL_OP_CRWR (0x7 << 8) 7599 #define SBI_RESPONSE_FAIL (0x1 << 1) 7600 #define SBI_RESPONSE_SUCCESS (0x0 << 1) 7601 #define SBI_BUSY (0x1 << 0) 7602 #define SBI_READY (0x0 << 0) 7603 7604 /* SBI offsets */ 7605 #define SBI_SSCDIVINTPHASE 0x0200 7606 #define SBI_SSCDIVINTPHASE6 0x0600 7607 #define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1 7608 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1) 7609 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1) 7610 #define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8 7611 #define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8) 7612 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8) 7613 #define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15) 7614 #define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0) 7615 #define SBI_SSCDITHPHASE 0x0204 7616 #define SBI_SSCCTL 0x020c 7617 #define SBI_SSCCTL6 0x060C 7618 #define SBI_SSCCTL_PATHALT (1 << 3) 7619 #define SBI_SSCCTL_DISABLE (1 << 0) 7620 #define SBI_SSCAUXDIV6 0x0610 7621 #define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4 7622 #define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4) 7623 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4) 7624 #define SBI_DBUFF0 0x2a00 7625 #define SBI_GEN0 0x1f00 7626 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0) 7627 7628 /* LPT PIXCLK_GATE */ 7629 #define PIXCLK_GATE _MMIO(0xC6020) 7630 #define PIXCLK_GATE_UNGATE (1 << 0) 7631 #define PIXCLK_GATE_GATE (0 << 0) 7632 7633 /* SPLL */ 7634 #define SPLL_CTL _MMIO(0x46020) 7635 #define SPLL_PLL_ENABLE (1 << 31) 7636 #define SPLL_REF_BCLK (0 << 28) 7637 #define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */ 7638 #define SPLL_REF_NON_SSC_HSW (2 << 28) 7639 #define SPLL_REF_PCH_SSC_BDW (2 << 28) 7640 #define SPLL_REF_LCPLL (3 << 28) 7641 #define SPLL_REF_MASK (3 << 28) 7642 #define SPLL_FREQ_810MHz (0 << 26) 7643 #define SPLL_FREQ_1350MHz (1 << 26) 7644 #define SPLL_FREQ_2700MHz (2 << 26) 7645 #define SPLL_FREQ_MASK (3 << 26) 7646 7647 /* WRPLL */ 7648 #define _WRPLL_CTL1 0x46040 7649 #define _WRPLL_CTL2 0x46060 7650 #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2) 7651 #define WRPLL_PLL_ENABLE (1 << 31) 7652 #define WRPLL_REF_BCLK (0 << 28) 7653 #define WRPLL_REF_PCH_SSC (1 << 28) 7654 #define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */ 7655 #define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */ 7656 #define WRPLL_REF_LCPLL (3 << 28) 7657 #define WRPLL_REF_MASK (3 << 28) 7658 /* WRPLL divider programming */ 7659 #define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0) 7660 #define WRPLL_DIVIDER_REF_MASK (0xff) 7661 #define WRPLL_DIVIDER_POST(x) ((x) << 8) 7662 #define WRPLL_DIVIDER_POST_MASK (0x3f << 8) 7663 #define WRPLL_DIVIDER_POST_SHIFT 8 7664 #define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16) 7665 #define WRPLL_DIVIDER_FB_SHIFT 16 7666 #define WRPLL_DIVIDER_FB_MASK (0xff << 16) 7667 7668 /* Port clock selection */ 7669 #define _PORT_CLK_SEL_A 0x46100 7670 #define _PORT_CLK_SEL_B 0x46104 7671 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B) 7672 #define PORT_CLK_SEL_LCPLL_2700 (0 << 29) 7673 #define PORT_CLK_SEL_LCPLL_1350 (1 << 29) 7674 #define PORT_CLK_SEL_LCPLL_810 (2 << 29) 7675 #define PORT_CLK_SEL_SPLL (3 << 29) 7676 #define PORT_CLK_SEL_WRPLL(pll) (((pll) + 4) << 29) 7677 #define PORT_CLK_SEL_WRPLL1 (4 << 29) 7678 #define PORT_CLK_SEL_WRPLL2 (5 << 29) 7679 #define PORT_CLK_SEL_NONE (7 << 29) 7680 #define PORT_CLK_SEL_MASK (7 << 29) 7681 7682 /* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */ 7683 #define DDI_CLK_SEL(port) PORT_CLK_SEL(port) 7684 #define DDI_CLK_SEL_NONE (0x0 << 28) 7685 #define DDI_CLK_SEL_MG (0x8 << 28) 7686 #define DDI_CLK_SEL_TBT_162 (0xC << 28) 7687 #define DDI_CLK_SEL_TBT_270 (0xD << 28) 7688 #define DDI_CLK_SEL_TBT_540 (0xE << 28) 7689 #define DDI_CLK_SEL_TBT_810 (0xF << 28) 7690 #define DDI_CLK_SEL_MASK (0xF << 28) 7691 7692 /* Transcoder clock selection */ 7693 #define _TRANS_CLK_SEL_A 0x46140 7694 #define _TRANS_CLK_SEL_B 0x46144 7695 #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B) 7696 /* For each transcoder, we need to select the corresponding port clock */ 7697 #define TRANS_CLK_SEL_DISABLED (0x0 << 29) 7698 #define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29) 7699 #define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28) 7700 #define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28) 7701 7702 7703 #define CDCLK_FREQ _MMIO(0x46200) 7704 7705 #define _TRANSA_MSA_MISC 0x60410 7706 #define _TRANSB_MSA_MISC 0x61410 7707 #define _TRANSC_MSA_MISC 0x62410 7708 #define _TRANS_EDP_MSA_MISC 0x6f410 7709 #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC) 7710 /* See DP_MSA_MISC_* for the bit definitions */ 7711 7712 #define _TRANS_A_SET_CONTEXT_LATENCY 0x6007C 7713 #define _TRANS_B_SET_CONTEXT_LATENCY 0x6107C 7714 #define _TRANS_C_SET_CONTEXT_LATENCY 0x6207C 7715 #define _TRANS_D_SET_CONTEXT_LATENCY 0x6307C 7716 #define TRANS_SET_CONTEXT_LATENCY(tran) _MMIO_TRANS2(tran, _TRANS_A_SET_CONTEXT_LATENCY) 7717 #define TRANS_SET_CONTEXT_LATENCY_MASK REG_GENMASK(15, 0) 7718 #define TRANS_SET_CONTEXT_LATENCY_VALUE(x) REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x)) 7719 7720 /* LCPLL Control */ 7721 #define LCPLL_CTL _MMIO(0x130040) 7722 #define LCPLL_PLL_DISABLE (1 << 31) 7723 #define LCPLL_PLL_LOCK (1 << 30) 7724 #define LCPLL_REF_NON_SSC (0 << 28) 7725 #define LCPLL_REF_BCLK (2 << 28) 7726 #define LCPLL_REF_PCH_SSC (3 << 28) 7727 #define LCPLL_REF_MASK (3 << 28) 7728 #define LCPLL_CLK_FREQ_MASK (3 << 26) 7729 #define LCPLL_CLK_FREQ_450 (0 << 26) 7730 #define LCPLL_CLK_FREQ_54O_BDW (1 << 26) 7731 #define LCPLL_CLK_FREQ_337_5_BDW (2 << 26) 7732 #define LCPLL_CLK_FREQ_675_BDW (3 << 26) 7733 #define LCPLL_CD_CLOCK_DISABLE (1 << 25) 7734 #define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24) 7735 #define LCPLL_CD2X_CLOCK_DISABLE (1 << 23) 7736 #define LCPLL_POWER_DOWN_ALLOW (1 << 22) 7737 #define LCPLL_CD_SOURCE_FCLK (1 << 21) 7738 #define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19) 7739 7740 /* 7741 * SKL Clocks 7742 */ 7743 7744 /* CDCLK_CTL */ 7745 #define CDCLK_CTL _MMIO(0x46000) 7746 #define CDCLK_FREQ_SEL_MASK (3 << 26) 7747 #define CDCLK_FREQ_450_432 (0 << 26) 7748 #define CDCLK_FREQ_540 (1 << 26) 7749 #define CDCLK_FREQ_337_308 (2 << 26) 7750 #define CDCLK_FREQ_675_617 (3 << 26) 7751 #define BXT_CDCLK_CD2X_DIV_SEL_MASK (3 << 22) 7752 #define BXT_CDCLK_CD2X_DIV_SEL_1 (0 << 22) 7753 #define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1 << 22) 7754 #define BXT_CDCLK_CD2X_DIV_SEL_2 (2 << 22) 7755 #define BXT_CDCLK_CD2X_DIV_SEL_4 (3 << 22) 7756 #define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20) 7757 #define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19) 7758 #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3) 7759 #define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19) 7760 #define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19) 7761 #define TGL_CDCLK_CD2X_PIPE(pipe) BXT_CDCLK_CD2X_PIPE(pipe) 7762 #define TGL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE_NONE 7763 #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16) 7764 #define CDCLK_FREQ_DECIMAL_MASK (0x7ff) 7765 7766 /* CDCLK_SQUASH_CTL */ 7767 #define CDCLK_SQUASH_CTL _MMIO(0x46008) 7768 #define CDCLK_SQUASH_ENABLE REG_BIT(31) 7769 #define CDCLK_SQUASH_WINDOW_SIZE_MASK REG_GENMASK(27, 24) 7770 #define CDCLK_SQUASH_WINDOW_SIZE(x) REG_FIELD_PREP(CDCLK_SQUASH_WINDOW_SIZE_MASK, (x)) 7771 #define CDCLK_SQUASH_WAVEFORM_MASK REG_GENMASK(15, 0) 7772 #define CDCLK_SQUASH_WAVEFORM(x) REG_FIELD_PREP(CDCLK_SQUASH_WAVEFORM_MASK, (x)) 7773 7774 /* LCPLL_CTL */ 7775 #define LCPLL1_CTL _MMIO(0x46010) 7776 #define LCPLL2_CTL _MMIO(0x46014) 7777 #define LCPLL_PLL_ENABLE (1 << 31) 7778 7779 /* DPLL control1 */ 7780 #define DPLL_CTRL1 _MMIO(0x6C058) 7781 #define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5)) 7782 #define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4)) 7783 #define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1)) 7784 #define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1) 7785 #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1)) 7786 #define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6)) 7787 #define DPLL_CTRL1_LINK_RATE_2700 0 7788 #define DPLL_CTRL1_LINK_RATE_1350 1 7789 #define DPLL_CTRL1_LINK_RATE_810 2 7790 #define DPLL_CTRL1_LINK_RATE_1620 3 7791 #define DPLL_CTRL1_LINK_RATE_1080 4 7792 #define DPLL_CTRL1_LINK_RATE_2160 5 7793 7794 /* DPLL control2 */ 7795 #define DPLL_CTRL2 _MMIO(0x6C05C) 7796 #define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15)) 7797 #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1)) 7798 #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1) 7799 #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1)) 7800 #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3)) 7801 7802 /* DPLL Status */ 7803 #define DPLL_STATUS _MMIO(0x6C060) 7804 #define DPLL_LOCK(id) (1 << ((id) * 8)) 7805 7806 /* DPLL cfg */ 7807 #define _DPLL1_CFGCR1 0x6C040 7808 #define _DPLL2_CFGCR1 0x6C048 7809 #define _DPLL3_CFGCR1 0x6C050 7810 #define DPLL_CFGCR1_FREQ_ENABLE (1 << 31) 7811 #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9) 7812 #define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9) 7813 #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff) 7814 7815 #define _DPLL1_CFGCR2 0x6C044 7816 #define _DPLL2_CFGCR2 0x6C04C 7817 #define _DPLL3_CFGCR2 0x6C054 7818 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8) 7819 #define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8) 7820 #define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7) 7821 #define DPLL_CFGCR2_KDIV_MASK (3 << 5) 7822 #define DPLL_CFGCR2_KDIV(x) ((x) << 5) 7823 #define DPLL_CFGCR2_KDIV_5 (0 << 5) 7824 #define DPLL_CFGCR2_KDIV_2 (1 << 5) 7825 #define DPLL_CFGCR2_KDIV_3 (2 << 5) 7826 #define DPLL_CFGCR2_KDIV_1 (3 << 5) 7827 #define DPLL_CFGCR2_PDIV_MASK (7 << 2) 7828 #define DPLL_CFGCR2_PDIV(x) ((x) << 2) 7829 #define DPLL_CFGCR2_PDIV_1 (0 << 2) 7830 #define DPLL_CFGCR2_PDIV_2 (1 << 2) 7831 #define DPLL_CFGCR2_PDIV_3 (2 << 2) 7832 #define DPLL_CFGCR2_PDIV_7 (4 << 2) 7833 #define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2) 7834 #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3) 7835 7836 #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1) 7837 #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2) 7838 7839 /* ICL Clocks */ 7840 #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280) 7841 #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24, 4, 5)) 7842 #define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10) 7843 #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \ 7844 (tc_port) + 12 : \ 7845 (tc_port) - TC_PORT_4 + 21)) 7846 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2) 7847 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 7848 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 7849 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27) 7850 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \ 7851 (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 7852 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \ 7853 ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 7854 7855 /* 7856 * DG1 Clocks 7857 * First registers controls the first A and B, while the second register 7858 * controls the phy C and D. The bits on these registers are the 7859 * same, but refer to different phys 7860 */ 7861 #define _DG1_DPCLKA_CFGCR0 0x164280 7862 #define _DG1_DPCLKA1_CFGCR0 0x16C280 7863 #define _DG1_DPCLKA_PHY_IDX(phy) ((phy) % 2) 7864 #define _DG1_DPCLKA_PLL_IDX(pll) ((pll) % 2) 7865 #define DG1_DPCLKA_CFGCR0(phy) _MMIO_PHY((phy) / 2, \ 7866 _DG1_DPCLKA_CFGCR0, \ 7867 _DG1_DPCLKA1_CFGCR0) 7868 #define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT(_DG1_DPCLKA_PHY_IDX(phy) + 10) 7869 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) (_DG1_DPCLKA_PHY_IDX(phy) * 2) 7870 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (_DG1_DPCLKA_PLL_IDX(pll) << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 7871 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 7872 7873 /* ADLS Clocks */ 7874 #define _ADLS_DPCLKA_CFGCR0 0x164280 7875 #define _ADLS_DPCLKA_CFGCR1 0x1642BC 7876 #define ADLS_DPCLKA_CFGCR(phy) _MMIO_PHY((phy) / 3, \ 7877 _ADLS_DPCLKA_CFGCR0, \ 7878 _ADLS_DPCLKA_CFGCR1) 7879 #define ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy) (((phy) % 3) * 2) 7880 /* ADLS DPCLKA_CFGCR0 DDI mask */ 7881 #define ADLS_DPCLKA_DDII_SEL_MASK REG_GENMASK(5, 4) 7882 #define ADLS_DPCLKA_DDIB_SEL_MASK REG_GENMASK(3, 2) 7883 #define ADLS_DPCLKA_DDIA_SEL_MASK REG_GENMASK(1, 0) 7884 /* ADLS DPCLKA_CFGCR1 DDI mask */ 7885 #define ADLS_DPCLKA_DDIK_SEL_MASK REG_GENMASK(3, 2) 7886 #define ADLS_DPCLKA_DDIJ_SEL_MASK REG_GENMASK(1, 0) 7887 #define ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy) _PICK((phy), \ 7888 ADLS_DPCLKA_DDIA_SEL_MASK, \ 7889 ADLS_DPCLKA_DDIB_SEL_MASK, \ 7890 ADLS_DPCLKA_DDII_SEL_MASK, \ 7891 ADLS_DPCLKA_DDIJ_SEL_MASK, \ 7892 ADLS_DPCLKA_DDIK_SEL_MASK) 7893 7894 /* ICL PLL */ 7895 #define DPLL0_ENABLE 0x46010 7896 #define DPLL1_ENABLE 0x46014 7897 #define _ADLS_DPLL2_ENABLE 0x46018 7898 #define _ADLS_DPLL3_ENABLE 0x46030 7899 #define PLL_ENABLE (1 << 31) 7900 #define PLL_LOCK (1 << 30) 7901 #define PLL_POWER_ENABLE (1 << 27) 7902 #define PLL_POWER_STATE (1 << 26) 7903 #define ICL_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \ 7904 _ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE) 7905 7906 #define _DG2_PLL3_ENABLE 0x4601C 7907 7908 #define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \ 7909 _ADLS_DPLL2_ENABLE, _DG2_PLL3_ENABLE) 7910 7911 #define TBT_PLL_ENABLE _MMIO(0x46020) 7912 7913 #define _MG_PLL1_ENABLE 0x46030 7914 #define _MG_PLL2_ENABLE 0x46034 7915 #define _MG_PLL3_ENABLE 0x46038 7916 #define _MG_PLL4_ENABLE 0x4603C 7917 /* Bits are the same as DPLL0_ENABLE */ 7918 #define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \ 7919 _MG_PLL2_ENABLE) 7920 7921 /* DG1 PLL */ 7922 #define DG1_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \ 7923 _MG_PLL1_ENABLE, _MG_PLL2_ENABLE) 7924 7925 /* ADL-P Type C PLL */ 7926 #define PORTTC1_PLL_ENABLE 0x46038 7927 #define PORTTC2_PLL_ENABLE 0x46040 7928 7929 #define ADLP_PORTTC_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), \ 7930 PORTTC1_PLL_ENABLE, \ 7931 PORTTC2_PLL_ENABLE) 7932 7933 #define _ICL_DPLL0_CFGCR0 0x164000 7934 #define _ICL_DPLL1_CFGCR0 0x164080 7935 #define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \ 7936 _ICL_DPLL1_CFGCR0) 7937 #define DPLL_CFGCR0_HDMI_MODE (1 << 30) 7938 #define DPLL_CFGCR0_SSC_ENABLE (1 << 29) 7939 #define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25) 7940 #define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25) 7941 #define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25) 7942 #define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25) 7943 #define DPLL_CFGCR0_LINK_RATE_810 (2 << 25) 7944 #define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25) 7945 #define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25) 7946 #define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25) 7947 #define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25) 7948 #define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25) 7949 #define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10) 7950 #define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10) 7951 #define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10) 7952 #define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff) 7953 7954 #define _ICL_DPLL0_CFGCR1 0x164004 7955 #define _ICL_DPLL1_CFGCR1 0x164084 7956 #define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \ 7957 _ICL_DPLL1_CFGCR1) 7958 #define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10) 7959 #define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10) 7960 #define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10) 7961 #define DPLL_CFGCR1_QDIV_MODE_SHIFT (9) 7962 #define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9) 7963 #define DPLL_CFGCR1_KDIV_MASK (7 << 6) 7964 #define DPLL_CFGCR1_KDIV_SHIFT (6) 7965 #define DPLL_CFGCR1_KDIV(x) ((x) << 6) 7966 #define DPLL_CFGCR1_KDIV_1 (1 << 6) 7967 #define DPLL_CFGCR1_KDIV_2 (2 << 6) 7968 #define DPLL_CFGCR1_KDIV_3 (4 << 6) 7969 #define DPLL_CFGCR1_PDIV_MASK (0xf << 2) 7970 #define DPLL_CFGCR1_PDIV_SHIFT (2) 7971 #define DPLL_CFGCR1_PDIV(x) ((x) << 2) 7972 #define DPLL_CFGCR1_PDIV_2 (1 << 2) 7973 #define DPLL_CFGCR1_PDIV_3 (2 << 2) 7974 #define DPLL_CFGCR1_PDIV_5 (4 << 2) 7975 #define DPLL_CFGCR1_PDIV_7 (8 << 2) 7976 #define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0) 7977 #define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0) 7978 #define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0) 7979 7980 #define _TGL_DPLL0_CFGCR0 0x164284 7981 #define _TGL_DPLL1_CFGCR0 0x16428C 7982 #define _TGL_TBTPLL_CFGCR0 0x16429C 7983 #define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ 7984 _TGL_DPLL1_CFGCR0, \ 7985 _TGL_TBTPLL_CFGCR0) 7986 #define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \ 7987 _TGL_DPLL1_CFGCR0) 7988 7989 #define _TGL_DPLL0_CFGCR1 0x164288 7990 #define _TGL_DPLL1_CFGCR1 0x164290 7991 #define _TGL_TBTPLL_CFGCR1 0x1642A0 7992 #define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ 7993 _TGL_DPLL1_CFGCR1, \ 7994 _TGL_TBTPLL_CFGCR1) 7995 #define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \ 7996 _TGL_DPLL1_CFGCR1) 7997 7998 #define _DG1_DPLL2_CFGCR0 0x16C284 7999 #define _DG1_DPLL3_CFGCR0 0x16C28C 8000 #define DG1_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ 8001 _TGL_DPLL1_CFGCR0, \ 8002 _DG1_DPLL2_CFGCR0, \ 8003 _DG1_DPLL3_CFGCR0) 8004 8005 #define _DG1_DPLL2_CFGCR1 0x16C288 8006 #define _DG1_DPLL3_CFGCR1 0x16C290 8007 #define DG1_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ 8008 _TGL_DPLL1_CFGCR1, \ 8009 _DG1_DPLL2_CFGCR1, \ 8010 _DG1_DPLL3_CFGCR1) 8011 8012 /* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */ 8013 #define _ADLS_DPLL3_CFGCR0 0x1642C0 8014 #define _ADLS_DPLL4_CFGCR0 0x164294 8015 #define ADLS_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ 8016 _TGL_DPLL1_CFGCR0, \ 8017 _ADLS_DPLL4_CFGCR0, \ 8018 _ADLS_DPLL3_CFGCR0) 8019 8020 #define _ADLS_DPLL3_CFGCR1 0x1642C4 8021 #define _ADLS_DPLL4_CFGCR1 0x164298 8022 #define ADLS_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ 8023 _TGL_DPLL1_CFGCR1, \ 8024 _ADLS_DPLL4_CFGCR1, \ 8025 _ADLS_DPLL3_CFGCR1) 8026 8027 #define _DKL_PHY1_BASE 0x168000 8028 #define _DKL_PHY2_BASE 0x169000 8029 #define _DKL_PHY3_BASE 0x16A000 8030 #define _DKL_PHY4_BASE 0x16B000 8031 #define _DKL_PHY5_BASE 0x16C000 8032 #define _DKL_PHY6_BASE 0x16D000 8033 8034 /* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */ 8035 #define _DKL_PLL_DIV0 0x200 8036 #define DKL_PLL_DIV0_INTEG_COEFF(x) ((x) << 16) 8037 #define DKL_PLL_DIV0_INTEG_COEFF_MASK (0x1F << 16) 8038 #define DKL_PLL_DIV0_PROP_COEFF(x) ((x) << 12) 8039 #define DKL_PLL_DIV0_PROP_COEFF_MASK (0xF << 12) 8040 #define DKL_PLL_DIV0_FBPREDIV_SHIFT (8) 8041 #define DKL_PLL_DIV0_FBPREDIV(x) ((x) << DKL_PLL_DIV0_FBPREDIV_SHIFT) 8042 #define DKL_PLL_DIV0_FBPREDIV_MASK (0xF << DKL_PLL_DIV0_FBPREDIV_SHIFT) 8043 #define DKL_PLL_DIV0_FBDIV_INT(x) ((x) << 0) 8044 #define DKL_PLL_DIV0_FBDIV_INT_MASK (0xFF << 0) 8045 #define DKL_PLL_DIV0(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ 8046 _DKL_PHY2_BASE) + \ 8047 _DKL_PLL_DIV0) 8048 8049 #define _DKL_PLL_DIV1 0x204 8050 #define DKL_PLL_DIV1_IREF_TRIM(x) ((x) << 16) 8051 #define DKL_PLL_DIV1_IREF_TRIM_MASK (0x1F << 16) 8052 #define DKL_PLL_DIV1_TDC_TARGET_CNT(x) ((x) << 0) 8053 #define DKL_PLL_DIV1_TDC_TARGET_CNT_MASK (0xFF << 0) 8054 #define DKL_PLL_DIV1(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ 8055 _DKL_PHY2_BASE) + \ 8056 _DKL_PLL_DIV1) 8057 8058 #define _DKL_PLL_SSC 0x210 8059 #define DKL_PLL_SSC_IREF_NDIV_RATIO(x) ((x) << 29) 8060 #define DKL_PLL_SSC_IREF_NDIV_RATIO_MASK (0x7 << 29) 8061 #define DKL_PLL_SSC_STEP_LEN(x) ((x) << 16) 8062 #define DKL_PLL_SSC_STEP_LEN_MASK (0xFF << 16) 8063 #define DKL_PLL_SSC_STEP_NUM(x) ((x) << 11) 8064 #define DKL_PLL_SSC_STEP_NUM_MASK (0x7 << 11) 8065 #define DKL_PLL_SSC_EN (1 << 9) 8066 #define DKL_PLL_SSC(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ 8067 _DKL_PHY2_BASE) + \ 8068 _DKL_PLL_SSC) 8069 8070 #define _DKL_PLL_BIAS 0x214 8071 #define DKL_PLL_BIAS_FRAC_EN_H (1 << 30) 8072 #define DKL_PLL_BIAS_FBDIV_SHIFT (8) 8073 #define DKL_PLL_BIAS_FBDIV_FRAC(x) ((x) << DKL_PLL_BIAS_FBDIV_SHIFT) 8074 #define DKL_PLL_BIAS_FBDIV_FRAC_MASK (0x3FFFFF << DKL_PLL_BIAS_FBDIV_SHIFT) 8075 #define DKL_PLL_BIAS(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ 8076 _DKL_PHY2_BASE) + \ 8077 _DKL_PLL_BIAS) 8078 8079 #define _DKL_PLL_TDC_COLDST_BIAS 0x218 8080 #define DKL_PLL_TDC_SSC_STEP_SIZE(x) ((x) << 8) 8081 #define DKL_PLL_TDC_SSC_STEP_SIZE_MASK (0xFF << 8) 8082 #define DKL_PLL_TDC_FEED_FWD_GAIN(x) ((x) << 0) 8083 #define DKL_PLL_TDC_FEED_FWD_GAIN_MASK (0xFF << 0) 8084 #define DKL_PLL_TDC_COLDST_BIAS(tc_port) _MMIO(_PORT(tc_port, \ 8085 _DKL_PHY1_BASE, \ 8086 _DKL_PHY2_BASE) + \ 8087 _DKL_PLL_TDC_COLDST_BIAS) 8088 8089 #define _DKL_REFCLKIN_CTL 0x12C 8090 /* Bits are the same as MG_REFCLKIN_CTL */ 8091 #define DKL_REFCLKIN_CTL(tc_port) _MMIO(_PORT(tc_port, \ 8092 _DKL_PHY1_BASE, \ 8093 _DKL_PHY2_BASE) + \ 8094 _DKL_REFCLKIN_CTL) 8095 8096 #define _DKL_CLKTOP2_HSCLKCTL 0xD4 8097 /* Bits are the same as MG_CLKTOP2_HSCLKCTL */ 8098 #define DKL_CLKTOP2_HSCLKCTL(tc_port) _MMIO(_PORT(tc_port, \ 8099 _DKL_PHY1_BASE, \ 8100 _DKL_PHY2_BASE) + \ 8101 _DKL_CLKTOP2_HSCLKCTL) 8102 8103 #define _DKL_CLKTOP2_CORECLKCTL1 0xD8 8104 /* Bits are the same as MG_CLKTOP2_CORECLKCTL1 */ 8105 #define DKL_CLKTOP2_CORECLKCTL1(tc_port) _MMIO(_PORT(tc_port, \ 8106 _DKL_PHY1_BASE, \ 8107 _DKL_PHY2_BASE) + \ 8108 _DKL_CLKTOP2_CORECLKCTL1) 8109 8110 #define _DKL_TX_DPCNTL0 0x2C0 8111 #define DKL_TX_PRESHOOT_COEFF(x) ((x) << 13) 8112 #define DKL_TX_PRESHOOT_COEFF_MASK (0x1f << 13) 8113 #define DKL_TX_DE_EMPHASIS_COEFF(x) ((x) << 8) 8114 #define DKL_TX_DE_EMPAHSIS_COEFF_MASK (0x1f << 8) 8115 #define DKL_TX_VSWING_CONTROL(x) ((x) << 0) 8116 #define DKL_TX_VSWING_CONTROL_MASK (0x7 << 0) 8117 #define DKL_TX_DPCNTL0(tc_port) _MMIO(_PORT(tc_port, \ 8118 _DKL_PHY1_BASE, \ 8119 _DKL_PHY2_BASE) + \ 8120 _DKL_TX_DPCNTL0) 8121 8122 #define _DKL_TX_DPCNTL1 0x2C4 8123 /* Bits are the same as DKL_TX_DPCNTRL0 */ 8124 #define DKL_TX_DPCNTL1(tc_port) _MMIO(_PORT(tc_port, \ 8125 _DKL_PHY1_BASE, \ 8126 _DKL_PHY2_BASE) + \ 8127 _DKL_TX_DPCNTL1) 8128 8129 #define _DKL_TX_DPCNTL2 0x2C8 8130 #define DKL_TX_DP20BITMODE REG_BIT(2) 8131 #define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK REG_GENMASK(4, 3) 8132 #define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK, (val)) 8133 #define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK REG_GENMASK(6, 5) 8134 #define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, (val)) 8135 #define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \ 8136 _DKL_PHY1_BASE, \ 8137 _DKL_PHY2_BASE) + \ 8138 _DKL_TX_DPCNTL2) 8139 8140 #define _DKL_TX_FW_CALIB 0x2F8 8141 #define DKL_TX_CFG_DISABLE_WAIT_INIT (1 << 7) 8142 #define DKL_TX_FW_CALIB(tc_port) _MMIO(_PORT(tc_port, \ 8143 _DKL_PHY1_BASE, \ 8144 _DKL_PHY2_BASE) + \ 8145 _DKL_TX_FW_CALIB) 8146 8147 #define _DKL_TX_PMD_LANE_SUS 0xD00 8148 #define DKL_TX_PMD_LANE_SUS(tc_port) _MMIO(_PORT(tc_port, \ 8149 _DKL_PHY1_BASE, \ 8150 _DKL_PHY2_BASE) + \ 8151 _DKL_TX_PMD_LANE_SUS) 8152 8153 #define _DKL_TX_DW17 0xDC4 8154 #define DKL_TX_DW17(tc_port) _MMIO(_PORT(tc_port, \ 8155 _DKL_PHY1_BASE, \ 8156 _DKL_PHY2_BASE) + \ 8157 _DKL_TX_DW17) 8158 8159 #define _DKL_TX_DW18 0xDC8 8160 #define DKL_TX_DW18(tc_port) _MMIO(_PORT(tc_port, \ 8161 _DKL_PHY1_BASE, \ 8162 _DKL_PHY2_BASE) + \ 8163 _DKL_TX_DW18) 8164 8165 #define _DKL_DP_MODE 0xA0 8166 #define DKL_DP_MODE(tc_port) _MMIO(_PORT(tc_port, \ 8167 _DKL_PHY1_BASE, \ 8168 _DKL_PHY2_BASE) + \ 8169 _DKL_DP_MODE) 8170 8171 #define _DKL_CMN_UC_DW27 0x36C 8172 #define DKL_CMN_UC_DW27_UC_HEALTH (0x1 << 15) 8173 #define DKL_CMN_UC_DW_27(tc_port) _MMIO(_PORT(tc_port, \ 8174 _DKL_PHY1_BASE, \ 8175 _DKL_PHY2_BASE) + \ 8176 _DKL_CMN_UC_DW27) 8177 8178 /* 8179 * Each Dekel PHY is addressed through a 4KB aperture. Each PHY has more than 8180 * 4KB of register space, so a separate index is programmed in HIP_INDEX_REG0 8181 * or HIP_INDEX_REG1, based on the port number, to set the upper 2 address 8182 * bits that point the 4KB window into the full PHY register space. 8183 */ 8184 #define _HIP_INDEX_REG0 0x1010A0 8185 #define _HIP_INDEX_REG1 0x1010A4 8186 #define HIP_INDEX_REG(tc_port) _MMIO((tc_port) < 4 ? _HIP_INDEX_REG0 \ 8187 : _HIP_INDEX_REG1) 8188 #define _HIP_INDEX_SHIFT(tc_port) (8 * ((tc_port) % 4)) 8189 #define HIP_INDEX_VAL(tc_port, val) ((val) << _HIP_INDEX_SHIFT(tc_port)) 8190 8191 /* BXT display engine PLL */ 8192 #define BXT_DE_PLL_CTL _MMIO(0x6d000) 8193 #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */ 8194 #define BXT_DE_PLL_RATIO_MASK 0xff 8195 8196 #define BXT_DE_PLL_ENABLE _MMIO(0x46070) 8197 #define BXT_DE_PLL_PLL_ENABLE (1 << 31) 8198 #define BXT_DE_PLL_LOCK (1 << 30) 8199 #define BXT_DE_PLL_FREQ_REQ (1 << 23) 8200 #define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22) 8201 #define ICL_CDCLK_PLL_RATIO(x) (x) 8202 #define ICL_CDCLK_PLL_RATIO_MASK 0xff 8203 8204 /* GEN9 DC */ 8205 #define DC_STATE_EN _MMIO(0x45504) 8206 #define DC_STATE_DISABLE 0 8207 #define DC_STATE_EN_DC3CO REG_BIT(30) 8208 #define DC_STATE_DC3CO_STATUS REG_BIT(29) 8209 #define DC_STATE_EN_UPTO_DC5 (1 << 0) 8210 #define DC_STATE_EN_DC9 (1 << 3) 8211 #define DC_STATE_EN_UPTO_DC6 (2 << 0) 8212 #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3 8213 8214 #define DC_STATE_DEBUG _MMIO(0x45520) 8215 #define DC_STATE_DEBUG_MASK_CORES (1 << 0) 8216 #define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1) 8217 8218 #define BXT_D_CR_DRP0_DUNIT8 0x1000 8219 #define BXT_D_CR_DRP0_DUNIT9 0x1200 8220 #define BXT_D_CR_DRP0_DUNIT_START 8 8221 #define BXT_D_CR_DRP0_DUNIT_END 11 8222 #define BXT_D_CR_DRP0_DUNIT(x) _MMIO(MCHBAR_MIRROR_BASE_SNB + \ 8223 _PICK_EVEN((x) - 8, BXT_D_CR_DRP0_DUNIT8,\ 8224 BXT_D_CR_DRP0_DUNIT9)) 8225 #define BXT_DRAM_RANK_MASK 0x3 8226 #define BXT_DRAM_RANK_SINGLE 0x1 8227 #define BXT_DRAM_RANK_DUAL 0x3 8228 #define BXT_DRAM_WIDTH_MASK (0x3 << 4) 8229 #define BXT_DRAM_WIDTH_SHIFT 4 8230 #define BXT_DRAM_WIDTH_X8 (0x0 << 4) 8231 #define BXT_DRAM_WIDTH_X16 (0x1 << 4) 8232 #define BXT_DRAM_WIDTH_X32 (0x2 << 4) 8233 #define BXT_DRAM_WIDTH_X64 (0x3 << 4) 8234 #define BXT_DRAM_SIZE_MASK (0x7 << 6) 8235 #define BXT_DRAM_SIZE_SHIFT 6 8236 #define BXT_DRAM_SIZE_4GBIT (0x0 << 6) 8237 #define BXT_DRAM_SIZE_6GBIT (0x1 << 6) 8238 #define BXT_DRAM_SIZE_8GBIT (0x2 << 6) 8239 #define BXT_DRAM_SIZE_12GBIT (0x3 << 6) 8240 #define BXT_DRAM_SIZE_16GBIT (0x4 << 6) 8241 #define BXT_DRAM_TYPE_MASK (0x7 << 22) 8242 #define BXT_DRAM_TYPE_SHIFT 22 8243 #define BXT_DRAM_TYPE_DDR3 (0x0 << 22) 8244 #define BXT_DRAM_TYPE_LPDDR3 (0x1 << 22) 8245 #define BXT_DRAM_TYPE_LPDDR4 (0x2 << 22) 8246 #define BXT_DRAM_TYPE_DDR4 (0x4 << 22) 8247 8248 #define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04) 8249 #define DG1_GEAR_TYPE REG_BIT(16) 8250 8251 #define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000) 8252 #define SKL_DRAM_DDR_TYPE_MASK (0x3 << 0) 8253 #define SKL_DRAM_DDR_TYPE_DDR4 (0 << 0) 8254 #define SKL_DRAM_DDR_TYPE_DDR3 (1 << 0) 8255 #define SKL_DRAM_DDR_TYPE_LPDDR3 (2 << 0) 8256 #define SKL_DRAM_DDR_TYPE_LPDDR4 (3 << 0) 8257 8258 #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C) 8259 #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010) 8260 #define SKL_DRAM_S_SHIFT 16 8261 #define SKL_DRAM_SIZE_MASK 0x3F 8262 #define SKL_DRAM_WIDTH_MASK (0x3 << 8) 8263 #define SKL_DRAM_WIDTH_SHIFT 8 8264 #define SKL_DRAM_WIDTH_X8 (0x0 << 8) 8265 #define SKL_DRAM_WIDTH_X16 (0x1 << 8) 8266 #define SKL_DRAM_WIDTH_X32 (0x2 << 8) 8267 #define SKL_DRAM_RANK_MASK (0x1 << 10) 8268 #define SKL_DRAM_RANK_SHIFT 10 8269 #define SKL_DRAM_RANK_1 (0x0 << 10) 8270 #define SKL_DRAM_RANK_2 (0x1 << 10) 8271 #define SKL_DRAM_RANK_MASK (0x1 << 10) 8272 #define ICL_DRAM_SIZE_MASK 0x7F 8273 #define ICL_DRAM_WIDTH_MASK (0x3 << 7) 8274 #define ICL_DRAM_WIDTH_SHIFT 7 8275 #define ICL_DRAM_WIDTH_X8 (0x0 << 7) 8276 #define ICL_DRAM_WIDTH_X16 (0x1 << 7) 8277 #define ICL_DRAM_WIDTH_X32 (0x2 << 7) 8278 #define ICL_DRAM_RANK_MASK (0x3 << 9) 8279 #define ICL_DRAM_RANK_SHIFT 9 8280 #define ICL_DRAM_RANK_1 (0x0 << 9) 8281 #define ICL_DRAM_RANK_2 (0x1 << 9) 8282 #define ICL_DRAM_RANK_3 (0x2 << 9) 8283 #define ICL_DRAM_RANK_4 (0x3 << 9) 8284 8285 #define SA_PERF_STATUS_0_0_0_MCHBAR_PC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918) 8286 #define DG1_QCLK_RATIO_MASK REG_GENMASK(9, 2) 8287 #define DG1_QCLK_REFERENCE REG_BIT(10) 8288 8289 #define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4000) 8290 #define DG1_DRAM_T_RDPRE_MASK REG_GENMASK(16, 11) 8291 #define DG1_DRAM_T_RP_MASK REG_GENMASK(6, 0) 8292 #define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4004) 8293 #define DG1_DRAM_T_RCD_MASK REG_GENMASK(15, 9) 8294 #define DG1_DRAM_T_RAS_MASK REG_GENMASK(8, 1) 8295 8296 /* 8297 * Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, 8298 * since on HSW we can't write to it using intel_uncore_write. 8299 */ 8300 #define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C) 8301 #define D_COMP_BDW _MMIO(0x138144) 8302 #define D_COMP_RCOMP_IN_PROGRESS (1 << 9) 8303 #define D_COMP_COMP_FORCE (1 << 8) 8304 #define D_COMP_COMP_DISABLE (1 << 0) 8305 8306 /* Pipe WM_LINETIME - watermark line time */ 8307 #define _WM_LINETIME_A 0x45270 8308 #define _WM_LINETIME_B 0x45274 8309 #define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B) 8310 #define HSW_LINETIME_MASK REG_GENMASK(8, 0) 8311 #define HSW_LINETIME(x) REG_FIELD_PREP(HSW_LINETIME_MASK, (x)) 8312 #define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16) 8313 #define HSW_IPS_LINETIME(x) REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x)) 8314 8315 /* SFUSE_STRAP */ 8316 #define SFUSE_STRAP _MMIO(0xc2014) 8317 #define SFUSE_STRAP_FUSE_LOCK (1 << 13) 8318 #define SFUSE_STRAP_RAW_FREQUENCY (1 << 8) 8319 #define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7) 8320 #define SFUSE_STRAP_CRT_DISABLED (1 << 6) 8321 #define SFUSE_STRAP_DDIF_DETECTED (1 << 3) 8322 #define SFUSE_STRAP_DDIB_DETECTED (1 << 2) 8323 #define SFUSE_STRAP_DDIC_DETECTED (1 << 1) 8324 #define SFUSE_STRAP_DDID_DETECTED (1 << 0) 8325 8326 #define WM_MISC _MMIO(0x45260) 8327 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0) 8328 8329 #define WM_DBG _MMIO(0x45280) 8330 #define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0) 8331 #define WM_DBG_DISALLOW_MAXFIFO (1 << 1) 8332 #define WM_DBG_DISALLOW_SPRITE (1 << 2) 8333 8334 /* pipe CSC */ 8335 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010 8336 #define _PIPE_A_CSC_COEFF_BY 0x49014 8337 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018 8338 #define _PIPE_A_CSC_COEFF_BU 0x4901c 8339 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020 8340 #define _PIPE_A_CSC_COEFF_BV 0x49024 8341 8342 #define _PIPE_A_CSC_MODE 0x49028 8343 #define ICL_CSC_ENABLE (1 << 31) /* icl+ */ 8344 #define ICL_OUTPUT_CSC_ENABLE (1 << 30) /* icl+ */ 8345 #define CSC_BLACK_SCREEN_OFFSET (1 << 2) /* ilk/snb */ 8346 #define CSC_POSITION_BEFORE_GAMMA (1 << 1) /* pre-glk */ 8347 #define CSC_MODE_YUV_TO_RGB (1 << 0) /* ilk/snb */ 8348 8349 #define _PIPE_A_CSC_PREOFF_HI 0x49030 8350 #define _PIPE_A_CSC_PREOFF_ME 0x49034 8351 #define _PIPE_A_CSC_PREOFF_LO 0x49038 8352 #define _PIPE_A_CSC_POSTOFF_HI 0x49040 8353 #define _PIPE_A_CSC_POSTOFF_ME 0x49044 8354 #define _PIPE_A_CSC_POSTOFF_LO 0x49048 8355 8356 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110 8357 #define _PIPE_B_CSC_COEFF_BY 0x49114 8358 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118 8359 #define _PIPE_B_CSC_COEFF_BU 0x4911c 8360 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120 8361 #define _PIPE_B_CSC_COEFF_BV 0x49124 8362 #define _PIPE_B_CSC_MODE 0x49128 8363 #define _PIPE_B_CSC_PREOFF_HI 0x49130 8364 #define _PIPE_B_CSC_PREOFF_ME 0x49134 8365 #define _PIPE_B_CSC_PREOFF_LO 0x49138 8366 #define _PIPE_B_CSC_POSTOFF_HI 0x49140 8367 #define _PIPE_B_CSC_POSTOFF_ME 0x49144 8368 #define _PIPE_B_CSC_POSTOFF_LO 0x49148 8369 8370 #define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY) 8371 #define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY) 8372 #define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU) 8373 #define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU) 8374 #define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV) 8375 #define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV) 8376 #define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE) 8377 #define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI) 8378 #define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME) 8379 #define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO) 8380 #define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI) 8381 #define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) 8382 #define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) 8383 8384 /* Pipe Output CSC */ 8385 #define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY 0x49050 8386 #define _PIPE_A_OUTPUT_CSC_COEFF_BY 0x49054 8387 #define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU 0x49058 8388 #define _PIPE_A_OUTPUT_CSC_COEFF_BU 0x4905c 8389 #define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV 0x49060 8390 #define _PIPE_A_OUTPUT_CSC_COEFF_BV 0x49064 8391 #define _PIPE_A_OUTPUT_CSC_PREOFF_HI 0x49068 8392 #define _PIPE_A_OUTPUT_CSC_PREOFF_ME 0x4906c 8393 #define _PIPE_A_OUTPUT_CSC_PREOFF_LO 0x49070 8394 #define _PIPE_A_OUTPUT_CSC_POSTOFF_HI 0x49074 8395 #define _PIPE_A_OUTPUT_CSC_POSTOFF_ME 0x49078 8396 #define _PIPE_A_OUTPUT_CSC_POSTOFF_LO 0x4907c 8397 8398 #define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY 0x49150 8399 #define _PIPE_B_OUTPUT_CSC_COEFF_BY 0x49154 8400 #define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU 0x49158 8401 #define _PIPE_B_OUTPUT_CSC_COEFF_BU 0x4915c 8402 #define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV 0x49160 8403 #define _PIPE_B_OUTPUT_CSC_COEFF_BV 0x49164 8404 #define _PIPE_B_OUTPUT_CSC_PREOFF_HI 0x49168 8405 #define _PIPE_B_OUTPUT_CSC_PREOFF_ME 0x4916c 8406 #define _PIPE_B_OUTPUT_CSC_PREOFF_LO 0x49170 8407 #define _PIPE_B_OUTPUT_CSC_POSTOFF_HI 0x49174 8408 #define _PIPE_B_OUTPUT_CSC_POSTOFF_ME 0x49178 8409 #define _PIPE_B_OUTPUT_CSC_POSTOFF_LO 0x4917c 8410 8411 #define PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe,\ 8412 _PIPE_A_OUTPUT_CSC_COEFF_RY_GY,\ 8413 _PIPE_B_OUTPUT_CSC_COEFF_RY_GY) 8414 #define PIPE_CSC_OUTPUT_COEFF_BY(pipe) _MMIO_PIPE(pipe, \ 8415 _PIPE_A_OUTPUT_CSC_COEFF_BY, \ 8416 _PIPE_B_OUTPUT_CSC_COEFF_BY) 8417 #define PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, \ 8418 _PIPE_A_OUTPUT_CSC_COEFF_RU_GU, \ 8419 _PIPE_B_OUTPUT_CSC_COEFF_RU_GU) 8420 #define PIPE_CSC_OUTPUT_COEFF_BU(pipe) _MMIO_PIPE(pipe, \ 8421 _PIPE_A_OUTPUT_CSC_COEFF_BU, \ 8422 _PIPE_B_OUTPUT_CSC_COEFF_BU) 8423 #define PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, \ 8424 _PIPE_A_OUTPUT_CSC_COEFF_RV_GV, \ 8425 _PIPE_B_OUTPUT_CSC_COEFF_RV_GV) 8426 #define PIPE_CSC_OUTPUT_COEFF_BV(pipe) _MMIO_PIPE(pipe, \ 8427 _PIPE_A_OUTPUT_CSC_COEFF_BV, \ 8428 _PIPE_B_OUTPUT_CSC_COEFF_BV) 8429 #define PIPE_CSC_OUTPUT_PREOFF_HI(pipe) _MMIO_PIPE(pipe, \ 8430 _PIPE_A_OUTPUT_CSC_PREOFF_HI, \ 8431 _PIPE_B_OUTPUT_CSC_PREOFF_HI) 8432 #define PIPE_CSC_OUTPUT_PREOFF_ME(pipe) _MMIO_PIPE(pipe, \ 8433 _PIPE_A_OUTPUT_CSC_PREOFF_ME, \ 8434 _PIPE_B_OUTPUT_CSC_PREOFF_ME) 8435 #define PIPE_CSC_OUTPUT_PREOFF_LO(pipe) _MMIO_PIPE(pipe, \ 8436 _PIPE_A_OUTPUT_CSC_PREOFF_LO, \ 8437 _PIPE_B_OUTPUT_CSC_PREOFF_LO) 8438 #define PIPE_CSC_OUTPUT_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, \ 8439 _PIPE_A_OUTPUT_CSC_POSTOFF_HI, \ 8440 _PIPE_B_OUTPUT_CSC_POSTOFF_HI) 8441 #define PIPE_CSC_OUTPUT_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, \ 8442 _PIPE_A_OUTPUT_CSC_POSTOFF_ME, \ 8443 _PIPE_B_OUTPUT_CSC_POSTOFF_ME) 8444 #define PIPE_CSC_OUTPUT_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, \ 8445 _PIPE_A_OUTPUT_CSC_POSTOFF_LO, \ 8446 _PIPE_B_OUTPUT_CSC_POSTOFF_LO) 8447 8448 /* pipe degamma/gamma LUTs on IVB+ */ 8449 #define _PAL_PREC_INDEX_A 0x4A400 8450 #define _PAL_PREC_INDEX_B 0x4AC00 8451 #define _PAL_PREC_INDEX_C 0x4B400 8452 #define PAL_PREC_10_12_BIT (0 << 31) 8453 #define PAL_PREC_SPLIT_MODE (1 << 31) 8454 #define PAL_PREC_AUTO_INCREMENT (1 << 15) 8455 #define PAL_PREC_INDEX_VALUE_MASK (0x3ff << 0) 8456 #define PAL_PREC_INDEX_VALUE(x) ((x) << 0) 8457 #define _PAL_PREC_DATA_A 0x4A404 8458 #define _PAL_PREC_DATA_B 0x4AC04 8459 #define _PAL_PREC_DATA_C 0x4B404 8460 #define _PAL_PREC_GC_MAX_A 0x4A410 8461 #define _PAL_PREC_GC_MAX_B 0x4AC10 8462 #define _PAL_PREC_GC_MAX_C 0x4B410 8463 #define PREC_PAL_DATA_RED_MASK REG_GENMASK(29, 20) 8464 #define PREC_PAL_DATA_GREEN_MASK REG_GENMASK(19, 10) 8465 #define PREC_PAL_DATA_BLUE_MASK REG_GENMASK(9, 0) 8466 #define _PAL_PREC_EXT_GC_MAX_A 0x4A420 8467 #define _PAL_PREC_EXT_GC_MAX_B 0x4AC20 8468 #define _PAL_PREC_EXT_GC_MAX_C 0x4B420 8469 #define _PAL_PREC_EXT2_GC_MAX_A 0x4A430 8470 #define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30 8471 #define _PAL_PREC_EXT2_GC_MAX_C 0x4B430 8472 8473 #define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B) 8474 #define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B) 8475 #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4) 8476 #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4) 8477 #define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4) 8478 8479 #define _PRE_CSC_GAMC_INDEX_A 0x4A484 8480 #define _PRE_CSC_GAMC_INDEX_B 0x4AC84 8481 #define _PRE_CSC_GAMC_INDEX_C 0x4B484 8482 #define PRE_CSC_GAMC_AUTO_INCREMENT (1 << 10) 8483 #define _PRE_CSC_GAMC_DATA_A 0x4A488 8484 #define _PRE_CSC_GAMC_DATA_B 0x4AC88 8485 #define _PRE_CSC_GAMC_DATA_C 0x4B488 8486 8487 #define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B) 8488 #define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B) 8489 8490 /* ICL Multi segmented gamma */ 8491 #define _PAL_PREC_MULTI_SEG_INDEX_A 0x4A408 8492 #define _PAL_PREC_MULTI_SEG_INDEX_B 0x4AC08 8493 #define PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT REG_BIT(15) 8494 #define PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK REG_GENMASK(4, 0) 8495 8496 #define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C 8497 #define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C 8498 #define PAL_PREC_MULTI_SEG_RED_LDW_MASK REG_GENMASK(29, 24) 8499 #define PAL_PREC_MULTI_SEG_RED_UDW_MASK REG_GENMASK(29, 20) 8500 #define PAL_PREC_MULTI_SEG_GREEN_LDW_MASK REG_GENMASK(19, 14) 8501 #define PAL_PREC_MULTI_SEG_GREEN_UDW_MASK REG_GENMASK(19, 10) 8502 #define PAL_PREC_MULTI_SEG_BLUE_LDW_MASK REG_GENMASK(9, 4) 8503 #define PAL_PREC_MULTI_SEG_BLUE_UDW_MASK REG_GENMASK(9, 0) 8504 8505 #define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \ 8506 _PAL_PREC_MULTI_SEG_INDEX_A, \ 8507 _PAL_PREC_MULTI_SEG_INDEX_B) 8508 #define PREC_PAL_MULTI_SEG_DATA(pipe) _MMIO_PIPE(pipe, \ 8509 _PAL_PREC_MULTI_SEG_DATA_A, \ 8510 _PAL_PREC_MULTI_SEG_DATA_B) 8511 8512 #define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4) 8513 8514 /* Plane CSC Registers */ 8515 #define _PLANE_CSC_RY_GY_1_A 0x70210 8516 #define _PLANE_CSC_RY_GY_2_A 0x70310 8517 8518 #define _PLANE_CSC_RY_GY_1_B 0x71210 8519 #define _PLANE_CSC_RY_GY_2_B 0x71310 8520 8521 #define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \ 8522 _PLANE_CSC_RY_GY_1_B) 8523 #define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \ 8524 _PLANE_INPUT_CSC_RY_GY_2_B) 8525 #define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \ 8526 _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \ 8527 _PLANE_CSC_RY_GY_2(pipe) + (index) * 4) 8528 8529 #define _PLANE_CSC_PREOFF_HI_1_A 0x70228 8530 #define _PLANE_CSC_PREOFF_HI_2_A 0x70328 8531 8532 #define _PLANE_CSC_PREOFF_HI_1_B 0x71228 8533 #define _PLANE_CSC_PREOFF_HI_2_B 0x71328 8534 8535 #define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \ 8536 _PLANE_CSC_PREOFF_HI_1_B) 8537 #define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \ 8538 _PLANE_CSC_PREOFF_HI_2_B) 8539 #define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \ 8540 (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \ 8541 (index) * 4) 8542 8543 #define _PLANE_CSC_POSTOFF_HI_1_A 0x70234 8544 #define _PLANE_CSC_POSTOFF_HI_2_A 0x70334 8545 8546 #define _PLANE_CSC_POSTOFF_HI_1_B 0x71234 8547 #define _PLANE_CSC_POSTOFF_HI_2_B 0x71334 8548 8549 #define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \ 8550 _PLANE_CSC_POSTOFF_HI_1_B) 8551 #define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \ 8552 _PLANE_CSC_POSTOFF_HI_2_B) 8553 #define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \ 8554 (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \ 8555 (index) * 4) 8556 8557 /* pipe CSC & degamma/gamma LUTs on CHV */ 8558 #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900) 8559 #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904) 8560 #define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908) 8561 #define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C) 8562 #define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910) 8563 #define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000) 8564 #define CGM_PIPE_DEGAMMA_RED_MASK REG_GENMASK(13, 0) 8565 #define CGM_PIPE_DEGAMMA_GREEN_MASK REG_GENMASK(29, 16) 8566 #define CGM_PIPE_DEGAMMA_BLUE_MASK REG_GENMASK(13, 0) 8567 #define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000) 8568 #define CGM_PIPE_GAMMA_RED_MASK REG_GENMASK(9, 0) 8569 #define CGM_PIPE_GAMMA_GREEN_MASK REG_GENMASK(25, 16) 8570 #define CGM_PIPE_GAMMA_BLUE_MASK REG_GENMASK(9, 0) 8571 #define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00) 8572 #define CGM_PIPE_MODE_GAMMA (1 << 2) 8573 #define CGM_PIPE_MODE_CSC (1 << 1) 8574 #define CGM_PIPE_MODE_DEGAMMA (1 << 0) 8575 8576 #define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900) 8577 #define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904) 8578 #define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908) 8579 #define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C) 8580 #define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910) 8581 #define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000) 8582 #define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000) 8583 #define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00) 8584 8585 #define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01) 8586 #define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23) 8587 #define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45) 8588 #define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67) 8589 #define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8) 8590 #define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4) 8591 #define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4) 8592 #define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE) 8593 8594 /* MIPI DSI registers */ 8595 8596 #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */ 8597 #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c)) 8598 8599 /* Gen11 DSI */ 8600 #define _MMIO_DSI(tc, dsi0, dsi1) _MMIO_TRANS((tc) - TRANSCODER_DSI_0, \ 8601 dsi0, dsi1) 8602 8603 #define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004) 8604 #define GLK_TX_ESC_CLK_DIV1_MASK 0x3FF 8605 #define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008) 8606 #define GLK_TX_ESC_CLK_DIV2_MASK 0x3FF 8607 8608 #define _ICL_DSI_ESC_CLK_DIV0 0x6b090 8609 #define _ICL_DSI_ESC_CLK_DIV1 0x6b890 8610 #define ICL_DSI_ESC_CLK_DIV(port) _MMIO_PORT((port), \ 8611 _ICL_DSI_ESC_CLK_DIV0, \ 8612 _ICL_DSI_ESC_CLK_DIV1) 8613 #define _ICL_DPHY_ESC_CLK_DIV0 0x162190 8614 #define _ICL_DPHY_ESC_CLK_DIV1 0x6C190 8615 #define ICL_DPHY_ESC_CLK_DIV(port) _MMIO_PORT((port), \ 8616 _ICL_DPHY_ESC_CLK_DIV0, \ 8617 _ICL_DPHY_ESC_CLK_DIV1) 8618 #define ICL_BYTE_CLK_PER_ESC_CLK_MASK (0x1f << 16) 8619 #define ICL_BYTE_CLK_PER_ESC_CLK_SHIFT 16 8620 #define ICL_ESC_CLK_DIV_MASK 0x1ff 8621 #define ICL_ESC_CLK_DIV_SHIFT 0 8622 #define DSI_MAX_ESC_CLK 20000 /* in KHz */ 8623 8624 #define _ADL_MIPIO_REG 0x180 8625 #define ADL_MIPIO_DW(port, dw) _MMIO(_ICL_COMBOPHY(port) + _ADL_MIPIO_REG + 4 * (dw)) 8626 #define TX_ESC_CLK_DIV_PHY_SEL REGBIT(16) 8627 #define TX_ESC_CLK_DIV_PHY_MASK REG_GENMASK(23, 16) 8628 #define TX_ESC_CLK_DIV_PHY REG_FIELD_PREP(TX_ESC_CLK_DIV_PHY_MASK, 0x7f) 8629 8630 #define _DSI_CMD_FRMCTL_0 0x6b034 8631 #define _DSI_CMD_FRMCTL_1 0x6b834 8632 #define DSI_CMD_FRMCTL(port) _MMIO_PORT(port, \ 8633 _DSI_CMD_FRMCTL_0,\ 8634 _DSI_CMD_FRMCTL_1) 8635 #define DSI_FRAME_UPDATE_REQUEST (1 << 31) 8636 #define DSI_PERIODIC_FRAME_UPDATE_ENABLE (1 << 29) 8637 #define DSI_NULL_PACKET_ENABLE (1 << 28) 8638 #define DSI_FRAME_IN_PROGRESS (1 << 0) 8639 8640 #define _DSI_INTR_MASK_REG_0 0x6b070 8641 #define _DSI_INTR_MASK_REG_1 0x6b870 8642 #define DSI_INTR_MASK_REG(port) _MMIO_PORT(port, \ 8643 _DSI_INTR_MASK_REG_0,\ 8644 _DSI_INTR_MASK_REG_1) 8645 8646 #define _DSI_INTR_IDENT_REG_0 0x6b074 8647 #define _DSI_INTR_IDENT_REG_1 0x6b874 8648 #define DSI_INTR_IDENT_REG(port) _MMIO_PORT(port, \ 8649 _DSI_INTR_IDENT_REG_0,\ 8650 _DSI_INTR_IDENT_REG_1) 8651 #define DSI_TE_EVENT (1 << 31) 8652 #define DSI_RX_DATA_OR_BTA_TERMINATED (1 << 30) 8653 #define DSI_TX_DATA (1 << 29) 8654 #define DSI_ULPS_ENTRY_DONE (1 << 28) 8655 #define DSI_NON_TE_TRIGGER_RECEIVED (1 << 27) 8656 #define DSI_HOST_CHKSUM_ERROR (1 << 26) 8657 #define DSI_HOST_MULTI_ECC_ERROR (1 << 25) 8658 #define DSI_HOST_SINGL_ECC_ERROR (1 << 24) 8659 #define DSI_HOST_CONTENTION_DETECTED (1 << 23) 8660 #define DSI_HOST_FALSE_CONTROL_ERROR (1 << 22) 8661 #define DSI_HOST_TIMEOUT_ERROR (1 << 21) 8662 #define DSI_HOST_LOW_POWER_TX_SYNC_ERROR (1 << 20) 8663 #define DSI_HOST_ESCAPE_MODE_ENTRY_ERROR (1 << 19) 8664 #define DSI_FRAME_UPDATE_DONE (1 << 16) 8665 #define DSI_PROTOCOL_VIOLATION_REPORTED (1 << 15) 8666 #define DSI_INVALID_TX_LENGTH (1 << 13) 8667 #define DSI_INVALID_VC (1 << 12) 8668 #define DSI_INVALID_DATA_TYPE (1 << 11) 8669 #define DSI_PERIPHERAL_CHKSUM_ERROR (1 << 10) 8670 #define DSI_PERIPHERAL_MULTI_ECC_ERROR (1 << 9) 8671 #define DSI_PERIPHERAL_SINGLE_ECC_ERROR (1 << 8) 8672 #define DSI_PERIPHERAL_CONTENTION_DETECTED (1 << 7) 8673 #define DSI_PERIPHERAL_FALSE_CTRL_ERROR (1 << 6) 8674 #define DSI_PERIPHERAL_TIMEOUT_ERROR (1 << 5) 8675 #define DSI_PERIPHERAL_LP_TX_SYNC_ERROR (1 << 4) 8676 #define DSI_PERIPHERAL_ESC_MODE_ENTRY_CMD_ERR (1 << 3) 8677 #define DSI_EOT_SYNC_ERROR (1 << 2) 8678 #define DSI_SOT_SYNC_ERROR (1 << 1) 8679 #define DSI_SOT_ERROR (1 << 0) 8680 8681 /* Gen4+ Timestamp and Pipe Frame time stamp registers */ 8682 #define GEN4_TIMESTAMP _MMIO(0x2358) 8683 #define ILK_TIMESTAMP_HI _MMIO(0x70070) 8684 #define IVB_TIMESTAMP_CTR _MMIO(0x44070) 8685 8686 #define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074) 8687 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0 8688 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff 8689 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12 8690 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12) 8691 8692 #define _PIPE_FRMTMSTMP_A 0x70048 8693 #define PIPE_FRMTMSTMP(pipe) \ 8694 _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A) 8695 8696 /* BXT MIPI clock controls */ 8697 #define BXT_MAX_VAR_OUTPUT_KHZ 39500 8698 8699 #define BXT_MIPI_CLOCK_CTL _MMIO(0x46090) 8700 #define BXT_MIPI1_DIV_SHIFT 26 8701 #define BXT_MIPI2_DIV_SHIFT 10 8702 #define BXT_MIPI_DIV_SHIFT(port) \ 8703 _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \ 8704 BXT_MIPI2_DIV_SHIFT) 8705 8706 /* TX control divider to select actual TX clock output from (8x/var) */ 8707 #define BXT_MIPI1_TX_ESCLK_SHIFT 26 8708 #define BXT_MIPI2_TX_ESCLK_SHIFT 10 8709 #define BXT_MIPI_TX_ESCLK_SHIFT(port) \ 8710 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \ 8711 BXT_MIPI2_TX_ESCLK_SHIFT) 8712 #define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (0x3F << 26) 8713 #define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (0x3F << 10) 8714 #define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \ 8715 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \ 8716 BXT_MIPI2_TX_ESCLK_FIXDIV_MASK) 8717 #define BXT_MIPI_TX_ESCLK_DIVIDER(port, val) \ 8718 (((val) & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port)) 8719 /* RX upper control divider to select actual RX clock output from 8x */ 8720 #define BXT_MIPI1_RX_ESCLK_UPPER_SHIFT 21 8721 #define BXT_MIPI2_RX_ESCLK_UPPER_SHIFT 5 8722 #define BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port) \ 8723 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \ 8724 BXT_MIPI2_RX_ESCLK_UPPER_SHIFT) 8725 #define BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 21) 8726 #define BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 5) 8727 #define BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port) \ 8728 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \ 8729 BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK) 8730 #define BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val) \ 8731 (((val) & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port)) 8732 /* 8/3X divider to select the actual 8/3X clock output from 8x */ 8733 #define BXT_MIPI1_8X_BY3_SHIFT 19 8734 #define BXT_MIPI2_8X_BY3_SHIFT 3 8735 #define BXT_MIPI_8X_BY3_SHIFT(port) \ 8736 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \ 8737 BXT_MIPI2_8X_BY3_SHIFT) 8738 #define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19) 8739 #define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3) 8740 #define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \ 8741 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \ 8742 BXT_MIPI2_8X_BY3_DIVIDER_MASK) 8743 #define BXT_MIPI_8X_BY3_DIVIDER(port, val) \ 8744 (((val) & 3) << BXT_MIPI_8X_BY3_SHIFT(port)) 8745 /* RX lower control divider to select actual RX clock output from 8x */ 8746 #define BXT_MIPI1_RX_ESCLK_LOWER_SHIFT 16 8747 #define BXT_MIPI2_RX_ESCLK_LOWER_SHIFT 0 8748 #define BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port) \ 8749 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \ 8750 BXT_MIPI2_RX_ESCLK_LOWER_SHIFT) 8751 #define BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 16) 8752 #define BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 0) 8753 #define BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port) \ 8754 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \ 8755 BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK) 8756 #define BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val) \ 8757 (((val) & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port)) 8758 8759 #define RX_DIVIDER_BIT_1_2 0x3 8760 #define RX_DIVIDER_BIT_3_4 0xC 8761 8762 /* BXT MIPI mode configure */ 8763 #define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8 8764 #define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8 8765 #define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(tc, \ 8766 _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE) 8767 8768 #define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC 8769 #define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC 8770 #define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(tc, \ 8771 _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE) 8772 8773 #define _BXT_MIPIA_TRANS_VTOTAL 0x6B100 8774 #define _BXT_MIPIC_TRANS_VTOTAL 0x6B900 8775 #define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(tc, \ 8776 _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL) 8777 8778 #define BXT_DSI_PLL_CTL _MMIO(0x161000) 8779 #define BXT_DSI_PLL_PVD_RATIO_SHIFT 16 8780 #define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT) 8781 #define BXT_DSI_PLL_PVD_RATIO_1 (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT) 8782 #define BXT_DSIC_16X_BY1 (0 << 10) 8783 #define BXT_DSIC_16X_BY2 (1 << 10) 8784 #define BXT_DSIC_16X_BY3 (2 << 10) 8785 #define BXT_DSIC_16X_BY4 (3 << 10) 8786 #define BXT_DSIC_16X_MASK (3 << 10) 8787 #define BXT_DSIA_16X_BY1 (0 << 8) 8788 #define BXT_DSIA_16X_BY2 (1 << 8) 8789 #define BXT_DSIA_16X_BY3 (2 << 8) 8790 #define BXT_DSIA_16X_BY4 (3 << 8) 8791 #define BXT_DSIA_16X_MASK (3 << 8) 8792 #define BXT_DSI_FREQ_SEL_SHIFT 8 8793 #define BXT_DSI_FREQ_SEL_MASK (0xF << BXT_DSI_FREQ_SEL_SHIFT) 8794 8795 #define BXT_DSI_PLL_RATIO_MAX 0x7D 8796 #define BXT_DSI_PLL_RATIO_MIN 0x22 8797 #define GLK_DSI_PLL_RATIO_MAX 0x6F 8798 #define GLK_DSI_PLL_RATIO_MIN 0x22 8799 #define BXT_DSI_PLL_RATIO_MASK 0xFF 8800 #define BXT_REF_CLOCK_KHZ 19200 8801 8802 #define BXT_DSI_PLL_ENABLE _MMIO(0x46080) 8803 #define BXT_DSI_PLL_DO_ENABLE (1 << 31) 8804 #define BXT_DSI_PLL_LOCKED (1 << 30) 8805 8806 #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) 8807 #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) 8808 #define MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL) 8809 8810 /* BXT port control */ 8811 #define _BXT_MIPIA_PORT_CTRL 0x6B0C0 8812 #define _BXT_MIPIC_PORT_CTRL 0x6B8C0 8813 #define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL) 8814 8815 /* ICL DSI MODE control */ 8816 #define _ICL_DSI_IO_MODECTL_0 0x6B094 8817 #define _ICL_DSI_IO_MODECTL_1 0x6B894 8818 #define ICL_DSI_IO_MODECTL(port) _MMIO_PORT(port, \ 8819 _ICL_DSI_IO_MODECTL_0, \ 8820 _ICL_DSI_IO_MODECTL_1) 8821 #define COMBO_PHY_MODE_DSI (1 << 0) 8822 8823 /* TGL DSI Chicken register */ 8824 #define _TGL_DSI_CHKN_REG_0 0x6B0C0 8825 #define _TGL_DSI_CHKN_REG_1 0x6B8C0 8826 #define TGL_DSI_CHKN_REG(port) _MMIO_PORT(port, \ 8827 _TGL_DSI_CHKN_REG_0, \ 8828 _TGL_DSI_CHKN_REG_1) 8829 #define TGL_DSI_CHKN_LSHS_GB_MASK REG_GENMASK(15, 12) 8830 #define TGL_DSI_CHKN_LSHS_GB(byte_clocks) REG_FIELD_PREP(TGL_DSI_CHKN_LSHS_GB_MASK, \ 8831 (byte_clocks)) 8832 8833 /* Display Stream Splitter Control */ 8834 #define DSS_CTL1 _MMIO(0x67400) 8835 #define SPLITTER_ENABLE (1 << 31) 8836 #define JOINER_ENABLE (1 << 30) 8837 #define DUAL_LINK_MODE_INTERLEAVE (1 << 24) 8838 #define DUAL_LINK_MODE_FRONTBACK (0 << 24) 8839 #define OVERLAP_PIXELS_MASK (0xf << 16) 8840 #define OVERLAP_PIXELS(pixels) ((pixels) << 16) 8841 #define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) 8842 #define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) 8843 #define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0 8844 8845 #define DSS_CTL2 _MMIO(0x67404) 8846 #define LEFT_BRANCH_VDSC_ENABLE (1 << 31) 8847 #define RIGHT_BRANCH_VDSC_ENABLE (1 << 15) 8848 #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) 8849 #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) 8850 8851 #define _ICL_PIPE_DSS_CTL1_PB 0x78200 8852 #define _ICL_PIPE_DSS_CTL1_PC 0x78400 8853 #define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8854 _ICL_PIPE_DSS_CTL1_PB, \ 8855 _ICL_PIPE_DSS_CTL1_PC) 8856 #define BIG_JOINER_ENABLE (1 << 29) 8857 #define MASTER_BIG_JOINER_ENABLE (1 << 28) 8858 #define VGA_CENTERING_ENABLE (1 << 27) 8859 #define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25) 8860 #define SPLITTER_CONFIGURATION_2_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0) 8861 #define SPLITTER_CONFIGURATION_4_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1) 8862 #define UNCOMPRESSED_JOINER_MASTER (1 << 21) 8863 #define UNCOMPRESSED_JOINER_SLAVE (1 << 20) 8864 8865 #define _ICL_PIPE_DSS_CTL2_PB 0x78204 8866 #define _ICL_PIPE_DSS_CTL2_PC 0x78404 8867 #define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8868 _ICL_PIPE_DSS_CTL2_PB, \ 8869 _ICL_PIPE_DSS_CTL2_PC) 8870 8871 #define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020) 8872 #define STAP_SELECT (1 << 0) 8873 8874 #define BXT_P_DSI_REGULATOR_TX_CTRL _MMIO(0x160054) 8875 #define HS_IO_CTRL_SELECT (1 << 0) 8876 8877 #define DPI_ENABLE (1 << 31) /* A + C */ 8878 #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 8879 #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27) 8880 #define DUAL_LINK_MODE_SHIFT 26 8881 #define DUAL_LINK_MODE_MASK (1 << 26) 8882 #define DUAL_LINK_MODE_FRONT_BACK (0 << 26) 8883 #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26) 8884 #define DITHERING_ENABLE (1 << 25) /* A + C */ 8885 #define FLOPPED_HSTX (1 << 23) 8886 #define DE_INVERT (1 << 19) /* XXX */ 8887 #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18 8888 #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18) 8889 #define AFE_LATCHOUT (1 << 17) 8890 #define LP_OUTPUT_HOLD (1 << 16) 8891 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15 8892 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15) 8893 #define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11 8894 #define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11) 8895 #define CSB_SHIFT 9 8896 #define CSB_MASK (3 << 9) 8897 #define CSB_20MHZ (0 << 9) 8898 #define CSB_10MHZ (1 << 9) 8899 #define CSB_40MHZ (2 << 9) 8900 #define BANDGAP_MASK (1 << 8) 8901 #define BANDGAP_PNW_CIRCUIT (0 << 8) 8902 #define BANDGAP_LNC_CIRCUIT (1 << 8) 8903 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5 8904 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5) 8905 #define TEARING_EFFECT_DELAY (1 << 4) /* A + C */ 8906 #define TEARING_EFFECT_SHIFT 2 /* A + C */ 8907 #define TEARING_EFFECT_MASK (3 << 2) 8908 #define TEARING_EFFECT_OFF (0 << 2) 8909 #define TEARING_EFFECT_DSI (1 << 2) 8910 #define TEARING_EFFECT_GPIO (2 << 2) 8911 #define LANE_CONFIGURATION_SHIFT 0 8912 #define LANE_CONFIGURATION_MASK (3 << 0) 8913 #define LANE_CONFIGURATION_4LANE (0 << 0) 8914 #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0) 8915 #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0) 8916 8917 #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) 8918 #define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) 8919 #define MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) 8920 #define TEARING_EFFECT_DELAY_SHIFT 0 8921 #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) 8922 8923 /* XXX: all bits reserved */ 8924 #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0) 8925 8926 /* MIPI DSI Controller and D-PHY registers */ 8927 8928 #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000) 8929 #define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800) 8930 #define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY) 8931 #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */ 8932 #define ULPS_STATE_MASK (3 << 1) 8933 #define ULPS_STATE_ENTER (2 << 1) 8934 #define ULPS_STATE_EXIT (1 << 1) 8935 #define ULPS_STATE_NORMAL_OPERATION (0 << 1) 8936 #define DEVICE_READY (1 << 0) 8937 8938 #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004) 8939 #define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804) 8940 #define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT) 8941 #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008) 8942 #define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808) 8943 #define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN) 8944 #define TEARING_EFFECT (1 << 31) 8945 #define SPL_PKT_SENT_INTERRUPT (1 << 30) 8946 #define GEN_READ_DATA_AVAIL (1 << 29) 8947 #define LP_GENERIC_WR_FIFO_FULL (1 << 28) 8948 #define HS_GENERIC_WR_FIFO_FULL (1 << 27) 8949 #define RX_PROT_VIOLATION (1 << 26) 8950 #define RX_INVALID_TX_LENGTH (1 << 25) 8951 #define ACK_WITH_NO_ERROR (1 << 24) 8952 #define TURN_AROUND_ACK_TIMEOUT (1 << 23) 8953 #define LP_RX_TIMEOUT (1 << 22) 8954 #define HS_TX_TIMEOUT (1 << 21) 8955 #define DPI_FIFO_UNDERRUN (1 << 20) 8956 #define LOW_CONTENTION (1 << 19) 8957 #define HIGH_CONTENTION (1 << 18) 8958 #define TXDSI_VC_ID_INVALID (1 << 17) 8959 #define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16) 8960 #define TXCHECKSUM_ERROR (1 << 15) 8961 #define TXECC_MULTIBIT_ERROR (1 << 14) 8962 #define TXECC_SINGLE_BIT_ERROR (1 << 13) 8963 #define TXFALSE_CONTROL_ERROR (1 << 12) 8964 #define RXDSI_VC_ID_INVALID (1 << 11) 8965 #define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10) 8966 #define RXCHECKSUM_ERROR (1 << 9) 8967 #define RXECC_MULTIBIT_ERROR (1 << 8) 8968 #define RXECC_SINGLE_BIT_ERROR (1 << 7) 8969 #define RXFALSE_CONTROL_ERROR (1 << 6) 8970 #define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5) 8971 #define RX_LP_TX_SYNC_ERROR (1 << 4) 8972 #define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3) 8973 #define RXEOT_SYNC_ERROR (1 << 2) 8974 #define RXSOT_SYNC_ERROR (1 << 1) 8975 #define RXSOT_ERROR (1 << 0) 8976 8977 #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c) 8978 #define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c) 8979 #define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG) 8980 #define CMD_MODE_DATA_WIDTH_MASK (7 << 13) 8981 #define CMD_MODE_NOT_SUPPORTED (0 << 13) 8982 #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13) 8983 #define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13) 8984 #define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13) 8985 #define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13) 8986 #define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13) 8987 #define VID_MODE_FORMAT_MASK (0xf << 7) 8988 #define VID_MODE_NOT_SUPPORTED (0 << 7) 8989 #define VID_MODE_FORMAT_RGB565 (1 << 7) 8990 #define VID_MODE_FORMAT_RGB666_PACKED (2 << 7) 8991 #define VID_MODE_FORMAT_RGB666 (3 << 7) 8992 #define VID_MODE_FORMAT_RGB888 (4 << 7) 8993 #define CMD_MODE_CHANNEL_NUMBER_SHIFT 5 8994 #define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5) 8995 #define VID_MODE_CHANNEL_NUMBER_SHIFT 3 8996 #define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3) 8997 #define DATA_LANES_PRG_REG_SHIFT 0 8998 #define DATA_LANES_PRG_REG_MASK (7 << 0) 8999 9000 #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010) 9001 #define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810) 9002 #define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT) 9003 #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff 9004 9005 #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014) 9006 #define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814) 9007 #define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT) 9008 #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff 9009 9010 #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018) 9011 #define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818) 9012 #define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT) 9013 #define TURN_AROUND_TIMEOUT_MASK 0x3f 9014 9015 #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c) 9016 #define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c) 9017 #define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER) 9018 #define DEVICE_RESET_TIMER_MASK 0xffff 9019 9020 #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020) 9021 #define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820) 9022 #define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION) 9023 #define VERTICAL_ADDRESS_SHIFT 16 9024 #define VERTICAL_ADDRESS_MASK (0xffff << 16) 9025 #define HORIZONTAL_ADDRESS_SHIFT 0 9026 #define HORIZONTAL_ADDRESS_MASK 0xffff 9027 9028 #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024) 9029 #define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824) 9030 #define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE) 9031 #define DBI_FIFO_EMPTY_HALF (0 << 0) 9032 #define DBI_FIFO_EMPTY_QUARTER (1 << 0) 9033 #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0) 9034 9035 /* regs below are bits 15:0 */ 9036 #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028) 9037 #define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828) 9038 #define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT) 9039 9040 #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c) 9041 #define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c) 9042 #define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT) 9043 9044 #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030) 9045 #define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830) 9046 #define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT) 9047 9048 #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034) 9049 #define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834) 9050 #define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT) 9051 9052 #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038) 9053 #define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838) 9054 #define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT) 9055 9056 #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c) 9057 #define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c) 9058 #define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT) 9059 9060 #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040) 9061 #define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840) 9062 #define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT) 9063 9064 #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044) 9065 #define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844) 9066 #define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT) 9067 9068 /* regs above are bits 15:0 */ 9069 9070 #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048) 9071 #define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848) 9072 #define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL) 9073 #define DPI_LP_MODE (1 << 6) 9074 #define BACKLIGHT_OFF (1 << 5) 9075 #define BACKLIGHT_ON (1 << 4) 9076 #define COLOR_MODE_OFF (1 << 3) 9077 #define COLOR_MODE_ON (1 << 2) 9078 #define TURN_ON (1 << 1) 9079 #define SHUTDOWN (1 << 0) 9080 9081 #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c) 9082 #define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c) 9083 #define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA) 9084 #define COMMAND_BYTE_SHIFT 0 9085 #define COMMAND_BYTE_MASK (0x3f << 0) 9086 9087 #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050) 9088 #define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850) 9089 #define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT) 9090 #define MASTER_INIT_TIMER_SHIFT 0 9091 #define MASTER_INIT_TIMER_MASK (0xffff << 0) 9092 9093 #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054) 9094 #define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854) 9095 #define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \ 9096 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE) 9097 #define MAX_RETURN_PKT_SIZE_SHIFT 0 9098 #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) 9099 9100 #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058) 9101 #define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858) 9102 #define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT) 9103 #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) 9104 #define DISABLE_VIDEO_BTA (1 << 3) 9105 #define IP_TG_CONFIG (1 << 2) 9106 #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0) 9107 #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0) 9108 #define VIDEO_MODE_BURST (3 << 0) 9109 9110 #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c) 9111 #define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c) 9112 #define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE) 9113 #define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9) 9114 #define BXT_DPHY_DEFEATURE_EN (1 << 8) 9115 #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) 9116 #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6) 9117 #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5) 9118 #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4) 9119 #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3) 9120 #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2) 9121 #define CLOCKSTOP (1 << 1) 9122 #define EOT_DISABLE (1 << 0) 9123 9124 #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060) 9125 #define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860) 9126 #define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK) 9127 #define LP_BYTECLK_SHIFT 0 9128 #define LP_BYTECLK_MASK (0xffff << 0) 9129 9130 #define _MIPIA_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb0a4) 9131 #define _MIPIC_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb8a4) 9132 #define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT) 9133 9134 #define _MIPIA_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb098) 9135 #define _MIPIC_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb898) 9136 #define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING) 9137 9138 /* bits 31:0 */ 9139 #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064) 9140 #define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864) 9141 #define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA) 9142 9143 /* bits 31:0 */ 9144 #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068) 9145 #define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868) 9146 #define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA) 9147 9148 #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c) 9149 #define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c) 9150 #define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL) 9151 #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070) 9152 #define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870) 9153 #define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL) 9154 #define LONG_PACKET_WORD_COUNT_SHIFT 8 9155 #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8) 9156 #define SHORT_PACKET_PARAM_SHIFT 8 9157 #define SHORT_PACKET_PARAM_MASK (0xffff << 8) 9158 #define VIRTUAL_CHANNEL_SHIFT 6 9159 #define VIRTUAL_CHANNEL_MASK (3 << 6) 9160 #define DATA_TYPE_SHIFT 0 9161 #define DATA_TYPE_MASK (0x3f << 0) 9162 /* data type values, see include/video/mipi_display.h */ 9163 9164 #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074) 9165 #define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874) 9166 #define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT) 9167 #define DPI_FIFO_EMPTY (1 << 28) 9168 #define DBI_FIFO_EMPTY (1 << 27) 9169 #define LP_CTRL_FIFO_EMPTY (1 << 26) 9170 #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25) 9171 #define LP_CTRL_FIFO_FULL (1 << 24) 9172 #define HS_CTRL_FIFO_EMPTY (1 << 18) 9173 #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17) 9174 #define HS_CTRL_FIFO_FULL (1 << 16) 9175 #define LP_DATA_FIFO_EMPTY (1 << 10) 9176 #define LP_DATA_FIFO_HALF_EMPTY (1 << 9) 9177 #define LP_DATA_FIFO_FULL (1 << 8) 9178 #define HS_DATA_FIFO_EMPTY (1 << 2) 9179 #define HS_DATA_FIFO_HALF_EMPTY (1 << 1) 9180 #define HS_DATA_FIFO_FULL (1 << 0) 9181 9182 #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078) 9183 #define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878) 9184 #define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE) 9185 #define DBI_HS_LP_MODE_MASK (1 << 0) 9186 #define DBI_LP_MODE (1 << 0) 9187 #define DBI_HS_MODE (0 << 0) 9188 9189 #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080) 9190 #define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880) 9191 #define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM) 9192 #define EXIT_ZERO_COUNT_SHIFT 24 9193 #define EXIT_ZERO_COUNT_MASK (0x3f << 24) 9194 #define TRAIL_COUNT_SHIFT 16 9195 #define TRAIL_COUNT_MASK (0x1f << 16) 9196 #define CLK_ZERO_COUNT_SHIFT 8 9197 #define CLK_ZERO_COUNT_MASK (0xff << 8) 9198 #define PREPARE_COUNT_SHIFT 0 9199 #define PREPARE_COUNT_MASK (0x3f << 0) 9200 9201 #define _ICL_DSI_T_INIT_MASTER_0 0x6b088 9202 #define _ICL_DSI_T_INIT_MASTER_1 0x6b888 9203 #define ICL_DSI_T_INIT_MASTER(port) _MMIO_PORT(port, \ 9204 _ICL_DSI_T_INIT_MASTER_0,\ 9205 _ICL_DSI_T_INIT_MASTER_1) 9206 9207 #define _DPHY_CLK_TIMING_PARAM_0 0x162180 9208 #define _DPHY_CLK_TIMING_PARAM_1 0x6c180 9209 #define DPHY_CLK_TIMING_PARAM(port) _MMIO_PORT(port, \ 9210 _DPHY_CLK_TIMING_PARAM_0,\ 9211 _DPHY_CLK_TIMING_PARAM_1) 9212 #define _DSI_CLK_TIMING_PARAM_0 0x6b080 9213 #define _DSI_CLK_TIMING_PARAM_1 0x6b880 9214 #define DSI_CLK_TIMING_PARAM(port) _MMIO_PORT(port, \ 9215 _DSI_CLK_TIMING_PARAM_0,\ 9216 _DSI_CLK_TIMING_PARAM_1) 9217 #define CLK_PREPARE_OVERRIDE (1 << 31) 9218 #define CLK_PREPARE(x) ((x) << 28) 9219 #define CLK_PREPARE_MASK (0x7 << 28) 9220 #define CLK_PREPARE_SHIFT 28 9221 #define CLK_ZERO_OVERRIDE (1 << 27) 9222 #define CLK_ZERO(x) ((x) << 20) 9223 #define CLK_ZERO_MASK (0xf << 20) 9224 #define CLK_ZERO_SHIFT 20 9225 #define CLK_PRE_OVERRIDE (1 << 19) 9226 #define CLK_PRE(x) ((x) << 16) 9227 #define CLK_PRE_MASK (0x3 << 16) 9228 #define CLK_PRE_SHIFT 16 9229 #define CLK_POST_OVERRIDE (1 << 15) 9230 #define CLK_POST(x) ((x) << 8) 9231 #define CLK_POST_MASK (0x7 << 8) 9232 #define CLK_POST_SHIFT 8 9233 #define CLK_TRAIL_OVERRIDE (1 << 7) 9234 #define CLK_TRAIL(x) ((x) << 0) 9235 #define CLK_TRAIL_MASK (0xf << 0) 9236 #define CLK_TRAIL_SHIFT 0 9237 9238 #define _DPHY_DATA_TIMING_PARAM_0 0x162184 9239 #define _DPHY_DATA_TIMING_PARAM_1 0x6c184 9240 #define DPHY_DATA_TIMING_PARAM(port) _MMIO_PORT(port, \ 9241 _DPHY_DATA_TIMING_PARAM_0,\ 9242 _DPHY_DATA_TIMING_PARAM_1) 9243 #define _DSI_DATA_TIMING_PARAM_0 0x6B084 9244 #define _DSI_DATA_TIMING_PARAM_1 0x6B884 9245 #define DSI_DATA_TIMING_PARAM(port) _MMIO_PORT(port, \ 9246 _DSI_DATA_TIMING_PARAM_0,\ 9247 _DSI_DATA_TIMING_PARAM_1) 9248 #define HS_PREPARE_OVERRIDE (1 << 31) 9249 #define HS_PREPARE(x) ((x) << 24) 9250 #define HS_PREPARE_MASK (0x7 << 24) 9251 #define HS_PREPARE_SHIFT 24 9252 #define HS_ZERO_OVERRIDE (1 << 23) 9253 #define HS_ZERO(x) ((x) << 16) 9254 #define HS_ZERO_MASK (0xf << 16) 9255 #define HS_ZERO_SHIFT 16 9256 #define HS_TRAIL_OVERRIDE (1 << 15) 9257 #define HS_TRAIL(x) ((x) << 8) 9258 #define HS_TRAIL_MASK (0x7 << 8) 9259 #define HS_TRAIL_SHIFT 8 9260 #define HS_EXIT_OVERRIDE (1 << 7) 9261 #define HS_EXIT(x) ((x) << 0) 9262 #define HS_EXIT_MASK (0x7 << 0) 9263 #define HS_EXIT_SHIFT 0 9264 9265 #define _DPHY_TA_TIMING_PARAM_0 0x162188 9266 #define _DPHY_TA_TIMING_PARAM_1 0x6c188 9267 #define DPHY_TA_TIMING_PARAM(port) _MMIO_PORT(port, \ 9268 _DPHY_TA_TIMING_PARAM_0,\ 9269 _DPHY_TA_TIMING_PARAM_1) 9270 #define _DSI_TA_TIMING_PARAM_0 0x6b098 9271 #define _DSI_TA_TIMING_PARAM_1 0x6b898 9272 #define DSI_TA_TIMING_PARAM(port) _MMIO_PORT(port, \ 9273 _DSI_TA_TIMING_PARAM_0,\ 9274 _DSI_TA_TIMING_PARAM_1) 9275 #define TA_SURE_OVERRIDE (1 << 31) 9276 #define TA_SURE(x) ((x) << 16) 9277 #define TA_SURE_MASK (0x1f << 16) 9278 #define TA_SURE_SHIFT 16 9279 #define TA_GO_OVERRIDE (1 << 15) 9280 #define TA_GO(x) ((x) << 8) 9281 #define TA_GO_MASK (0xf << 8) 9282 #define TA_GO_SHIFT 8 9283 #define TA_GET_OVERRIDE (1 << 7) 9284 #define TA_GET(x) ((x) << 0) 9285 #define TA_GET_MASK (0xf << 0) 9286 #define TA_GET_SHIFT 0 9287 9288 /* DSI transcoder configuration */ 9289 #define _DSI_TRANS_FUNC_CONF_0 0x6b030 9290 #define _DSI_TRANS_FUNC_CONF_1 0x6b830 9291 #define DSI_TRANS_FUNC_CONF(tc) _MMIO_DSI(tc, \ 9292 _DSI_TRANS_FUNC_CONF_0,\ 9293 _DSI_TRANS_FUNC_CONF_1) 9294 #define OP_MODE_MASK (0x3 << 28) 9295 #define OP_MODE_SHIFT 28 9296 #define CMD_MODE_NO_GATE (0x0 << 28) 9297 #define CMD_MODE_TE_GATE (0x1 << 28) 9298 #define VIDEO_MODE_SYNC_EVENT (0x2 << 28) 9299 #define VIDEO_MODE_SYNC_PULSE (0x3 << 28) 9300 #define TE_SOURCE_GPIO (1 << 27) 9301 #define LINK_READY (1 << 20) 9302 #define PIX_FMT_MASK (0x3 << 16) 9303 #define PIX_FMT_SHIFT 16 9304 #define PIX_FMT_RGB565 (0x0 << 16) 9305 #define PIX_FMT_RGB666_PACKED (0x1 << 16) 9306 #define PIX_FMT_RGB666_LOOSE (0x2 << 16) 9307 #define PIX_FMT_RGB888 (0x3 << 16) 9308 #define PIX_FMT_RGB101010 (0x4 << 16) 9309 #define PIX_FMT_RGB121212 (0x5 << 16) 9310 #define PIX_FMT_COMPRESSED (0x6 << 16) 9311 #define BGR_TRANSMISSION (1 << 15) 9312 #define PIX_VIRT_CHAN(x) ((x) << 12) 9313 #define PIX_VIRT_CHAN_MASK (0x3 << 12) 9314 #define PIX_VIRT_CHAN_SHIFT 12 9315 #define PIX_BUF_THRESHOLD_MASK (0x3 << 10) 9316 #define PIX_BUF_THRESHOLD_SHIFT 10 9317 #define PIX_BUF_THRESHOLD_1_4 (0x0 << 10) 9318 #define PIX_BUF_THRESHOLD_1_2 (0x1 << 10) 9319 #define PIX_BUF_THRESHOLD_3_4 (0x2 << 10) 9320 #define PIX_BUF_THRESHOLD_FULL (0x3 << 10) 9321 #define CONTINUOUS_CLK_MASK (0x3 << 8) 9322 #define CONTINUOUS_CLK_SHIFT 8 9323 #define CLK_ENTER_LP_AFTER_DATA (0x0 << 8) 9324 #define CLK_HS_OR_LP (0x2 << 8) 9325 #define CLK_HS_CONTINUOUS (0x3 << 8) 9326 #define LINK_CALIBRATION_MASK (0x3 << 4) 9327 #define LINK_CALIBRATION_SHIFT 4 9328 #define CALIBRATION_DISABLED (0x0 << 4) 9329 #define CALIBRATION_ENABLED_INITIAL_ONLY (0x2 << 4) 9330 #define CALIBRATION_ENABLED_INITIAL_PERIODIC (0x3 << 4) 9331 #define BLANKING_PACKET_ENABLE (1 << 2) 9332 #define S3D_ORIENTATION_LANDSCAPE (1 << 1) 9333 #define EOTP_DISABLED (1 << 0) 9334 9335 #define _DSI_CMD_RXCTL_0 0x6b0d4 9336 #define _DSI_CMD_RXCTL_1 0x6b8d4 9337 #define DSI_CMD_RXCTL(tc) _MMIO_DSI(tc, \ 9338 _DSI_CMD_RXCTL_0,\ 9339 _DSI_CMD_RXCTL_1) 9340 #define READ_UNLOADS_DW (1 << 16) 9341 #define RECEIVED_UNASSIGNED_TRIGGER (1 << 15) 9342 #define RECEIVED_ACKNOWLEDGE_TRIGGER (1 << 14) 9343 #define RECEIVED_TEAR_EFFECT_TRIGGER (1 << 13) 9344 #define RECEIVED_RESET_TRIGGER (1 << 12) 9345 #define RECEIVED_PAYLOAD_WAS_LOST (1 << 11) 9346 #define RECEIVED_CRC_WAS_LOST (1 << 10) 9347 #define NUMBER_RX_PLOAD_DW_MASK (0xff << 0) 9348 #define NUMBER_RX_PLOAD_DW_SHIFT 0 9349 9350 #define _DSI_CMD_TXCTL_0 0x6b0d0 9351 #define _DSI_CMD_TXCTL_1 0x6b8d0 9352 #define DSI_CMD_TXCTL(tc) _MMIO_DSI(tc, \ 9353 _DSI_CMD_TXCTL_0,\ 9354 _DSI_CMD_TXCTL_1) 9355 #define KEEP_LINK_IN_HS (1 << 24) 9356 #define FREE_HEADER_CREDIT_MASK (0x1f << 8) 9357 #define FREE_HEADER_CREDIT_SHIFT 0x8 9358 #define FREE_PLOAD_CREDIT_MASK (0xff << 0) 9359 #define FREE_PLOAD_CREDIT_SHIFT 0 9360 #define MAX_HEADER_CREDIT 0x10 9361 #define MAX_PLOAD_CREDIT 0x40 9362 9363 #define _DSI_CMD_TXHDR_0 0x6b100 9364 #define _DSI_CMD_TXHDR_1 0x6b900 9365 #define DSI_CMD_TXHDR(tc) _MMIO_DSI(tc, \ 9366 _DSI_CMD_TXHDR_0,\ 9367 _DSI_CMD_TXHDR_1) 9368 #define PAYLOAD_PRESENT (1 << 31) 9369 #define LP_DATA_TRANSFER (1 << 30) 9370 #define VBLANK_FENCE (1 << 29) 9371 #define PARAM_WC_MASK (0xffff << 8) 9372 #define PARAM_WC_LOWER_SHIFT 8 9373 #define PARAM_WC_UPPER_SHIFT 16 9374 #define VC_MASK (0x3 << 6) 9375 #define VC_SHIFT 6 9376 #define DT_MASK (0x3f << 0) 9377 #define DT_SHIFT 0 9378 9379 #define _DSI_CMD_TXPYLD_0 0x6b104 9380 #define _DSI_CMD_TXPYLD_1 0x6b904 9381 #define DSI_CMD_TXPYLD(tc) _MMIO_DSI(tc, \ 9382 _DSI_CMD_TXPYLD_0,\ 9383 _DSI_CMD_TXPYLD_1) 9384 9385 #define _DSI_LP_MSG_0 0x6b0d8 9386 #define _DSI_LP_MSG_1 0x6b8d8 9387 #define DSI_LP_MSG(tc) _MMIO_DSI(tc, \ 9388 _DSI_LP_MSG_0,\ 9389 _DSI_LP_MSG_1) 9390 #define LPTX_IN_PROGRESS (1 << 17) 9391 #define LINK_IN_ULPS (1 << 16) 9392 #define LINK_ULPS_TYPE_LP11 (1 << 8) 9393 #define LINK_ENTER_ULPS (1 << 0) 9394 9395 /* DSI timeout registers */ 9396 #define _DSI_HSTX_TO_0 0x6b044 9397 #define _DSI_HSTX_TO_1 0x6b844 9398 #define DSI_HSTX_TO(tc) _MMIO_DSI(tc, \ 9399 _DSI_HSTX_TO_0,\ 9400 _DSI_HSTX_TO_1) 9401 #define HSTX_TIMEOUT_VALUE_MASK (0xffff << 16) 9402 #define HSTX_TIMEOUT_VALUE_SHIFT 16 9403 #define HSTX_TIMEOUT_VALUE(x) ((x) << 16) 9404 #define HSTX_TIMED_OUT (1 << 0) 9405 9406 #define _DSI_LPRX_HOST_TO_0 0x6b048 9407 #define _DSI_LPRX_HOST_TO_1 0x6b848 9408 #define DSI_LPRX_HOST_TO(tc) _MMIO_DSI(tc, \ 9409 _DSI_LPRX_HOST_TO_0,\ 9410 _DSI_LPRX_HOST_TO_1) 9411 #define LPRX_TIMED_OUT (1 << 16) 9412 #define LPRX_TIMEOUT_VALUE_MASK (0xffff << 0) 9413 #define LPRX_TIMEOUT_VALUE_SHIFT 0 9414 #define LPRX_TIMEOUT_VALUE(x) ((x) << 0) 9415 9416 #define _DSI_PWAIT_TO_0 0x6b040 9417 #define _DSI_PWAIT_TO_1 0x6b840 9418 #define DSI_PWAIT_TO(tc) _MMIO_DSI(tc, \ 9419 _DSI_PWAIT_TO_0,\ 9420 _DSI_PWAIT_TO_1) 9421 #define PRESET_TIMEOUT_VALUE_MASK (0xffff << 16) 9422 #define PRESET_TIMEOUT_VALUE_SHIFT 16 9423 #define PRESET_TIMEOUT_VALUE(x) ((x) << 16) 9424 #define PRESPONSE_TIMEOUT_VALUE_MASK (0xffff << 0) 9425 #define PRESPONSE_TIMEOUT_VALUE_SHIFT 0 9426 #define PRESPONSE_TIMEOUT_VALUE(x) ((x) << 0) 9427 9428 #define _DSI_TA_TO_0 0x6b04c 9429 #define _DSI_TA_TO_1 0x6b84c 9430 #define DSI_TA_TO(tc) _MMIO_DSI(tc, \ 9431 _DSI_TA_TO_0,\ 9432 _DSI_TA_TO_1) 9433 #define TA_TIMED_OUT (1 << 16) 9434 #define TA_TIMEOUT_VALUE_MASK (0xffff << 0) 9435 #define TA_TIMEOUT_VALUE_SHIFT 0 9436 #define TA_TIMEOUT_VALUE(x) ((x) << 0) 9437 9438 /* bits 31:0 */ 9439 #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084) 9440 #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884) 9441 #define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL) 9442 9443 #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb088) 9444 #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb888) 9445 #define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT) 9446 #define LP_HS_SSW_CNT_SHIFT 16 9447 #define LP_HS_SSW_CNT_MASK (0xffff << 16) 9448 #define HS_LP_PWR_SW_CNT_SHIFT 0 9449 #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0) 9450 9451 #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c) 9452 #define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c) 9453 #define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL) 9454 #define STOP_STATE_STALL_COUNTER_SHIFT 0 9455 #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) 9456 9457 #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090) 9458 #define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890) 9459 #define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1) 9460 #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094) 9461 #define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894) 9462 #define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1) 9463 #define RX_CONTENTION_DETECTED (1 << 0) 9464 9465 /* XXX: only pipe A ?!? */ 9466 #define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100) 9467 #define DBI_TYPEC_ENABLE (1 << 31) 9468 #define DBI_TYPEC_WIP (1 << 30) 9469 #define DBI_TYPEC_OPTION_SHIFT 28 9470 #define DBI_TYPEC_OPTION_MASK (3 << 28) 9471 #define DBI_TYPEC_FREQ_SHIFT 24 9472 #define DBI_TYPEC_FREQ_MASK (0xf << 24) 9473 #define DBI_TYPEC_OVERRIDE (1 << 8) 9474 #define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0 9475 #define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0) 9476 9477 9478 /* MIPI adapter registers */ 9479 9480 #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104) 9481 #define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904) 9482 #define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL) 9483 #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */ 9484 #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) 9485 #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5) 9486 #define ESCAPE_CLOCK_DIVIDER_2 (1 << 5) 9487 #define ESCAPE_CLOCK_DIVIDER_4 (2 << 5) 9488 #define READ_REQUEST_PRIORITY_SHIFT 3 9489 #define READ_REQUEST_PRIORITY_MASK (3 << 3) 9490 #define READ_REQUEST_PRIORITY_LOW (0 << 3) 9491 #define READ_REQUEST_PRIORITY_HIGH (3 << 3) 9492 #define RGB_FLIP_TO_BGR (1 << 2) 9493 9494 #define BXT_PIPE_SELECT_SHIFT 7 9495 #define BXT_PIPE_SELECT_MASK (7 << 7) 9496 #define BXT_PIPE_SELECT(pipe) ((pipe) << 7) 9497 #define GLK_PHY_STATUS_PORT_READY (1 << 31) /* RO */ 9498 #define GLK_ULPS_NOT_ACTIVE (1 << 30) /* RO */ 9499 #define GLK_MIPIIO_RESET_RELEASED (1 << 28) 9500 #define GLK_CLOCK_LANE_STOP_STATE (1 << 27) /* RO */ 9501 #define GLK_DATA_LANE_STOP_STATE (1 << 26) /* RO */ 9502 #define GLK_LP_WAKE (1 << 22) 9503 #define GLK_LP11_LOW_PWR_MODE (1 << 21) 9504 #define GLK_LP00_LOW_PWR_MODE (1 << 20) 9505 #define GLK_FIREWALL_ENABLE (1 << 16) 9506 #define BXT_PIXEL_OVERLAP_CNT_MASK (0xf << 10) 9507 #define BXT_PIXEL_OVERLAP_CNT_SHIFT 10 9508 #define BXT_DSC_ENABLE (1 << 3) 9509 #define BXT_RGB_FLIP (1 << 2) 9510 #define GLK_MIPIIO_PORT_POWERED (1 << 1) /* RO */ 9511 #define GLK_MIPIIO_ENABLE (1 << 0) 9512 9513 #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108) 9514 #define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908) 9515 #define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS) 9516 #define DATA_MEM_ADDRESS_SHIFT 5 9517 #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) 9518 #define DATA_VALID (1 << 0) 9519 9520 #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c) 9521 #define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c) 9522 #define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH) 9523 #define DATA_LENGTH_SHIFT 0 9524 #define DATA_LENGTH_MASK (0xfffff << 0) 9525 9526 #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110) 9527 #define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910) 9528 #define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS) 9529 #define COMMAND_MEM_ADDRESS_SHIFT 5 9530 #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) 9531 #define AUTO_PWG_ENABLE (1 << 2) 9532 #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1) 9533 #define COMMAND_VALID (1 << 0) 9534 9535 #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114) 9536 #define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914) 9537 #define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH) 9538 #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */ 9539 #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n))) 9540 9541 #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118) 9542 #define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918) 9543 #define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */ 9544 9545 #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138) 9546 #define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938) 9547 #define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID) 9548 #define READ_DATA_VALID(n) (1 << (n)) 9549 9550 #define GEN12_GSMBASE _MMIO(0x108100) 9551 #define GEN12_DSMBASE _MMIO(0x1080C0) 9552 9553 #define XEHP_CLOCK_GATE_DIS _MMIO(0x101014) 9554 #define SGSI_SIDECLK_DIS REG_BIT(17) 9555 #define SGGI_DIS REG_BIT(15) 9556 #define SGR_DIS REG_BIT(13) 9557 9558 #define _ICL_PHY_MISC_A 0x64C00 9559 #define _ICL_PHY_MISC_B 0x64C04 9560 #define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, \ 9561 _ICL_PHY_MISC_B) 9562 #define ICL_PHY_MISC_MUX_DDID (1 << 28) 9563 #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23) 9564 #define DG2_PHY_DP_TX_ACK_MASK REG_GENMASK(23, 20) 9565 9566 /* Icelake Display Stream Compression Registers */ 9567 #define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200) 9568 #define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00) 9569 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270 9570 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370 9571 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470 9572 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570 9573 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9574 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \ 9575 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC) 9576 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9577 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \ 9578 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC) 9579 #define DSC_VBR_ENABLE (1 << 19) 9580 #define DSC_422_ENABLE (1 << 18) 9581 #define DSC_COLOR_SPACE_CONVERSION (1 << 17) 9582 #define DSC_BLOCK_PREDICTION (1 << 16) 9583 #define DSC_LINE_BUF_DEPTH_SHIFT 12 9584 #define DSC_BPC_SHIFT 8 9585 #define DSC_VER_MIN_SHIFT 4 9586 #define DSC_VER_MAJ (0x1 << 0) 9587 9588 #define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204) 9589 #define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04) 9590 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274 9591 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374 9592 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474 9593 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC 0x78574 9594 #define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9595 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \ 9596 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC) 9597 #define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9598 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \ 9599 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC) 9600 #define DSC_BPP(bpp) ((bpp) << 0) 9601 9602 #define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208) 9603 #define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08) 9604 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278 9605 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378 9606 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478 9607 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC 0x78578 9608 #define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9609 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \ 9610 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC) 9611 #define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9612 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \ 9613 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC) 9614 #define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16) 9615 #define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0) 9616 9617 #define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C) 9618 #define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C) 9619 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C 9620 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C 9621 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C 9622 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC 0x7857C 9623 #define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9624 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \ 9625 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC) 9626 #define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9627 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \ 9628 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC) 9629 #define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16) 9630 #define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0) 9631 9632 #define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210) 9633 #define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10) 9634 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280 9635 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380 9636 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480 9637 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC 0x78580 9638 #define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9639 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \ 9640 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC) 9641 #define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9642 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \ 9643 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC) 9644 #define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16) 9645 #define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0) 9646 9647 #define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214) 9648 #define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14) 9649 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284 9650 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384 9651 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484 9652 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC 0x78584 9653 #define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9654 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \ 9655 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC) 9656 #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9657 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \ 9658 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC) 9659 #define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16) 9660 #define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0) 9661 9662 #define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218) 9663 #define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18) 9664 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288 9665 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388 9666 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488 9667 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC 0x78588 9668 #define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9669 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \ 9670 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC) 9671 #define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9672 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \ 9673 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC) 9674 #define DSC_FLATNESS_MAX_QP(max_qp) ((max_qp) << 24) 9675 #define DSC_FLATNESS_MIN_QP(min_qp) ((min_qp) << 16) 9676 #define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8) 9677 #define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0) 9678 9679 #define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C) 9680 #define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C) 9681 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C 9682 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C 9683 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C 9684 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC 0x7858C 9685 #define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9686 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \ 9687 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC) 9688 #define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9689 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \ 9690 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC) 9691 #define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16) 9692 #define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0) 9693 9694 #define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220) 9695 #define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20) 9696 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290 9697 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390 9698 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490 9699 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC 0x78590 9700 #define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9701 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \ 9702 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC) 9703 #define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9704 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \ 9705 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC) 9706 #define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16) 9707 #define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0) 9708 9709 #define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224) 9710 #define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24) 9711 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294 9712 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394 9713 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494 9714 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC 0x78594 9715 #define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9716 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \ 9717 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC) 9718 #define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9719 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \ 9720 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC) 9721 #define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16) 9722 #define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0) 9723 9724 #define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228) 9725 #define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28) 9726 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298 9727 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398 9728 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498 9729 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC 0x78598 9730 #define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9731 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \ 9732 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC) 9733 #define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9734 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \ 9735 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC) 9736 #define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low) ((rc_tgt_off_low) << 20) 9737 #define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) ((rc_tgt_off_high) << 16) 9738 #define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8) 9739 #define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0) 9740 9741 #define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C) 9742 #define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C) 9743 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C 9744 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C 9745 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C 9746 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC 0x7859C 9747 #define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9748 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \ 9749 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC) 9750 #define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9751 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \ 9752 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC) 9753 9754 #define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260) 9755 #define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60) 9756 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0 9757 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0 9758 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0 9759 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC 0x785A0 9760 #define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9761 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \ 9762 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC) 9763 #define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9764 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \ 9765 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC) 9766 9767 #define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264) 9768 #define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64) 9769 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4 9770 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4 9771 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4 9772 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC 0x785A4 9773 #define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9774 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \ 9775 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC) 9776 #define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9777 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \ 9778 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC) 9779 9780 #define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268) 9781 #define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68) 9782 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8 9783 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8 9784 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8 9785 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC 0x785A8 9786 #define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9787 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \ 9788 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC) 9789 #define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9790 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \ 9791 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC) 9792 9793 #define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C) 9794 #define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C) 9795 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC 9796 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC 9797 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC 9798 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC 0x785AC 9799 #define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9800 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \ 9801 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC) 9802 #define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9803 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \ 9804 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC) 9805 9806 #define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270) 9807 #define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70) 9808 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0 9809 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0 9810 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0 9811 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC 0x785B0 9812 #define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9813 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \ 9814 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC) 9815 #define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9816 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \ 9817 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC) 9818 #define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame) << 20) 9819 #define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16) 9820 #define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0) 9821 9822 /* Icelake Rate Control Buffer Threshold Registers */ 9823 #define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230) 9824 #define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4) 9825 #define DSCC_RC_BUF_THRESH_0 _MMIO(0x6BA30) 9826 #define DSCC_RC_BUF_THRESH_0_UDW _MMIO(0x6BA30 + 4) 9827 #define _ICL_DSC0_RC_BUF_THRESH_0_PB (0x78254) 9828 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB (0x78254 + 4) 9829 #define _ICL_DSC1_RC_BUF_THRESH_0_PB (0x78354) 9830 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB (0x78354 + 4) 9831 #define _ICL_DSC0_RC_BUF_THRESH_0_PC (0x78454) 9832 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC (0x78454 + 4) 9833 #define _ICL_DSC1_RC_BUF_THRESH_0_PC (0x78554) 9834 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC (0x78554 + 4) 9835 #define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9836 _ICL_DSC0_RC_BUF_THRESH_0_PB, \ 9837 _ICL_DSC0_RC_BUF_THRESH_0_PC) 9838 #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9839 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \ 9840 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC) 9841 #define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9842 _ICL_DSC1_RC_BUF_THRESH_0_PB, \ 9843 _ICL_DSC1_RC_BUF_THRESH_0_PC) 9844 #define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9845 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \ 9846 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC) 9847 9848 #define DSCA_RC_BUF_THRESH_1 _MMIO(0x6B238) 9849 #define DSCA_RC_BUF_THRESH_1_UDW _MMIO(0x6B238 + 4) 9850 #define DSCC_RC_BUF_THRESH_1 _MMIO(0x6BA38) 9851 #define DSCC_RC_BUF_THRESH_1_UDW _MMIO(0x6BA38 + 4) 9852 #define _ICL_DSC0_RC_BUF_THRESH_1_PB (0x7825C) 9853 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB (0x7825C + 4) 9854 #define _ICL_DSC1_RC_BUF_THRESH_1_PB (0x7835C) 9855 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB (0x7835C + 4) 9856 #define _ICL_DSC0_RC_BUF_THRESH_1_PC (0x7845C) 9857 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC (0x7845C + 4) 9858 #define _ICL_DSC1_RC_BUF_THRESH_1_PC (0x7855C) 9859 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC (0x7855C + 4) 9860 #define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9861 _ICL_DSC0_RC_BUF_THRESH_1_PB, \ 9862 _ICL_DSC0_RC_BUF_THRESH_1_PC) 9863 #define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9864 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \ 9865 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC) 9866 #define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9867 _ICL_DSC1_RC_BUF_THRESH_1_PB, \ 9868 _ICL_DSC1_RC_BUF_THRESH_1_PC) 9869 #define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 9870 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \ 9871 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC) 9872 9873 #define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0) 9874 #define MODULAR_FIA_MASK (1 << 4) 9875 #define TC_LIVE_STATE_TBT(idx) (1 << ((idx) * 8 + 6)) 9876 #define TC_LIVE_STATE_TC(idx) (1 << ((idx) * 8 + 5)) 9877 #define DP_LANE_ASSIGNMENT_SHIFT(idx) ((idx) * 8) 9878 #define DP_LANE_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 8)) 9879 #define DP_LANE_ASSIGNMENT(idx, x) ((x) << ((idx) * 8)) 9880 9881 #define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890) 9882 #define DP_PHY_MODE_STATUS_COMPLETED(idx) (1 << (idx)) 9883 9884 #define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894) 9885 #define DP_PHY_MODE_STATUS_NOT_SAFE(idx) (1 << (idx)) 9886 9887 #define PORT_TX_DFLEXPA1(fia) _MMIO_FIA((fia), 0x00880) 9888 #define DP_PIN_ASSIGNMENT_SHIFT(idx) ((idx) * 4) 9889 #define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4)) 9890 #define DP_PIN_ASSIGNMENT(idx, x) ((x) << ((idx) * 4)) 9891 9892 #define _TCSS_DDI_STATUS_1 0x161500 9893 #define _TCSS_DDI_STATUS_2 0x161504 9894 #define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \ 9895 _TCSS_DDI_STATUS_1, \ 9896 _TCSS_DDI_STATUS_2)) 9897 #define TCSS_DDI_STATUS_READY REG_BIT(2) 9898 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1) 9899 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0) 9900 9901 #define PRIMARY_SPI_TRIGGER _MMIO(0x102040) 9902 #define PRIMARY_SPI_ADDRESS _MMIO(0x102080) 9903 #define PRIMARY_SPI_REGIONID _MMIO(0x102084) 9904 #define SPI_STATIC_REGIONS _MMIO(0x102090) 9905 #define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0) 9906 #define OROM_OFFSET _MMIO(0x1020c0) 9907 #define OROM_OFFSET_MASK REG_GENMASK(20, 16) 9908 9909 /* This register controls the Display State Buffer (DSB) engines. */ 9910 #define _DSBSL_INSTANCE_BASE 0x70B00 9911 #define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \ 9912 (pipe) * 0x1000 + (id) * 0x100) 9913 #define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0) 9914 #define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4) 9915 #define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8) 9916 #define DSB_ENABLE (1 << 31) 9917 #define DSB_STATUS (1 << 0) 9918 9919 #define TGL_ROOT_DEVICE_ID 0x9A00 9920 #define TGL_ROOT_DEVICE_MASK 0xFF00 9921 #define TGL_ROOT_DEVICE_SKU_MASK 0xF 9922 #define TGL_ROOT_DEVICE_SKU_ULX 0x2 9923 #define TGL_ROOT_DEVICE_SKU_ULT 0x4 9924 9925 #define CLKREQ_POLICY _MMIO(0x101038) 9926 #define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1) 9927 9928 #define CLKGATE_DIS_MISC _MMIO(0x46534) 9929 #define CLKGATE_DIS_MISC_DMASC_GATING_DIS REG_BIT(21) 9930 9931 #endif /* _I915_REG_H_ */ 9932