1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef __INTEL_PERF_OA_REGS__ 7 #define __INTEL_PERF_OA_REGS__ 8 9 #include "i915_reg_defs.h" 10 11 #define GEN7_OACONTROL _MMIO(0x2360) 12 #define GEN7_OACONTROL_CTX_MASK 0xFFFFF000 13 #define GEN7_OACONTROL_TIMER_PERIOD_MASK 0x3F 14 #define GEN7_OACONTROL_TIMER_PERIOD_SHIFT 6 15 #define GEN7_OACONTROL_TIMER_ENABLE (1 << 5) 16 #define GEN7_OACONTROL_FORMAT_A13 (0 << 2) 17 #define GEN7_OACONTROL_FORMAT_A29 (1 << 2) 18 #define GEN7_OACONTROL_FORMAT_A13_B8_C8 (2 << 2) 19 #define GEN7_OACONTROL_FORMAT_A29_B8_C8 (3 << 2) 20 #define GEN7_OACONTROL_FORMAT_B4_C8 (4 << 2) 21 #define GEN7_OACONTROL_FORMAT_A45_B8_C8 (5 << 2) 22 #define GEN7_OACONTROL_FORMAT_B4_C8_A16 (6 << 2) 23 #define GEN7_OACONTROL_FORMAT_C4_B8 (7 << 2) 24 #define GEN7_OACONTROL_FORMAT_SHIFT 2 25 #define GEN7_OACONTROL_PER_CTX_ENABLE (1 << 1) 26 #define GEN7_OACONTROL_ENABLE (1 << 0) 27 28 #define GEN8_OACTXID _MMIO(0x2364) 29 30 #define GEN8_OA_DEBUG _MMIO(0x2B04) 31 #define GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1 << 5) 32 #define GEN9_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6) 33 #define GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2) 34 #define GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1) 35 36 #define GEN8_OACONTROL _MMIO(0x2B00) 37 #define GEN8_OA_REPORT_FORMAT_A12 (0 << 2) 38 #define GEN8_OA_REPORT_FORMAT_A12_B8_C8 (2 << 2) 39 #define GEN8_OA_REPORT_FORMAT_A36_B8_C8 (5 << 2) 40 #define GEN8_OA_REPORT_FORMAT_C4_B8 (7 << 2) 41 #define GEN8_OA_REPORT_FORMAT_SHIFT 2 42 #define GEN8_OA_SPECIFIC_CONTEXT_ENABLE (1 << 1) 43 #define GEN8_OA_COUNTER_ENABLE (1 << 0) 44 45 #define GEN8_OACTXCONTROL _MMIO(0x2360) 46 #define GEN8_OA_TIMER_PERIOD_MASK 0x3F 47 #define GEN8_OA_TIMER_PERIOD_SHIFT 2 48 #define GEN8_OA_TIMER_ENABLE (1 << 1) 49 #define GEN8_OA_COUNTER_RESUME (1 << 0) 50 51 #define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */ 52 #define GEN7_OABUFFER_OVERRUN_DISABLE (1 << 3) 53 #define GEN7_OABUFFER_EDGE_TRIGGER (1 << 2) 54 #define GEN7_OABUFFER_STOP_RESUME_ENABLE (1 << 1) 55 #define GEN7_OABUFFER_RESUME (1 << 0) 56 57 #define GEN8_OABUFFER_UDW _MMIO(0x23b4) 58 #define GEN8_OABUFFER _MMIO(0x2b14) 59 #define GEN8_OABUFFER_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */ 60 61 #define GEN7_OASTATUS1 _MMIO(0x2364) 62 #define GEN7_OASTATUS1_TAIL_MASK 0xffffffc0 63 #define GEN7_OASTATUS1_COUNTER_OVERFLOW (1 << 2) 64 #define GEN7_OASTATUS1_OABUFFER_OVERFLOW (1 << 1) 65 #define GEN7_OASTATUS1_REPORT_LOST (1 << 0) 66 67 #define GEN7_OASTATUS2 _MMIO(0x2368) 68 #define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0 69 #define GEN7_OASTATUS2_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */ 70 71 #define GEN8_OASTATUS _MMIO(0x2b08) 72 #define GEN8_OASTATUS_TAIL_POINTER_WRAP (1 << 17) 73 #define GEN8_OASTATUS_HEAD_POINTER_WRAP (1 << 16) 74 #define GEN8_OASTATUS_OVERRUN_STATUS (1 << 3) 75 #define GEN8_OASTATUS_COUNTER_OVERFLOW (1 << 2) 76 #define GEN8_OASTATUS_OABUFFER_OVERFLOW (1 << 1) 77 #define GEN8_OASTATUS_REPORT_LOST (1 << 0) 78 79 #define GEN8_OAHEADPTR _MMIO(0x2B0C) 80 #define GEN8_OAHEADPTR_MASK 0xffffffc0 81 #define GEN8_OATAILPTR _MMIO(0x2B10) 82 #define GEN8_OATAILPTR_MASK 0xffffffc0 83 84 #define OABUFFER_SIZE_128K (0 << 3) 85 #define OABUFFER_SIZE_256K (1 << 3) 86 #define OABUFFER_SIZE_512K (2 << 3) 87 #define OABUFFER_SIZE_1M (3 << 3) 88 #define OABUFFER_SIZE_2M (4 << 3) 89 #define OABUFFER_SIZE_4M (5 << 3) 90 #define OABUFFER_SIZE_8M (6 << 3) 91 #define OABUFFER_SIZE_16M (7 << 3) 92 93 #define GEN12_OA_TLB_INV_CR _MMIO(0xceec) 94 95 /* Gen12 OAR unit */ 96 #define GEN12_OAR_OACONTROL _MMIO(0x2960) 97 #define GEN12_OAR_OACONTROL_COUNTER_FORMAT_SHIFT 1 98 #define GEN12_OAR_OACONTROL_COUNTER_ENABLE (1 << 0) 99 100 #define GEN12_OACTXCONTROL(base) _MMIO((base) + 0x360) 101 #define GEN12_OAR_OASTATUS _MMIO(0x2968) 102 103 /* Gen12 OAG unit */ 104 #define GEN12_OAG_OAHEADPTR _MMIO(0xdb00) 105 #define GEN12_OAG_OAHEADPTR_MASK 0xffffffc0 106 #define GEN12_OAG_OATAILPTR _MMIO(0xdb04) 107 #define GEN12_OAG_OATAILPTR_MASK 0xffffffc0 108 109 #define GEN12_OAG_OABUFFER _MMIO(0xdb08) 110 #define GEN12_OAG_OABUFFER_BUFFER_SIZE_MASK (0x7) 111 #define GEN12_OAG_OABUFFER_BUFFER_SIZE_SHIFT (3) 112 #define GEN12_OAG_OABUFFER_MEMORY_SELECT (1 << 0) /* 0: PPGTT, 1: GGTT */ 113 114 #define GEN12_OAG_OAGLBCTXCTRL _MMIO(0x2b28) 115 #define GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT 2 116 #define GEN12_OAG_OAGLBCTXCTRL_TIMER_ENABLE (1 << 1) 117 #define GEN12_OAG_OAGLBCTXCTRL_COUNTER_RESUME (1 << 0) 118 119 #define GEN12_OAG_OACONTROL _MMIO(0xdaf4) 120 #define GEN12_OAG_OACONTROL_OA_COUNTER_FORMAT_SHIFT 2 121 #define GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE (1 << 0) 122 123 #define GEN12_OAG_OA_DEBUG _MMIO(0xdaf8) 124 #define GEN12_OAG_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6) 125 #define GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1 << 5) 126 #define GEN12_OAG_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2) 127 #define GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1) 128 129 #define GEN12_OAG_OASTATUS _MMIO(0xdafc) 130 #define GEN12_OAG_OASTATUS_COUNTER_OVERFLOW (1 << 2) 131 #define GEN12_OAG_OASTATUS_BUFFER_OVERFLOW (1 << 1) 132 #define GEN12_OAG_OASTATUS_REPORT_LOST (1 << 0) 133 134 #define GDT_CHICKEN_BITS _MMIO(0x9840) 135 #define GT_NOA_ENABLE 0x00000080 136 137 #define GEN12_SQCNT1 _MMIO(0x8718) 138 #define GEN12_SQCNT1_PMON_ENABLE REG_BIT(30) 139 #define GEN12_SQCNT1_OABPC REG_BIT(29) 140 141 #endif /* __INTEL_PERF_OA_REGS__ */ 142