1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <drm/drm_color_mgmt.h> 26 #include <drm/drm_drv.h> 27 #include <drm/intel/i915_pciids.h> 28 29 #include "display/intel_display_driver.h" 30 #include "gt/intel_gt_regs.h" 31 #include "gt/intel_sa_media.h" 32 #include "gem/i915_gem_object_types.h" 33 34 #include "i915_driver.h" 35 #include "i915_drv.h" 36 #include "i915_pci.h" 37 #include "i915_reg.h" 38 #include "intel_pci_config.h" 39 40 __diag_push(); 41 __diag_ignore_all("-Woverride-init", "Allow field initialization overrides for device info"); 42 43 #define PLATFORM(x) .platform = (x) 44 #define GEN(x) \ 45 .__runtime.graphics.ip.ver = (x), \ 46 .__runtime.media.ip.ver = (x) 47 48 #define LEGACY_CACHELEVEL \ 49 .cachelevel_to_pat = { \ 50 [I915_CACHE_NONE] = 0, \ 51 [I915_CACHE_LLC] = 1, \ 52 [I915_CACHE_L3_LLC] = 2, \ 53 [I915_CACHE_WT] = 3, \ 54 } 55 56 #define TGL_CACHELEVEL \ 57 .cachelevel_to_pat = { \ 58 [I915_CACHE_NONE] = 3, \ 59 [I915_CACHE_LLC] = 0, \ 60 [I915_CACHE_L3_LLC] = 0, \ 61 [I915_CACHE_WT] = 2, \ 62 } 63 64 #define MTL_CACHELEVEL \ 65 .cachelevel_to_pat = { \ 66 [I915_CACHE_NONE] = 2, \ 67 [I915_CACHE_LLC] = 3, \ 68 [I915_CACHE_L3_LLC] = 3, \ 69 [I915_CACHE_WT] = 1, \ 70 } 71 72 /* Keep in gen based order, and chronological order within a gen */ 73 74 #define GEN_DEFAULT_PAGE_SIZES \ 75 .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K 76 77 #define GEN_DEFAULT_REGIONS \ 78 .memory_regions = BIT(INTEL_REGION_SMEM) | BIT(INTEL_REGION_STOLEN_SMEM) 79 80 #define I830_FEATURES \ 81 GEN(2), \ 82 .is_mobile = 1, \ 83 .gpu_reset_clobbers_display = true, \ 84 .has_3d_pipeline = 1, \ 85 .hws_needs_physical = 1, \ 86 .unfenced_needs_alignment = 1, \ 87 .platform_engine_mask = BIT(RCS0), \ 88 .has_snoop = true, \ 89 .has_coherent_ggtt = false, \ 90 .dma_mask_size = 32, \ 91 .max_pat_index = 3, \ 92 GEN_DEFAULT_PAGE_SIZES, \ 93 GEN_DEFAULT_REGIONS, \ 94 LEGACY_CACHELEVEL 95 96 #define I845_FEATURES \ 97 GEN(2), \ 98 .has_3d_pipeline = 1, \ 99 .gpu_reset_clobbers_display = true, \ 100 .hws_needs_physical = 1, \ 101 .unfenced_needs_alignment = 1, \ 102 .platform_engine_mask = BIT(RCS0), \ 103 .has_snoop = true, \ 104 .has_coherent_ggtt = false, \ 105 .dma_mask_size = 32, \ 106 .max_pat_index = 3, \ 107 GEN_DEFAULT_PAGE_SIZES, \ 108 GEN_DEFAULT_REGIONS, \ 109 LEGACY_CACHELEVEL 110 111 static const struct intel_device_info i830_info = { 112 I830_FEATURES, 113 PLATFORM(INTEL_I830), 114 }; 115 116 static const struct intel_device_info i845g_info = { 117 I845_FEATURES, 118 PLATFORM(INTEL_I845G), 119 }; 120 121 static const struct intel_device_info i85x_info = { 122 I830_FEATURES, 123 PLATFORM(INTEL_I85X), 124 }; 125 126 static const struct intel_device_info i865g_info = { 127 I845_FEATURES, 128 PLATFORM(INTEL_I865G), 129 }; 130 131 #define GEN3_FEATURES \ 132 GEN(3), \ 133 .gpu_reset_clobbers_display = true, \ 134 .platform_engine_mask = BIT(RCS0), \ 135 .has_3d_pipeline = 1, \ 136 .has_snoop = true, \ 137 .has_coherent_ggtt = true, \ 138 .dma_mask_size = 32, \ 139 .max_pat_index = 3, \ 140 GEN_DEFAULT_PAGE_SIZES, \ 141 GEN_DEFAULT_REGIONS, \ 142 LEGACY_CACHELEVEL 143 144 static const struct intel_device_info i915g_info = { 145 GEN3_FEATURES, 146 PLATFORM(INTEL_I915G), 147 .has_coherent_ggtt = false, 148 .hws_needs_physical = 1, 149 .unfenced_needs_alignment = 1, 150 }; 151 152 static const struct intel_device_info i915gm_info = { 153 GEN3_FEATURES, 154 PLATFORM(INTEL_I915GM), 155 .is_mobile = 1, 156 .hws_needs_physical = 1, 157 .unfenced_needs_alignment = 1, 158 }; 159 160 static const struct intel_device_info i945g_info = { 161 GEN3_FEATURES, 162 PLATFORM(INTEL_I945G), 163 .hws_needs_physical = 1, 164 .unfenced_needs_alignment = 1, 165 }; 166 167 static const struct intel_device_info i945gm_info = { 168 GEN3_FEATURES, 169 PLATFORM(INTEL_I945GM), 170 .is_mobile = 1, 171 .hws_needs_physical = 1, 172 .unfenced_needs_alignment = 1, 173 }; 174 175 static const struct intel_device_info g33_info = { 176 GEN3_FEATURES, 177 PLATFORM(INTEL_G33), 178 .dma_mask_size = 36, 179 }; 180 181 static const struct intel_device_info pnv_g_info = { 182 GEN3_FEATURES, 183 PLATFORM(INTEL_PINEVIEW), 184 .dma_mask_size = 36, 185 }; 186 187 static const struct intel_device_info pnv_m_info = { 188 GEN3_FEATURES, 189 PLATFORM(INTEL_PINEVIEW), 190 .is_mobile = 1, 191 .dma_mask_size = 36, 192 }; 193 194 #define GEN4_FEATURES \ 195 GEN(4), \ 196 .gpu_reset_clobbers_display = true, \ 197 .platform_engine_mask = BIT(RCS0), \ 198 .has_3d_pipeline = 1, \ 199 .has_snoop = true, \ 200 .has_coherent_ggtt = true, \ 201 .dma_mask_size = 36, \ 202 .max_pat_index = 3, \ 203 GEN_DEFAULT_PAGE_SIZES, \ 204 GEN_DEFAULT_REGIONS, \ 205 LEGACY_CACHELEVEL 206 207 static const struct intel_device_info i965g_info = { 208 GEN4_FEATURES, 209 PLATFORM(INTEL_I965G), 210 .hws_needs_physical = 1, 211 .has_snoop = false, 212 }; 213 214 static const struct intel_device_info i965gm_info = { 215 GEN4_FEATURES, 216 PLATFORM(INTEL_I965GM), 217 .is_mobile = 1, 218 .hws_needs_physical = 1, 219 .has_snoop = false, 220 }; 221 222 static const struct intel_device_info g45_info = { 223 GEN4_FEATURES, 224 PLATFORM(INTEL_G45), 225 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), 226 .gpu_reset_clobbers_display = false, 227 }; 228 229 static const struct intel_device_info gm45_info = { 230 GEN4_FEATURES, 231 PLATFORM(INTEL_GM45), 232 .is_mobile = 1, 233 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), 234 .gpu_reset_clobbers_display = false, 235 }; 236 237 #define GEN5_FEATURES \ 238 GEN(5), \ 239 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \ 240 .has_3d_pipeline = 1, \ 241 .has_snoop = true, \ 242 .has_coherent_ggtt = true, \ 243 /* ilk does support rc6, but we do not implement [power] contexts */ \ 244 .has_rc6 = 0, \ 245 .dma_mask_size = 36, \ 246 .max_pat_index = 3, \ 247 GEN_DEFAULT_PAGE_SIZES, \ 248 GEN_DEFAULT_REGIONS, \ 249 LEGACY_CACHELEVEL 250 251 static const struct intel_device_info ilk_d_info = { 252 GEN5_FEATURES, 253 PLATFORM(INTEL_IRONLAKE), 254 }; 255 256 static const struct intel_device_info ilk_m_info = { 257 GEN5_FEATURES, 258 PLATFORM(INTEL_IRONLAKE), 259 .is_mobile = 1, 260 .has_rps = true, 261 }; 262 263 #define GEN6_FEATURES \ 264 GEN(6), \ 265 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 266 .has_3d_pipeline = 1, \ 267 .has_coherent_ggtt = true, \ 268 .has_llc = 1, \ 269 .has_rc6 = 1, \ 270 /* snb does support rc6p, but enabling it causes various issues */ \ 271 .has_rc6p = 0, \ 272 .has_rps = true, \ 273 .dma_mask_size = 40, \ 274 .max_pat_index = 3, \ 275 .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \ 276 .__runtime.ppgtt_size = 31, \ 277 GEN_DEFAULT_PAGE_SIZES, \ 278 GEN_DEFAULT_REGIONS, \ 279 LEGACY_CACHELEVEL 280 281 #define SNB_D_PLATFORM \ 282 GEN6_FEATURES, \ 283 PLATFORM(INTEL_SANDYBRIDGE) 284 285 static const struct intel_device_info snb_d_gt1_info = { 286 SNB_D_PLATFORM, 287 .gt = 1, 288 }; 289 290 static const struct intel_device_info snb_d_gt2_info = { 291 SNB_D_PLATFORM, 292 .gt = 2, 293 }; 294 295 #define SNB_M_PLATFORM \ 296 GEN6_FEATURES, \ 297 PLATFORM(INTEL_SANDYBRIDGE), \ 298 .is_mobile = 1 299 300 301 static const struct intel_device_info snb_m_gt1_info = { 302 SNB_M_PLATFORM, 303 .gt = 1, 304 }; 305 306 static const struct intel_device_info snb_m_gt2_info = { 307 SNB_M_PLATFORM, 308 .gt = 2, 309 }; 310 311 #define GEN7_FEATURES \ 312 GEN(7), \ 313 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 314 .has_3d_pipeline = 1, \ 315 .has_coherent_ggtt = true, \ 316 .has_llc = 1, \ 317 .has_rc6 = 1, \ 318 .has_rc6p = 1, \ 319 .has_reset_engine = true, \ 320 .has_rps = true, \ 321 .dma_mask_size = 40, \ 322 .max_pat_index = 3, \ 323 .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \ 324 .__runtime.ppgtt_size = 31, \ 325 GEN_DEFAULT_PAGE_SIZES, \ 326 GEN_DEFAULT_REGIONS, \ 327 LEGACY_CACHELEVEL 328 329 #define IVB_D_PLATFORM \ 330 GEN7_FEATURES, \ 331 PLATFORM(INTEL_IVYBRIDGE), \ 332 .has_l3_dpf = 1 333 334 static const struct intel_device_info ivb_d_gt1_info = { 335 IVB_D_PLATFORM, 336 .gt = 1, 337 }; 338 339 static const struct intel_device_info ivb_d_gt2_info = { 340 IVB_D_PLATFORM, 341 .gt = 2, 342 }; 343 344 #define IVB_M_PLATFORM \ 345 GEN7_FEATURES, \ 346 PLATFORM(INTEL_IVYBRIDGE), \ 347 .is_mobile = 1, \ 348 .has_l3_dpf = 1 349 350 static const struct intel_device_info ivb_m_gt1_info = { 351 IVB_M_PLATFORM, 352 .gt = 1, 353 }; 354 355 static const struct intel_device_info ivb_m_gt2_info = { 356 IVB_M_PLATFORM, 357 .gt = 2, 358 }; 359 360 static const struct intel_device_info ivb_q_info = { 361 GEN7_FEATURES, 362 PLATFORM(INTEL_IVYBRIDGE), 363 .gt = 2, 364 .has_l3_dpf = 1, 365 }; 366 367 static const struct intel_device_info vlv_info = { 368 PLATFORM(INTEL_VALLEYVIEW), 369 GEN(7), 370 .is_lp = 1, 371 .has_runtime_pm = 1, 372 .has_rc6 = 1, 373 .has_reset_engine = true, 374 .has_rps = true, 375 .dma_mask_size = 40, 376 .max_pat_index = 3, 377 .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, 378 .__runtime.ppgtt_size = 31, 379 .has_snoop = true, 380 .has_coherent_ggtt = false, 381 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), 382 GEN_DEFAULT_PAGE_SIZES, 383 GEN_DEFAULT_REGIONS, 384 LEGACY_CACHELEVEL, 385 }; 386 387 #define G75_FEATURES \ 388 GEN7_FEATURES, \ 389 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ 390 .has_rc6p = 0 /* RC6p removed-by HSW */, \ 391 .has_runtime_pm = 1 392 393 #define HSW_PLATFORM \ 394 G75_FEATURES, \ 395 PLATFORM(INTEL_HASWELL), \ 396 .has_l3_dpf = 1 397 398 static const struct intel_device_info hsw_gt1_info = { 399 HSW_PLATFORM, 400 .gt = 1, 401 }; 402 403 static const struct intel_device_info hsw_gt2_info = { 404 HSW_PLATFORM, 405 .gt = 2, 406 }; 407 408 static const struct intel_device_info hsw_gt3_info = { 409 HSW_PLATFORM, 410 .gt = 3, 411 }; 412 413 #define GEN8_FEATURES \ 414 G75_FEATURES, \ 415 GEN(8), \ 416 .has_logical_ring_contexts = 1, \ 417 .dma_mask_size = 39, \ 418 .__runtime.ppgtt_type = INTEL_PPGTT_FULL, \ 419 .__runtime.ppgtt_size = 48, \ 420 .has_64bit_reloc = 1 421 422 #define BDW_PLATFORM \ 423 GEN8_FEATURES, \ 424 PLATFORM(INTEL_BROADWELL) 425 426 static const struct intel_device_info bdw_gt1_info = { 427 BDW_PLATFORM, 428 .gt = 1, 429 }; 430 431 static const struct intel_device_info bdw_gt2_info = { 432 BDW_PLATFORM, 433 .gt = 2, 434 }; 435 436 static const struct intel_device_info bdw_rsvd_info = { 437 BDW_PLATFORM, 438 .gt = 3, 439 /* According to the device ID those devices are GT3, they were 440 * previously treated as not GT3, keep it like that. 441 */ 442 }; 443 444 static const struct intel_device_info bdw_gt3_info = { 445 BDW_PLATFORM, 446 .gt = 3, 447 .platform_engine_mask = 448 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 449 }; 450 451 static const struct intel_device_info chv_info = { 452 PLATFORM(INTEL_CHERRYVIEW), 453 GEN(8), 454 .is_lp = 1, 455 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), 456 .has_64bit_reloc = 1, 457 .has_runtime_pm = 1, 458 .has_rc6 = 1, 459 .has_rps = true, 460 .has_logical_ring_contexts = 1, 461 .dma_mask_size = 39, 462 .max_pat_index = 3, 463 .__runtime.ppgtt_type = INTEL_PPGTT_FULL, 464 .__runtime.ppgtt_size = 32, 465 .has_reset_engine = 1, 466 .has_snoop = true, 467 .has_coherent_ggtt = false, 468 GEN_DEFAULT_PAGE_SIZES, 469 GEN_DEFAULT_REGIONS, 470 LEGACY_CACHELEVEL, 471 }; 472 473 #define GEN9_DEFAULT_PAGE_SIZES \ 474 .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \ 475 I915_GTT_PAGE_SIZE_64K 476 477 #define GEN9_FEATURES \ 478 GEN8_FEATURES, \ 479 GEN(9), \ 480 GEN9_DEFAULT_PAGE_SIZES, \ 481 .has_gt_uc = 1 482 483 #define SKL_PLATFORM \ 484 GEN9_FEATURES, \ 485 PLATFORM(INTEL_SKYLAKE) 486 487 static const struct intel_device_info skl_gt1_info = { 488 SKL_PLATFORM, 489 .gt = 1, 490 }; 491 492 static const struct intel_device_info skl_gt2_info = { 493 SKL_PLATFORM, 494 .gt = 2, 495 }; 496 497 #define SKL_GT3_PLUS_PLATFORM \ 498 SKL_PLATFORM, \ 499 .platform_engine_mask = \ 500 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1) 501 502 503 static const struct intel_device_info skl_gt3_info = { 504 SKL_GT3_PLUS_PLATFORM, 505 .gt = 3, 506 }; 507 508 static const struct intel_device_info skl_gt4_info = { 509 SKL_GT3_PLUS_PLATFORM, 510 .gt = 4, 511 }; 512 513 #define GEN9_LP_FEATURES \ 514 GEN(9), \ 515 .is_lp = 1, \ 516 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ 517 .has_3d_pipeline = 1, \ 518 .has_64bit_reloc = 1, \ 519 .has_runtime_pm = 1, \ 520 .has_rc6 = 1, \ 521 .has_rps = true, \ 522 .has_logical_ring_contexts = 1, \ 523 .has_gt_uc = 1, \ 524 .dma_mask_size = 39, \ 525 .__runtime.ppgtt_type = INTEL_PPGTT_FULL, \ 526 .__runtime.ppgtt_size = 48, \ 527 .has_reset_engine = 1, \ 528 .has_snoop = true, \ 529 .has_coherent_ggtt = false, \ 530 .max_pat_index = 3, \ 531 GEN9_DEFAULT_PAGE_SIZES, \ 532 GEN_DEFAULT_REGIONS, \ 533 LEGACY_CACHELEVEL 534 535 static const struct intel_device_info bxt_info = { 536 GEN9_LP_FEATURES, 537 PLATFORM(INTEL_BROXTON), 538 }; 539 540 static const struct intel_device_info glk_info = { 541 GEN9_LP_FEATURES, 542 PLATFORM(INTEL_GEMINILAKE), 543 }; 544 545 #define KBL_PLATFORM \ 546 GEN9_FEATURES, \ 547 PLATFORM(INTEL_KABYLAKE) 548 549 static const struct intel_device_info kbl_gt1_info = { 550 KBL_PLATFORM, 551 .gt = 1, 552 }; 553 554 static const struct intel_device_info kbl_gt2_info = { 555 KBL_PLATFORM, 556 .gt = 2, 557 }; 558 559 static const struct intel_device_info kbl_gt3_info = { 560 KBL_PLATFORM, 561 .gt = 3, 562 .platform_engine_mask = 563 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 564 }; 565 566 #define CFL_PLATFORM \ 567 GEN9_FEATURES, \ 568 PLATFORM(INTEL_COFFEELAKE) 569 570 static const struct intel_device_info cfl_gt1_info = { 571 CFL_PLATFORM, 572 .gt = 1, 573 }; 574 575 static const struct intel_device_info cfl_gt2_info = { 576 CFL_PLATFORM, 577 .gt = 2, 578 }; 579 580 static const struct intel_device_info cfl_gt3_info = { 581 CFL_PLATFORM, 582 .gt = 3, 583 .platform_engine_mask = 584 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 585 }; 586 587 #define CML_PLATFORM \ 588 GEN9_FEATURES, \ 589 PLATFORM(INTEL_COMETLAKE) 590 591 static const struct intel_device_info cml_gt1_info = { 592 CML_PLATFORM, 593 .gt = 1, 594 }; 595 596 static const struct intel_device_info cml_gt2_info = { 597 CML_PLATFORM, 598 .gt = 2, 599 }; 600 601 #define GEN11_DEFAULT_PAGE_SIZES \ 602 .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \ 603 I915_GTT_PAGE_SIZE_64K | \ 604 I915_GTT_PAGE_SIZE_2M 605 606 #define GEN11_FEATURES \ 607 GEN9_FEATURES, \ 608 GEN11_DEFAULT_PAGE_SIZES, \ 609 GEN(11), \ 610 .has_coherent_ggtt = false, \ 611 .has_logical_ring_elsq = 1 612 613 static const struct intel_device_info icl_info = { 614 GEN11_FEATURES, 615 PLATFORM(INTEL_ICELAKE), 616 .platform_engine_mask = 617 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 618 }; 619 620 static const struct intel_device_info ehl_info = { 621 GEN11_FEATURES, 622 PLATFORM(INTEL_ELKHARTLAKE), 623 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), 624 .__runtime.ppgtt_size = 36, 625 }; 626 627 static const struct intel_device_info jsl_info = { 628 GEN11_FEATURES, 629 PLATFORM(INTEL_JASPERLAKE), 630 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), 631 .__runtime.ppgtt_size = 36, 632 }; 633 634 #define GEN12_FEATURES \ 635 GEN11_FEATURES, \ 636 GEN(12), \ 637 TGL_CACHELEVEL, \ 638 .has_global_mocs = 1, \ 639 .has_pxp = 1, \ 640 .max_pat_index = 3 641 642 static const struct intel_device_info tgl_info = { 643 GEN12_FEATURES, 644 PLATFORM(INTEL_TIGERLAKE), 645 .platform_engine_mask = 646 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 647 }; 648 649 static const struct intel_device_info rkl_info = { 650 GEN12_FEATURES, 651 PLATFORM(INTEL_ROCKETLAKE), 652 .platform_engine_mask = 653 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0), 654 }; 655 656 #define DGFX_FEATURES \ 657 .memory_regions = BIT(INTEL_REGION_SMEM) | BIT(INTEL_REGION_LMEM_0) | BIT(INTEL_REGION_STOLEN_LMEM), \ 658 .has_llc = 0, \ 659 .has_pxp = 0, \ 660 .has_snoop = 1, \ 661 .is_dgfx = 1, \ 662 .has_heci_gscfi = 1 663 664 static const struct intel_device_info dg1_info = { 665 GEN12_FEATURES, 666 DGFX_FEATURES, 667 .__runtime.graphics.ip.rel = 10, 668 PLATFORM(INTEL_DG1), 669 .require_force_probe = 1, 670 .platform_engine_mask = 671 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | 672 BIT(VCS0) | BIT(VCS2), 673 /* Wa_16011227922 */ 674 .__runtime.ppgtt_size = 47, 675 }; 676 677 static const struct intel_device_info adl_s_info = { 678 GEN12_FEATURES, 679 PLATFORM(INTEL_ALDERLAKE_S), 680 .platform_engine_mask = 681 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 682 .dma_mask_size = 39, 683 }; 684 685 static const struct intel_device_info adl_p_info = { 686 GEN12_FEATURES, 687 PLATFORM(INTEL_ALDERLAKE_P), 688 .platform_engine_mask = 689 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 690 .__runtime.ppgtt_size = 48, 691 .dma_mask_size = 39, 692 }; 693 694 #undef GEN 695 696 #define XE_HP_PAGE_SIZES \ 697 .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \ 698 I915_GTT_PAGE_SIZE_64K | \ 699 I915_GTT_PAGE_SIZE_2M 700 701 #define XE_HP_FEATURES \ 702 XE_HP_PAGE_SIZES, \ 703 TGL_CACHELEVEL, \ 704 .dma_mask_size = 46, \ 705 .has_3d_pipeline = 1, \ 706 .has_64bit_reloc = 1, \ 707 .has_flat_ccs = 1, \ 708 .has_global_mocs = 1, \ 709 .has_gt_uc = 1, \ 710 .has_llc = 1, \ 711 .has_logical_ring_contexts = 1, \ 712 .has_logical_ring_elsq = 1, \ 713 .has_mslice_steering = 1, \ 714 .has_oa_bpc_reporting = 1, \ 715 .has_oa_slice_contrib_limits = 1, \ 716 .has_oam = 1, \ 717 .has_rc6 = 1, \ 718 .has_reset_engine = 1, \ 719 .has_rps = 1, \ 720 .has_runtime_pm = 1, \ 721 .max_pat_index = 3, \ 722 .__runtime.ppgtt_size = 48, \ 723 .__runtime.ppgtt_type = INTEL_PPGTT_FULL 724 725 #define DG2_FEATURES \ 726 XE_HP_FEATURES, \ 727 DGFX_FEATURES, \ 728 .__runtime.graphics.ip.ver = 12, \ 729 .__runtime.graphics.ip.rel = 55, \ 730 .__runtime.media.ip.ver = 12, \ 731 .__runtime.media.ip.rel = 55, \ 732 PLATFORM(INTEL_DG2), \ 733 .has_64k_pages = 1, \ 734 .has_guc_deprivilege = 1, \ 735 .has_heci_pxp = 1, \ 736 .has_media_ratio_mode = 1, \ 737 .platform_engine_mask = \ 738 BIT(RCS0) | BIT(BCS0) | \ 739 BIT(VECS0) | BIT(VECS1) | \ 740 BIT(VCS0) | BIT(VCS2) | \ 741 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3) 742 743 static const struct intel_device_info dg2_info = { 744 DG2_FEATURES, 745 }; 746 747 static const struct intel_device_info ats_m_info = { 748 DG2_FEATURES, 749 .require_force_probe = 1, 750 .tuning_thread_rr_after_dep = 1, 751 }; 752 753 static const struct intel_gt_definition xelpmp_extra_gt[] = { 754 { 755 .type = GT_MEDIA, 756 .name = "Standalone Media GT", 757 .gsi_offset = MTL_MEDIA_GSI_BASE, 758 .engine_mask = BIT(VECS0) | BIT(VCS0) | BIT(VCS2) | BIT(GSC0), 759 }, 760 {} 761 }; 762 763 static const struct intel_device_info mtl_info = { 764 XE_HP_FEATURES, 765 /* 766 * Real graphics IP version will be obtained from hardware GMD_ID 767 * register. Value provided here is just for sanity checking. 768 */ 769 .__runtime.graphics.ip.ver = 12, 770 .__runtime.graphics.ip.rel = 70, 771 .__runtime.media.ip.ver = 13, 772 PLATFORM(INTEL_METEORLAKE), 773 .extra_gt_list = xelpmp_extra_gt, 774 .has_flat_ccs = 0, 775 .has_gmd_id = 1, 776 .has_guc_deprivilege = 1, 777 .has_guc_tlb_invalidation = 1, 778 .has_llc = 0, 779 .has_mslice_steering = 0, 780 .has_snoop = 1, 781 .max_pat_index = 4, 782 .has_pxp = 1, 783 .memory_regions = BIT(INTEL_REGION_SMEM) | BIT(INTEL_REGION_STOLEN_LMEM), 784 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0), 785 MTL_CACHELEVEL, 786 }; 787 788 #undef PLATFORM 789 790 __diag_pop(); 791 792 /* 793 * Make sure any device matches here are from most specific to most 794 * general. For example, since the Quanta match is based on the subsystem 795 * and subvendor IDs, we need it to come before the more general IVB 796 * PCI ID matches, otherwise we'll use the wrong info struct above. 797 */ 798 static const struct pci_device_id pciidlist[] = { 799 INTEL_I830_IDS(INTEL_VGA_DEVICE, &i830_info), 800 INTEL_I845G_IDS(INTEL_VGA_DEVICE, &i845g_info), 801 INTEL_I85X_IDS(INTEL_VGA_DEVICE, &i85x_info), 802 INTEL_I865G_IDS(INTEL_VGA_DEVICE, &i865g_info), 803 INTEL_I915G_IDS(INTEL_VGA_DEVICE, &i915g_info), 804 INTEL_I915GM_IDS(INTEL_VGA_DEVICE, &i915gm_info), 805 INTEL_I945G_IDS(INTEL_VGA_DEVICE, &i945g_info), 806 INTEL_I945GM_IDS(INTEL_VGA_DEVICE, &i945gm_info), 807 INTEL_I965G_IDS(INTEL_VGA_DEVICE, &i965g_info), 808 INTEL_G33_IDS(INTEL_VGA_DEVICE, &g33_info), 809 INTEL_I965GM_IDS(INTEL_VGA_DEVICE, &i965gm_info), 810 INTEL_GM45_IDS(INTEL_VGA_DEVICE, &gm45_info), 811 INTEL_G45_IDS(INTEL_VGA_DEVICE, &g45_info), 812 INTEL_PNV_G_IDS(INTEL_VGA_DEVICE, &pnv_g_info), 813 INTEL_PNV_M_IDS(INTEL_VGA_DEVICE, &pnv_m_info), 814 INTEL_ILK_D_IDS(INTEL_VGA_DEVICE, &ilk_d_info), 815 INTEL_ILK_M_IDS(INTEL_VGA_DEVICE, &ilk_m_info), 816 INTEL_SNB_D_GT1_IDS(INTEL_VGA_DEVICE, &snb_d_gt1_info), 817 INTEL_SNB_D_GT2_IDS(INTEL_VGA_DEVICE, &snb_d_gt2_info), 818 INTEL_SNB_M_GT1_IDS(INTEL_VGA_DEVICE, &snb_m_gt1_info), 819 INTEL_SNB_M_GT2_IDS(INTEL_VGA_DEVICE, &snb_m_gt2_info), 820 INTEL_IVB_Q_IDS(INTEL_VGA_DEVICE, &ivb_q_info), /* must be first IVB */ 821 INTEL_IVB_M_GT1_IDS(INTEL_VGA_DEVICE, &ivb_m_gt1_info), 822 INTEL_IVB_M_GT2_IDS(INTEL_VGA_DEVICE, &ivb_m_gt2_info), 823 INTEL_IVB_D_GT1_IDS(INTEL_VGA_DEVICE, &ivb_d_gt1_info), 824 INTEL_IVB_D_GT2_IDS(INTEL_VGA_DEVICE, &ivb_d_gt2_info), 825 INTEL_HSW_GT1_IDS(INTEL_VGA_DEVICE, &hsw_gt1_info), 826 INTEL_HSW_GT2_IDS(INTEL_VGA_DEVICE, &hsw_gt2_info), 827 INTEL_HSW_GT3_IDS(INTEL_VGA_DEVICE, &hsw_gt3_info), 828 INTEL_VLV_IDS(INTEL_VGA_DEVICE, &vlv_info), 829 INTEL_BDW_GT1_IDS(INTEL_VGA_DEVICE, &bdw_gt1_info), 830 INTEL_BDW_GT2_IDS(INTEL_VGA_DEVICE, &bdw_gt2_info), 831 INTEL_BDW_GT3_IDS(INTEL_VGA_DEVICE, &bdw_gt3_info), 832 INTEL_BDW_RSVD_IDS(INTEL_VGA_DEVICE, &bdw_rsvd_info), 833 INTEL_CHV_IDS(INTEL_VGA_DEVICE, &chv_info), 834 INTEL_SKL_GT1_IDS(INTEL_VGA_DEVICE, &skl_gt1_info), 835 INTEL_SKL_GT2_IDS(INTEL_VGA_DEVICE, &skl_gt2_info), 836 INTEL_SKL_GT3_IDS(INTEL_VGA_DEVICE, &skl_gt3_info), 837 INTEL_SKL_GT4_IDS(INTEL_VGA_DEVICE, &skl_gt4_info), 838 INTEL_BXT_IDS(INTEL_VGA_DEVICE, &bxt_info), 839 INTEL_GLK_IDS(INTEL_VGA_DEVICE, &glk_info), 840 INTEL_KBL_GT1_IDS(INTEL_VGA_DEVICE, &kbl_gt1_info), 841 INTEL_KBL_GT2_IDS(INTEL_VGA_DEVICE, &kbl_gt2_info), 842 INTEL_KBL_GT3_IDS(INTEL_VGA_DEVICE, &kbl_gt3_info), 843 INTEL_KBL_GT4_IDS(INTEL_VGA_DEVICE, &kbl_gt3_info), 844 INTEL_AML_KBL_GT2_IDS(INTEL_VGA_DEVICE, &kbl_gt2_info), 845 INTEL_CFL_S_GT1_IDS(INTEL_VGA_DEVICE, &cfl_gt1_info), 846 INTEL_CFL_S_GT2_IDS(INTEL_VGA_DEVICE, &cfl_gt2_info), 847 INTEL_CFL_H_GT1_IDS(INTEL_VGA_DEVICE, &cfl_gt1_info), 848 INTEL_CFL_H_GT2_IDS(INTEL_VGA_DEVICE, &cfl_gt2_info), 849 INTEL_CFL_U_GT2_IDS(INTEL_VGA_DEVICE, &cfl_gt2_info), 850 INTEL_CFL_U_GT3_IDS(INTEL_VGA_DEVICE, &cfl_gt3_info), 851 INTEL_WHL_U_GT1_IDS(INTEL_VGA_DEVICE, &cfl_gt1_info), 852 INTEL_WHL_U_GT2_IDS(INTEL_VGA_DEVICE, &cfl_gt2_info), 853 INTEL_AML_CFL_GT2_IDS(INTEL_VGA_DEVICE, &cfl_gt2_info), 854 INTEL_WHL_U_GT3_IDS(INTEL_VGA_DEVICE, &cfl_gt3_info), 855 INTEL_CML_GT1_IDS(INTEL_VGA_DEVICE, &cml_gt1_info), 856 INTEL_CML_GT2_IDS(INTEL_VGA_DEVICE, &cml_gt2_info), 857 INTEL_CML_U_GT1_IDS(INTEL_VGA_DEVICE, &cml_gt1_info), 858 INTEL_CML_U_GT2_IDS(INTEL_VGA_DEVICE, &cml_gt2_info), 859 INTEL_ICL_IDS(INTEL_VGA_DEVICE, &icl_info), 860 INTEL_EHL_IDS(INTEL_VGA_DEVICE, &ehl_info), 861 INTEL_JSL_IDS(INTEL_VGA_DEVICE, &jsl_info), 862 INTEL_TGL_IDS(INTEL_VGA_DEVICE, &tgl_info), 863 INTEL_RKL_IDS(INTEL_VGA_DEVICE, &rkl_info), 864 INTEL_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_info), 865 INTEL_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_info), 866 INTEL_ADLN_IDS(INTEL_VGA_DEVICE, &adl_p_info), 867 INTEL_DG1_IDS(INTEL_VGA_DEVICE, &dg1_info), 868 INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_info), 869 INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &adl_p_info), 870 INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &adl_p_info), 871 INTEL_DG2_IDS(INTEL_VGA_DEVICE, &dg2_info), 872 INTEL_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_info), 873 INTEL_MTL_IDS(INTEL_VGA_DEVICE, &mtl_info), 874 {} 875 }; 876 MODULE_DEVICE_TABLE(pci, pciidlist); 877 878 static void i915_pci_remove(struct pci_dev *pdev) 879 { 880 struct drm_i915_private *i915; 881 882 i915 = pdev_to_i915(pdev); 883 if (!i915) /* driver load aborted, nothing to cleanup */ 884 return; 885 886 i915_driver_remove(i915); 887 pci_set_drvdata(pdev, NULL); 888 } 889 890 /* is device_id present in comma separated list of ids */ 891 static bool device_id_in_list(u16 device_id, const char *devices, bool negative) 892 { 893 char *s, *p, *tok; 894 bool ret; 895 896 if (!devices || !*devices) 897 return false; 898 899 /* match everything */ 900 if (negative && strcmp(devices, "!*") == 0) 901 return true; 902 if (!negative && strcmp(devices, "*") == 0) 903 return true; 904 905 s = kstrdup(devices, GFP_KERNEL); 906 if (!s) 907 return false; 908 909 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) { 910 u16 val; 911 912 if (negative && tok[0] == '!') 913 tok++; 914 else if ((negative && tok[0] != '!') || 915 (!negative && tok[0] == '!')) 916 continue; 917 918 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) { 919 ret = true; 920 break; 921 } 922 } 923 924 kfree(s); 925 926 return ret; 927 } 928 929 static bool id_forced(u16 device_id) 930 { 931 return device_id_in_list(device_id, i915_modparams.force_probe, false); 932 } 933 934 static bool id_blocked(u16 device_id) 935 { 936 return device_id_in_list(device_id, i915_modparams.force_probe, true); 937 } 938 939 bool i915_pci_resource_valid(struct pci_dev *pdev, int bar) 940 { 941 if (!pci_resource_flags(pdev, bar)) 942 return false; 943 944 if (pci_resource_flags(pdev, bar) & IORESOURCE_UNSET) 945 return false; 946 947 if (!pci_resource_len(pdev, bar)) 948 return false; 949 950 return true; 951 } 952 953 static bool intel_mmio_bar_valid(struct pci_dev *pdev, struct intel_device_info *intel_info) 954 { 955 return i915_pci_resource_valid(pdev, intel_mmio_bar(intel_info->__runtime.graphics.ip.ver)); 956 } 957 958 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 959 { 960 struct intel_device_info *intel_info = 961 (struct intel_device_info *) ent->driver_data; 962 int err; 963 964 if (intel_info->require_force_probe && !id_forced(pdev->device)) { 965 dev_info(&pdev->dev, 966 "Your graphics device %04x is not properly supported by i915 in this\n" 967 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n" 968 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n" 969 "or (recommended) check for kernel updates.\n", 970 pdev->device, pdev->device, pdev->device); 971 return -ENODEV; 972 } 973 974 if (id_blocked(pdev->device)) { 975 dev_info(&pdev->dev, "I915 probe blocked for Device ID %04x.\n", 976 pdev->device); 977 return -ENODEV; 978 } 979 980 if (intel_info->require_force_probe) { 981 dev_info(&pdev->dev, "Force probing unsupported Device ID %04x, tainting kernel\n", 982 pdev->device); 983 add_taint(TAINT_USER, LOCKDEP_STILL_OK); 984 } 985 986 /* Only bind to function 0 of the device. Early generations 987 * used function 1 as a placeholder for multi-head. This causes 988 * us confusion instead, especially on the systems where both 989 * functions have the same PCI-ID! 990 */ 991 if (PCI_FUNC(pdev->devfn)) 992 return -ENODEV; 993 994 if (!intel_mmio_bar_valid(pdev, intel_info)) 995 return -ENXIO; 996 997 /* Detect if we need to wait for other drivers early on */ 998 if (intel_display_driver_probe_defer(pdev)) 999 return -EPROBE_DEFER; 1000 1001 err = i915_driver_probe(pdev, ent); 1002 if (err) 1003 return err; 1004 1005 if (i915_inject_probe_failure(pdev_to_i915(pdev))) { 1006 i915_pci_remove(pdev); 1007 return -ENODEV; 1008 } 1009 1010 err = i915_live_selftests(pdev); 1011 if (err) { 1012 i915_pci_remove(pdev); 1013 return err > 0 ? -ENOTTY : err; 1014 } 1015 1016 err = i915_perf_selftests(pdev); 1017 if (err) { 1018 i915_pci_remove(pdev); 1019 return err > 0 ? -ENOTTY : err; 1020 } 1021 1022 return 0; 1023 } 1024 1025 static void i915_pci_shutdown(struct pci_dev *pdev) 1026 { 1027 struct drm_i915_private *i915 = pdev_to_i915(pdev); 1028 1029 i915_driver_shutdown(i915); 1030 } 1031 1032 static struct pci_driver i915_pci_driver = { 1033 .name = DRIVER_NAME, 1034 .id_table = pciidlist, 1035 .probe = i915_pci_probe, 1036 .remove = i915_pci_remove, 1037 .shutdown = i915_pci_shutdown, 1038 .driver.pm = &i915_pm_ops, 1039 }; 1040 1041 int i915_pci_register_driver(void) 1042 { 1043 return pci_register_driver(&i915_pci_driver); 1044 } 1045 1046 void i915_pci_unregister_driver(void) 1047 { 1048 pci_unregister_driver(&i915_pci_driver); 1049 } 1050