1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <drm/drm_drv.h> 26 #include <drm/i915_pciids.h> 27 28 #include "i915_driver.h" 29 #include "i915_drv.h" 30 #include "i915_pci.h" 31 #include "i915_reg.h" 32 33 #define PLATFORM(x) .platform = (x) 34 #define GEN(x) \ 35 .graphics.ver = (x), \ 36 .media.ver = (x), \ 37 .display.ver = (x) 38 39 #define I845_PIPE_OFFSETS \ 40 .pipe_offsets = { \ 41 [TRANSCODER_A] = PIPE_A_OFFSET, \ 42 }, \ 43 .trans_offsets = { \ 44 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 45 } 46 47 #define I9XX_PIPE_OFFSETS \ 48 .pipe_offsets = { \ 49 [TRANSCODER_A] = PIPE_A_OFFSET, \ 50 [TRANSCODER_B] = PIPE_B_OFFSET, \ 51 }, \ 52 .trans_offsets = { \ 53 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 54 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 55 } 56 57 #define IVB_PIPE_OFFSETS \ 58 .pipe_offsets = { \ 59 [TRANSCODER_A] = PIPE_A_OFFSET, \ 60 [TRANSCODER_B] = PIPE_B_OFFSET, \ 61 [TRANSCODER_C] = PIPE_C_OFFSET, \ 62 }, \ 63 .trans_offsets = { \ 64 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 65 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 66 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 67 } 68 69 #define HSW_PIPE_OFFSETS \ 70 .pipe_offsets = { \ 71 [TRANSCODER_A] = PIPE_A_OFFSET, \ 72 [TRANSCODER_B] = PIPE_B_OFFSET, \ 73 [TRANSCODER_C] = PIPE_C_OFFSET, \ 74 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 75 }, \ 76 .trans_offsets = { \ 77 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 78 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 79 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 80 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 81 } 82 83 #define CHV_PIPE_OFFSETS \ 84 .pipe_offsets = { \ 85 [TRANSCODER_A] = PIPE_A_OFFSET, \ 86 [TRANSCODER_B] = PIPE_B_OFFSET, \ 87 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \ 88 }, \ 89 .trans_offsets = { \ 90 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 91 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 92 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \ 93 } 94 95 #define I845_CURSOR_OFFSETS \ 96 .cursor_offsets = { \ 97 [PIPE_A] = CURSOR_A_OFFSET, \ 98 } 99 100 #define I9XX_CURSOR_OFFSETS \ 101 .cursor_offsets = { \ 102 [PIPE_A] = CURSOR_A_OFFSET, \ 103 [PIPE_B] = CURSOR_B_OFFSET, \ 104 } 105 106 #define CHV_CURSOR_OFFSETS \ 107 .cursor_offsets = { \ 108 [PIPE_A] = CURSOR_A_OFFSET, \ 109 [PIPE_B] = CURSOR_B_OFFSET, \ 110 [PIPE_C] = CHV_CURSOR_C_OFFSET, \ 111 } 112 113 #define IVB_CURSOR_OFFSETS \ 114 .cursor_offsets = { \ 115 [PIPE_A] = CURSOR_A_OFFSET, \ 116 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 117 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 118 } 119 120 #define TGL_CURSOR_OFFSETS \ 121 .cursor_offsets = { \ 122 [PIPE_A] = CURSOR_A_OFFSET, \ 123 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 124 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 125 [PIPE_D] = TGL_CURSOR_D_OFFSET, \ 126 } 127 128 #define I9XX_COLORS \ 129 .color = { .gamma_lut_size = 256 } 130 #define I965_COLORS \ 131 .color = { .gamma_lut_size = 129, \ 132 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 133 } 134 #define ILK_COLORS \ 135 .color = { .gamma_lut_size = 1024 } 136 #define IVB_COLORS \ 137 .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 } 138 #define CHV_COLORS \ 139 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \ 140 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 141 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 142 } 143 #define GLK_COLORS \ 144 .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \ 145 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 146 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 147 } 148 #define ICL_COLORS \ 149 .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145, \ 150 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 151 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 152 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 153 } 154 155 /* Keep in gen based order, and chronological order within a gen */ 156 157 #define GEN_DEFAULT_PAGE_SIZES \ 158 .page_sizes = I915_GTT_PAGE_SIZE_4K 159 160 #define GEN_DEFAULT_REGIONS \ 161 .memory_regions = REGION_SMEM | REGION_STOLEN_SMEM 162 163 #define I830_FEATURES \ 164 GEN(2), \ 165 .is_mobile = 1, \ 166 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 167 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 168 .display.has_overlay = 1, \ 169 .display.cursor_needs_physical = 1, \ 170 .display.overlay_needs_physical = 1, \ 171 .display.has_gmch = 1, \ 172 .gpu_reset_clobbers_display = true, \ 173 .hws_needs_physical = 1, \ 174 .unfenced_needs_alignment = 1, \ 175 .platform_engine_mask = BIT(RCS0), \ 176 .has_snoop = true, \ 177 .has_coherent_ggtt = false, \ 178 .dma_mask_size = 32, \ 179 I9XX_PIPE_OFFSETS, \ 180 I9XX_CURSOR_OFFSETS, \ 181 I9XX_COLORS, \ 182 GEN_DEFAULT_PAGE_SIZES, \ 183 GEN_DEFAULT_REGIONS 184 185 #define I845_FEATURES \ 186 GEN(2), \ 187 .display.pipe_mask = BIT(PIPE_A), \ 188 .display.cpu_transcoder_mask = BIT(TRANSCODER_A), \ 189 .display.has_overlay = 1, \ 190 .display.overlay_needs_physical = 1, \ 191 .display.has_gmch = 1, \ 192 .gpu_reset_clobbers_display = true, \ 193 .hws_needs_physical = 1, \ 194 .unfenced_needs_alignment = 1, \ 195 .platform_engine_mask = BIT(RCS0), \ 196 .has_snoop = true, \ 197 .has_coherent_ggtt = false, \ 198 .dma_mask_size = 32, \ 199 I845_PIPE_OFFSETS, \ 200 I845_CURSOR_OFFSETS, \ 201 I9XX_COLORS, \ 202 GEN_DEFAULT_PAGE_SIZES, \ 203 GEN_DEFAULT_REGIONS 204 205 static const struct intel_device_info i830_info = { 206 I830_FEATURES, 207 PLATFORM(INTEL_I830), 208 }; 209 210 static const struct intel_device_info i845g_info = { 211 I845_FEATURES, 212 PLATFORM(INTEL_I845G), 213 }; 214 215 static const struct intel_device_info i85x_info = { 216 I830_FEATURES, 217 PLATFORM(INTEL_I85X), 218 .display.fbc_mask = BIT(INTEL_FBC_A), 219 }; 220 221 static const struct intel_device_info i865g_info = { 222 I845_FEATURES, 223 PLATFORM(INTEL_I865G), 224 .display.fbc_mask = BIT(INTEL_FBC_A), 225 }; 226 227 #define GEN3_FEATURES \ 228 GEN(3), \ 229 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 230 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 231 .display.has_gmch = 1, \ 232 .gpu_reset_clobbers_display = true, \ 233 .platform_engine_mask = BIT(RCS0), \ 234 .has_snoop = true, \ 235 .has_coherent_ggtt = true, \ 236 .dma_mask_size = 32, \ 237 I9XX_PIPE_OFFSETS, \ 238 I9XX_CURSOR_OFFSETS, \ 239 I9XX_COLORS, \ 240 GEN_DEFAULT_PAGE_SIZES, \ 241 GEN_DEFAULT_REGIONS 242 243 static const struct intel_device_info i915g_info = { 244 GEN3_FEATURES, 245 PLATFORM(INTEL_I915G), 246 .has_coherent_ggtt = false, 247 .display.cursor_needs_physical = 1, 248 .display.has_overlay = 1, 249 .display.overlay_needs_physical = 1, 250 .hws_needs_physical = 1, 251 .unfenced_needs_alignment = 1, 252 }; 253 254 static const struct intel_device_info i915gm_info = { 255 GEN3_FEATURES, 256 PLATFORM(INTEL_I915GM), 257 .is_mobile = 1, 258 .display.cursor_needs_physical = 1, 259 .display.has_overlay = 1, 260 .display.overlay_needs_physical = 1, 261 .display.supports_tv = 1, 262 .display.fbc_mask = BIT(INTEL_FBC_A), 263 .hws_needs_physical = 1, 264 .unfenced_needs_alignment = 1, 265 }; 266 267 static const struct intel_device_info i945g_info = { 268 GEN3_FEATURES, 269 PLATFORM(INTEL_I945G), 270 .display.has_hotplug = 1, 271 .display.cursor_needs_physical = 1, 272 .display.has_overlay = 1, 273 .display.overlay_needs_physical = 1, 274 .hws_needs_physical = 1, 275 .unfenced_needs_alignment = 1, 276 }; 277 278 static const struct intel_device_info i945gm_info = { 279 GEN3_FEATURES, 280 PLATFORM(INTEL_I945GM), 281 .is_mobile = 1, 282 .display.has_hotplug = 1, 283 .display.cursor_needs_physical = 1, 284 .display.has_overlay = 1, 285 .display.overlay_needs_physical = 1, 286 .display.supports_tv = 1, 287 .display.fbc_mask = BIT(INTEL_FBC_A), 288 .hws_needs_physical = 1, 289 .unfenced_needs_alignment = 1, 290 }; 291 292 static const struct intel_device_info g33_info = { 293 GEN3_FEATURES, 294 PLATFORM(INTEL_G33), 295 .display.has_hotplug = 1, 296 .display.has_overlay = 1, 297 .dma_mask_size = 36, 298 }; 299 300 static const struct intel_device_info pnv_g_info = { 301 GEN3_FEATURES, 302 PLATFORM(INTEL_PINEVIEW), 303 .display.has_hotplug = 1, 304 .display.has_overlay = 1, 305 .dma_mask_size = 36, 306 }; 307 308 static const struct intel_device_info pnv_m_info = { 309 GEN3_FEATURES, 310 PLATFORM(INTEL_PINEVIEW), 311 .is_mobile = 1, 312 .display.has_hotplug = 1, 313 .display.has_overlay = 1, 314 .dma_mask_size = 36, 315 }; 316 317 #define GEN4_FEATURES \ 318 GEN(4), \ 319 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 320 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 321 .display.has_hotplug = 1, \ 322 .display.has_gmch = 1, \ 323 .gpu_reset_clobbers_display = true, \ 324 .platform_engine_mask = BIT(RCS0), \ 325 .has_snoop = true, \ 326 .has_coherent_ggtt = true, \ 327 .dma_mask_size = 36, \ 328 I9XX_PIPE_OFFSETS, \ 329 I9XX_CURSOR_OFFSETS, \ 330 I965_COLORS, \ 331 GEN_DEFAULT_PAGE_SIZES, \ 332 GEN_DEFAULT_REGIONS 333 334 static const struct intel_device_info i965g_info = { 335 GEN4_FEATURES, 336 PLATFORM(INTEL_I965G), 337 .display.has_overlay = 1, 338 .hws_needs_physical = 1, 339 .has_snoop = false, 340 }; 341 342 static const struct intel_device_info i965gm_info = { 343 GEN4_FEATURES, 344 PLATFORM(INTEL_I965GM), 345 .is_mobile = 1, 346 .display.fbc_mask = BIT(INTEL_FBC_A), 347 .display.has_overlay = 1, 348 .display.supports_tv = 1, 349 .hws_needs_physical = 1, 350 .has_snoop = false, 351 }; 352 353 static const struct intel_device_info g45_info = { 354 GEN4_FEATURES, 355 PLATFORM(INTEL_G45), 356 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), 357 .gpu_reset_clobbers_display = false, 358 }; 359 360 static const struct intel_device_info gm45_info = { 361 GEN4_FEATURES, 362 PLATFORM(INTEL_GM45), 363 .is_mobile = 1, 364 .display.fbc_mask = BIT(INTEL_FBC_A), 365 .display.supports_tv = 1, 366 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), 367 .gpu_reset_clobbers_display = false, 368 }; 369 370 #define GEN5_FEATURES \ 371 GEN(5), \ 372 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 373 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 374 .display.has_hotplug = 1, \ 375 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \ 376 .has_snoop = true, \ 377 .has_coherent_ggtt = true, \ 378 /* ilk does support rc6, but we do not implement [power] contexts */ \ 379 .has_rc6 = 0, \ 380 .dma_mask_size = 36, \ 381 I9XX_PIPE_OFFSETS, \ 382 I9XX_CURSOR_OFFSETS, \ 383 ILK_COLORS, \ 384 GEN_DEFAULT_PAGE_SIZES, \ 385 GEN_DEFAULT_REGIONS 386 387 static const struct intel_device_info ilk_d_info = { 388 GEN5_FEATURES, 389 PLATFORM(INTEL_IRONLAKE), 390 }; 391 392 static const struct intel_device_info ilk_m_info = { 393 GEN5_FEATURES, 394 PLATFORM(INTEL_IRONLAKE), 395 .is_mobile = 1, 396 .has_rps = true, 397 .display.fbc_mask = BIT(INTEL_FBC_A), 398 }; 399 400 #define GEN6_FEATURES \ 401 GEN(6), \ 402 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 403 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 404 .display.has_hotplug = 1, \ 405 .display.fbc_mask = BIT(INTEL_FBC_A), \ 406 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 407 .has_coherent_ggtt = true, \ 408 .has_llc = 1, \ 409 .has_rc6 = 1, \ 410 .has_rc6p = 1, \ 411 .has_rps = true, \ 412 .dma_mask_size = 40, \ 413 .ppgtt_type = INTEL_PPGTT_ALIASING, \ 414 .ppgtt_size = 31, \ 415 I9XX_PIPE_OFFSETS, \ 416 I9XX_CURSOR_OFFSETS, \ 417 ILK_COLORS, \ 418 GEN_DEFAULT_PAGE_SIZES, \ 419 GEN_DEFAULT_REGIONS 420 421 #define SNB_D_PLATFORM \ 422 GEN6_FEATURES, \ 423 PLATFORM(INTEL_SANDYBRIDGE) 424 425 static const struct intel_device_info snb_d_gt1_info = { 426 SNB_D_PLATFORM, 427 .gt = 1, 428 }; 429 430 static const struct intel_device_info snb_d_gt2_info = { 431 SNB_D_PLATFORM, 432 .gt = 2, 433 }; 434 435 #define SNB_M_PLATFORM \ 436 GEN6_FEATURES, \ 437 PLATFORM(INTEL_SANDYBRIDGE), \ 438 .is_mobile = 1 439 440 441 static const struct intel_device_info snb_m_gt1_info = { 442 SNB_M_PLATFORM, 443 .gt = 1, 444 }; 445 446 static const struct intel_device_info snb_m_gt2_info = { 447 SNB_M_PLATFORM, 448 .gt = 2, 449 }; 450 451 #define GEN7_FEATURES \ 452 GEN(7), \ 453 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 454 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \ 455 .display.has_hotplug = 1, \ 456 .display.fbc_mask = BIT(INTEL_FBC_A), \ 457 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 458 .has_coherent_ggtt = true, \ 459 .has_llc = 1, \ 460 .has_rc6 = 1, \ 461 .has_rc6p = 1, \ 462 .has_reset_engine = true, \ 463 .has_rps = true, \ 464 .dma_mask_size = 40, \ 465 .ppgtt_type = INTEL_PPGTT_ALIASING, \ 466 .ppgtt_size = 31, \ 467 IVB_PIPE_OFFSETS, \ 468 IVB_CURSOR_OFFSETS, \ 469 IVB_COLORS, \ 470 GEN_DEFAULT_PAGE_SIZES, \ 471 GEN_DEFAULT_REGIONS 472 473 #define IVB_D_PLATFORM \ 474 GEN7_FEATURES, \ 475 PLATFORM(INTEL_IVYBRIDGE), \ 476 .has_l3_dpf = 1 477 478 static const struct intel_device_info ivb_d_gt1_info = { 479 IVB_D_PLATFORM, 480 .gt = 1, 481 }; 482 483 static const struct intel_device_info ivb_d_gt2_info = { 484 IVB_D_PLATFORM, 485 .gt = 2, 486 }; 487 488 #define IVB_M_PLATFORM \ 489 GEN7_FEATURES, \ 490 PLATFORM(INTEL_IVYBRIDGE), \ 491 .is_mobile = 1, \ 492 .has_l3_dpf = 1 493 494 static const struct intel_device_info ivb_m_gt1_info = { 495 IVB_M_PLATFORM, 496 .gt = 1, 497 }; 498 499 static const struct intel_device_info ivb_m_gt2_info = { 500 IVB_M_PLATFORM, 501 .gt = 2, 502 }; 503 504 static const struct intel_device_info ivb_q_info = { 505 GEN7_FEATURES, 506 PLATFORM(INTEL_IVYBRIDGE), 507 .gt = 2, 508 .display.pipe_mask = 0, /* legal, last one wins */ 509 .display.cpu_transcoder_mask = 0, 510 .has_l3_dpf = 1, 511 }; 512 513 static const struct intel_device_info vlv_info = { 514 PLATFORM(INTEL_VALLEYVIEW), 515 GEN(7), 516 .is_lp = 1, 517 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), 518 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), 519 .has_runtime_pm = 1, 520 .has_rc6 = 1, 521 .has_reset_engine = true, 522 .has_rps = true, 523 .display.has_gmch = 1, 524 .display.has_hotplug = 1, 525 .dma_mask_size = 40, 526 .ppgtt_type = INTEL_PPGTT_ALIASING, 527 .ppgtt_size = 31, 528 .has_snoop = true, 529 .has_coherent_ggtt = false, 530 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), 531 .display_mmio_offset = VLV_DISPLAY_BASE, 532 I9XX_PIPE_OFFSETS, 533 I9XX_CURSOR_OFFSETS, 534 I965_COLORS, 535 GEN_DEFAULT_PAGE_SIZES, 536 GEN_DEFAULT_REGIONS, 537 }; 538 539 #define G75_FEATURES \ 540 GEN7_FEATURES, \ 541 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ 542 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 543 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \ 544 .display.has_ddi = 1, \ 545 .display.has_fpga_dbg = 1, \ 546 .display.has_dp_mst = 1, \ 547 .has_rc6p = 0 /* RC6p removed-by HSW */, \ 548 HSW_PIPE_OFFSETS, \ 549 .has_runtime_pm = 1 550 551 #define HSW_PLATFORM \ 552 G75_FEATURES, \ 553 PLATFORM(INTEL_HASWELL), \ 554 .has_l3_dpf = 1 555 556 static const struct intel_device_info hsw_gt1_info = { 557 HSW_PLATFORM, 558 .gt = 1, 559 }; 560 561 static const struct intel_device_info hsw_gt2_info = { 562 HSW_PLATFORM, 563 .gt = 2, 564 }; 565 566 static const struct intel_device_info hsw_gt3_info = { 567 HSW_PLATFORM, 568 .gt = 3, 569 }; 570 571 #define GEN8_FEATURES \ 572 G75_FEATURES, \ 573 GEN(8), \ 574 .has_logical_ring_contexts = 1, \ 575 .dma_mask_size = 39, \ 576 .ppgtt_type = INTEL_PPGTT_FULL, \ 577 .ppgtt_size = 48, \ 578 .has_64bit_reloc = 1 579 580 #define BDW_PLATFORM \ 581 GEN8_FEATURES, \ 582 PLATFORM(INTEL_BROADWELL) 583 584 static const struct intel_device_info bdw_gt1_info = { 585 BDW_PLATFORM, 586 .gt = 1, 587 }; 588 589 static const struct intel_device_info bdw_gt2_info = { 590 BDW_PLATFORM, 591 .gt = 2, 592 }; 593 594 static const struct intel_device_info bdw_rsvd_info = { 595 BDW_PLATFORM, 596 .gt = 3, 597 /* According to the device ID those devices are GT3, they were 598 * previously treated as not GT3, keep it like that. 599 */ 600 }; 601 602 static const struct intel_device_info bdw_gt3_info = { 603 BDW_PLATFORM, 604 .gt = 3, 605 .platform_engine_mask = 606 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 607 }; 608 609 static const struct intel_device_info chv_info = { 610 PLATFORM(INTEL_CHERRYVIEW), 611 GEN(8), 612 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 613 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), 614 .display.has_hotplug = 1, 615 .is_lp = 1, 616 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), 617 .has_64bit_reloc = 1, 618 .has_runtime_pm = 1, 619 .has_rc6 = 1, 620 .has_rps = true, 621 .has_logical_ring_contexts = 1, 622 .display.has_gmch = 1, 623 .dma_mask_size = 39, 624 .ppgtt_type = INTEL_PPGTT_FULL, 625 .ppgtt_size = 32, 626 .has_reset_engine = 1, 627 .has_snoop = true, 628 .has_coherent_ggtt = false, 629 .display_mmio_offset = VLV_DISPLAY_BASE, 630 CHV_PIPE_OFFSETS, 631 CHV_CURSOR_OFFSETS, 632 CHV_COLORS, 633 GEN_DEFAULT_PAGE_SIZES, 634 GEN_DEFAULT_REGIONS, 635 }; 636 637 #define GEN9_DEFAULT_PAGE_SIZES \ 638 .page_sizes = I915_GTT_PAGE_SIZE_4K | \ 639 I915_GTT_PAGE_SIZE_64K 640 641 #define GEN9_FEATURES \ 642 GEN8_FEATURES, \ 643 GEN(9), \ 644 GEN9_DEFAULT_PAGE_SIZES, \ 645 .display.has_dmc = 1, \ 646 .has_gt_uc = 1, \ 647 .display.has_hdcp = 1, \ 648 .display.has_ipc = 1, \ 649 .display.has_psr = 1, \ 650 .display.has_psr_hw_tracking = 1, \ 651 .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \ 652 .dbuf.slice_mask = BIT(DBUF_S1) 653 654 #define SKL_PLATFORM \ 655 GEN9_FEATURES, \ 656 PLATFORM(INTEL_SKYLAKE) 657 658 static const struct intel_device_info skl_gt1_info = { 659 SKL_PLATFORM, 660 .gt = 1, 661 }; 662 663 static const struct intel_device_info skl_gt2_info = { 664 SKL_PLATFORM, 665 .gt = 2, 666 }; 667 668 #define SKL_GT3_PLUS_PLATFORM \ 669 SKL_PLATFORM, \ 670 .platform_engine_mask = \ 671 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1) 672 673 674 static const struct intel_device_info skl_gt3_info = { 675 SKL_GT3_PLUS_PLATFORM, 676 .gt = 3, 677 }; 678 679 static const struct intel_device_info skl_gt4_info = { 680 SKL_GT3_PLUS_PLATFORM, 681 .gt = 4, 682 }; 683 684 #define GEN9_LP_FEATURES \ 685 GEN(9), \ 686 .is_lp = 1, \ 687 .dbuf.slice_mask = BIT(DBUF_S1), \ 688 .display.has_hotplug = 1, \ 689 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ 690 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 691 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 692 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ 693 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \ 694 .has_64bit_reloc = 1, \ 695 .display.has_ddi = 1, \ 696 .display.has_fpga_dbg = 1, \ 697 .display.fbc_mask = BIT(INTEL_FBC_A), \ 698 .display.has_hdcp = 1, \ 699 .display.has_psr = 1, \ 700 .display.has_psr_hw_tracking = 1, \ 701 .has_runtime_pm = 1, \ 702 .display.has_dmc = 1, \ 703 .has_rc6 = 1, \ 704 .has_rps = true, \ 705 .display.has_dp_mst = 1, \ 706 .has_logical_ring_contexts = 1, \ 707 .has_gt_uc = 1, \ 708 .dma_mask_size = 39, \ 709 .ppgtt_type = INTEL_PPGTT_FULL, \ 710 .ppgtt_size = 48, \ 711 .has_reset_engine = 1, \ 712 .has_snoop = true, \ 713 .has_coherent_ggtt = false, \ 714 .display.has_ipc = 1, \ 715 HSW_PIPE_OFFSETS, \ 716 IVB_CURSOR_OFFSETS, \ 717 IVB_COLORS, \ 718 GEN9_DEFAULT_PAGE_SIZES, \ 719 GEN_DEFAULT_REGIONS 720 721 static const struct intel_device_info bxt_info = { 722 GEN9_LP_FEATURES, 723 PLATFORM(INTEL_BROXTON), 724 .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */ 725 }; 726 727 static const struct intel_device_info glk_info = { 728 GEN9_LP_FEATURES, 729 PLATFORM(INTEL_GEMINILAKE), 730 .display.ver = 10, 731 .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ 732 GLK_COLORS, 733 }; 734 735 #define KBL_PLATFORM \ 736 GEN9_FEATURES, \ 737 PLATFORM(INTEL_KABYLAKE) 738 739 static const struct intel_device_info kbl_gt1_info = { 740 KBL_PLATFORM, 741 .gt = 1, 742 }; 743 744 static const struct intel_device_info kbl_gt2_info = { 745 KBL_PLATFORM, 746 .gt = 2, 747 }; 748 749 static const struct intel_device_info kbl_gt3_info = { 750 KBL_PLATFORM, 751 .gt = 3, 752 .platform_engine_mask = 753 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 754 }; 755 756 #define CFL_PLATFORM \ 757 GEN9_FEATURES, \ 758 PLATFORM(INTEL_COFFEELAKE) 759 760 static const struct intel_device_info cfl_gt1_info = { 761 CFL_PLATFORM, 762 .gt = 1, 763 }; 764 765 static const struct intel_device_info cfl_gt2_info = { 766 CFL_PLATFORM, 767 .gt = 2, 768 }; 769 770 static const struct intel_device_info cfl_gt3_info = { 771 CFL_PLATFORM, 772 .gt = 3, 773 .platform_engine_mask = 774 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 775 }; 776 777 #define CML_PLATFORM \ 778 GEN9_FEATURES, \ 779 PLATFORM(INTEL_COMETLAKE) 780 781 static const struct intel_device_info cml_gt1_info = { 782 CML_PLATFORM, 783 .gt = 1, 784 }; 785 786 static const struct intel_device_info cml_gt2_info = { 787 CML_PLATFORM, 788 .gt = 2, 789 }; 790 791 #define GEN11_DEFAULT_PAGE_SIZES \ 792 .page_sizes = I915_GTT_PAGE_SIZE_4K | \ 793 I915_GTT_PAGE_SIZE_64K | \ 794 I915_GTT_PAGE_SIZE_2M 795 796 #define GEN11_FEATURES \ 797 GEN9_FEATURES, \ 798 GEN11_DEFAULT_PAGE_SIZES, \ 799 .display.abox_mask = BIT(0), \ 800 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 801 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ 802 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ 803 .pipe_offsets = { \ 804 [TRANSCODER_A] = PIPE_A_OFFSET, \ 805 [TRANSCODER_B] = PIPE_B_OFFSET, \ 806 [TRANSCODER_C] = PIPE_C_OFFSET, \ 807 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 808 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 809 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 810 }, \ 811 .trans_offsets = { \ 812 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 813 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 814 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 815 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 816 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 817 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 818 }, \ 819 GEN(11), \ 820 ICL_COLORS, \ 821 .dbuf.size = 2048, \ 822 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \ 823 .display.has_dsc = 1, \ 824 .has_coherent_ggtt = false, \ 825 .has_logical_ring_elsq = 1 826 827 static const struct intel_device_info icl_info = { 828 GEN11_FEATURES, 829 PLATFORM(INTEL_ICELAKE), 830 .platform_engine_mask = 831 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 832 }; 833 834 static const struct intel_device_info ehl_info = { 835 GEN11_FEATURES, 836 PLATFORM(INTEL_ELKHARTLAKE), 837 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), 838 .ppgtt_size = 36, 839 }; 840 841 static const struct intel_device_info jsl_info = { 842 GEN11_FEATURES, 843 PLATFORM(INTEL_JASPERLAKE), 844 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), 845 .ppgtt_size = 36, 846 }; 847 848 #define GEN12_FEATURES \ 849 GEN11_FEATURES, \ 850 GEN(12), \ 851 .display.abox_mask = GENMASK(2, 1), \ 852 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ 853 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 854 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \ 855 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ 856 .pipe_offsets = { \ 857 [TRANSCODER_A] = PIPE_A_OFFSET, \ 858 [TRANSCODER_B] = PIPE_B_OFFSET, \ 859 [TRANSCODER_C] = PIPE_C_OFFSET, \ 860 [TRANSCODER_D] = PIPE_D_OFFSET, \ 861 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 862 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 863 }, \ 864 .trans_offsets = { \ 865 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 866 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 867 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 868 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 869 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 870 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 871 }, \ 872 TGL_CURSOR_OFFSETS, \ 873 .has_global_mocs = 1, \ 874 .has_pxp = 1, \ 875 .display.has_dsb = 0 /* FIXME: LUT load is broken with DSB */ 876 877 static const struct intel_device_info tgl_info = { 878 GEN12_FEATURES, 879 PLATFORM(INTEL_TIGERLAKE), 880 .display.has_modular_fia = 1, 881 .platform_engine_mask = 882 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 883 }; 884 885 static const struct intel_device_info rkl_info = { 886 GEN12_FEATURES, 887 PLATFORM(INTEL_ROCKETLAKE), 888 .display.abox_mask = BIT(0), 889 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 890 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 891 BIT(TRANSCODER_C), 892 .display.has_hti = 1, 893 .display.has_psr_hw_tracking = 0, 894 .platform_engine_mask = 895 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0), 896 }; 897 898 #define DGFX_FEATURES \ 899 .memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN_LMEM, \ 900 .has_llc = 0, \ 901 .has_pxp = 0, \ 902 .has_snoop = 1, \ 903 .is_dgfx = 1 904 905 static const struct intel_device_info dg1_info = { 906 GEN12_FEATURES, 907 DGFX_FEATURES, 908 .graphics.rel = 10, 909 PLATFORM(INTEL_DG1), 910 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 911 .require_force_probe = 1, 912 .platform_engine_mask = 913 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | 914 BIT(VCS0) | BIT(VCS2), 915 /* Wa_16011227922 */ 916 .ppgtt_size = 47, 917 }; 918 919 static const struct intel_device_info adl_s_info = { 920 GEN12_FEATURES, 921 PLATFORM(INTEL_ALDERLAKE_S), 922 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 923 .display.has_hti = 1, 924 .display.has_psr_hw_tracking = 0, 925 .platform_engine_mask = 926 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 927 .dma_mask_size = 39, 928 }; 929 930 #define XE_LPD_CURSOR_OFFSETS \ 931 .cursor_offsets = { \ 932 [PIPE_A] = CURSOR_A_OFFSET, \ 933 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 934 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 935 [PIPE_D] = TGL_CURSOR_D_OFFSET, \ 936 } 937 938 #define XE_LPD_FEATURES \ 939 .display.abox_mask = GENMASK(1, 0), \ 940 .color = { .degamma_lut_size = 128, .gamma_lut_size = 1024, \ 941 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 942 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 943 }, \ 944 .dbuf.size = 4096, \ 945 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \ 946 BIT(DBUF_S4), \ 947 .display.has_ddi = 1, \ 948 .display.has_dmc = 1, \ 949 .display.has_dp_mst = 1, \ 950 .display.has_dsb = 1, \ 951 .display.has_dsc = 1, \ 952 .display.fbc_mask = BIT(INTEL_FBC_A), \ 953 .display.has_fpga_dbg = 1, \ 954 .display.has_hdcp = 1, \ 955 .display.has_hotplug = 1, \ 956 .display.has_ipc = 1, \ 957 .display.has_psr = 1, \ 958 .display.ver = 13, \ 959 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ 960 .pipe_offsets = { \ 961 [TRANSCODER_A] = PIPE_A_OFFSET, \ 962 [TRANSCODER_B] = PIPE_B_OFFSET, \ 963 [TRANSCODER_C] = PIPE_C_OFFSET, \ 964 [TRANSCODER_D] = PIPE_D_OFFSET, \ 965 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 966 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 967 }, \ 968 .trans_offsets = { \ 969 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 970 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 971 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 972 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 973 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 974 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 975 }, \ 976 XE_LPD_CURSOR_OFFSETS 977 978 static const struct intel_device_info adl_p_info = { 979 GEN12_FEATURES, 980 XE_LPD_FEATURES, 981 PLATFORM(INTEL_ALDERLAKE_P), 982 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 983 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | 984 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), 985 .display.has_cdclk_crawl = 1, 986 .display.has_modular_fia = 1, 987 .display.has_psr_hw_tracking = 0, 988 .platform_engine_mask = 989 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 990 .ppgtt_size = 48, 991 .dma_mask_size = 39, 992 }; 993 994 #undef GEN 995 996 #define XE_HP_PAGE_SIZES \ 997 .page_sizes = I915_GTT_PAGE_SIZE_4K | \ 998 I915_GTT_PAGE_SIZE_64K | \ 999 I915_GTT_PAGE_SIZE_2M 1000 1001 #define XE_HP_FEATURES \ 1002 .graphics.ver = 12, \ 1003 .graphics.rel = 50, \ 1004 XE_HP_PAGE_SIZES, \ 1005 .dma_mask_size = 46, \ 1006 .has_64bit_reloc = 1, \ 1007 .has_global_mocs = 1, \ 1008 .has_gt_uc = 1, \ 1009 .has_llc = 1, \ 1010 .has_logical_ring_contexts = 1, \ 1011 .has_logical_ring_elsq = 1, \ 1012 .has_mslices = 1, \ 1013 .has_rc6 = 1, \ 1014 .has_reset_engine = 1, \ 1015 .has_rps = 1, \ 1016 .has_runtime_pm = 1, \ 1017 .ppgtt_size = 48, \ 1018 .ppgtt_type = INTEL_PPGTT_FULL 1019 1020 #define XE_HPM_FEATURES \ 1021 .media.ver = 12, \ 1022 .media.rel = 50 1023 1024 __maybe_unused 1025 static const struct intel_device_info xehpsdv_info = { 1026 XE_HP_FEATURES, 1027 XE_HPM_FEATURES, 1028 DGFX_FEATURES, 1029 PLATFORM(INTEL_XEHPSDV), 1030 .display = { }, 1031 .has_64k_pages = 1, 1032 .platform_engine_mask = 1033 BIT(RCS0) | BIT(BCS0) | 1034 BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) | 1035 BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) | 1036 BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7), 1037 .require_force_probe = 1, 1038 }; 1039 1040 __maybe_unused 1041 static const struct intel_device_info dg2_info = { 1042 XE_HP_FEATURES, 1043 XE_HPM_FEATURES, 1044 XE_LPD_FEATURES, 1045 DGFX_FEATURES, 1046 .graphics.rel = 55, 1047 .media.rel = 55, 1048 PLATFORM(INTEL_DG2), 1049 .has_64k_pages = 1, 1050 .platform_engine_mask = 1051 BIT(RCS0) | BIT(BCS0) | 1052 BIT(VECS0) | BIT(VECS1) | 1053 BIT(VCS0) | BIT(VCS2), 1054 .require_force_probe = 1, 1055 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 1056 BIT(TRANSCODER_C) | BIT(TRANSCODER_D), 1057 }; 1058 1059 #undef PLATFORM 1060 1061 /* 1062 * Make sure any device matches here are from most specific to most 1063 * general. For example, since the Quanta match is based on the subsystem 1064 * and subvendor IDs, we need it to come before the more general IVB 1065 * PCI ID matches, otherwise we'll use the wrong info struct above. 1066 */ 1067 static const struct pci_device_id pciidlist[] = { 1068 INTEL_I830_IDS(&i830_info), 1069 INTEL_I845G_IDS(&i845g_info), 1070 INTEL_I85X_IDS(&i85x_info), 1071 INTEL_I865G_IDS(&i865g_info), 1072 INTEL_I915G_IDS(&i915g_info), 1073 INTEL_I915GM_IDS(&i915gm_info), 1074 INTEL_I945G_IDS(&i945g_info), 1075 INTEL_I945GM_IDS(&i945gm_info), 1076 INTEL_I965G_IDS(&i965g_info), 1077 INTEL_G33_IDS(&g33_info), 1078 INTEL_I965GM_IDS(&i965gm_info), 1079 INTEL_GM45_IDS(&gm45_info), 1080 INTEL_G45_IDS(&g45_info), 1081 INTEL_PINEVIEW_G_IDS(&pnv_g_info), 1082 INTEL_PINEVIEW_M_IDS(&pnv_m_info), 1083 INTEL_IRONLAKE_D_IDS(&ilk_d_info), 1084 INTEL_IRONLAKE_M_IDS(&ilk_m_info), 1085 INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info), 1086 INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info), 1087 INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info), 1088 INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info), 1089 INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */ 1090 INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info), 1091 INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info), 1092 INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info), 1093 INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info), 1094 INTEL_HSW_GT1_IDS(&hsw_gt1_info), 1095 INTEL_HSW_GT2_IDS(&hsw_gt2_info), 1096 INTEL_HSW_GT3_IDS(&hsw_gt3_info), 1097 INTEL_VLV_IDS(&vlv_info), 1098 INTEL_BDW_GT1_IDS(&bdw_gt1_info), 1099 INTEL_BDW_GT2_IDS(&bdw_gt2_info), 1100 INTEL_BDW_GT3_IDS(&bdw_gt3_info), 1101 INTEL_BDW_RSVD_IDS(&bdw_rsvd_info), 1102 INTEL_CHV_IDS(&chv_info), 1103 INTEL_SKL_GT1_IDS(&skl_gt1_info), 1104 INTEL_SKL_GT2_IDS(&skl_gt2_info), 1105 INTEL_SKL_GT3_IDS(&skl_gt3_info), 1106 INTEL_SKL_GT4_IDS(&skl_gt4_info), 1107 INTEL_BXT_IDS(&bxt_info), 1108 INTEL_GLK_IDS(&glk_info), 1109 INTEL_KBL_GT1_IDS(&kbl_gt1_info), 1110 INTEL_KBL_GT2_IDS(&kbl_gt2_info), 1111 INTEL_KBL_GT3_IDS(&kbl_gt3_info), 1112 INTEL_KBL_GT4_IDS(&kbl_gt3_info), 1113 INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info), 1114 INTEL_CFL_S_GT1_IDS(&cfl_gt1_info), 1115 INTEL_CFL_S_GT2_IDS(&cfl_gt2_info), 1116 INTEL_CFL_H_GT1_IDS(&cfl_gt1_info), 1117 INTEL_CFL_H_GT2_IDS(&cfl_gt2_info), 1118 INTEL_CFL_U_GT2_IDS(&cfl_gt2_info), 1119 INTEL_CFL_U_GT3_IDS(&cfl_gt3_info), 1120 INTEL_WHL_U_GT1_IDS(&cfl_gt1_info), 1121 INTEL_WHL_U_GT2_IDS(&cfl_gt2_info), 1122 INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info), 1123 INTEL_WHL_U_GT3_IDS(&cfl_gt3_info), 1124 INTEL_CML_GT1_IDS(&cml_gt1_info), 1125 INTEL_CML_GT2_IDS(&cml_gt2_info), 1126 INTEL_CML_U_GT1_IDS(&cml_gt1_info), 1127 INTEL_CML_U_GT2_IDS(&cml_gt2_info), 1128 INTEL_ICL_11_IDS(&icl_info), 1129 INTEL_EHL_IDS(&ehl_info), 1130 INTEL_JSL_IDS(&jsl_info), 1131 INTEL_TGL_12_IDS(&tgl_info), 1132 INTEL_RKL_IDS(&rkl_info), 1133 INTEL_ADLS_IDS(&adl_s_info), 1134 INTEL_ADLP_IDS(&adl_p_info), 1135 INTEL_ADLN_IDS(&adl_p_info), 1136 INTEL_DG1_IDS(&dg1_info), 1137 INTEL_RPLS_IDS(&adl_s_info), 1138 {0, 0, 0} 1139 }; 1140 MODULE_DEVICE_TABLE(pci, pciidlist); 1141 1142 static void i915_pci_remove(struct pci_dev *pdev) 1143 { 1144 struct drm_i915_private *i915; 1145 1146 i915 = pci_get_drvdata(pdev); 1147 if (!i915) /* driver load aborted, nothing to cleanup */ 1148 return; 1149 1150 i915_driver_remove(i915); 1151 pci_set_drvdata(pdev, NULL); 1152 } 1153 1154 /* is device_id present in comma separated list of ids */ 1155 static bool force_probe(u16 device_id, const char *devices) 1156 { 1157 char *s, *p, *tok; 1158 bool ret; 1159 1160 if (!devices || !*devices) 1161 return false; 1162 1163 /* match everything */ 1164 if (strcmp(devices, "*") == 0) 1165 return true; 1166 1167 s = kstrdup(devices, GFP_KERNEL); 1168 if (!s) 1169 return false; 1170 1171 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) { 1172 u16 val; 1173 1174 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) { 1175 ret = true; 1176 break; 1177 } 1178 } 1179 1180 kfree(s); 1181 1182 return ret; 1183 } 1184 1185 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1186 { 1187 struct intel_device_info *intel_info = 1188 (struct intel_device_info *) ent->driver_data; 1189 int err; 1190 1191 if (intel_info->require_force_probe && 1192 !force_probe(pdev->device, i915_modparams.force_probe)) { 1193 dev_info(&pdev->dev, 1194 "Your graphics device %04x is not properly supported by the driver in this\n" 1195 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n" 1196 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n" 1197 "or (recommended) check for kernel updates.\n", 1198 pdev->device, pdev->device, pdev->device); 1199 return -ENODEV; 1200 } 1201 1202 /* Only bind to function 0 of the device. Early generations 1203 * used function 1 as a placeholder for multi-head. This causes 1204 * us confusion instead, especially on the systems where both 1205 * functions have the same PCI-ID! 1206 */ 1207 if (PCI_FUNC(pdev->devfn)) 1208 return -ENODEV; 1209 1210 /* Detect if we need to wait for other drivers early on */ 1211 if (intel_modeset_probe_defer(pdev)) 1212 return -EPROBE_DEFER; 1213 1214 err = i915_driver_probe(pdev, ent); 1215 if (err) 1216 return err; 1217 1218 if (i915_inject_probe_failure(pci_get_drvdata(pdev))) { 1219 i915_pci_remove(pdev); 1220 return -ENODEV; 1221 } 1222 1223 err = i915_live_selftests(pdev); 1224 if (err) { 1225 i915_pci_remove(pdev); 1226 return err > 0 ? -ENOTTY : err; 1227 } 1228 1229 err = i915_perf_selftests(pdev); 1230 if (err) { 1231 i915_pci_remove(pdev); 1232 return err > 0 ? -ENOTTY : err; 1233 } 1234 1235 return 0; 1236 } 1237 1238 static void i915_pci_shutdown(struct pci_dev *pdev) 1239 { 1240 struct drm_i915_private *i915 = pci_get_drvdata(pdev); 1241 1242 i915_driver_shutdown(i915); 1243 } 1244 1245 static struct pci_driver i915_pci_driver = { 1246 .name = DRIVER_NAME, 1247 .id_table = pciidlist, 1248 .probe = i915_pci_probe, 1249 .remove = i915_pci_remove, 1250 .shutdown = i915_pci_shutdown, 1251 .driver.pm = &i915_pm_ops, 1252 }; 1253 1254 int i915_pci_register_driver(void) 1255 { 1256 return pci_register_driver(&i915_pci_driver); 1257 } 1258 1259 void i915_pci_unregister_driver(void) 1260 { 1261 pci_unregister_driver(&i915_pci_driver); 1262 } 1263