1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <drm/drm_color_mgmt.h> 26 #include <drm/drm_drv.h> 27 #include <drm/i915_pciids.h> 28 29 #include "display/intel_display.h" 30 #include "display/intel_display_driver.h" 31 #include "gt/intel_gt_regs.h" 32 #include "gt/intel_sa_media.h" 33 #include "gem/i915_gem_object_types.h" 34 35 #include "i915_driver.h" 36 #include "i915_drv.h" 37 #include "i915_pci.h" 38 #include "i915_reg.h" 39 #include "intel_pci_config.h" 40 41 __diag_push(); 42 __diag_ignore_all("-Woverride-init", "Allow field initialization overrides for device info"); 43 44 #define PLATFORM(x) .platform = (x) 45 #define GEN(x) \ 46 .__runtime.graphics.ip.ver = (x), \ 47 .__runtime.media.ip.ver = (x) 48 49 #define LEGACY_CACHELEVEL \ 50 .cachelevel_to_pat = { \ 51 [I915_CACHE_NONE] = 0, \ 52 [I915_CACHE_LLC] = 1, \ 53 [I915_CACHE_L3_LLC] = 2, \ 54 [I915_CACHE_WT] = 3, \ 55 } 56 57 #define TGL_CACHELEVEL \ 58 .cachelevel_to_pat = { \ 59 [I915_CACHE_NONE] = 3, \ 60 [I915_CACHE_LLC] = 0, \ 61 [I915_CACHE_L3_LLC] = 0, \ 62 [I915_CACHE_WT] = 2, \ 63 } 64 65 #define MTL_CACHELEVEL \ 66 .cachelevel_to_pat = { \ 67 [I915_CACHE_NONE] = 2, \ 68 [I915_CACHE_LLC] = 3, \ 69 [I915_CACHE_L3_LLC] = 3, \ 70 [I915_CACHE_WT] = 1, \ 71 } 72 73 /* Keep in gen based order, and chronological order within a gen */ 74 75 #define GEN_DEFAULT_PAGE_SIZES \ 76 .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K 77 78 #define GEN_DEFAULT_REGIONS \ 79 .memory_regions = REGION_SMEM | REGION_STOLEN_SMEM 80 81 #define I830_FEATURES \ 82 GEN(2), \ 83 .is_mobile = 1, \ 84 .gpu_reset_clobbers_display = true, \ 85 .has_3d_pipeline = 1, \ 86 .hws_needs_physical = 1, \ 87 .unfenced_needs_alignment = 1, \ 88 .platform_engine_mask = BIT(RCS0), \ 89 .has_snoop = true, \ 90 .has_coherent_ggtt = false, \ 91 .dma_mask_size = 32, \ 92 .max_pat_index = 3, \ 93 GEN_DEFAULT_PAGE_SIZES, \ 94 GEN_DEFAULT_REGIONS, \ 95 LEGACY_CACHELEVEL 96 97 #define I845_FEATURES \ 98 GEN(2), \ 99 .has_3d_pipeline = 1, \ 100 .gpu_reset_clobbers_display = true, \ 101 .hws_needs_physical = 1, \ 102 .unfenced_needs_alignment = 1, \ 103 .platform_engine_mask = BIT(RCS0), \ 104 .has_snoop = true, \ 105 .has_coherent_ggtt = false, \ 106 .dma_mask_size = 32, \ 107 .max_pat_index = 3, \ 108 GEN_DEFAULT_PAGE_SIZES, \ 109 GEN_DEFAULT_REGIONS, \ 110 LEGACY_CACHELEVEL 111 112 static const struct intel_device_info i830_info = { 113 I830_FEATURES, 114 PLATFORM(INTEL_I830), 115 }; 116 117 static const struct intel_device_info i845g_info = { 118 I845_FEATURES, 119 PLATFORM(INTEL_I845G), 120 }; 121 122 static const struct intel_device_info i85x_info = { 123 I830_FEATURES, 124 PLATFORM(INTEL_I85X), 125 }; 126 127 static const struct intel_device_info i865g_info = { 128 I845_FEATURES, 129 PLATFORM(INTEL_I865G), 130 }; 131 132 #define GEN3_FEATURES \ 133 GEN(3), \ 134 .gpu_reset_clobbers_display = true, \ 135 .platform_engine_mask = BIT(RCS0), \ 136 .has_3d_pipeline = 1, \ 137 .has_snoop = true, \ 138 .has_coherent_ggtt = true, \ 139 .dma_mask_size = 32, \ 140 .max_pat_index = 3, \ 141 GEN_DEFAULT_PAGE_SIZES, \ 142 GEN_DEFAULT_REGIONS, \ 143 LEGACY_CACHELEVEL 144 145 static const struct intel_device_info i915g_info = { 146 GEN3_FEATURES, 147 PLATFORM(INTEL_I915G), 148 .has_coherent_ggtt = false, 149 .hws_needs_physical = 1, 150 .unfenced_needs_alignment = 1, 151 }; 152 153 static const struct intel_device_info i915gm_info = { 154 GEN3_FEATURES, 155 PLATFORM(INTEL_I915GM), 156 .is_mobile = 1, 157 .hws_needs_physical = 1, 158 .unfenced_needs_alignment = 1, 159 }; 160 161 static const struct intel_device_info i945g_info = { 162 GEN3_FEATURES, 163 PLATFORM(INTEL_I945G), 164 .hws_needs_physical = 1, 165 .unfenced_needs_alignment = 1, 166 }; 167 168 static const struct intel_device_info i945gm_info = { 169 GEN3_FEATURES, 170 PLATFORM(INTEL_I945GM), 171 .is_mobile = 1, 172 .hws_needs_physical = 1, 173 .unfenced_needs_alignment = 1, 174 }; 175 176 static const struct intel_device_info g33_info = { 177 GEN3_FEATURES, 178 PLATFORM(INTEL_G33), 179 .dma_mask_size = 36, 180 }; 181 182 static const struct intel_device_info pnv_g_info = { 183 GEN3_FEATURES, 184 PLATFORM(INTEL_PINEVIEW), 185 .dma_mask_size = 36, 186 }; 187 188 static const struct intel_device_info pnv_m_info = { 189 GEN3_FEATURES, 190 PLATFORM(INTEL_PINEVIEW), 191 .is_mobile = 1, 192 .dma_mask_size = 36, 193 }; 194 195 #define GEN4_FEATURES \ 196 GEN(4), \ 197 .gpu_reset_clobbers_display = true, \ 198 .platform_engine_mask = BIT(RCS0), \ 199 .has_3d_pipeline = 1, \ 200 .has_snoop = true, \ 201 .has_coherent_ggtt = true, \ 202 .dma_mask_size = 36, \ 203 .max_pat_index = 3, \ 204 GEN_DEFAULT_PAGE_SIZES, \ 205 GEN_DEFAULT_REGIONS, \ 206 LEGACY_CACHELEVEL 207 208 static const struct intel_device_info i965g_info = { 209 GEN4_FEATURES, 210 PLATFORM(INTEL_I965G), 211 .hws_needs_physical = 1, 212 .has_snoop = false, 213 }; 214 215 static const struct intel_device_info i965gm_info = { 216 GEN4_FEATURES, 217 PLATFORM(INTEL_I965GM), 218 .is_mobile = 1, 219 .hws_needs_physical = 1, 220 .has_snoop = false, 221 }; 222 223 static const struct intel_device_info g45_info = { 224 GEN4_FEATURES, 225 PLATFORM(INTEL_G45), 226 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), 227 .gpu_reset_clobbers_display = false, 228 }; 229 230 static const struct intel_device_info gm45_info = { 231 GEN4_FEATURES, 232 PLATFORM(INTEL_GM45), 233 .is_mobile = 1, 234 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), 235 .gpu_reset_clobbers_display = false, 236 }; 237 238 #define GEN5_FEATURES \ 239 GEN(5), \ 240 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \ 241 .has_3d_pipeline = 1, \ 242 .has_snoop = true, \ 243 .has_coherent_ggtt = true, \ 244 /* ilk does support rc6, but we do not implement [power] contexts */ \ 245 .has_rc6 = 0, \ 246 .dma_mask_size = 36, \ 247 .max_pat_index = 3, \ 248 GEN_DEFAULT_PAGE_SIZES, \ 249 GEN_DEFAULT_REGIONS, \ 250 LEGACY_CACHELEVEL 251 252 static const struct intel_device_info ilk_d_info = { 253 GEN5_FEATURES, 254 PLATFORM(INTEL_IRONLAKE), 255 }; 256 257 static const struct intel_device_info ilk_m_info = { 258 GEN5_FEATURES, 259 PLATFORM(INTEL_IRONLAKE), 260 .is_mobile = 1, 261 .has_rps = true, 262 }; 263 264 #define GEN6_FEATURES \ 265 GEN(6), \ 266 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 267 .has_3d_pipeline = 1, \ 268 .has_coherent_ggtt = true, \ 269 .has_llc = 1, \ 270 .has_rc6 = 1, \ 271 /* snb does support rc6p, but enabling it causes various issues */ \ 272 .has_rc6p = 0, \ 273 .has_rps = true, \ 274 .dma_mask_size = 40, \ 275 .max_pat_index = 3, \ 276 .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \ 277 .__runtime.ppgtt_size = 31, \ 278 GEN_DEFAULT_PAGE_SIZES, \ 279 GEN_DEFAULT_REGIONS, \ 280 LEGACY_CACHELEVEL 281 282 #define SNB_D_PLATFORM \ 283 GEN6_FEATURES, \ 284 PLATFORM(INTEL_SANDYBRIDGE) 285 286 static const struct intel_device_info snb_d_gt1_info = { 287 SNB_D_PLATFORM, 288 .gt = 1, 289 }; 290 291 static const struct intel_device_info snb_d_gt2_info = { 292 SNB_D_PLATFORM, 293 .gt = 2, 294 }; 295 296 #define SNB_M_PLATFORM \ 297 GEN6_FEATURES, \ 298 PLATFORM(INTEL_SANDYBRIDGE), \ 299 .is_mobile = 1 300 301 302 static const struct intel_device_info snb_m_gt1_info = { 303 SNB_M_PLATFORM, 304 .gt = 1, 305 }; 306 307 static const struct intel_device_info snb_m_gt2_info = { 308 SNB_M_PLATFORM, 309 .gt = 2, 310 }; 311 312 #define GEN7_FEATURES \ 313 GEN(7), \ 314 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 315 .has_3d_pipeline = 1, \ 316 .has_coherent_ggtt = true, \ 317 .has_llc = 1, \ 318 .has_rc6 = 1, \ 319 .has_rc6p = 1, \ 320 .has_reset_engine = true, \ 321 .has_rps = true, \ 322 .dma_mask_size = 40, \ 323 .max_pat_index = 3, \ 324 .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \ 325 .__runtime.ppgtt_size = 31, \ 326 GEN_DEFAULT_PAGE_SIZES, \ 327 GEN_DEFAULT_REGIONS, \ 328 LEGACY_CACHELEVEL 329 330 #define IVB_D_PLATFORM \ 331 GEN7_FEATURES, \ 332 PLATFORM(INTEL_IVYBRIDGE), \ 333 .has_l3_dpf = 1 334 335 static const struct intel_device_info ivb_d_gt1_info = { 336 IVB_D_PLATFORM, 337 .gt = 1, 338 }; 339 340 static const struct intel_device_info ivb_d_gt2_info = { 341 IVB_D_PLATFORM, 342 .gt = 2, 343 }; 344 345 #define IVB_M_PLATFORM \ 346 GEN7_FEATURES, \ 347 PLATFORM(INTEL_IVYBRIDGE), \ 348 .is_mobile = 1, \ 349 .has_l3_dpf = 1 350 351 static const struct intel_device_info ivb_m_gt1_info = { 352 IVB_M_PLATFORM, 353 .gt = 1, 354 }; 355 356 static const struct intel_device_info ivb_m_gt2_info = { 357 IVB_M_PLATFORM, 358 .gt = 2, 359 }; 360 361 static const struct intel_device_info ivb_q_info = { 362 GEN7_FEATURES, 363 PLATFORM(INTEL_IVYBRIDGE), 364 .gt = 2, 365 .has_l3_dpf = 1, 366 }; 367 368 static const struct intel_device_info vlv_info = { 369 PLATFORM(INTEL_VALLEYVIEW), 370 GEN(7), 371 .is_lp = 1, 372 .has_runtime_pm = 1, 373 .has_rc6 = 1, 374 .has_reset_engine = true, 375 .has_rps = true, 376 .dma_mask_size = 40, 377 .max_pat_index = 3, 378 .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, 379 .__runtime.ppgtt_size = 31, 380 .has_snoop = true, 381 .has_coherent_ggtt = false, 382 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), 383 GEN_DEFAULT_PAGE_SIZES, 384 GEN_DEFAULT_REGIONS, 385 LEGACY_CACHELEVEL, 386 }; 387 388 #define G75_FEATURES \ 389 GEN7_FEATURES, \ 390 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ 391 .has_rc6p = 0 /* RC6p removed-by HSW */, \ 392 .has_runtime_pm = 1 393 394 #define HSW_PLATFORM \ 395 G75_FEATURES, \ 396 PLATFORM(INTEL_HASWELL), \ 397 .has_l3_dpf = 1 398 399 static const struct intel_device_info hsw_gt1_info = { 400 HSW_PLATFORM, 401 .gt = 1, 402 }; 403 404 static const struct intel_device_info hsw_gt2_info = { 405 HSW_PLATFORM, 406 .gt = 2, 407 }; 408 409 static const struct intel_device_info hsw_gt3_info = { 410 HSW_PLATFORM, 411 .gt = 3, 412 }; 413 414 #define GEN8_FEATURES \ 415 G75_FEATURES, \ 416 GEN(8), \ 417 .has_logical_ring_contexts = 1, \ 418 .dma_mask_size = 39, \ 419 .__runtime.ppgtt_type = INTEL_PPGTT_FULL, \ 420 .__runtime.ppgtt_size = 48, \ 421 .has_64bit_reloc = 1 422 423 #define BDW_PLATFORM \ 424 GEN8_FEATURES, \ 425 PLATFORM(INTEL_BROADWELL) 426 427 static const struct intel_device_info bdw_gt1_info = { 428 BDW_PLATFORM, 429 .gt = 1, 430 }; 431 432 static const struct intel_device_info bdw_gt2_info = { 433 BDW_PLATFORM, 434 .gt = 2, 435 }; 436 437 static const struct intel_device_info bdw_rsvd_info = { 438 BDW_PLATFORM, 439 .gt = 3, 440 /* According to the device ID those devices are GT3, they were 441 * previously treated as not GT3, keep it like that. 442 */ 443 }; 444 445 static const struct intel_device_info bdw_gt3_info = { 446 BDW_PLATFORM, 447 .gt = 3, 448 .platform_engine_mask = 449 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 450 }; 451 452 static const struct intel_device_info chv_info = { 453 PLATFORM(INTEL_CHERRYVIEW), 454 GEN(8), 455 .is_lp = 1, 456 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), 457 .has_64bit_reloc = 1, 458 .has_runtime_pm = 1, 459 .has_rc6 = 1, 460 .has_rps = true, 461 .has_logical_ring_contexts = 1, 462 .dma_mask_size = 39, 463 .max_pat_index = 3, 464 .__runtime.ppgtt_type = INTEL_PPGTT_FULL, 465 .__runtime.ppgtt_size = 32, 466 .has_reset_engine = 1, 467 .has_snoop = true, 468 .has_coherent_ggtt = false, 469 GEN_DEFAULT_PAGE_SIZES, 470 GEN_DEFAULT_REGIONS, 471 LEGACY_CACHELEVEL, 472 }; 473 474 #define GEN9_DEFAULT_PAGE_SIZES \ 475 .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \ 476 I915_GTT_PAGE_SIZE_64K 477 478 #define GEN9_FEATURES \ 479 GEN8_FEATURES, \ 480 GEN(9), \ 481 GEN9_DEFAULT_PAGE_SIZES, \ 482 .has_gt_uc = 1 483 484 #define SKL_PLATFORM \ 485 GEN9_FEATURES, \ 486 PLATFORM(INTEL_SKYLAKE) 487 488 static const struct intel_device_info skl_gt1_info = { 489 SKL_PLATFORM, 490 .gt = 1, 491 }; 492 493 static const struct intel_device_info skl_gt2_info = { 494 SKL_PLATFORM, 495 .gt = 2, 496 }; 497 498 #define SKL_GT3_PLUS_PLATFORM \ 499 SKL_PLATFORM, \ 500 .platform_engine_mask = \ 501 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1) 502 503 504 static const struct intel_device_info skl_gt3_info = { 505 SKL_GT3_PLUS_PLATFORM, 506 .gt = 3, 507 }; 508 509 static const struct intel_device_info skl_gt4_info = { 510 SKL_GT3_PLUS_PLATFORM, 511 .gt = 4, 512 }; 513 514 #define GEN9_LP_FEATURES \ 515 GEN(9), \ 516 .is_lp = 1, \ 517 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ 518 .has_3d_pipeline = 1, \ 519 .has_64bit_reloc = 1, \ 520 .has_runtime_pm = 1, \ 521 .has_rc6 = 1, \ 522 .has_rps = true, \ 523 .has_logical_ring_contexts = 1, \ 524 .has_gt_uc = 1, \ 525 .dma_mask_size = 39, \ 526 .__runtime.ppgtt_type = INTEL_PPGTT_FULL, \ 527 .__runtime.ppgtt_size = 48, \ 528 .has_reset_engine = 1, \ 529 .has_snoop = true, \ 530 .has_coherent_ggtt = false, \ 531 .max_pat_index = 3, \ 532 GEN9_DEFAULT_PAGE_SIZES, \ 533 GEN_DEFAULT_REGIONS, \ 534 LEGACY_CACHELEVEL 535 536 static const struct intel_device_info bxt_info = { 537 GEN9_LP_FEATURES, 538 PLATFORM(INTEL_BROXTON), 539 }; 540 541 static const struct intel_device_info glk_info = { 542 GEN9_LP_FEATURES, 543 PLATFORM(INTEL_GEMINILAKE), 544 }; 545 546 #define KBL_PLATFORM \ 547 GEN9_FEATURES, \ 548 PLATFORM(INTEL_KABYLAKE) 549 550 static const struct intel_device_info kbl_gt1_info = { 551 KBL_PLATFORM, 552 .gt = 1, 553 }; 554 555 static const struct intel_device_info kbl_gt2_info = { 556 KBL_PLATFORM, 557 .gt = 2, 558 }; 559 560 static const struct intel_device_info kbl_gt3_info = { 561 KBL_PLATFORM, 562 .gt = 3, 563 .platform_engine_mask = 564 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 565 }; 566 567 #define CFL_PLATFORM \ 568 GEN9_FEATURES, \ 569 PLATFORM(INTEL_COFFEELAKE) 570 571 static const struct intel_device_info cfl_gt1_info = { 572 CFL_PLATFORM, 573 .gt = 1, 574 }; 575 576 static const struct intel_device_info cfl_gt2_info = { 577 CFL_PLATFORM, 578 .gt = 2, 579 }; 580 581 static const struct intel_device_info cfl_gt3_info = { 582 CFL_PLATFORM, 583 .gt = 3, 584 .platform_engine_mask = 585 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 586 }; 587 588 #define CML_PLATFORM \ 589 GEN9_FEATURES, \ 590 PLATFORM(INTEL_COMETLAKE) 591 592 static const struct intel_device_info cml_gt1_info = { 593 CML_PLATFORM, 594 .gt = 1, 595 }; 596 597 static const struct intel_device_info cml_gt2_info = { 598 CML_PLATFORM, 599 .gt = 2, 600 }; 601 602 #define GEN11_DEFAULT_PAGE_SIZES \ 603 .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \ 604 I915_GTT_PAGE_SIZE_64K | \ 605 I915_GTT_PAGE_SIZE_2M 606 607 #define GEN11_FEATURES \ 608 GEN9_FEATURES, \ 609 GEN11_DEFAULT_PAGE_SIZES, \ 610 GEN(11), \ 611 .has_coherent_ggtt = false, \ 612 .has_logical_ring_elsq = 1 613 614 static const struct intel_device_info icl_info = { 615 GEN11_FEATURES, 616 PLATFORM(INTEL_ICELAKE), 617 .platform_engine_mask = 618 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 619 }; 620 621 static const struct intel_device_info ehl_info = { 622 GEN11_FEATURES, 623 PLATFORM(INTEL_ELKHARTLAKE), 624 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), 625 .__runtime.ppgtt_size = 36, 626 }; 627 628 static const struct intel_device_info jsl_info = { 629 GEN11_FEATURES, 630 PLATFORM(INTEL_JASPERLAKE), 631 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), 632 .__runtime.ppgtt_size = 36, 633 }; 634 635 #define GEN12_FEATURES \ 636 GEN11_FEATURES, \ 637 GEN(12), \ 638 TGL_CACHELEVEL, \ 639 .has_global_mocs = 1, \ 640 .has_pxp = 1, \ 641 .max_pat_index = 3 642 643 static const struct intel_device_info tgl_info = { 644 GEN12_FEATURES, 645 PLATFORM(INTEL_TIGERLAKE), 646 .platform_engine_mask = 647 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 648 }; 649 650 static const struct intel_device_info rkl_info = { 651 GEN12_FEATURES, 652 PLATFORM(INTEL_ROCKETLAKE), 653 .platform_engine_mask = 654 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0), 655 }; 656 657 #define DGFX_FEATURES \ 658 .memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN_LMEM, \ 659 .has_llc = 0, \ 660 .has_pxp = 0, \ 661 .has_snoop = 1, \ 662 .is_dgfx = 1, \ 663 .has_heci_gscfi = 1 664 665 static const struct intel_device_info dg1_info = { 666 GEN12_FEATURES, 667 DGFX_FEATURES, 668 .__runtime.graphics.ip.rel = 10, 669 PLATFORM(INTEL_DG1), 670 .require_force_probe = 1, 671 .platform_engine_mask = 672 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | 673 BIT(VCS0) | BIT(VCS2), 674 /* Wa_16011227922 */ 675 .__runtime.ppgtt_size = 47, 676 }; 677 678 static const struct intel_device_info adl_s_info = { 679 GEN12_FEATURES, 680 PLATFORM(INTEL_ALDERLAKE_S), 681 .platform_engine_mask = 682 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 683 .dma_mask_size = 39, 684 }; 685 686 static const struct intel_device_info adl_p_info = { 687 GEN12_FEATURES, 688 PLATFORM(INTEL_ALDERLAKE_P), 689 .platform_engine_mask = 690 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 691 .__runtime.ppgtt_size = 48, 692 .dma_mask_size = 39, 693 }; 694 695 #undef GEN 696 697 #define XE_HP_PAGE_SIZES \ 698 .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \ 699 I915_GTT_PAGE_SIZE_64K | \ 700 I915_GTT_PAGE_SIZE_2M 701 702 #define XE_HP_FEATURES \ 703 XE_HP_PAGE_SIZES, \ 704 TGL_CACHELEVEL, \ 705 .dma_mask_size = 46, \ 706 .has_3d_pipeline = 1, \ 707 .has_64bit_reloc = 1, \ 708 .has_flat_ccs = 1, \ 709 .has_global_mocs = 1, \ 710 .has_gt_uc = 1, \ 711 .has_llc = 1, \ 712 .has_logical_ring_contexts = 1, \ 713 .has_logical_ring_elsq = 1, \ 714 .has_mslice_steering = 1, \ 715 .has_oa_bpc_reporting = 1, \ 716 .has_oa_slice_contrib_limits = 1, \ 717 .has_oam = 1, \ 718 .has_rc6 = 1, \ 719 .has_reset_engine = 1, \ 720 .has_rps = 1, \ 721 .has_runtime_pm = 1, \ 722 .max_pat_index = 3, \ 723 .__runtime.ppgtt_size = 48, \ 724 .__runtime.ppgtt_type = INTEL_PPGTT_FULL 725 726 #define DG2_FEATURES \ 727 XE_HP_FEATURES, \ 728 DGFX_FEATURES, \ 729 .__runtime.graphics.ip.ver = 12, \ 730 .__runtime.graphics.ip.rel = 55, \ 731 .__runtime.media.ip.ver = 12, \ 732 .__runtime.media.ip.rel = 55, \ 733 PLATFORM(INTEL_DG2), \ 734 .has_64k_pages = 1, \ 735 .has_guc_deprivilege = 1, \ 736 .has_heci_pxp = 1, \ 737 .has_media_ratio_mode = 1, \ 738 .platform_engine_mask = \ 739 BIT(RCS0) | BIT(BCS0) | \ 740 BIT(VECS0) | BIT(VECS1) | \ 741 BIT(VCS0) | BIT(VCS2) | \ 742 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3) 743 744 static const struct intel_device_info dg2_info = { 745 DG2_FEATURES, 746 }; 747 748 static const struct intel_device_info ats_m_info = { 749 DG2_FEATURES, 750 .require_force_probe = 1, 751 .tuning_thread_rr_after_dep = 1, 752 }; 753 754 static const struct intel_gt_definition xelpmp_extra_gt[] = { 755 { 756 .type = GT_MEDIA, 757 .name = "Standalone Media GT", 758 .gsi_offset = MTL_MEDIA_GSI_BASE, 759 .engine_mask = BIT(VECS0) | BIT(VCS0) | BIT(VCS2) | BIT(GSC0), 760 }, 761 {} 762 }; 763 764 static const struct intel_device_info mtl_info = { 765 XE_HP_FEATURES, 766 /* 767 * Real graphics IP version will be obtained from hardware GMD_ID 768 * register. Value provided here is just for sanity checking. 769 */ 770 .__runtime.graphics.ip.ver = 12, 771 .__runtime.graphics.ip.rel = 70, 772 .__runtime.media.ip.ver = 13, 773 PLATFORM(INTEL_METEORLAKE), 774 .extra_gt_list = xelpmp_extra_gt, 775 .has_flat_ccs = 0, 776 .has_gmd_id = 1, 777 .has_guc_deprivilege = 1, 778 .has_guc_tlb_invalidation = 1, 779 .has_llc = 0, 780 .has_mslice_steering = 0, 781 .has_snoop = 1, 782 .max_pat_index = 4, 783 .has_pxp = 1, 784 .memory_regions = REGION_SMEM | REGION_STOLEN_LMEM, 785 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0), 786 MTL_CACHELEVEL, 787 }; 788 789 #undef PLATFORM 790 791 __diag_pop(); 792 793 /* 794 * Make sure any device matches here are from most specific to most 795 * general. For example, since the Quanta match is based on the subsystem 796 * and subvendor IDs, we need it to come before the more general IVB 797 * PCI ID matches, otherwise we'll use the wrong info struct above. 798 */ 799 static const struct pci_device_id pciidlist[] = { 800 INTEL_I830_IDS(&i830_info), 801 INTEL_I845G_IDS(&i845g_info), 802 INTEL_I85X_IDS(&i85x_info), 803 INTEL_I865G_IDS(&i865g_info), 804 INTEL_I915G_IDS(&i915g_info), 805 INTEL_I915GM_IDS(&i915gm_info), 806 INTEL_I945G_IDS(&i945g_info), 807 INTEL_I945GM_IDS(&i945gm_info), 808 INTEL_I965G_IDS(&i965g_info), 809 INTEL_G33_IDS(&g33_info), 810 INTEL_I965GM_IDS(&i965gm_info), 811 INTEL_GM45_IDS(&gm45_info), 812 INTEL_G45_IDS(&g45_info), 813 INTEL_PINEVIEW_G_IDS(&pnv_g_info), 814 INTEL_PINEVIEW_M_IDS(&pnv_m_info), 815 INTEL_IRONLAKE_D_IDS(&ilk_d_info), 816 INTEL_IRONLAKE_M_IDS(&ilk_m_info), 817 INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info), 818 INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info), 819 INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info), 820 INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info), 821 INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */ 822 INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info), 823 INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info), 824 INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info), 825 INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info), 826 INTEL_HSW_GT1_IDS(&hsw_gt1_info), 827 INTEL_HSW_GT2_IDS(&hsw_gt2_info), 828 INTEL_HSW_GT3_IDS(&hsw_gt3_info), 829 INTEL_VLV_IDS(&vlv_info), 830 INTEL_BDW_GT1_IDS(&bdw_gt1_info), 831 INTEL_BDW_GT2_IDS(&bdw_gt2_info), 832 INTEL_BDW_GT3_IDS(&bdw_gt3_info), 833 INTEL_BDW_RSVD_IDS(&bdw_rsvd_info), 834 INTEL_CHV_IDS(&chv_info), 835 INTEL_SKL_GT1_IDS(&skl_gt1_info), 836 INTEL_SKL_GT2_IDS(&skl_gt2_info), 837 INTEL_SKL_GT3_IDS(&skl_gt3_info), 838 INTEL_SKL_GT4_IDS(&skl_gt4_info), 839 INTEL_BXT_IDS(&bxt_info), 840 INTEL_GLK_IDS(&glk_info), 841 INTEL_KBL_GT1_IDS(&kbl_gt1_info), 842 INTEL_KBL_GT2_IDS(&kbl_gt2_info), 843 INTEL_KBL_GT3_IDS(&kbl_gt3_info), 844 INTEL_KBL_GT4_IDS(&kbl_gt3_info), 845 INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info), 846 INTEL_CFL_S_GT1_IDS(&cfl_gt1_info), 847 INTEL_CFL_S_GT2_IDS(&cfl_gt2_info), 848 INTEL_CFL_H_GT1_IDS(&cfl_gt1_info), 849 INTEL_CFL_H_GT2_IDS(&cfl_gt2_info), 850 INTEL_CFL_U_GT2_IDS(&cfl_gt2_info), 851 INTEL_CFL_U_GT3_IDS(&cfl_gt3_info), 852 INTEL_WHL_U_GT1_IDS(&cfl_gt1_info), 853 INTEL_WHL_U_GT2_IDS(&cfl_gt2_info), 854 INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info), 855 INTEL_WHL_U_GT3_IDS(&cfl_gt3_info), 856 INTEL_CML_GT1_IDS(&cml_gt1_info), 857 INTEL_CML_GT2_IDS(&cml_gt2_info), 858 INTEL_CML_U_GT1_IDS(&cml_gt1_info), 859 INTEL_CML_U_GT2_IDS(&cml_gt2_info), 860 INTEL_ICL_11_IDS(&icl_info), 861 INTEL_EHL_IDS(&ehl_info), 862 INTEL_JSL_IDS(&jsl_info), 863 INTEL_TGL_12_IDS(&tgl_info), 864 INTEL_RKL_IDS(&rkl_info), 865 INTEL_ADLS_IDS(&adl_s_info), 866 INTEL_ADLP_IDS(&adl_p_info), 867 INTEL_ADLN_IDS(&adl_p_info), 868 INTEL_DG1_IDS(&dg1_info), 869 INTEL_RPLS_IDS(&adl_s_info), 870 INTEL_RPLP_IDS(&adl_p_info), 871 INTEL_DG2_IDS(&dg2_info), 872 INTEL_ATS_M_IDS(&ats_m_info), 873 INTEL_MTL_IDS(&mtl_info), 874 {} 875 }; 876 MODULE_DEVICE_TABLE(pci, pciidlist); 877 878 static void i915_pci_remove(struct pci_dev *pdev) 879 { 880 struct drm_i915_private *i915; 881 882 i915 = pci_get_drvdata(pdev); 883 if (!i915) /* driver load aborted, nothing to cleanup */ 884 return; 885 886 i915_driver_remove(i915); 887 pci_set_drvdata(pdev, NULL); 888 } 889 890 /* is device_id present in comma separated list of ids */ 891 static bool device_id_in_list(u16 device_id, const char *devices, bool negative) 892 { 893 char *s, *p, *tok; 894 bool ret; 895 896 if (!devices || !*devices) 897 return false; 898 899 /* match everything */ 900 if (negative && strcmp(devices, "!*") == 0) 901 return true; 902 if (!negative && strcmp(devices, "*") == 0) 903 return true; 904 905 s = kstrdup(devices, GFP_KERNEL); 906 if (!s) 907 return false; 908 909 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) { 910 u16 val; 911 912 if (negative && tok[0] == '!') 913 tok++; 914 else if ((negative && tok[0] != '!') || 915 (!negative && tok[0] == '!')) 916 continue; 917 918 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) { 919 ret = true; 920 break; 921 } 922 } 923 924 kfree(s); 925 926 return ret; 927 } 928 929 static bool id_forced(u16 device_id) 930 { 931 return device_id_in_list(device_id, i915_modparams.force_probe, false); 932 } 933 934 static bool id_blocked(u16 device_id) 935 { 936 return device_id_in_list(device_id, i915_modparams.force_probe, true); 937 } 938 939 bool i915_pci_resource_valid(struct pci_dev *pdev, int bar) 940 { 941 if (!pci_resource_flags(pdev, bar)) 942 return false; 943 944 if (pci_resource_flags(pdev, bar) & IORESOURCE_UNSET) 945 return false; 946 947 if (!pci_resource_len(pdev, bar)) 948 return false; 949 950 return true; 951 } 952 953 static bool intel_mmio_bar_valid(struct pci_dev *pdev, struct intel_device_info *intel_info) 954 { 955 return i915_pci_resource_valid(pdev, intel_mmio_bar(intel_info->__runtime.graphics.ip.ver)); 956 } 957 958 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 959 { 960 struct intel_device_info *intel_info = 961 (struct intel_device_info *) ent->driver_data; 962 int err; 963 964 if (intel_info->require_force_probe && !id_forced(pdev->device)) { 965 dev_info(&pdev->dev, 966 "Your graphics device %04x is not properly supported by i915 in this\n" 967 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n" 968 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n" 969 "or (recommended) check for kernel updates.\n", 970 pdev->device, pdev->device, pdev->device); 971 return -ENODEV; 972 } 973 974 if (id_blocked(pdev->device)) { 975 dev_info(&pdev->dev, "I915 probe blocked for Device ID %04x.\n", 976 pdev->device); 977 return -ENODEV; 978 } 979 980 if (intel_info->require_force_probe) { 981 dev_info(&pdev->dev, "Force probing unsupported Device ID %04x, tainting kernel\n", 982 pdev->device); 983 add_taint(TAINT_USER, LOCKDEP_STILL_OK); 984 } 985 986 /* Only bind to function 0 of the device. Early generations 987 * used function 1 as a placeholder for multi-head. This causes 988 * us confusion instead, especially on the systems where both 989 * functions have the same PCI-ID! 990 */ 991 if (PCI_FUNC(pdev->devfn)) 992 return -ENODEV; 993 994 if (!intel_mmio_bar_valid(pdev, intel_info)) 995 return -ENXIO; 996 997 /* Detect if we need to wait for other drivers early on */ 998 if (intel_display_driver_probe_defer(pdev)) 999 return -EPROBE_DEFER; 1000 1001 err = i915_driver_probe(pdev, ent); 1002 if (err) 1003 return err; 1004 1005 if (i915_inject_probe_failure(pci_get_drvdata(pdev))) { 1006 i915_pci_remove(pdev); 1007 return -ENODEV; 1008 } 1009 1010 err = i915_live_selftests(pdev); 1011 if (err) { 1012 i915_pci_remove(pdev); 1013 return err > 0 ? -ENOTTY : err; 1014 } 1015 1016 err = i915_perf_selftests(pdev); 1017 if (err) { 1018 i915_pci_remove(pdev); 1019 return err > 0 ? -ENOTTY : err; 1020 } 1021 1022 return 0; 1023 } 1024 1025 static void i915_pci_shutdown(struct pci_dev *pdev) 1026 { 1027 struct drm_i915_private *i915 = pci_get_drvdata(pdev); 1028 1029 i915_driver_shutdown(i915); 1030 } 1031 1032 static struct pci_driver i915_pci_driver = { 1033 .name = DRIVER_NAME, 1034 .id_table = pciidlist, 1035 .probe = i915_pci_probe, 1036 .remove = i915_pci_remove, 1037 .shutdown = i915_pci_shutdown, 1038 .driver.pm = &i915_pm_ops, 1039 }; 1040 1041 int i915_pci_register_driver(void) 1042 { 1043 return pci_register_driver(&i915_pci_driver); 1044 } 1045 1046 void i915_pci_unregister_driver(void) 1047 { 1048 pci_unregister_driver(&i915_pci_driver); 1049 } 1050