1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/console.h> 26 #include <linux/vga_switcheroo.h> 27 28 #include <drm/drm_drv.h> 29 #include <drm/i915_pciids.h> 30 31 #include "display/intel_fbdev.h" 32 33 #include "i915_drv.h" 34 #include "i915_perf.h" 35 #include "i915_globals.h" 36 #include "i915_selftest.h" 37 38 #define PLATFORM(x) .platform = (x) 39 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1) 40 41 #define I845_PIPE_OFFSETS \ 42 .pipe_offsets = { \ 43 [TRANSCODER_A] = PIPE_A_OFFSET, \ 44 }, \ 45 .trans_offsets = { \ 46 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 47 } 48 49 #define I9XX_PIPE_OFFSETS \ 50 .pipe_offsets = { \ 51 [TRANSCODER_A] = PIPE_A_OFFSET, \ 52 [TRANSCODER_B] = PIPE_B_OFFSET, \ 53 }, \ 54 .trans_offsets = { \ 55 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 56 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 57 } 58 59 #define IVB_PIPE_OFFSETS \ 60 .pipe_offsets = { \ 61 [TRANSCODER_A] = PIPE_A_OFFSET, \ 62 [TRANSCODER_B] = PIPE_B_OFFSET, \ 63 [TRANSCODER_C] = PIPE_C_OFFSET, \ 64 }, \ 65 .trans_offsets = { \ 66 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 67 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 68 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 69 } 70 71 #define HSW_PIPE_OFFSETS \ 72 .pipe_offsets = { \ 73 [TRANSCODER_A] = PIPE_A_OFFSET, \ 74 [TRANSCODER_B] = PIPE_B_OFFSET, \ 75 [TRANSCODER_C] = PIPE_C_OFFSET, \ 76 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 77 }, \ 78 .trans_offsets = { \ 79 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 80 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 81 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 82 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 83 } 84 85 #define CHV_PIPE_OFFSETS \ 86 .pipe_offsets = { \ 87 [TRANSCODER_A] = PIPE_A_OFFSET, \ 88 [TRANSCODER_B] = PIPE_B_OFFSET, \ 89 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \ 90 }, \ 91 .trans_offsets = { \ 92 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 93 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 94 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \ 95 } 96 97 #define I845_CURSOR_OFFSETS \ 98 .cursor_offsets = { \ 99 [PIPE_A] = CURSOR_A_OFFSET, \ 100 } 101 102 #define I9XX_CURSOR_OFFSETS \ 103 .cursor_offsets = { \ 104 [PIPE_A] = CURSOR_A_OFFSET, \ 105 [PIPE_B] = CURSOR_B_OFFSET, \ 106 } 107 108 #define CHV_CURSOR_OFFSETS \ 109 .cursor_offsets = { \ 110 [PIPE_A] = CURSOR_A_OFFSET, \ 111 [PIPE_B] = CURSOR_B_OFFSET, \ 112 [PIPE_C] = CHV_CURSOR_C_OFFSET, \ 113 } 114 115 #define IVB_CURSOR_OFFSETS \ 116 .cursor_offsets = { \ 117 [PIPE_A] = CURSOR_A_OFFSET, \ 118 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 119 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 120 } 121 122 #define TGL_CURSOR_OFFSETS \ 123 .cursor_offsets = { \ 124 [PIPE_A] = CURSOR_A_OFFSET, \ 125 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 126 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 127 [PIPE_D] = TGL_CURSOR_D_OFFSET, \ 128 } 129 130 #define I9XX_COLORS \ 131 .color = { .gamma_lut_size = 256 } 132 #define I965_COLORS \ 133 .color = { .gamma_lut_size = 129, \ 134 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 135 } 136 #define ILK_COLORS \ 137 .color = { .gamma_lut_size = 1024 } 138 #define IVB_COLORS \ 139 .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 } 140 #define CHV_COLORS \ 141 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \ 142 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 143 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 144 } 145 #define GLK_COLORS \ 146 .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \ 147 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 148 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 149 } 150 151 /* Keep in gen based order, and chronological order within a gen */ 152 153 #define GEN_DEFAULT_PAGE_SIZES \ 154 .page_sizes = I915_GTT_PAGE_SIZE_4K 155 156 #define GEN_DEFAULT_REGIONS \ 157 .memory_regions = REGION_SMEM | REGION_STOLEN 158 159 #define I830_FEATURES \ 160 GEN(2), \ 161 .is_mobile = 1, \ 162 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 163 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 164 .display.has_overlay = 1, \ 165 .display.cursor_needs_physical = 1, \ 166 .display.overlay_needs_physical = 1, \ 167 .display.has_gmch = 1, \ 168 .gpu_reset_clobbers_display = true, \ 169 .hws_needs_physical = 1, \ 170 .unfenced_needs_alignment = 1, \ 171 .engine_mask = BIT(RCS0), \ 172 .has_snoop = true, \ 173 .has_coherent_ggtt = false, \ 174 .dma_mask_size = 32, \ 175 I9XX_PIPE_OFFSETS, \ 176 I9XX_CURSOR_OFFSETS, \ 177 I9XX_COLORS, \ 178 GEN_DEFAULT_PAGE_SIZES, \ 179 GEN_DEFAULT_REGIONS 180 181 #define I845_FEATURES \ 182 GEN(2), \ 183 .pipe_mask = BIT(PIPE_A), \ 184 .cpu_transcoder_mask = BIT(TRANSCODER_A), \ 185 .display.has_overlay = 1, \ 186 .display.overlay_needs_physical = 1, \ 187 .display.has_gmch = 1, \ 188 .gpu_reset_clobbers_display = true, \ 189 .hws_needs_physical = 1, \ 190 .unfenced_needs_alignment = 1, \ 191 .engine_mask = BIT(RCS0), \ 192 .has_snoop = true, \ 193 .has_coherent_ggtt = false, \ 194 .dma_mask_size = 32, \ 195 I845_PIPE_OFFSETS, \ 196 I845_CURSOR_OFFSETS, \ 197 I9XX_COLORS, \ 198 GEN_DEFAULT_PAGE_SIZES, \ 199 GEN_DEFAULT_REGIONS 200 201 static const struct intel_device_info i830_info = { 202 I830_FEATURES, 203 PLATFORM(INTEL_I830), 204 }; 205 206 static const struct intel_device_info i845g_info = { 207 I845_FEATURES, 208 PLATFORM(INTEL_I845G), 209 }; 210 211 static const struct intel_device_info i85x_info = { 212 I830_FEATURES, 213 PLATFORM(INTEL_I85X), 214 .display.has_fbc = 1, 215 }; 216 217 static const struct intel_device_info i865g_info = { 218 I845_FEATURES, 219 PLATFORM(INTEL_I865G), 220 }; 221 222 #define GEN3_FEATURES \ 223 GEN(3), \ 224 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 225 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 226 .display.has_gmch = 1, \ 227 .gpu_reset_clobbers_display = true, \ 228 .engine_mask = BIT(RCS0), \ 229 .has_snoop = true, \ 230 .has_coherent_ggtt = true, \ 231 .dma_mask_size = 32, \ 232 I9XX_PIPE_OFFSETS, \ 233 I9XX_CURSOR_OFFSETS, \ 234 I9XX_COLORS, \ 235 GEN_DEFAULT_PAGE_SIZES, \ 236 GEN_DEFAULT_REGIONS 237 238 static const struct intel_device_info i915g_info = { 239 GEN3_FEATURES, 240 PLATFORM(INTEL_I915G), 241 .has_coherent_ggtt = false, 242 .display.cursor_needs_physical = 1, 243 .display.has_overlay = 1, 244 .display.overlay_needs_physical = 1, 245 .hws_needs_physical = 1, 246 .unfenced_needs_alignment = 1, 247 }; 248 249 static const struct intel_device_info i915gm_info = { 250 GEN3_FEATURES, 251 PLATFORM(INTEL_I915GM), 252 .is_mobile = 1, 253 .display.cursor_needs_physical = 1, 254 .display.has_overlay = 1, 255 .display.overlay_needs_physical = 1, 256 .display.supports_tv = 1, 257 .display.has_fbc = 1, 258 .hws_needs_physical = 1, 259 .unfenced_needs_alignment = 1, 260 }; 261 262 static const struct intel_device_info i945g_info = { 263 GEN3_FEATURES, 264 PLATFORM(INTEL_I945G), 265 .display.has_hotplug = 1, 266 .display.cursor_needs_physical = 1, 267 .display.has_overlay = 1, 268 .display.overlay_needs_physical = 1, 269 .hws_needs_physical = 1, 270 .unfenced_needs_alignment = 1, 271 }; 272 273 static const struct intel_device_info i945gm_info = { 274 GEN3_FEATURES, 275 PLATFORM(INTEL_I945GM), 276 .is_mobile = 1, 277 .display.has_hotplug = 1, 278 .display.cursor_needs_physical = 1, 279 .display.has_overlay = 1, 280 .display.overlay_needs_physical = 1, 281 .display.supports_tv = 1, 282 .display.has_fbc = 1, 283 .hws_needs_physical = 1, 284 .unfenced_needs_alignment = 1, 285 }; 286 287 static const struct intel_device_info g33_info = { 288 GEN3_FEATURES, 289 PLATFORM(INTEL_G33), 290 .display.has_hotplug = 1, 291 .display.has_overlay = 1, 292 .dma_mask_size = 36, 293 }; 294 295 static const struct intel_device_info pnv_g_info = { 296 GEN3_FEATURES, 297 PLATFORM(INTEL_PINEVIEW), 298 .display.has_hotplug = 1, 299 .display.has_overlay = 1, 300 .dma_mask_size = 36, 301 }; 302 303 static const struct intel_device_info pnv_m_info = { 304 GEN3_FEATURES, 305 PLATFORM(INTEL_PINEVIEW), 306 .is_mobile = 1, 307 .display.has_hotplug = 1, 308 .display.has_overlay = 1, 309 .dma_mask_size = 36, 310 }; 311 312 #define GEN4_FEATURES \ 313 GEN(4), \ 314 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 315 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 316 .display.has_hotplug = 1, \ 317 .display.has_gmch = 1, \ 318 .gpu_reset_clobbers_display = true, \ 319 .engine_mask = BIT(RCS0), \ 320 .has_snoop = true, \ 321 .has_coherent_ggtt = true, \ 322 .dma_mask_size = 36, \ 323 I9XX_PIPE_OFFSETS, \ 324 I9XX_CURSOR_OFFSETS, \ 325 I965_COLORS, \ 326 GEN_DEFAULT_PAGE_SIZES, \ 327 GEN_DEFAULT_REGIONS 328 329 static const struct intel_device_info i965g_info = { 330 GEN4_FEATURES, 331 PLATFORM(INTEL_I965G), 332 .display.has_overlay = 1, 333 .hws_needs_physical = 1, 334 .has_snoop = false, 335 }; 336 337 static const struct intel_device_info i965gm_info = { 338 GEN4_FEATURES, 339 PLATFORM(INTEL_I965GM), 340 .is_mobile = 1, 341 .display.has_fbc = 1, 342 .display.has_overlay = 1, 343 .display.supports_tv = 1, 344 .hws_needs_physical = 1, 345 .has_snoop = false, 346 }; 347 348 static const struct intel_device_info g45_info = { 349 GEN4_FEATURES, 350 PLATFORM(INTEL_G45), 351 .engine_mask = BIT(RCS0) | BIT(VCS0), 352 .gpu_reset_clobbers_display = false, 353 }; 354 355 static const struct intel_device_info gm45_info = { 356 GEN4_FEATURES, 357 PLATFORM(INTEL_GM45), 358 .is_mobile = 1, 359 .display.has_fbc = 1, 360 .display.supports_tv = 1, 361 .engine_mask = BIT(RCS0) | BIT(VCS0), 362 .gpu_reset_clobbers_display = false, 363 }; 364 365 #define GEN5_FEATURES \ 366 GEN(5), \ 367 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 368 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 369 .display.has_hotplug = 1, \ 370 .engine_mask = BIT(RCS0) | BIT(VCS0), \ 371 .has_snoop = true, \ 372 .has_coherent_ggtt = true, \ 373 /* ilk does support rc6, but we do not implement [power] contexts */ \ 374 .has_rc6 = 0, \ 375 .dma_mask_size = 36, \ 376 I9XX_PIPE_OFFSETS, \ 377 I9XX_CURSOR_OFFSETS, \ 378 ILK_COLORS, \ 379 GEN_DEFAULT_PAGE_SIZES, \ 380 GEN_DEFAULT_REGIONS 381 382 static const struct intel_device_info ilk_d_info = { 383 GEN5_FEATURES, 384 PLATFORM(INTEL_IRONLAKE), 385 }; 386 387 static const struct intel_device_info ilk_m_info = { 388 GEN5_FEATURES, 389 PLATFORM(INTEL_IRONLAKE), 390 .is_mobile = 1, 391 .display.has_fbc = 1, 392 }; 393 394 #define GEN6_FEATURES \ 395 GEN(6), \ 396 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 397 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 398 .display.has_hotplug = 1, \ 399 .display.has_fbc = 1, \ 400 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 401 .has_coherent_ggtt = true, \ 402 .has_llc = 1, \ 403 .has_rc6 = 1, \ 404 .has_rc6p = 1, \ 405 .has_rps = true, \ 406 .dma_mask_size = 40, \ 407 .ppgtt_type = INTEL_PPGTT_ALIASING, \ 408 .ppgtt_size = 31, \ 409 I9XX_PIPE_OFFSETS, \ 410 I9XX_CURSOR_OFFSETS, \ 411 ILK_COLORS, \ 412 GEN_DEFAULT_PAGE_SIZES, \ 413 GEN_DEFAULT_REGIONS 414 415 #define SNB_D_PLATFORM \ 416 GEN6_FEATURES, \ 417 PLATFORM(INTEL_SANDYBRIDGE) 418 419 static const struct intel_device_info snb_d_gt1_info = { 420 SNB_D_PLATFORM, 421 .gt = 1, 422 }; 423 424 static const struct intel_device_info snb_d_gt2_info = { 425 SNB_D_PLATFORM, 426 .gt = 2, 427 }; 428 429 #define SNB_M_PLATFORM \ 430 GEN6_FEATURES, \ 431 PLATFORM(INTEL_SANDYBRIDGE), \ 432 .is_mobile = 1 433 434 435 static const struct intel_device_info snb_m_gt1_info = { 436 SNB_M_PLATFORM, 437 .gt = 1, 438 }; 439 440 static const struct intel_device_info snb_m_gt2_info = { 441 SNB_M_PLATFORM, 442 .gt = 2, 443 }; 444 445 #define GEN7_FEATURES \ 446 GEN(7), \ 447 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 448 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \ 449 .display.has_hotplug = 1, \ 450 .display.has_fbc = 1, \ 451 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 452 .has_coherent_ggtt = true, \ 453 .has_llc = 1, \ 454 .has_rc6 = 1, \ 455 .has_rc6p = 1, \ 456 .has_rps = true, \ 457 .dma_mask_size = 40, \ 458 .ppgtt_type = INTEL_PPGTT_ALIASING, \ 459 .ppgtt_size = 31, \ 460 IVB_PIPE_OFFSETS, \ 461 IVB_CURSOR_OFFSETS, \ 462 IVB_COLORS, \ 463 GEN_DEFAULT_PAGE_SIZES, \ 464 GEN_DEFAULT_REGIONS 465 466 #define IVB_D_PLATFORM \ 467 GEN7_FEATURES, \ 468 PLATFORM(INTEL_IVYBRIDGE), \ 469 .has_l3_dpf = 1 470 471 static const struct intel_device_info ivb_d_gt1_info = { 472 IVB_D_PLATFORM, 473 .gt = 1, 474 }; 475 476 static const struct intel_device_info ivb_d_gt2_info = { 477 IVB_D_PLATFORM, 478 .gt = 2, 479 }; 480 481 #define IVB_M_PLATFORM \ 482 GEN7_FEATURES, \ 483 PLATFORM(INTEL_IVYBRIDGE), \ 484 .is_mobile = 1, \ 485 .has_l3_dpf = 1 486 487 static const struct intel_device_info ivb_m_gt1_info = { 488 IVB_M_PLATFORM, 489 .gt = 1, 490 }; 491 492 static const struct intel_device_info ivb_m_gt2_info = { 493 IVB_M_PLATFORM, 494 .gt = 2, 495 }; 496 497 static const struct intel_device_info ivb_q_info = { 498 GEN7_FEATURES, 499 PLATFORM(INTEL_IVYBRIDGE), 500 .gt = 2, 501 .pipe_mask = 0, /* legal, last one wins */ 502 .cpu_transcoder_mask = 0, 503 .has_l3_dpf = 1, 504 }; 505 506 static const struct intel_device_info vlv_info = { 507 PLATFORM(INTEL_VALLEYVIEW), 508 GEN(7), 509 .is_lp = 1, 510 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), 511 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), 512 .has_runtime_pm = 1, 513 .has_rc6 = 1, 514 .has_rps = true, 515 .display.has_gmch = 1, 516 .display.has_hotplug = 1, 517 .dma_mask_size = 40, 518 .ppgtt_type = INTEL_PPGTT_ALIASING, 519 .ppgtt_size = 31, 520 .has_snoop = true, 521 .has_coherent_ggtt = false, 522 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), 523 .display_mmio_offset = VLV_DISPLAY_BASE, 524 I9XX_PIPE_OFFSETS, 525 I9XX_CURSOR_OFFSETS, 526 I965_COLORS, 527 GEN_DEFAULT_PAGE_SIZES, 528 GEN_DEFAULT_REGIONS, 529 }; 530 531 #define G75_FEATURES \ 532 GEN7_FEATURES, \ 533 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ 534 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 535 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \ 536 .display.has_ddi = 1, \ 537 .has_fpga_dbg = 1, \ 538 .display.has_psr = 1, \ 539 .display.has_psr_hw_tracking = 1, \ 540 .display.has_dp_mst = 1, \ 541 .has_rc6p = 0 /* RC6p removed-by HSW */, \ 542 HSW_PIPE_OFFSETS, \ 543 .has_runtime_pm = 1 544 545 #define HSW_PLATFORM \ 546 G75_FEATURES, \ 547 PLATFORM(INTEL_HASWELL), \ 548 .has_l3_dpf = 1 549 550 static const struct intel_device_info hsw_gt1_info = { 551 HSW_PLATFORM, 552 .gt = 1, 553 }; 554 555 static const struct intel_device_info hsw_gt2_info = { 556 HSW_PLATFORM, 557 .gt = 2, 558 }; 559 560 static const struct intel_device_info hsw_gt3_info = { 561 HSW_PLATFORM, 562 .gt = 3, 563 }; 564 565 #define GEN8_FEATURES \ 566 G75_FEATURES, \ 567 GEN(8), \ 568 .has_logical_ring_contexts = 1, \ 569 .dma_mask_size = 39, \ 570 .ppgtt_type = INTEL_PPGTT_FULL, \ 571 .ppgtt_size = 48, \ 572 .has_64bit_reloc = 1, \ 573 .has_reset_engine = 1 574 575 #define BDW_PLATFORM \ 576 GEN8_FEATURES, \ 577 PLATFORM(INTEL_BROADWELL) 578 579 static const struct intel_device_info bdw_gt1_info = { 580 BDW_PLATFORM, 581 .gt = 1, 582 }; 583 584 static const struct intel_device_info bdw_gt2_info = { 585 BDW_PLATFORM, 586 .gt = 2, 587 }; 588 589 static const struct intel_device_info bdw_rsvd_info = { 590 BDW_PLATFORM, 591 .gt = 3, 592 /* According to the device ID those devices are GT3, they were 593 * previously treated as not GT3, keep it like that. 594 */ 595 }; 596 597 static const struct intel_device_info bdw_gt3_info = { 598 BDW_PLATFORM, 599 .gt = 3, 600 .engine_mask = 601 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 602 }; 603 604 static const struct intel_device_info chv_info = { 605 PLATFORM(INTEL_CHERRYVIEW), 606 GEN(8), 607 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 608 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), 609 .display.has_hotplug = 1, 610 .is_lp = 1, 611 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), 612 .has_64bit_reloc = 1, 613 .has_runtime_pm = 1, 614 .has_rc6 = 1, 615 .has_rps = true, 616 .has_logical_ring_contexts = 1, 617 .display.has_gmch = 1, 618 .dma_mask_size = 39, 619 .ppgtt_type = INTEL_PPGTT_FULL, 620 .ppgtt_size = 32, 621 .has_reset_engine = 1, 622 .has_snoop = true, 623 .has_coherent_ggtt = false, 624 .display_mmio_offset = VLV_DISPLAY_BASE, 625 CHV_PIPE_OFFSETS, 626 CHV_CURSOR_OFFSETS, 627 CHV_COLORS, 628 GEN_DEFAULT_PAGE_SIZES, 629 GEN_DEFAULT_REGIONS, 630 }; 631 632 #define GEN9_DEFAULT_PAGE_SIZES \ 633 .page_sizes = I915_GTT_PAGE_SIZE_4K | \ 634 I915_GTT_PAGE_SIZE_64K 635 636 #define GEN9_FEATURES \ 637 GEN8_FEATURES, \ 638 GEN(9), \ 639 GEN9_DEFAULT_PAGE_SIZES, \ 640 .has_logical_ring_preemption = 1, \ 641 .display.has_csr = 1, \ 642 .has_gt_uc = 1, \ 643 .display.has_hdcp = 1, \ 644 .display.has_ipc = 1, \ 645 .ddb_size = 896, \ 646 .num_supported_dbuf_slices = 1 647 648 #define SKL_PLATFORM \ 649 GEN9_FEATURES, \ 650 PLATFORM(INTEL_SKYLAKE) 651 652 static const struct intel_device_info skl_gt1_info = { 653 SKL_PLATFORM, 654 .gt = 1, 655 }; 656 657 static const struct intel_device_info skl_gt2_info = { 658 SKL_PLATFORM, 659 .gt = 2, 660 }; 661 662 #define SKL_GT3_PLUS_PLATFORM \ 663 SKL_PLATFORM, \ 664 .engine_mask = \ 665 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1) 666 667 668 static const struct intel_device_info skl_gt3_info = { 669 SKL_GT3_PLUS_PLATFORM, 670 .gt = 3, 671 }; 672 673 static const struct intel_device_info skl_gt4_info = { 674 SKL_GT3_PLUS_PLATFORM, 675 .gt = 4, 676 }; 677 678 #define GEN9_LP_FEATURES \ 679 GEN(9), \ 680 .is_lp = 1, \ 681 .num_supported_dbuf_slices = 1, \ 682 .display.has_hotplug = 1, \ 683 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ 684 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 685 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 686 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ 687 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \ 688 .has_64bit_reloc = 1, \ 689 .display.has_ddi = 1, \ 690 .has_fpga_dbg = 1, \ 691 .display.has_fbc = 1, \ 692 .display.has_hdcp = 1, \ 693 .display.has_psr = 1, \ 694 .display.has_psr_hw_tracking = 1, \ 695 .has_runtime_pm = 1, \ 696 .display.has_csr = 1, \ 697 .has_rc6 = 1, \ 698 .has_rps = true, \ 699 .display.has_dp_mst = 1, \ 700 .has_logical_ring_contexts = 1, \ 701 .has_logical_ring_preemption = 1, \ 702 .has_gt_uc = 1, \ 703 .dma_mask_size = 39, \ 704 .ppgtt_type = INTEL_PPGTT_FULL, \ 705 .ppgtt_size = 48, \ 706 .has_reset_engine = 1, \ 707 .has_snoop = true, \ 708 .has_coherent_ggtt = false, \ 709 .display.has_ipc = 1, \ 710 HSW_PIPE_OFFSETS, \ 711 IVB_CURSOR_OFFSETS, \ 712 IVB_COLORS, \ 713 GEN9_DEFAULT_PAGE_SIZES, \ 714 GEN_DEFAULT_REGIONS 715 716 static const struct intel_device_info bxt_info = { 717 GEN9_LP_FEATURES, 718 PLATFORM(INTEL_BROXTON), 719 .ddb_size = 512, 720 }; 721 722 static const struct intel_device_info glk_info = { 723 GEN9_LP_FEATURES, 724 PLATFORM(INTEL_GEMINILAKE), 725 .ddb_size = 1024, 726 GLK_COLORS, 727 }; 728 729 #define KBL_PLATFORM \ 730 GEN9_FEATURES, \ 731 PLATFORM(INTEL_KABYLAKE) 732 733 static const struct intel_device_info kbl_gt1_info = { 734 KBL_PLATFORM, 735 .gt = 1, 736 }; 737 738 static const struct intel_device_info kbl_gt2_info = { 739 KBL_PLATFORM, 740 .gt = 2, 741 }; 742 743 static const struct intel_device_info kbl_gt3_info = { 744 KBL_PLATFORM, 745 .gt = 3, 746 .engine_mask = 747 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 748 }; 749 750 #define CFL_PLATFORM \ 751 GEN9_FEATURES, \ 752 PLATFORM(INTEL_COFFEELAKE) 753 754 static const struct intel_device_info cfl_gt1_info = { 755 CFL_PLATFORM, 756 .gt = 1, 757 }; 758 759 static const struct intel_device_info cfl_gt2_info = { 760 CFL_PLATFORM, 761 .gt = 2, 762 }; 763 764 static const struct intel_device_info cfl_gt3_info = { 765 CFL_PLATFORM, 766 .gt = 3, 767 .engine_mask = 768 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 769 }; 770 771 #define CML_PLATFORM \ 772 GEN9_FEATURES, \ 773 PLATFORM(INTEL_COMETLAKE) 774 775 static const struct intel_device_info cml_gt1_info = { 776 CML_PLATFORM, 777 .gt = 1, 778 }; 779 780 static const struct intel_device_info cml_gt2_info = { 781 CML_PLATFORM, 782 .gt = 2, 783 }; 784 785 #define GEN10_FEATURES \ 786 GEN9_FEATURES, \ 787 GEN(10), \ 788 .ddb_size = 1024, \ 789 .display.has_dsc = 1, \ 790 .has_coherent_ggtt = false, \ 791 GLK_COLORS 792 793 static const struct intel_device_info cnl_info = { 794 GEN10_FEATURES, 795 PLATFORM(INTEL_CANNONLAKE), 796 .gt = 2, 797 }; 798 799 #define GEN11_DEFAULT_PAGE_SIZES \ 800 .page_sizes = I915_GTT_PAGE_SIZE_4K | \ 801 I915_GTT_PAGE_SIZE_64K | \ 802 I915_GTT_PAGE_SIZE_2M 803 804 #define GEN11_FEATURES \ 805 GEN10_FEATURES, \ 806 GEN11_DEFAULT_PAGE_SIZES, \ 807 .abox_mask = BIT(0), \ 808 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 809 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ 810 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ 811 .pipe_offsets = { \ 812 [TRANSCODER_A] = PIPE_A_OFFSET, \ 813 [TRANSCODER_B] = PIPE_B_OFFSET, \ 814 [TRANSCODER_C] = PIPE_C_OFFSET, \ 815 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 816 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 817 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 818 }, \ 819 .trans_offsets = { \ 820 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 821 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 822 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 823 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 824 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 825 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 826 }, \ 827 GEN(11), \ 828 .ddb_size = 2048, \ 829 .num_supported_dbuf_slices = 2, \ 830 .has_logical_ring_elsq = 1, \ 831 .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 } 832 833 static const struct intel_device_info icl_info = { 834 GEN11_FEATURES, 835 PLATFORM(INTEL_ICELAKE), 836 .engine_mask = 837 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 838 }; 839 840 static const struct intel_device_info ehl_info = { 841 GEN11_FEATURES, 842 PLATFORM(INTEL_ELKHARTLAKE), 843 .require_force_probe = 1, 844 .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), 845 .ppgtt_size = 36, 846 }; 847 848 #define GEN12_FEATURES \ 849 GEN11_FEATURES, \ 850 GEN(12), \ 851 .abox_mask = GENMASK(2, 1), \ 852 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ 853 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 854 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \ 855 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ 856 .pipe_offsets = { \ 857 [TRANSCODER_A] = PIPE_A_OFFSET, \ 858 [TRANSCODER_B] = PIPE_B_OFFSET, \ 859 [TRANSCODER_C] = PIPE_C_OFFSET, \ 860 [TRANSCODER_D] = PIPE_D_OFFSET, \ 861 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 862 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 863 }, \ 864 .trans_offsets = { \ 865 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 866 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 867 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 868 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 869 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 870 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 871 }, \ 872 TGL_CURSOR_OFFSETS, \ 873 .has_global_mocs = 1, \ 874 .display.has_dsb = 1 875 876 static const struct intel_device_info tgl_info = { 877 GEN12_FEATURES, 878 PLATFORM(INTEL_TIGERLAKE), 879 .display.has_modular_fia = 1, 880 .engine_mask = 881 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 882 }; 883 884 static const struct intel_device_info rkl_info = { 885 GEN12_FEATURES, 886 PLATFORM(INTEL_ROCKETLAKE), 887 .abox_mask = BIT(0), 888 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 889 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 890 BIT(TRANSCODER_C), 891 .require_force_probe = 1, 892 .display.has_psr_hw_tracking = 0, 893 .engine_mask = 894 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0), 895 }; 896 897 #define GEN12_DGFX_FEATURES \ 898 GEN12_FEATURES, \ 899 .is_dgfx = 1 900 901 #undef GEN 902 #undef PLATFORM 903 904 /* 905 * Make sure any device matches here are from most specific to most 906 * general. For example, since the Quanta match is based on the subsystem 907 * and subvendor IDs, we need it to come before the more general IVB 908 * PCI ID matches, otherwise we'll use the wrong info struct above. 909 */ 910 static const struct pci_device_id pciidlist[] = { 911 INTEL_I830_IDS(&i830_info), 912 INTEL_I845G_IDS(&i845g_info), 913 INTEL_I85X_IDS(&i85x_info), 914 INTEL_I865G_IDS(&i865g_info), 915 INTEL_I915G_IDS(&i915g_info), 916 INTEL_I915GM_IDS(&i915gm_info), 917 INTEL_I945G_IDS(&i945g_info), 918 INTEL_I945GM_IDS(&i945gm_info), 919 INTEL_I965G_IDS(&i965g_info), 920 INTEL_G33_IDS(&g33_info), 921 INTEL_I965GM_IDS(&i965gm_info), 922 INTEL_GM45_IDS(&gm45_info), 923 INTEL_G45_IDS(&g45_info), 924 INTEL_PINEVIEW_G_IDS(&pnv_g_info), 925 INTEL_PINEVIEW_M_IDS(&pnv_m_info), 926 INTEL_IRONLAKE_D_IDS(&ilk_d_info), 927 INTEL_IRONLAKE_M_IDS(&ilk_m_info), 928 INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info), 929 INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info), 930 INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info), 931 INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info), 932 INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */ 933 INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info), 934 INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info), 935 INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info), 936 INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info), 937 INTEL_HSW_GT1_IDS(&hsw_gt1_info), 938 INTEL_HSW_GT2_IDS(&hsw_gt2_info), 939 INTEL_HSW_GT3_IDS(&hsw_gt3_info), 940 INTEL_VLV_IDS(&vlv_info), 941 INTEL_BDW_GT1_IDS(&bdw_gt1_info), 942 INTEL_BDW_GT2_IDS(&bdw_gt2_info), 943 INTEL_BDW_GT3_IDS(&bdw_gt3_info), 944 INTEL_BDW_RSVD_IDS(&bdw_rsvd_info), 945 INTEL_CHV_IDS(&chv_info), 946 INTEL_SKL_GT1_IDS(&skl_gt1_info), 947 INTEL_SKL_GT2_IDS(&skl_gt2_info), 948 INTEL_SKL_GT3_IDS(&skl_gt3_info), 949 INTEL_SKL_GT4_IDS(&skl_gt4_info), 950 INTEL_BXT_IDS(&bxt_info), 951 INTEL_GLK_IDS(&glk_info), 952 INTEL_KBL_GT1_IDS(&kbl_gt1_info), 953 INTEL_KBL_GT2_IDS(&kbl_gt2_info), 954 INTEL_KBL_GT3_IDS(&kbl_gt3_info), 955 INTEL_KBL_GT4_IDS(&kbl_gt3_info), 956 INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info), 957 INTEL_CFL_S_GT1_IDS(&cfl_gt1_info), 958 INTEL_CFL_S_GT2_IDS(&cfl_gt2_info), 959 INTEL_CFL_H_GT1_IDS(&cfl_gt1_info), 960 INTEL_CFL_H_GT2_IDS(&cfl_gt2_info), 961 INTEL_CFL_U_GT2_IDS(&cfl_gt2_info), 962 INTEL_CFL_U_GT3_IDS(&cfl_gt3_info), 963 INTEL_WHL_U_GT1_IDS(&cfl_gt1_info), 964 INTEL_WHL_U_GT2_IDS(&cfl_gt2_info), 965 INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info), 966 INTEL_WHL_U_GT3_IDS(&cfl_gt3_info), 967 INTEL_CML_GT1_IDS(&cml_gt1_info), 968 INTEL_CML_GT2_IDS(&cml_gt2_info), 969 INTEL_CML_U_GT1_IDS(&cml_gt1_info), 970 INTEL_CML_U_GT2_IDS(&cml_gt2_info), 971 INTEL_CNL_IDS(&cnl_info), 972 INTEL_ICL_11_IDS(&icl_info), 973 INTEL_EHL_IDS(&ehl_info), 974 INTEL_TGL_12_IDS(&tgl_info), 975 INTEL_RKL_IDS(&rkl_info), 976 {0, 0, 0} 977 }; 978 MODULE_DEVICE_TABLE(pci, pciidlist); 979 980 static void i915_pci_remove(struct pci_dev *pdev) 981 { 982 struct drm_i915_private *i915; 983 984 i915 = pci_get_drvdata(pdev); 985 if (!i915) /* driver load aborted, nothing to cleanup */ 986 return; 987 988 i915_driver_remove(i915); 989 pci_set_drvdata(pdev, NULL); 990 991 drm_dev_put(&i915->drm); 992 } 993 994 /* is device_id present in comma separated list of ids */ 995 static bool force_probe(u16 device_id, const char *devices) 996 { 997 char *s, *p, *tok; 998 bool ret; 999 1000 if (!devices || !*devices) 1001 return false; 1002 1003 /* match everything */ 1004 if (strcmp(devices, "*") == 0) 1005 return true; 1006 1007 s = kstrdup(devices, GFP_KERNEL); 1008 if (!s) 1009 return false; 1010 1011 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) { 1012 u16 val; 1013 1014 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) { 1015 ret = true; 1016 break; 1017 } 1018 } 1019 1020 kfree(s); 1021 1022 return ret; 1023 } 1024 1025 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1026 { 1027 struct intel_device_info *intel_info = 1028 (struct intel_device_info *) ent->driver_data; 1029 int err; 1030 1031 if (intel_info->require_force_probe && 1032 !force_probe(pdev->device, i915_modparams.force_probe)) { 1033 dev_info(&pdev->dev, 1034 "Your graphics device %04x is not properly supported by the driver in this\n" 1035 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n" 1036 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n" 1037 "or (recommended) check for kernel updates.\n", 1038 pdev->device, pdev->device, pdev->device); 1039 return -ENODEV; 1040 } 1041 1042 /* Only bind to function 0 of the device. Early generations 1043 * used function 1 as a placeholder for multi-head. This causes 1044 * us confusion instead, especially on the systems where both 1045 * functions have the same PCI-ID! 1046 */ 1047 if (PCI_FUNC(pdev->devfn)) 1048 return -ENODEV; 1049 1050 /* 1051 * apple-gmux is needed on dual GPU MacBook Pro 1052 * to probe the panel if we're the inactive GPU. 1053 */ 1054 if (vga_switcheroo_client_probe_defer(pdev)) 1055 return -EPROBE_DEFER; 1056 1057 err = i915_driver_probe(pdev, ent); 1058 if (err) 1059 return err; 1060 1061 if (i915_inject_probe_failure(pci_get_drvdata(pdev))) { 1062 i915_pci_remove(pdev); 1063 return -ENODEV; 1064 } 1065 1066 err = i915_live_selftests(pdev); 1067 if (err) { 1068 i915_pci_remove(pdev); 1069 return err > 0 ? -ENOTTY : err; 1070 } 1071 1072 err = i915_perf_selftests(pdev); 1073 if (err) { 1074 i915_pci_remove(pdev); 1075 return err > 0 ? -ENOTTY : err; 1076 } 1077 1078 return 0; 1079 } 1080 1081 static struct pci_driver i915_pci_driver = { 1082 .name = DRIVER_NAME, 1083 .id_table = pciidlist, 1084 .probe = i915_pci_probe, 1085 .remove = i915_pci_remove, 1086 .driver.pm = &i915_pm_ops, 1087 }; 1088 1089 static int __init i915_init(void) 1090 { 1091 bool use_kms = true; 1092 int err; 1093 1094 err = i915_globals_init(); 1095 if (err) 1096 return err; 1097 1098 err = i915_mock_selftests(); 1099 if (err) 1100 return err > 0 ? 0 : err; 1101 1102 /* 1103 * Enable KMS by default, unless explicitly overriden by 1104 * either the i915.modeset prarameter or by the 1105 * vga_text_mode_force boot option. 1106 */ 1107 1108 if (i915_modparams.modeset == 0) 1109 use_kms = false; 1110 1111 if (vgacon_text_force() && i915_modparams.modeset == -1) 1112 use_kms = false; 1113 1114 if (!use_kms) { 1115 /* Silently fail loading to not upset userspace. */ 1116 DRM_DEBUG_DRIVER("KMS disabled.\n"); 1117 return 0; 1118 } 1119 1120 err = pci_register_driver(&i915_pci_driver); 1121 if (err) 1122 return err; 1123 1124 i915_perf_sysctl_register(); 1125 return 0; 1126 } 1127 1128 static void __exit i915_exit(void) 1129 { 1130 if (!i915_pci_driver.driver.owner) 1131 return; 1132 1133 i915_perf_sysctl_unregister(); 1134 pci_unregister_driver(&i915_pci_driver); 1135 i915_globals_exit(); 1136 } 1137 1138 module_init(i915_init); 1139 module_exit(i915_exit); 1140 1141 MODULE_AUTHOR("Tungsten Graphics, Inc."); 1142 MODULE_AUTHOR("Intel Corporation"); 1143 1144 MODULE_DESCRIPTION(DRIVER_DESC); 1145 MODULE_LICENSE("GPL and additional rights"); 1146