1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/console.h> 26 #include <linux/vgaarb.h> 27 #include <linux/vga_switcheroo.h> 28 29 #include <drm/drm_drv.h> 30 31 #include "i915_active.h" 32 #include "i915_drv.h" 33 #include "i915_selftest.h" 34 35 #define PLATFORM(x) .platform = (x), .platform_mask = BIT(x) 36 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1) 37 38 #define GEN_DEFAULT_PIPEOFFSETS \ 39 .pipe_offsets = { \ 40 [TRANSCODER_A] = PIPE_A_OFFSET, \ 41 [TRANSCODER_B] = PIPE_B_OFFSET, \ 42 [TRANSCODER_C] = PIPE_C_OFFSET, \ 43 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 44 }, \ 45 .trans_offsets = { \ 46 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 47 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 48 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 49 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 50 } 51 52 #define GEN_CHV_PIPEOFFSETS \ 53 .pipe_offsets = { \ 54 [TRANSCODER_A] = PIPE_A_OFFSET, \ 55 [TRANSCODER_B] = PIPE_B_OFFSET, \ 56 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \ 57 }, \ 58 .trans_offsets = { \ 59 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 60 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 61 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \ 62 } 63 64 #define CURSOR_OFFSETS \ 65 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET } 66 67 #define IVB_CURSOR_OFFSETS \ 68 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET } 69 70 #define BDW_COLORS \ 71 .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 } 72 #define CHV_COLORS \ 73 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \ 74 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 75 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 76 } 77 #define GLK_COLORS \ 78 .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024, \ 79 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 80 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 81 } 82 83 /* Keep in gen based order, and chronological order within a gen */ 84 85 #define GEN_DEFAULT_PAGE_SIZES \ 86 .page_sizes = I915_GTT_PAGE_SIZE_4K 87 88 #define GEN2_FEATURES \ 89 GEN(2), \ 90 .num_pipes = 1, \ 91 .display.has_overlay = 1, \ 92 .display.overlay_needs_physical = 1, \ 93 .display.has_gmch = 1, \ 94 .gpu_reset_clobbers_display = true, \ 95 .hws_needs_physical = 1, \ 96 .unfenced_needs_alignment = 1, \ 97 .ring_mask = RENDER_RING, \ 98 .has_snoop = true, \ 99 .has_coherent_ggtt = false, \ 100 GEN_DEFAULT_PIPEOFFSETS, \ 101 GEN_DEFAULT_PAGE_SIZES, \ 102 CURSOR_OFFSETS 103 104 static const struct intel_device_info intel_i830_info = { 105 GEN2_FEATURES, 106 PLATFORM(INTEL_I830), 107 .is_mobile = 1, 108 .display.cursor_needs_physical = 1, 109 .num_pipes = 2, /* legal, last one wins */ 110 }; 111 112 static const struct intel_device_info intel_i845g_info = { 113 GEN2_FEATURES, 114 PLATFORM(INTEL_I845G), 115 }; 116 117 static const struct intel_device_info intel_i85x_info = { 118 GEN2_FEATURES, 119 PLATFORM(INTEL_I85X), 120 .is_mobile = 1, 121 .num_pipes = 2, /* legal, last one wins */ 122 .display.cursor_needs_physical = 1, 123 .display.has_fbc = 1, 124 }; 125 126 static const struct intel_device_info intel_i865g_info = { 127 GEN2_FEATURES, 128 PLATFORM(INTEL_I865G), 129 }; 130 131 #define GEN3_FEATURES \ 132 GEN(3), \ 133 .num_pipes = 2, \ 134 .display.has_gmch = 1, \ 135 .gpu_reset_clobbers_display = true, \ 136 .ring_mask = RENDER_RING, \ 137 .has_snoop = true, \ 138 .has_coherent_ggtt = true, \ 139 GEN_DEFAULT_PIPEOFFSETS, \ 140 GEN_DEFAULT_PAGE_SIZES, \ 141 CURSOR_OFFSETS 142 143 static const struct intel_device_info intel_i915g_info = { 144 GEN3_FEATURES, 145 PLATFORM(INTEL_I915G), 146 .has_coherent_ggtt = false, 147 .display.cursor_needs_physical = 1, 148 .display.has_overlay = 1, 149 .display.overlay_needs_physical = 1, 150 .hws_needs_physical = 1, 151 .unfenced_needs_alignment = 1, 152 }; 153 154 static const struct intel_device_info intel_i915gm_info = { 155 GEN3_FEATURES, 156 PLATFORM(INTEL_I915GM), 157 .is_mobile = 1, 158 .display.cursor_needs_physical = 1, 159 .display.has_overlay = 1, 160 .display.overlay_needs_physical = 1, 161 .display.supports_tv = 1, 162 .display.has_fbc = 1, 163 .hws_needs_physical = 1, 164 .unfenced_needs_alignment = 1, 165 }; 166 167 static const struct intel_device_info intel_i945g_info = { 168 GEN3_FEATURES, 169 PLATFORM(INTEL_I945G), 170 .display.has_hotplug = 1, 171 .display.cursor_needs_physical = 1, 172 .display.has_overlay = 1, 173 .display.overlay_needs_physical = 1, 174 .hws_needs_physical = 1, 175 .unfenced_needs_alignment = 1, 176 }; 177 178 static const struct intel_device_info intel_i945gm_info = { 179 GEN3_FEATURES, 180 PLATFORM(INTEL_I945GM), 181 .is_mobile = 1, 182 .display.has_hotplug = 1, 183 .display.cursor_needs_physical = 1, 184 .display.has_overlay = 1, 185 .display.overlay_needs_physical = 1, 186 .display.supports_tv = 1, 187 .display.has_fbc = 1, 188 .hws_needs_physical = 1, 189 .unfenced_needs_alignment = 1, 190 }; 191 192 static const struct intel_device_info intel_g33_info = { 193 GEN3_FEATURES, 194 PLATFORM(INTEL_G33), 195 .display.has_hotplug = 1, 196 .display.has_overlay = 1, 197 }; 198 199 static const struct intel_device_info intel_pineview_info = { 200 GEN3_FEATURES, 201 PLATFORM(INTEL_PINEVIEW), 202 .is_mobile = 1, 203 .display.has_hotplug = 1, 204 .display.has_overlay = 1, 205 }; 206 207 #define GEN4_FEATURES \ 208 GEN(4), \ 209 .num_pipes = 2, \ 210 .display.has_hotplug = 1, \ 211 .display.has_gmch = 1, \ 212 .gpu_reset_clobbers_display = true, \ 213 .ring_mask = RENDER_RING, \ 214 .has_snoop = true, \ 215 .has_coherent_ggtt = true, \ 216 GEN_DEFAULT_PIPEOFFSETS, \ 217 GEN_DEFAULT_PAGE_SIZES, \ 218 CURSOR_OFFSETS 219 220 static const struct intel_device_info intel_i965g_info = { 221 GEN4_FEATURES, 222 PLATFORM(INTEL_I965G), 223 .display.has_overlay = 1, 224 .hws_needs_physical = 1, 225 .has_snoop = false, 226 }; 227 228 static const struct intel_device_info intel_i965gm_info = { 229 GEN4_FEATURES, 230 PLATFORM(INTEL_I965GM), 231 .is_mobile = 1, 232 .display.has_fbc = 1, 233 .display.has_overlay = 1, 234 .display.supports_tv = 1, 235 .hws_needs_physical = 1, 236 .has_snoop = false, 237 }; 238 239 static const struct intel_device_info intel_g45_info = { 240 GEN4_FEATURES, 241 PLATFORM(INTEL_G45), 242 .ring_mask = RENDER_RING | BSD_RING, 243 .gpu_reset_clobbers_display = false, 244 }; 245 246 static const struct intel_device_info intel_gm45_info = { 247 GEN4_FEATURES, 248 PLATFORM(INTEL_GM45), 249 .is_mobile = 1, 250 .display.has_fbc = 1, 251 .display.supports_tv = 1, 252 .ring_mask = RENDER_RING | BSD_RING, 253 .gpu_reset_clobbers_display = false, 254 }; 255 256 #define GEN5_FEATURES \ 257 GEN(5), \ 258 .num_pipes = 2, \ 259 .display.has_hotplug = 1, \ 260 .ring_mask = RENDER_RING | BSD_RING, \ 261 .has_snoop = true, \ 262 .has_coherent_ggtt = true, \ 263 /* ilk does support rc6, but we do not implement [power] contexts */ \ 264 .has_rc6 = 0, \ 265 GEN_DEFAULT_PIPEOFFSETS, \ 266 GEN_DEFAULT_PAGE_SIZES, \ 267 CURSOR_OFFSETS 268 269 static const struct intel_device_info intel_ironlake_d_info = { 270 GEN5_FEATURES, 271 PLATFORM(INTEL_IRONLAKE), 272 }; 273 274 static const struct intel_device_info intel_ironlake_m_info = { 275 GEN5_FEATURES, 276 PLATFORM(INTEL_IRONLAKE), 277 .is_mobile = 1, 278 .display.has_fbc = 1, 279 }; 280 281 #define GEN6_FEATURES \ 282 GEN(6), \ 283 .num_pipes = 2, \ 284 .display.has_hotplug = 1, \ 285 .display.has_fbc = 1, \ 286 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ 287 .has_coherent_ggtt = true, \ 288 .has_llc = 1, \ 289 .has_rc6 = 1, \ 290 .has_rc6p = 1, \ 291 .ppgtt = INTEL_PPGTT_ALIASING, \ 292 GEN_DEFAULT_PIPEOFFSETS, \ 293 GEN_DEFAULT_PAGE_SIZES, \ 294 CURSOR_OFFSETS 295 296 #define SNB_D_PLATFORM \ 297 GEN6_FEATURES, \ 298 PLATFORM(INTEL_SANDYBRIDGE) 299 300 static const struct intel_device_info intel_sandybridge_d_gt1_info = { 301 SNB_D_PLATFORM, 302 .gt = 1, 303 }; 304 305 static const struct intel_device_info intel_sandybridge_d_gt2_info = { 306 SNB_D_PLATFORM, 307 .gt = 2, 308 }; 309 310 #define SNB_M_PLATFORM \ 311 GEN6_FEATURES, \ 312 PLATFORM(INTEL_SANDYBRIDGE), \ 313 .is_mobile = 1 314 315 316 static const struct intel_device_info intel_sandybridge_m_gt1_info = { 317 SNB_M_PLATFORM, 318 .gt = 1, 319 }; 320 321 static const struct intel_device_info intel_sandybridge_m_gt2_info = { 322 SNB_M_PLATFORM, 323 .gt = 2, 324 }; 325 326 #define GEN7_FEATURES \ 327 GEN(7), \ 328 .num_pipes = 3, \ 329 .display.has_hotplug = 1, \ 330 .display.has_fbc = 1, \ 331 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ 332 .has_coherent_ggtt = true, \ 333 .has_llc = 1, \ 334 .has_rc6 = 1, \ 335 .has_rc6p = 1, \ 336 .ppgtt = INTEL_PPGTT_FULL, \ 337 GEN_DEFAULT_PIPEOFFSETS, \ 338 GEN_DEFAULT_PAGE_SIZES, \ 339 IVB_CURSOR_OFFSETS 340 341 #define IVB_D_PLATFORM \ 342 GEN7_FEATURES, \ 343 PLATFORM(INTEL_IVYBRIDGE), \ 344 .has_l3_dpf = 1 345 346 static const struct intel_device_info intel_ivybridge_d_gt1_info = { 347 IVB_D_PLATFORM, 348 .gt = 1, 349 }; 350 351 static const struct intel_device_info intel_ivybridge_d_gt2_info = { 352 IVB_D_PLATFORM, 353 .gt = 2, 354 }; 355 356 #define IVB_M_PLATFORM \ 357 GEN7_FEATURES, \ 358 PLATFORM(INTEL_IVYBRIDGE), \ 359 .is_mobile = 1, \ 360 .has_l3_dpf = 1 361 362 static const struct intel_device_info intel_ivybridge_m_gt1_info = { 363 IVB_M_PLATFORM, 364 .gt = 1, 365 }; 366 367 static const struct intel_device_info intel_ivybridge_m_gt2_info = { 368 IVB_M_PLATFORM, 369 .gt = 2, 370 }; 371 372 static const struct intel_device_info intel_ivybridge_q_info = { 373 GEN7_FEATURES, 374 PLATFORM(INTEL_IVYBRIDGE), 375 .gt = 2, 376 .num_pipes = 0, /* legal, last one wins */ 377 .has_l3_dpf = 1, 378 }; 379 380 static const struct intel_device_info intel_valleyview_info = { 381 PLATFORM(INTEL_VALLEYVIEW), 382 GEN(7), 383 .is_lp = 1, 384 .num_pipes = 2, 385 .has_runtime_pm = 1, 386 .has_rc6 = 1, 387 .display.has_gmch = 1, 388 .display.has_hotplug = 1, 389 .ppgtt = INTEL_PPGTT_FULL, 390 .has_snoop = true, 391 .has_coherent_ggtt = false, 392 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, 393 .display_mmio_offset = VLV_DISPLAY_BASE, 394 GEN_DEFAULT_PAGE_SIZES, 395 GEN_DEFAULT_PIPEOFFSETS, 396 CURSOR_OFFSETS 397 }; 398 399 #define G75_FEATURES \ 400 GEN7_FEATURES, \ 401 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ 402 .display.has_ddi = 1, \ 403 .has_fpga_dbg = 1, \ 404 .display.has_psr = 1, \ 405 .display.has_dp_mst = 1, \ 406 .has_rc6p = 0 /* RC6p removed-by HSW */, \ 407 .has_runtime_pm = 1 408 409 #define HSW_PLATFORM \ 410 G75_FEATURES, \ 411 PLATFORM(INTEL_HASWELL), \ 412 .has_l3_dpf = 1 413 414 static const struct intel_device_info intel_haswell_gt1_info = { 415 HSW_PLATFORM, 416 .gt = 1, 417 }; 418 419 static const struct intel_device_info intel_haswell_gt2_info = { 420 HSW_PLATFORM, 421 .gt = 2, 422 }; 423 424 static const struct intel_device_info intel_haswell_gt3_info = { 425 HSW_PLATFORM, 426 .gt = 3, 427 }; 428 429 #define GEN8_FEATURES \ 430 G75_FEATURES, \ 431 GEN(8), \ 432 BDW_COLORS, \ 433 .page_sizes = I915_GTT_PAGE_SIZE_4K | \ 434 I915_GTT_PAGE_SIZE_2M, \ 435 .has_logical_ring_contexts = 1, \ 436 .ppgtt = INTEL_PPGTT_FULL_4LVL, \ 437 .has_64bit_reloc = 1, \ 438 .has_reset_engine = 1 439 440 #define BDW_PLATFORM \ 441 GEN8_FEATURES, \ 442 PLATFORM(INTEL_BROADWELL) 443 444 static const struct intel_device_info intel_broadwell_gt1_info = { 445 BDW_PLATFORM, 446 .gt = 1, 447 }; 448 449 static const struct intel_device_info intel_broadwell_gt2_info = { 450 BDW_PLATFORM, 451 .gt = 2, 452 }; 453 454 static const struct intel_device_info intel_broadwell_rsvd_info = { 455 BDW_PLATFORM, 456 .gt = 3, 457 /* According to the device ID those devices are GT3, they were 458 * previously treated as not GT3, keep it like that. 459 */ 460 }; 461 462 static const struct intel_device_info intel_broadwell_gt3_info = { 463 BDW_PLATFORM, 464 .gt = 3, 465 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 466 }; 467 468 static const struct intel_device_info intel_cherryview_info = { 469 PLATFORM(INTEL_CHERRYVIEW), 470 GEN(8), 471 .num_pipes = 3, 472 .display.has_hotplug = 1, 473 .is_lp = 1, 474 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 475 .has_64bit_reloc = 1, 476 .has_runtime_pm = 1, 477 .has_rc6 = 1, 478 .has_logical_ring_contexts = 1, 479 .display.has_gmch = 1, 480 .ppgtt = INTEL_PPGTT_FULL, 481 .has_reset_engine = 1, 482 .has_snoop = true, 483 .has_coherent_ggtt = false, 484 .display_mmio_offset = VLV_DISPLAY_BASE, 485 GEN_DEFAULT_PAGE_SIZES, 486 GEN_CHV_PIPEOFFSETS, 487 CURSOR_OFFSETS, 488 CHV_COLORS, 489 }; 490 491 #define GEN9_DEFAULT_PAGE_SIZES \ 492 .page_sizes = I915_GTT_PAGE_SIZE_4K | \ 493 I915_GTT_PAGE_SIZE_64K | \ 494 I915_GTT_PAGE_SIZE_2M 495 496 #define GEN9_FEATURES \ 497 GEN8_FEATURES, \ 498 GEN(9), \ 499 GEN9_DEFAULT_PAGE_SIZES, \ 500 .has_logical_ring_preemption = 1, \ 501 .display.has_csr = 1, \ 502 .has_guc = 1, \ 503 .display.has_ipc = 1, \ 504 .ddb_size = 896 505 506 #define SKL_PLATFORM \ 507 GEN9_FEATURES, \ 508 /* Display WA #0477 WaDisableIPC: skl */ \ 509 .display.has_ipc = 0, \ 510 PLATFORM(INTEL_SKYLAKE) 511 512 static const struct intel_device_info intel_skylake_gt1_info = { 513 SKL_PLATFORM, 514 .gt = 1, 515 }; 516 517 static const struct intel_device_info intel_skylake_gt2_info = { 518 SKL_PLATFORM, 519 .gt = 2, 520 }; 521 522 #define SKL_GT3_PLUS_PLATFORM \ 523 SKL_PLATFORM, \ 524 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING 525 526 527 static const struct intel_device_info intel_skylake_gt3_info = { 528 SKL_GT3_PLUS_PLATFORM, 529 .gt = 3, 530 }; 531 532 static const struct intel_device_info intel_skylake_gt4_info = { 533 SKL_GT3_PLUS_PLATFORM, 534 .gt = 4, 535 }; 536 537 #define GEN9_LP_FEATURES \ 538 GEN(9), \ 539 .is_lp = 1, \ 540 .display.has_hotplug = 1, \ 541 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ 542 .num_pipes = 3, \ 543 .has_64bit_reloc = 1, \ 544 .display.has_ddi = 1, \ 545 .has_fpga_dbg = 1, \ 546 .display.has_fbc = 1, \ 547 .display.has_psr = 1, \ 548 .has_runtime_pm = 1, \ 549 .display.has_csr = 1, \ 550 .has_rc6 = 1, \ 551 .display.has_dp_mst = 1, \ 552 .has_logical_ring_contexts = 1, \ 553 .has_logical_ring_preemption = 1, \ 554 .has_guc = 1, \ 555 .ppgtt = INTEL_PPGTT_FULL_4LVL, \ 556 .has_reset_engine = 1, \ 557 .has_snoop = true, \ 558 .has_coherent_ggtt = false, \ 559 .display.has_ipc = 1, \ 560 GEN9_DEFAULT_PAGE_SIZES, \ 561 GEN_DEFAULT_PIPEOFFSETS, \ 562 IVB_CURSOR_OFFSETS, \ 563 BDW_COLORS 564 565 static const struct intel_device_info intel_broxton_info = { 566 GEN9_LP_FEATURES, 567 PLATFORM(INTEL_BROXTON), 568 .ddb_size = 512, 569 }; 570 571 static const struct intel_device_info intel_geminilake_info = { 572 GEN9_LP_FEATURES, 573 PLATFORM(INTEL_GEMINILAKE), 574 .ddb_size = 1024, 575 GLK_COLORS, 576 }; 577 578 #define KBL_PLATFORM \ 579 GEN9_FEATURES, \ 580 PLATFORM(INTEL_KABYLAKE) 581 582 static const struct intel_device_info intel_kabylake_gt1_info = { 583 KBL_PLATFORM, 584 .gt = 1, 585 }; 586 587 static const struct intel_device_info intel_kabylake_gt2_info = { 588 KBL_PLATFORM, 589 .gt = 2, 590 }; 591 592 static const struct intel_device_info intel_kabylake_gt3_info = { 593 KBL_PLATFORM, 594 .gt = 3, 595 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 596 }; 597 598 #define CFL_PLATFORM \ 599 GEN9_FEATURES, \ 600 PLATFORM(INTEL_COFFEELAKE) 601 602 static const struct intel_device_info intel_coffeelake_gt1_info = { 603 CFL_PLATFORM, 604 .gt = 1, 605 }; 606 607 static const struct intel_device_info intel_coffeelake_gt2_info = { 608 CFL_PLATFORM, 609 .gt = 2, 610 }; 611 612 static const struct intel_device_info intel_coffeelake_gt3_info = { 613 CFL_PLATFORM, 614 .gt = 3, 615 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 616 }; 617 618 #define GEN10_FEATURES \ 619 GEN9_FEATURES, \ 620 GEN(10), \ 621 .ddb_size = 1024, \ 622 .has_coherent_ggtt = false, \ 623 GLK_COLORS 624 625 static const struct intel_device_info intel_cannonlake_info = { 626 GEN10_FEATURES, 627 PLATFORM(INTEL_CANNONLAKE), 628 .gt = 2, 629 }; 630 631 #define GEN11_FEATURES \ 632 GEN10_FEATURES, \ 633 .pipe_offsets = { \ 634 [TRANSCODER_A] = PIPE_A_OFFSET, \ 635 [TRANSCODER_B] = PIPE_B_OFFSET, \ 636 [TRANSCODER_C] = PIPE_C_OFFSET, \ 637 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 638 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 639 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 640 }, \ 641 .trans_offsets = { \ 642 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 643 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 644 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 645 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 646 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 647 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 648 }, \ 649 GEN(11), \ 650 .ddb_size = 2048, \ 651 .has_logical_ring_elsq = 1 652 653 static const struct intel_device_info intel_icelake_11_info = { 654 GEN11_FEATURES, 655 PLATFORM(INTEL_ICELAKE), 656 .is_alpha_support = 1, 657 .ring_mask = RENDER_RING | BLT_RING | VEBOX_RING | BSD_RING | BSD3_RING, 658 }; 659 660 #undef GEN 661 #undef PLATFORM 662 663 /* 664 * Make sure any device matches here are from most specific to most 665 * general. For example, since the Quanta match is based on the subsystem 666 * and subvendor IDs, we need it to come before the more general IVB 667 * PCI ID matches, otherwise we'll use the wrong info struct above. 668 */ 669 static const struct pci_device_id pciidlist[] = { 670 INTEL_I830_IDS(&intel_i830_info), 671 INTEL_I845G_IDS(&intel_i845g_info), 672 INTEL_I85X_IDS(&intel_i85x_info), 673 INTEL_I865G_IDS(&intel_i865g_info), 674 INTEL_I915G_IDS(&intel_i915g_info), 675 INTEL_I915GM_IDS(&intel_i915gm_info), 676 INTEL_I945G_IDS(&intel_i945g_info), 677 INTEL_I945GM_IDS(&intel_i945gm_info), 678 INTEL_I965G_IDS(&intel_i965g_info), 679 INTEL_G33_IDS(&intel_g33_info), 680 INTEL_I965GM_IDS(&intel_i965gm_info), 681 INTEL_GM45_IDS(&intel_gm45_info), 682 INTEL_G45_IDS(&intel_g45_info), 683 INTEL_PINEVIEW_IDS(&intel_pineview_info), 684 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), 685 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), 686 INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info), 687 INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info), 688 INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info), 689 INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info), 690 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ 691 INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info), 692 INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info), 693 INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info), 694 INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info), 695 INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info), 696 INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info), 697 INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info), 698 INTEL_VLV_IDS(&intel_valleyview_info), 699 INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info), 700 INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info), 701 INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info), 702 INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info), 703 INTEL_CHV_IDS(&intel_cherryview_info), 704 INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info), 705 INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info), 706 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), 707 INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info), 708 INTEL_BXT_IDS(&intel_broxton_info), 709 INTEL_GLK_IDS(&intel_geminilake_info), 710 INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info), 711 INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info), 712 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info), 713 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info), 714 INTEL_AML_KBL_GT2_IDS(&intel_kabylake_gt2_info), 715 INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info), 716 INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info), 717 INTEL_CFL_H_GT1_IDS(&intel_coffeelake_gt1_info), 718 INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info), 719 INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info), 720 INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info), 721 INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info), 722 INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info), 723 INTEL_AML_CFL_GT2_IDS(&intel_coffeelake_gt2_info), 724 INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info), 725 INTEL_CNL_IDS(&intel_cannonlake_info), 726 INTEL_ICL_11_IDS(&intel_icelake_11_info), 727 {0, 0, 0} 728 }; 729 MODULE_DEVICE_TABLE(pci, pciidlist); 730 731 static void i915_pci_remove(struct pci_dev *pdev) 732 { 733 struct drm_device *dev; 734 735 dev = pci_get_drvdata(pdev); 736 if (!dev) /* driver load aborted, nothing to cleanup */ 737 return; 738 739 i915_driver_unload(dev); 740 drm_dev_put(dev); 741 742 pci_set_drvdata(pdev, NULL); 743 } 744 745 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 746 { 747 struct intel_device_info *intel_info = 748 (struct intel_device_info *) ent->driver_data; 749 int err; 750 751 if (IS_ALPHA_SUPPORT(intel_info) && !i915_modparams.alpha_support) { 752 DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n" 753 "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n" 754 "to enable support in this kernel version, or check for kernel updates.\n"); 755 return -ENODEV; 756 } 757 758 /* Only bind to function 0 of the device. Early generations 759 * used function 1 as a placeholder for multi-head. This causes 760 * us confusion instead, especially on the systems where both 761 * functions have the same PCI-ID! 762 */ 763 if (PCI_FUNC(pdev->devfn)) 764 return -ENODEV; 765 766 /* 767 * apple-gmux is needed on dual GPU MacBook Pro 768 * to probe the panel if we're the inactive GPU. 769 */ 770 if (vga_switcheroo_client_probe_defer(pdev)) 771 return -EPROBE_DEFER; 772 773 err = i915_driver_load(pdev, ent); 774 if (err) 775 return err; 776 777 if (i915_inject_load_failure()) { 778 i915_pci_remove(pdev); 779 return -ENODEV; 780 } 781 782 err = i915_live_selftests(pdev); 783 if (err) { 784 i915_pci_remove(pdev); 785 return err > 0 ? -ENOTTY : err; 786 } 787 788 return 0; 789 } 790 791 static struct pci_driver i915_pci_driver = { 792 .name = DRIVER_NAME, 793 .id_table = pciidlist, 794 .probe = i915_pci_probe, 795 .remove = i915_pci_remove, 796 .driver.pm = &i915_pm_ops, 797 }; 798 799 static int __init i915_init(void) 800 { 801 bool use_kms = true; 802 int err; 803 804 i915_global_active_init(); 805 806 err = i915_mock_selftests(); 807 if (err) 808 return err > 0 ? 0 : err; 809 810 /* 811 * Enable KMS by default, unless explicitly overriden by 812 * either the i915.modeset prarameter or by the 813 * vga_text_mode_force boot option. 814 */ 815 816 if (i915_modparams.modeset == 0) 817 use_kms = false; 818 819 if (vgacon_text_force() && i915_modparams.modeset == -1) 820 use_kms = false; 821 822 if (!use_kms) { 823 /* Silently fail loading to not upset userspace. */ 824 DRM_DEBUG_DRIVER("KMS disabled.\n"); 825 return 0; 826 } 827 828 return pci_register_driver(&i915_pci_driver); 829 } 830 831 static void __exit i915_exit(void) 832 { 833 if (!i915_pci_driver.driver.owner) 834 return; 835 836 pci_unregister_driver(&i915_pci_driver); 837 i915_global_active_exit(); 838 } 839 840 module_init(i915_init); 841 module_exit(i915_exit); 842 843 MODULE_AUTHOR("Tungsten Graphics, Inc."); 844 MODULE_AUTHOR("Intel Corporation"); 845 846 MODULE_DESCRIPTION(DRIVER_DESC); 847 MODULE_LICENSE("GPL and additional rights"); 848