1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/console.h> 26 #include <linux/vga_switcheroo.h> 27 28 #include <drm/drm_drv.h> 29 30 #include "display/intel_fbdev.h" 31 32 #include "i915_drv.h" 33 #include "i915_perf.h" 34 #include "i915_globals.h" 35 #include "i915_selftest.h" 36 37 #define PLATFORM(x) .platform = (x) 38 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1) 39 40 #define I845_PIPE_OFFSETS \ 41 .pipe_offsets = { \ 42 [TRANSCODER_A] = PIPE_A_OFFSET, \ 43 }, \ 44 .trans_offsets = { \ 45 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 46 } 47 48 #define I9XX_PIPE_OFFSETS \ 49 .pipe_offsets = { \ 50 [TRANSCODER_A] = PIPE_A_OFFSET, \ 51 [TRANSCODER_B] = PIPE_B_OFFSET, \ 52 }, \ 53 .trans_offsets = { \ 54 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 55 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 56 } 57 58 #define IVB_PIPE_OFFSETS \ 59 .pipe_offsets = { \ 60 [TRANSCODER_A] = PIPE_A_OFFSET, \ 61 [TRANSCODER_B] = PIPE_B_OFFSET, \ 62 [TRANSCODER_C] = PIPE_C_OFFSET, \ 63 }, \ 64 .trans_offsets = { \ 65 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 66 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 67 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 68 } 69 70 #define HSW_PIPE_OFFSETS \ 71 .pipe_offsets = { \ 72 [TRANSCODER_A] = PIPE_A_OFFSET, \ 73 [TRANSCODER_B] = PIPE_B_OFFSET, \ 74 [TRANSCODER_C] = PIPE_C_OFFSET, \ 75 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 76 }, \ 77 .trans_offsets = { \ 78 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 79 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 80 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 81 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 82 } 83 84 #define CHV_PIPE_OFFSETS \ 85 .pipe_offsets = { \ 86 [TRANSCODER_A] = PIPE_A_OFFSET, \ 87 [TRANSCODER_B] = PIPE_B_OFFSET, \ 88 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \ 89 }, \ 90 .trans_offsets = { \ 91 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 92 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 93 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \ 94 } 95 96 #define I845_CURSOR_OFFSETS \ 97 .cursor_offsets = { \ 98 [PIPE_A] = CURSOR_A_OFFSET, \ 99 } 100 101 #define I9XX_CURSOR_OFFSETS \ 102 .cursor_offsets = { \ 103 [PIPE_A] = CURSOR_A_OFFSET, \ 104 [PIPE_B] = CURSOR_B_OFFSET, \ 105 } 106 107 #define CHV_CURSOR_OFFSETS \ 108 .cursor_offsets = { \ 109 [PIPE_A] = CURSOR_A_OFFSET, \ 110 [PIPE_B] = CURSOR_B_OFFSET, \ 111 [PIPE_C] = CHV_CURSOR_C_OFFSET, \ 112 } 113 114 #define IVB_CURSOR_OFFSETS \ 115 .cursor_offsets = { \ 116 [PIPE_A] = CURSOR_A_OFFSET, \ 117 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 118 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 119 } 120 121 #define TGL_CURSOR_OFFSETS \ 122 .cursor_offsets = { \ 123 [PIPE_A] = CURSOR_A_OFFSET, \ 124 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 125 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 126 [PIPE_D] = TGL_CURSOR_D_OFFSET, \ 127 } 128 129 #define I9XX_COLORS \ 130 .color = { .gamma_lut_size = 256 } 131 #define I965_COLORS \ 132 .color = { .gamma_lut_size = 129, \ 133 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 134 } 135 #define ILK_COLORS \ 136 .color = { .gamma_lut_size = 1024 } 137 #define IVB_COLORS \ 138 .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 } 139 #define CHV_COLORS \ 140 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \ 141 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 142 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 143 } 144 #define GLK_COLORS \ 145 .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \ 146 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 147 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 148 } 149 150 /* Keep in gen based order, and chronological order within a gen */ 151 152 #define GEN_DEFAULT_PAGE_SIZES \ 153 .page_sizes = I915_GTT_PAGE_SIZE_4K 154 155 #define GEN_DEFAULT_REGIONS \ 156 .memory_regions = REGION_SMEM | REGION_STOLEN 157 158 #define I830_FEATURES \ 159 GEN(2), \ 160 .is_mobile = 1, \ 161 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 162 .display.has_overlay = 1, \ 163 .display.cursor_needs_physical = 1, \ 164 .display.overlay_needs_physical = 1, \ 165 .display.has_gmch = 1, \ 166 .gpu_reset_clobbers_display = true, \ 167 .hws_needs_physical = 1, \ 168 .unfenced_needs_alignment = 1, \ 169 .engine_mask = BIT(RCS0), \ 170 .has_snoop = true, \ 171 .has_coherent_ggtt = false, \ 172 I9XX_PIPE_OFFSETS, \ 173 I9XX_CURSOR_OFFSETS, \ 174 I9XX_COLORS, \ 175 GEN_DEFAULT_PAGE_SIZES, \ 176 GEN_DEFAULT_REGIONS 177 178 #define I845_FEATURES \ 179 GEN(2), \ 180 .pipe_mask = BIT(PIPE_A), \ 181 .display.has_overlay = 1, \ 182 .display.overlay_needs_physical = 1, \ 183 .display.has_gmch = 1, \ 184 .gpu_reset_clobbers_display = true, \ 185 .hws_needs_physical = 1, \ 186 .unfenced_needs_alignment = 1, \ 187 .engine_mask = BIT(RCS0), \ 188 .has_snoop = true, \ 189 .has_coherent_ggtt = false, \ 190 I845_PIPE_OFFSETS, \ 191 I845_CURSOR_OFFSETS, \ 192 I9XX_COLORS, \ 193 GEN_DEFAULT_PAGE_SIZES, \ 194 GEN_DEFAULT_REGIONS 195 196 static const struct intel_device_info i830_info = { 197 I830_FEATURES, 198 PLATFORM(INTEL_I830), 199 }; 200 201 static const struct intel_device_info i845g_info = { 202 I845_FEATURES, 203 PLATFORM(INTEL_I845G), 204 }; 205 206 static const struct intel_device_info i85x_info = { 207 I830_FEATURES, 208 PLATFORM(INTEL_I85X), 209 .display.has_fbc = 1, 210 }; 211 212 static const struct intel_device_info i865g_info = { 213 I845_FEATURES, 214 PLATFORM(INTEL_I865G), 215 }; 216 217 #define GEN3_FEATURES \ 218 GEN(3), \ 219 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 220 .display.has_gmch = 1, \ 221 .gpu_reset_clobbers_display = true, \ 222 .engine_mask = BIT(RCS0), \ 223 .has_snoop = true, \ 224 .has_coherent_ggtt = true, \ 225 I9XX_PIPE_OFFSETS, \ 226 I9XX_CURSOR_OFFSETS, \ 227 I9XX_COLORS, \ 228 GEN_DEFAULT_PAGE_SIZES, \ 229 GEN_DEFAULT_REGIONS 230 231 static const struct intel_device_info i915g_info = { 232 GEN3_FEATURES, 233 PLATFORM(INTEL_I915G), 234 .has_coherent_ggtt = false, 235 .display.cursor_needs_physical = 1, 236 .display.has_overlay = 1, 237 .display.overlay_needs_physical = 1, 238 .hws_needs_physical = 1, 239 .unfenced_needs_alignment = 1, 240 }; 241 242 static const struct intel_device_info i915gm_info = { 243 GEN3_FEATURES, 244 PLATFORM(INTEL_I915GM), 245 .is_mobile = 1, 246 .display.cursor_needs_physical = 1, 247 .display.has_overlay = 1, 248 .display.overlay_needs_physical = 1, 249 .display.supports_tv = 1, 250 .display.has_fbc = 1, 251 .hws_needs_physical = 1, 252 .unfenced_needs_alignment = 1, 253 }; 254 255 static const struct intel_device_info i945g_info = { 256 GEN3_FEATURES, 257 PLATFORM(INTEL_I945G), 258 .display.has_hotplug = 1, 259 .display.cursor_needs_physical = 1, 260 .display.has_overlay = 1, 261 .display.overlay_needs_physical = 1, 262 .hws_needs_physical = 1, 263 .unfenced_needs_alignment = 1, 264 }; 265 266 static const struct intel_device_info i945gm_info = { 267 GEN3_FEATURES, 268 PLATFORM(INTEL_I945GM), 269 .is_mobile = 1, 270 .display.has_hotplug = 1, 271 .display.cursor_needs_physical = 1, 272 .display.has_overlay = 1, 273 .display.overlay_needs_physical = 1, 274 .display.supports_tv = 1, 275 .display.has_fbc = 1, 276 .hws_needs_physical = 1, 277 .unfenced_needs_alignment = 1, 278 }; 279 280 static const struct intel_device_info g33_info = { 281 GEN3_FEATURES, 282 PLATFORM(INTEL_G33), 283 .display.has_hotplug = 1, 284 .display.has_overlay = 1, 285 }; 286 287 static const struct intel_device_info pnv_g_info = { 288 GEN3_FEATURES, 289 PLATFORM(INTEL_PINEVIEW), 290 .display.has_hotplug = 1, 291 .display.has_overlay = 1, 292 }; 293 294 static const struct intel_device_info pnv_m_info = { 295 GEN3_FEATURES, 296 PLATFORM(INTEL_PINEVIEW), 297 .is_mobile = 1, 298 .display.has_hotplug = 1, 299 .display.has_overlay = 1, 300 }; 301 302 #define GEN4_FEATURES \ 303 GEN(4), \ 304 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 305 .display.has_hotplug = 1, \ 306 .display.has_gmch = 1, \ 307 .gpu_reset_clobbers_display = true, \ 308 .engine_mask = BIT(RCS0), \ 309 .has_snoop = true, \ 310 .has_coherent_ggtt = true, \ 311 I9XX_PIPE_OFFSETS, \ 312 I9XX_CURSOR_OFFSETS, \ 313 I965_COLORS, \ 314 GEN_DEFAULT_PAGE_SIZES, \ 315 GEN_DEFAULT_REGIONS 316 317 static const struct intel_device_info i965g_info = { 318 GEN4_FEATURES, 319 PLATFORM(INTEL_I965G), 320 .display.has_overlay = 1, 321 .hws_needs_physical = 1, 322 .has_snoop = false, 323 }; 324 325 static const struct intel_device_info i965gm_info = { 326 GEN4_FEATURES, 327 PLATFORM(INTEL_I965GM), 328 .is_mobile = 1, 329 .display.has_fbc = 1, 330 .display.has_overlay = 1, 331 .display.supports_tv = 1, 332 .hws_needs_physical = 1, 333 .has_snoop = false, 334 }; 335 336 static const struct intel_device_info g45_info = { 337 GEN4_FEATURES, 338 PLATFORM(INTEL_G45), 339 .engine_mask = BIT(RCS0) | BIT(VCS0), 340 .gpu_reset_clobbers_display = false, 341 }; 342 343 static const struct intel_device_info gm45_info = { 344 GEN4_FEATURES, 345 PLATFORM(INTEL_GM45), 346 .is_mobile = 1, 347 .display.has_fbc = 1, 348 .display.supports_tv = 1, 349 .engine_mask = BIT(RCS0) | BIT(VCS0), 350 .gpu_reset_clobbers_display = false, 351 }; 352 353 #define GEN5_FEATURES \ 354 GEN(5), \ 355 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 356 .display.has_hotplug = 1, \ 357 .engine_mask = BIT(RCS0) | BIT(VCS0), \ 358 .has_snoop = true, \ 359 .has_coherent_ggtt = true, \ 360 /* ilk does support rc6, but we do not implement [power] contexts */ \ 361 .has_rc6 = 0, \ 362 I9XX_PIPE_OFFSETS, \ 363 I9XX_CURSOR_OFFSETS, \ 364 ILK_COLORS, \ 365 GEN_DEFAULT_PAGE_SIZES, \ 366 GEN_DEFAULT_REGIONS 367 368 static const struct intel_device_info ilk_d_info = { 369 GEN5_FEATURES, 370 PLATFORM(INTEL_IRONLAKE), 371 }; 372 373 static const struct intel_device_info ilk_m_info = { 374 GEN5_FEATURES, 375 PLATFORM(INTEL_IRONLAKE), 376 .is_mobile = 1, 377 .display.has_fbc = 1, 378 }; 379 380 #define GEN6_FEATURES \ 381 GEN(6), \ 382 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 383 .display.has_hotplug = 1, \ 384 .display.has_fbc = 1, \ 385 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 386 .has_coherent_ggtt = true, \ 387 .has_llc = 1, \ 388 .has_rc6 = 1, \ 389 .has_rc6p = 1, \ 390 .has_rps = true, \ 391 .ppgtt_type = INTEL_PPGTT_ALIASING, \ 392 .ppgtt_size = 31, \ 393 I9XX_PIPE_OFFSETS, \ 394 I9XX_CURSOR_OFFSETS, \ 395 ILK_COLORS, \ 396 GEN_DEFAULT_PAGE_SIZES, \ 397 GEN_DEFAULT_REGIONS 398 399 #define SNB_D_PLATFORM \ 400 GEN6_FEATURES, \ 401 PLATFORM(INTEL_SANDYBRIDGE) 402 403 static const struct intel_device_info snb_d_gt1_info = { 404 SNB_D_PLATFORM, 405 .gt = 1, 406 }; 407 408 static const struct intel_device_info snb_d_gt2_info = { 409 SNB_D_PLATFORM, 410 .gt = 2, 411 }; 412 413 #define SNB_M_PLATFORM \ 414 GEN6_FEATURES, \ 415 PLATFORM(INTEL_SANDYBRIDGE), \ 416 .is_mobile = 1 417 418 419 static const struct intel_device_info snb_m_gt1_info = { 420 SNB_M_PLATFORM, 421 .gt = 1, 422 }; 423 424 static const struct intel_device_info snb_m_gt2_info = { 425 SNB_M_PLATFORM, 426 .gt = 2, 427 }; 428 429 #define GEN7_FEATURES \ 430 GEN(7), \ 431 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 432 .display.has_hotplug = 1, \ 433 .display.has_fbc = 1, \ 434 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 435 .has_coherent_ggtt = true, \ 436 .has_llc = 1, \ 437 .has_rc6 = 1, \ 438 .has_rc6p = 1, \ 439 .has_rps = true, \ 440 .ppgtt_type = INTEL_PPGTT_ALIASING, \ 441 .ppgtt_size = 31, \ 442 IVB_PIPE_OFFSETS, \ 443 IVB_CURSOR_OFFSETS, \ 444 IVB_COLORS, \ 445 GEN_DEFAULT_PAGE_SIZES, \ 446 GEN_DEFAULT_REGIONS 447 448 #define IVB_D_PLATFORM \ 449 GEN7_FEATURES, \ 450 PLATFORM(INTEL_IVYBRIDGE), \ 451 .has_l3_dpf = 1 452 453 static const struct intel_device_info ivb_d_gt1_info = { 454 IVB_D_PLATFORM, 455 .gt = 1, 456 }; 457 458 static const struct intel_device_info ivb_d_gt2_info = { 459 IVB_D_PLATFORM, 460 .gt = 2, 461 }; 462 463 #define IVB_M_PLATFORM \ 464 GEN7_FEATURES, \ 465 PLATFORM(INTEL_IVYBRIDGE), \ 466 .is_mobile = 1, \ 467 .has_l3_dpf = 1 468 469 static const struct intel_device_info ivb_m_gt1_info = { 470 IVB_M_PLATFORM, 471 .gt = 1, 472 }; 473 474 static const struct intel_device_info ivb_m_gt2_info = { 475 IVB_M_PLATFORM, 476 .gt = 2, 477 }; 478 479 static const struct intel_device_info ivb_q_info = { 480 GEN7_FEATURES, 481 PLATFORM(INTEL_IVYBRIDGE), 482 .gt = 2, 483 .pipe_mask = 0, /* legal, last one wins */ 484 .has_l3_dpf = 1, 485 }; 486 487 static const struct intel_device_info vlv_info = { 488 PLATFORM(INTEL_VALLEYVIEW), 489 GEN(7), 490 .is_lp = 1, 491 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), 492 .has_runtime_pm = 1, 493 .has_rc6 = 1, 494 .has_rps = true, 495 .display.has_gmch = 1, 496 .display.has_hotplug = 1, 497 .ppgtt_type = INTEL_PPGTT_ALIASING, 498 .ppgtt_size = 31, 499 .has_snoop = true, 500 .has_coherent_ggtt = false, 501 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), 502 .display_mmio_offset = VLV_DISPLAY_BASE, 503 I9XX_PIPE_OFFSETS, 504 I9XX_CURSOR_OFFSETS, 505 I965_COLORS, 506 GEN_DEFAULT_PAGE_SIZES, 507 GEN_DEFAULT_REGIONS, 508 }; 509 510 #define G75_FEATURES \ 511 GEN7_FEATURES, \ 512 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ 513 .display.has_ddi = 1, \ 514 .has_fpga_dbg = 1, \ 515 .display.has_psr = 1, \ 516 .display.has_dp_mst = 1, \ 517 .has_rc6p = 0 /* RC6p removed-by HSW */, \ 518 HSW_PIPE_OFFSETS, \ 519 .has_runtime_pm = 1 520 521 #define HSW_PLATFORM \ 522 G75_FEATURES, \ 523 PLATFORM(INTEL_HASWELL), \ 524 .has_l3_dpf = 1 525 526 static const struct intel_device_info hsw_gt1_info = { 527 HSW_PLATFORM, 528 .gt = 1, 529 }; 530 531 static const struct intel_device_info hsw_gt2_info = { 532 HSW_PLATFORM, 533 .gt = 2, 534 }; 535 536 static const struct intel_device_info hsw_gt3_info = { 537 HSW_PLATFORM, 538 .gt = 3, 539 }; 540 541 #define GEN8_FEATURES \ 542 G75_FEATURES, \ 543 GEN(8), \ 544 .has_logical_ring_contexts = 1, \ 545 .ppgtt_type = INTEL_PPGTT_FULL, \ 546 .ppgtt_size = 48, \ 547 .has_64bit_reloc = 1, \ 548 .has_reset_engine = 1 549 550 #define BDW_PLATFORM \ 551 GEN8_FEATURES, \ 552 PLATFORM(INTEL_BROADWELL) 553 554 static const struct intel_device_info bdw_gt1_info = { 555 BDW_PLATFORM, 556 .gt = 1, 557 }; 558 559 static const struct intel_device_info bdw_gt2_info = { 560 BDW_PLATFORM, 561 .gt = 2, 562 }; 563 564 static const struct intel_device_info bdw_rsvd_info = { 565 BDW_PLATFORM, 566 .gt = 3, 567 /* According to the device ID those devices are GT3, they were 568 * previously treated as not GT3, keep it like that. 569 */ 570 }; 571 572 static const struct intel_device_info bdw_gt3_info = { 573 BDW_PLATFORM, 574 .gt = 3, 575 .engine_mask = 576 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 577 }; 578 579 static const struct intel_device_info chv_info = { 580 PLATFORM(INTEL_CHERRYVIEW), 581 GEN(8), 582 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 583 .display.has_hotplug = 1, 584 .is_lp = 1, 585 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), 586 .has_64bit_reloc = 1, 587 .has_runtime_pm = 1, 588 .has_rc6 = 1, 589 .has_rps = true, 590 .has_logical_ring_contexts = 1, 591 .display.has_gmch = 1, 592 .ppgtt_type = INTEL_PPGTT_ALIASING, 593 .ppgtt_size = 32, 594 .has_reset_engine = 1, 595 .has_snoop = true, 596 .has_coherent_ggtt = false, 597 .display_mmio_offset = VLV_DISPLAY_BASE, 598 CHV_PIPE_OFFSETS, 599 CHV_CURSOR_OFFSETS, 600 CHV_COLORS, 601 GEN_DEFAULT_PAGE_SIZES, 602 GEN_DEFAULT_REGIONS, 603 }; 604 605 #define GEN9_DEFAULT_PAGE_SIZES \ 606 .page_sizes = I915_GTT_PAGE_SIZE_4K | \ 607 I915_GTT_PAGE_SIZE_64K 608 609 #define GEN9_FEATURES \ 610 GEN8_FEATURES, \ 611 GEN(9), \ 612 GEN9_DEFAULT_PAGE_SIZES, \ 613 .has_logical_ring_preemption = 1, \ 614 .display.has_csr = 1, \ 615 .has_gt_uc = 1, \ 616 .display.has_hdcp = 1, \ 617 .display.has_ipc = 1, \ 618 .ddb_size = 896, \ 619 .num_supported_dbuf_slices = 1 620 621 #define SKL_PLATFORM \ 622 GEN9_FEATURES, \ 623 PLATFORM(INTEL_SKYLAKE) 624 625 static const struct intel_device_info skl_gt1_info = { 626 SKL_PLATFORM, 627 .gt = 1, 628 }; 629 630 static const struct intel_device_info skl_gt2_info = { 631 SKL_PLATFORM, 632 .gt = 2, 633 }; 634 635 #define SKL_GT3_PLUS_PLATFORM \ 636 SKL_PLATFORM, \ 637 .engine_mask = \ 638 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1) 639 640 641 static const struct intel_device_info skl_gt3_info = { 642 SKL_GT3_PLUS_PLATFORM, 643 .gt = 3, 644 }; 645 646 static const struct intel_device_info skl_gt4_info = { 647 SKL_GT3_PLUS_PLATFORM, 648 .gt = 4, 649 }; 650 651 #define GEN9_LP_FEATURES \ 652 GEN(9), \ 653 .is_lp = 1, \ 654 .num_supported_dbuf_slices = 1, \ 655 .display.has_hotplug = 1, \ 656 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ 657 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 658 .has_64bit_reloc = 1, \ 659 .display.has_ddi = 1, \ 660 .has_fpga_dbg = 1, \ 661 .display.has_fbc = 1, \ 662 .display.has_hdcp = 1, \ 663 .display.has_psr = 1, \ 664 .has_runtime_pm = 1, \ 665 .display.has_csr = 1, \ 666 .has_rc6 = 1, \ 667 .has_rps = true, \ 668 .display.has_dp_mst = 1, \ 669 .has_logical_ring_contexts = 1, \ 670 .has_logical_ring_preemption = 1, \ 671 .has_gt_uc = 1, \ 672 .ppgtt_type = INTEL_PPGTT_FULL, \ 673 .ppgtt_size = 48, \ 674 .has_reset_engine = 1, \ 675 .has_snoop = true, \ 676 .has_coherent_ggtt = false, \ 677 .display.has_ipc = 1, \ 678 HSW_PIPE_OFFSETS, \ 679 IVB_CURSOR_OFFSETS, \ 680 IVB_COLORS, \ 681 GEN9_DEFAULT_PAGE_SIZES, \ 682 GEN_DEFAULT_REGIONS 683 684 static const struct intel_device_info bxt_info = { 685 GEN9_LP_FEATURES, 686 PLATFORM(INTEL_BROXTON), 687 .ddb_size = 512, 688 }; 689 690 static const struct intel_device_info glk_info = { 691 GEN9_LP_FEATURES, 692 PLATFORM(INTEL_GEMINILAKE), 693 .ddb_size = 1024, 694 GLK_COLORS, 695 }; 696 697 #define KBL_PLATFORM \ 698 GEN9_FEATURES, \ 699 PLATFORM(INTEL_KABYLAKE) 700 701 static const struct intel_device_info kbl_gt1_info = { 702 KBL_PLATFORM, 703 .gt = 1, 704 }; 705 706 static const struct intel_device_info kbl_gt2_info = { 707 KBL_PLATFORM, 708 .gt = 2, 709 }; 710 711 static const struct intel_device_info kbl_gt3_info = { 712 KBL_PLATFORM, 713 .gt = 3, 714 .engine_mask = 715 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 716 }; 717 718 #define CFL_PLATFORM \ 719 GEN9_FEATURES, \ 720 PLATFORM(INTEL_COFFEELAKE) 721 722 static const struct intel_device_info cfl_gt1_info = { 723 CFL_PLATFORM, 724 .gt = 1, 725 }; 726 727 static const struct intel_device_info cfl_gt2_info = { 728 CFL_PLATFORM, 729 .gt = 2, 730 }; 731 732 static const struct intel_device_info cfl_gt3_info = { 733 CFL_PLATFORM, 734 .gt = 3, 735 .engine_mask = 736 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 737 }; 738 739 #define GEN10_FEATURES \ 740 GEN9_FEATURES, \ 741 GEN(10), \ 742 .ddb_size = 1024, \ 743 .display.has_dsc = 1, \ 744 .has_coherent_ggtt = false, \ 745 GLK_COLORS 746 747 static const struct intel_device_info cnl_info = { 748 GEN10_FEATURES, 749 PLATFORM(INTEL_CANNONLAKE), 750 .gt = 2, 751 }; 752 753 #define GEN11_DEFAULT_PAGE_SIZES \ 754 .page_sizes = I915_GTT_PAGE_SIZE_4K | \ 755 I915_GTT_PAGE_SIZE_64K | \ 756 I915_GTT_PAGE_SIZE_2M 757 758 #define GEN11_FEATURES \ 759 GEN10_FEATURES, \ 760 GEN11_DEFAULT_PAGE_SIZES, \ 761 .pipe_offsets = { \ 762 [TRANSCODER_A] = PIPE_A_OFFSET, \ 763 [TRANSCODER_B] = PIPE_B_OFFSET, \ 764 [TRANSCODER_C] = PIPE_C_OFFSET, \ 765 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 766 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 767 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 768 }, \ 769 .trans_offsets = { \ 770 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 771 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 772 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 773 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 774 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 775 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 776 }, \ 777 GEN(11), \ 778 .ddb_size = 2048, \ 779 .num_supported_dbuf_slices = 2, \ 780 .has_logical_ring_elsq = 1, \ 781 .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 } 782 783 static const struct intel_device_info icl_info = { 784 GEN11_FEATURES, 785 PLATFORM(INTEL_ICELAKE), 786 .engine_mask = 787 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 788 }; 789 790 static const struct intel_device_info ehl_info = { 791 GEN11_FEATURES, 792 PLATFORM(INTEL_ELKHARTLAKE), 793 .require_force_probe = 1, 794 .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), 795 .ppgtt_size = 36, 796 }; 797 798 #define GEN12_FEATURES \ 799 GEN11_FEATURES, \ 800 GEN(12), \ 801 .pipe_offsets = { \ 802 [TRANSCODER_A] = PIPE_A_OFFSET, \ 803 [TRANSCODER_B] = PIPE_B_OFFSET, \ 804 [TRANSCODER_C] = PIPE_C_OFFSET, \ 805 [TRANSCODER_D] = PIPE_D_OFFSET, \ 806 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 807 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 808 }, \ 809 .trans_offsets = { \ 810 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 811 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 812 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 813 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 814 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 815 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 816 }, \ 817 TGL_CURSOR_OFFSETS, \ 818 .has_global_mocs = 1, \ 819 .display.has_dsb = 1 820 821 static const struct intel_device_info tgl_info = { 822 GEN12_FEATURES, 823 PLATFORM(INTEL_TIGERLAKE), 824 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 825 .require_force_probe = 1, 826 .display.has_modular_fia = 1, 827 .engine_mask = 828 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 829 }; 830 831 #define GEN12_DGFX_FEATURES \ 832 GEN12_FEATURES, \ 833 .is_dgfx = 1 834 835 #undef GEN 836 #undef PLATFORM 837 838 /* 839 * Make sure any device matches here are from most specific to most 840 * general. For example, since the Quanta match is based on the subsystem 841 * and subvendor IDs, we need it to come before the more general IVB 842 * PCI ID matches, otherwise we'll use the wrong info struct above. 843 */ 844 static const struct pci_device_id pciidlist[] = { 845 INTEL_I830_IDS(&i830_info), 846 INTEL_I845G_IDS(&i845g_info), 847 INTEL_I85X_IDS(&i85x_info), 848 INTEL_I865G_IDS(&i865g_info), 849 INTEL_I915G_IDS(&i915g_info), 850 INTEL_I915GM_IDS(&i915gm_info), 851 INTEL_I945G_IDS(&i945g_info), 852 INTEL_I945GM_IDS(&i945gm_info), 853 INTEL_I965G_IDS(&i965g_info), 854 INTEL_G33_IDS(&g33_info), 855 INTEL_I965GM_IDS(&i965gm_info), 856 INTEL_GM45_IDS(&gm45_info), 857 INTEL_G45_IDS(&g45_info), 858 INTEL_PINEVIEW_G_IDS(&pnv_g_info), 859 INTEL_PINEVIEW_M_IDS(&pnv_m_info), 860 INTEL_IRONLAKE_D_IDS(&ilk_d_info), 861 INTEL_IRONLAKE_M_IDS(&ilk_m_info), 862 INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info), 863 INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info), 864 INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info), 865 INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info), 866 INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */ 867 INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info), 868 INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info), 869 INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info), 870 INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info), 871 INTEL_HSW_GT1_IDS(&hsw_gt1_info), 872 INTEL_HSW_GT2_IDS(&hsw_gt2_info), 873 INTEL_HSW_GT3_IDS(&hsw_gt3_info), 874 INTEL_VLV_IDS(&vlv_info), 875 INTEL_BDW_GT1_IDS(&bdw_gt1_info), 876 INTEL_BDW_GT2_IDS(&bdw_gt2_info), 877 INTEL_BDW_GT3_IDS(&bdw_gt3_info), 878 INTEL_BDW_RSVD_IDS(&bdw_rsvd_info), 879 INTEL_CHV_IDS(&chv_info), 880 INTEL_SKL_GT1_IDS(&skl_gt1_info), 881 INTEL_SKL_GT2_IDS(&skl_gt2_info), 882 INTEL_SKL_GT3_IDS(&skl_gt3_info), 883 INTEL_SKL_GT4_IDS(&skl_gt4_info), 884 INTEL_BXT_IDS(&bxt_info), 885 INTEL_GLK_IDS(&glk_info), 886 INTEL_KBL_GT1_IDS(&kbl_gt1_info), 887 INTEL_KBL_GT2_IDS(&kbl_gt2_info), 888 INTEL_KBL_GT3_IDS(&kbl_gt3_info), 889 INTEL_KBL_GT4_IDS(&kbl_gt3_info), 890 INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info), 891 INTEL_CFL_S_GT1_IDS(&cfl_gt1_info), 892 INTEL_CFL_S_GT2_IDS(&cfl_gt2_info), 893 INTEL_CFL_H_GT1_IDS(&cfl_gt1_info), 894 INTEL_CFL_H_GT2_IDS(&cfl_gt2_info), 895 INTEL_CFL_U_GT2_IDS(&cfl_gt2_info), 896 INTEL_CFL_U_GT3_IDS(&cfl_gt3_info), 897 INTEL_WHL_U_GT1_IDS(&cfl_gt1_info), 898 INTEL_WHL_U_GT2_IDS(&cfl_gt2_info), 899 INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info), 900 INTEL_WHL_U_GT3_IDS(&cfl_gt3_info), 901 INTEL_CML_GT1_IDS(&cfl_gt1_info), 902 INTEL_CML_GT2_IDS(&cfl_gt2_info), 903 INTEL_CML_U_GT1_IDS(&cfl_gt1_info), 904 INTEL_CML_U_GT2_IDS(&cfl_gt2_info), 905 INTEL_CNL_IDS(&cnl_info), 906 INTEL_ICL_11_IDS(&icl_info), 907 INTEL_EHL_IDS(&ehl_info), 908 INTEL_TGL_12_IDS(&tgl_info), 909 {0, 0, 0} 910 }; 911 MODULE_DEVICE_TABLE(pci, pciidlist); 912 913 static void i915_pci_remove(struct pci_dev *pdev) 914 { 915 struct drm_i915_private *i915; 916 917 i915 = pci_get_drvdata(pdev); 918 if (!i915) /* driver load aborted, nothing to cleanup */ 919 return; 920 921 i915_driver_remove(i915); 922 pci_set_drvdata(pdev, NULL); 923 924 drm_dev_put(&i915->drm); 925 } 926 927 /* is device_id present in comma separated list of ids */ 928 static bool force_probe(u16 device_id, const char *devices) 929 { 930 char *s, *p, *tok; 931 bool ret; 932 933 if (!devices || !*devices) 934 return false; 935 936 /* match everything */ 937 if (strcmp(devices, "*") == 0) 938 return true; 939 940 s = kstrdup(devices, GFP_KERNEL); 941 if (!s) 942 return false; 943 944 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) { 945 u16 val; 946 947 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) { 948 ret = true; 949 break; 950 } 951 } 952 953 kfree(s); 954 955 return ret; 956 } 957 958 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 959 { 960 struct intel_device_info *intel_info = 961 (struct intel_device_info *) ent->driver_data; 962 int err; 963 964 if (intel_info->require_force_probe && 965 !force_probe(pdev->device, i915_modparams.force_probe)) { 966 dev_info(&pdev->dev, 967 "Your graphics device %04x is not properly supported by the driver in this\n" 968 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n" 969 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n" 970 "or (recommended) check for kernel updates.\n", 971 pdev->device, pdev->device, pdev->device); 972 return -ENODEV; 973 } 974 975 /* Only bind to function 0 of the device. Early generations 976 * used function 1 as a placeholder for multi-head. This causes 977 * us confusion instead, especially on the systems where both 978 * functions have the same PCI-ID! 979 */ 980 if (PCI_FUNC(pdev->devfn)) 981 return -ENODEV; 982 983 /* 984 * apple-gmux is needed on dual GPU MacBook Pro 985 * to probe the panel if we're the inactive GPU. 986 */ 987 if (vga_switcheroo_client_probe_defer(pdev)) 988 return -EPROBE_DEFER; 989 990 err = i915_driver_probe(pdev, ent); 991 if (err) 992 return err; 993 994 if (i915_inject_probe_failure(pci_get_drvdata(pdev))) { 995 i915_pci_remove(pdev); 996 return -ENODEV; 997 } 998 999 err = i915_live_selftests(pdev); 1000 if (err) { 1001 i915_pci_remove(pdev); 1002 return err > 0 ? -ENOTTY : err; 1003 } 1004 1005 err = i915_perf_selftests(pdev); 1006 if (err) { 1007 i915_pci_remove(pdev); 1008 return err > 0 ? -ENOTTY : err; 1009 } 1010 1011 return 0; 1012 } 1013 1014 static struct pci_driver i915_pci_driver = { 1015 .name = DRIVER_NAME, 1016 .id_table = pciidlist, 1017 .probe = i915_pci_probe, 1018 .remove = i915_pci_remove, 1019 .driver.pm = &i915_pm_ops, 1020 }; 1021 1022 static int __init i915_init(void) 1023 { 1024 bool use_kms = true; 1025 int err; 1026 1027 err = i915_globals_init(); 1028 if (err) 1029 return err; 1030 1031 err = i915_mock_selftests(); 1032 if (err) 1033 return err > 0 ? 0 : err; 1034 1035 /* 1036 * Enable KMS by default, unless explicitly overriden by 1037 * either the i915.modeset prarameter or by the 1038 * vga_text_mode_force boot option. 1039 */ 1040 1041 if (i915_modparams.modeset == 0) 1042 use_kms = false; 1043 1044 if (vgacon_text_force() && i915_modparams.modeset == -1) 1045 use_kms = false; 1046 1047 if (!use_kms) { 1048 /* Silently fail loading to not upset userspace. */ 1049 DRM_DEBUG_DRIVER("KMS disabled.\n"); 1050 return 0; 1051 } 1052 1053 err = pci_register_driver(&i915_pci_driver); 1054 if (err) 1055 return err; 1056 1057 i915_perf_sysctl_register(); 1058 return 0; 1059 } 1060 1061 static void __exit i915_exit(void) 1062 { 1063 if (!i915_pci_driver.driver.owner) 1064 return; 1065 1066 i915_perf_sysctl_unregister(); 1067 pci_unregister_driver(&i915_pci_driver); 1068 i915_globals_exit(); 1069 } 1070 1071 module_init(i915_init); 1072 module_exit(i915_exit); 1073 1074 MODULE_AUTHOR("Tungsten Graphics, Inc."); 1075 MODULE_AUTHOR("Intel Corporation"); 1076 1077 MODULE_DESCRIPTION(DRIVER_DESC); 1078 MODULE_LICENSE("GPL and additional rights"); 1079